From patchwork Tue Dec 14 03:58:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=TxWekLjB; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JCl3W2m3Rz9s5P for ; Tue, 14 Dec 2021 14:58:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230000AbhLND61 (ORCPT ); Mon, 13 Dec 2021 22:58:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233473AbhLND61 (ORCPT ); Mon, 13 Dec 2021 22:58:27 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A89A0C061574; Mon, 13 Dec 2021 19:58:26 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id gx15-20020a17090b124f00b001a695f3734aso15087755pjb.0; Mon, 13 Dec 2021 19:58:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AmoK+hw/VDuDSmUiZvkIrRjThwbV3KHs/0+W71eQGM4=; b=TxWekLjBbatS+wUHawW22nnqVmRfu5EEI2PugrNEoRElgmjBpAyLWzC7EXVsIrlile bA1P0iekLCtvm2zN968dsofv7hdkzl9unSFKYYbxH1F39t3gQZJjFZKbY/3STd4p4Yi3 k6FEjCJL8KIQrIoKSLvRaf7V8H9TXKCM9cLB8ThI0K6dOYASPWzem1mRPQ7MXx1Q582G ZBuuhLJebj2/QBR7rFPS80AdWYJADH2gddu/wjI4m30/59EUGfV6Z3FduqWx2Bk+7MKm r9W86HwrVBwNWqP6+pzsAHmj0lu3M/6ao4R14ZVq0UjVnB9XEVlnFyv7lAvHpL2Luq3c 1fWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AmoK+hw/VDuDSmUiZvkIrRjThwbV3KHs/0+W71eQGM4=; b=vAmCKYpJrIvIYF0N7PVtrLYk+knFZ1euLoV2tGeFgdvB1NTZWC6MgcRevod4x4xLsp rH3PDlHltBx6zHLZUcacFEiTBIgUHVamKPFIZfbsBo1IN0fKNKojhVkHqo3ctkcvqQYJ yus2xy+9wJNlsFazgJjjJuu59LNkBelZ6nB95Rm6MLFSlSU1EQdYQHydHGpL+cSbmrCf /K0MmTlenxgUKdGOzKeCSPEVLaUfHYNUws6lYjRw/bUACB56DZBYus3lZs+9VGAgiq74 9liIt3wveJMlBIWVH/L34G7PW56kIteLIPNw0Z74NthlRFXa1zI2f5jDoMs8zhnqDqs5 n9EQ== X-Gm-Message-State: AOAM530vQFiBZoFvvdckvp+Im6Yimyy252d6uMYWvdW1k78QxLTMtNJS B5gXVBXpcBKDjE3pAZ7mvMtrO1FSdgs= X-Google-Smtp-Source: ABdhPJwAo5BgBH1aH3aBZfk+YdSV45D+9nWr4FeaLa4KheTbhyw0cJBGMp1PqQBh5lRyRdJJEIning== X-Received: by 2002:a17:902:d2c3:b0:146:6c28:191e with SMTP id n3-20020a170902d2c300b001466c28191emr2683833plc.7.1639454305876; Mon, 13 Dec 2021 19:58:25 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o17sm11430356pgb.42.2021.12.13.19.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 19:58:25 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 1/6] ARM: dts: Cygnus: Fixed iProc PCIe controller properties Date: Mon, 13 Dec 2021 19:58:15 -0800 Message-Id: <20211214035820.2984289-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211214035820.2984289-1-f.fainelli@gmail.com> References: <20211214035820.2984289-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..e73a19409d71 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ pcie0: pcie@18012000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ pcie1: pcie@18013000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Tue Dec 14 03:58:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Hk57xSk4; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Mon, 13 Dec 2021 19:58:27 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o17sm11430356pgb.42.2021.12.13.19.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 19:58:26 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 2/6] ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Date: Mon, 13 Dec 2021 19:58:16 -0800 Message-Id: <20211214035820.2984289-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211214035820.2984289-1-f.fainelli@gmail.com> References: <20211214035820.2984289-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d71..ad65be871938 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ otp: otp@301c800 { status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; From patchwork Tue Dec 14 03:58:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=LB04x1mO; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JCl3m3Xqnz9s3q for ; Tue, 14 Dec 2021 14:58:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233573AbhLND6c (ORCPT ); Mon, 13 Dec 2021 22:58:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233558AbhLND6a (ORCPT ); Mon, 13 Dec 2021 22:58:30 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4409C0613F8; Mon, 13 Dec 2021 19:58:29 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id y7so12702981plp.0; Mon, 13 Dec 2021 19:58:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=LB04x1mOY0EfpsXQFHT0385OPgqMxqnezuCSRKRQIYyV6pHq07SFep9Rt02ThAbs2I DxTXNnwE4be66eoZQNGf7cra+MMNFl8RRYSPC4RfH4zQfjUdy8h++hK4GdetaNgWK2c+ fP9bQl2Sb7Lcy8MABVfDISe7k7SK+XvQwdp0Edb+vFX5vr/5YoYMxY9w7maK2JXr/8jM DUrtVTWQywQBYdGZjgJ3SmAGHoCXzUQXIjaJMvi5QvtEcILy7kEfYHPCXSx+BC0GRdI9 CJWMR6AyVZ6fr4eNQn3XwdrnbHe3sDntjgXNCvhpNwOuoF4YIZsjUoedxspVQbKtCzdH qAlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=a1LHWgc0WDaco6VEIsZv0e02c3jdwZpW4bcR9sSpah6gmwQQNFkhuufLhdzGIneSle 5SZMd+u9zPlk1c4jK8EepB6+45WWPbW6vYw1MErMBCEZGg/PnK5FHizbJKT6TSVRkQ/5 Gdbjl8qD7w8jmKKPEl+ymlq04nNIW6Zu9UzD8USTaVHAAuNnhfo1PbtLXzcBI3o046Zd SGiViAWvzrxf0DA1zEvynedaPfH0SIZcCtDPwgUvM+olXJflUgK+H25zMQbv6RX8PaSg erPCI6T0W3Xh788+V6FCjUSp85eZI+qPCRb+/CFF9AfM/GQiImmkx2VwJYQQ0DwuayCS Jbuw== X-Gm-Message-State: AOAM530LdBxwg915zKICxaaAi1QlFUo4mU7OA4NOdjwrcNO2ESZXxsFH O7Uwrz/j+u+y+d2YdaYBSFyPymuKAPw= X-Google-Smtp-Source: ABdhPJzVRDHpnHWBHT00swMJfpAiOoxy6pc2oZirFVhtc9kKMEzF7ReJK7ShOmRr8oRz3H+yHDc36g== X-Received: by 2002:a17:903:408c:b0:142:45a9:672c with SMTP id z12-20020a170903408c00b0014245a9672cmr3379296plc.7.1639454308767; Mon, 13 Dec 2021 19:58:28 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o17sm11430356pgb.42.2021.12.13.19.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 19:58:28 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 3/6] ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Date: Mon, 13 Dec 2021 19:58:17 -0800 Message-Id: <20211214035820.2984289-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211214035820.2984289-1-f.fainelli@gmail.com> References: <20211214035820.2984289-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Tue Dec 14 03:58:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=DZhJTuI7; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JCl3n1Yw2z9s3q for ; Tue, 14 Dec 2021 14:58:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233663AbhLND6e (ORCPT ); Mon, 13 Dec 2021 22:58:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233553AbhLND6b (ORCPT ); Mon, 13 Dec 2021 22:58:31 -0500 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E9DAC061748; Mon, 13 Dec 2021 19:58:31 -0800 (PST) Received: by mail-pg1-x52b.google.com with SMTP id l18so11594119pgj.9; Mon, 13 Dec 2021 19:58:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=DZhJTuI7YzW03odBx/bNqEurSo33emVPAj/azvE7XrsemmvRymdUBsKJBff4HbXKL2 cnSjxAD0V8TCBQegRSQlL+p0cgFJMvRJ1wJbXAfZi1y34kZYEk6AwnM+89LQBT5BG/Gx TLDlsGdZNcSXZghV/JbjO+CQKgmkVmsk29Qqdk2nWMy5rLqJlV2/U0pE6Jv9gEk4xq+/ 3KHIYynY4PhX/vuw3djmgN7GA/Q39Zc65HDLyr0AXnaEkHd13V65VJyfbC4/rgGQZ9DT YmJHkEVbcALis4r63k2ABnepHaAqCawCwDzISMYVrtVLoOHh3CzPgDf486gRtqKM0MlI Oh3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=LBrxgmlMFljoeW2wuMWurXOSk1e9H1oOfhe0TfctjQDkF3Atyo0CE6CAtJ/fq7Gs9c whgihaB6gVxHBEirXiwL0EXDdeXz3qjXXCT9X34NsyEC6l+bd4HxLgKBnPBrXhlZc5wa KievA+H56kS5DGsGTbjGXA9uoP8lohnLlt2gkY0RzfbRJb8EeawTKjl2LhdbLhH1uoQA MgwKM3tJbm7n8vysAEJdP1QhVTvdRHltJ/Kjo6AX8kvgbMv071eBHIgpQWBBR5Zo60TN iYCcrLmJZnmfc1xwNtDhN5kubTpVSpJZc81L8fecB1Ip4gUWSns3vZjWbPNJqyTBlpR2 e4gw== X-Gm-Message-State: AOAM533w0ZK/8xs3GjjP6ouodS/irOxQsyVk24Uh2GgJVPtTOJW+4Alz 2bBpzahhF0eS2II5GlNerjJOJIBzaMQ= X-Google-Smtp-Source: ABdhPJxV9k0ZL4Gqs67Vg9VKizi/lSyC7nsQ/hfmdjfPA6IUerHTOc5040md/BDFUMBR4ca4StXqUg== X-Received: by 2002:a62:8103:0:b0:4ae:d63e:9d85 with SMTP id t3-20020a628103000000b004aed63e9d85mr2108727pfd.69.1639454310360; Mon, 13 Dec 2021 19:58:30 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o17sm11430356pgb.42.2021.12.13.19.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 19:58:29 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 4/6] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Date: Mon, 13 Dec 2021 19:58:18 -0800 Message-Id: <20211214035820.2984289-5-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211214035820.2984289-1-f.fainelli@gmail.com> References: <20211214035820.2984289-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ pcie2: pcie@18014000 { status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Tue Dec 14 03:58:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Signed-off-by: Florian Fainelli --- .../bindings/phy/brcm,cygnus-pcie-phy.txt | 47 ------------ .../bindings/phy/brcm,cygnus-pcie-phy.yaml | 76 +++++++++++++++++++ 2 files changed, 76 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt deleted file mode 100644 index 10efff28b52b..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt +++ /dev/null @@ -1,47 +0,0 @@ -Broadcom Cygnus PCIe PHY - -Required properties: -- compatible: must be "brcm,cygnus-pcie-phy" -- reg: base address and length of the PCIe PHY block -- #address-cells: must be 1 -- #size-cells: must be 0 - -Each PCIe PHY should be represented by a child node - -Required properties For the child node: -- reg: the PHY ID -0 - PCIe RC 0 -1 - PCIe RC 1 -- #phy-cells: must be 0 - -Example: - pcie_phy: phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - /* users of the PCIe phy */ - - pcie0: pcie@18012000 { - ... - ... - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - }; - - pcie1: pcie@18013000 { - ... - ... - phys = ; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml new file mode 100644 index 000000000000..045699c65779 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Cygnus PCIe PHY + +maintainers: + - Ray Jui + - Scott Branden + +properties: + $nodename: + pattern: "^pcie[-|_]phy(@.*)?$" + + compatible: + items: + - const: brcm,cygnus-pcie-phy + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe PHY block + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^pcie-phy@[0-9]+$": + type: object + description: > + PCIe PHY child nodes + + properties: + reg: + maxItems: 1 + description: > + The PCIe PHY port number + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + pcie_phy: pcie_phy@301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_phy: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_phy: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; From patchwork Tue Dec 14 03:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1567559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=ptqCGE1e; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JCl3p4w20z9s3q for ; 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Mon, 13 Dec 2021 19:58:32 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 6/6] dt-bindings: pci: Convert iProc PCIe to YAML Date: Mon, 13 Dec 2021 19:58:20 -0800 Message-Id: <20211214035820.2984289-7-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211214035820.2984289-1-f.fainelli@gmail.com> References: <20211214035820.2984289-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Conver the iProc PCIe controller Device Tree binding to YAML now that all DTS in arch/arm and arch/arm64 have been fixed to be compliant. Signed-off-by: Florian Fainelli --- .../bindings/pci/brcm,iproc-pcie.txt | 133 ------------- .../bindings/pci/brcm,iproc-pcie.yaml | 184 ++++++++++++++++++ 2 files changed, 184 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt deleted file mode 100644 index df065aa53a83..000000000000 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ /dev/null @@ -1,133 +0,0 @@ -* Broadcom iProc PCIe controller with the platform bus interface - -Required properties: -- compatible: - "brcm,iproc-pcie" for the first generation of PAXB based controller, -used in SoCs including NSP, Cygnus, NS2, and Pegasus - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based -controllers, used in Stingray - "brcm,iproc-pcie-paxc" for the first generation of PAXC based -controller, used in NS2 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -controller, used in Stingray - PAXB-based root complex is used for external endpoint devices. PAXC-based -root complex is connected to emulated endpoint devices internal to the ASIC -- reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers -- linux,pci-domain: PCI domain ID. Should be unique for each host controller -- bus-range: PCI bus numbers covered -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions - -Optional properties: -- phys: phandle of the PCIe PHY device -- phy-names: must be "pcie-phy" -- dma-coherent: present if DMA operations are coherent -- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done - by the ASIC after power on reset. In this case, SW is required to configure -the mapping, based on inbound memory regions specified by this property. - -- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -by the ASIC after power on reset. In this case, SW needs to configure it - -If the brcm,pcie-ob property is present, the following properties become -effective: - -Required: -- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -address used by the iProc PCIe core (not the PCIe address) - -MSI support (optional): - -For older platforms without MSI integrated in the GIC, iProc PCIe core provides -an event queue based MSI support. The iProc MSI uses host memories to store -MSI posted writes in the event queues - -On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used - -- msi-map: Maps a Requester ID to an MSI controller and associated MSI -sideband data - -- msi-parent: Link to the device node of the MSI controller, used when no MSI -sideband data is passed between the iProc PCIe controller and the MSI -controller - -Refer to the following binding documents for more detailed description on -the use of 'msi-map' and 'msi-parent': - Documentation/devicetree/bindings/pci/pci-msi.txt - Documentation/devicetree/bindings/interrupt-controller/msi.txt - -When the iProc event queue based MSI is used, one needs to define the -following properties in the MSI device node: -- compatible: Must be "brcm,iproc-msi" -- msi-controller: claims itself as an MSI controller -- interrupts: List of interrupt IDs from its parent interrupt device - -Optional properties: -- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -require the interrupt enable registers to be set explicitly to enable MSI - -Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; - - brcm,pcie-ob; - brcm,pcie-ob-axi-offset = <0x00000000>; - - msi-parent = <&msi0>; - - /* iProc event queue based MSI */ - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&phy 1 6>; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml new file mode 100644 index 000000000000..0972868735fc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PCIe controller with the platform bus interface + +maintainers: + - Ray Jui + - Scott Branden + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + # for the first generation of PAXB based controller, used in SoCs + # including NSP, Cygnus, NS2, and Pegasus + - brcm,iproc-pcie + # for the second generation of PAXB-based controllers, used in + # Stingray + - brcm,iproc-pcie-paxb-v2 + # For the first generation of PAXC based controller, used in NS2 + - brcm,iproc-pcie-paxc + # For the second generation of PAXC based controller, used in Stingray + - brcm,iproc-pcie-paxc-v2 + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe controller I/O register space + + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 1 + + ranges: + minItems: 1 + maxItems: 2 + description: > + Ranges for the PCI memory and I/O regions + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + bus-range: true + + dma-coherent: true + + "#address-cells": true + + "#size-cells": true + + device_type: true + + brcm,pcie-ob: + type: boolean + description: > + Some iProc SoCs do not have the outbound address mapping done by the + ASIC after power on reset. In this case, SW needs to configure it + + brcm,pcie-ob-axi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The offset from the AXI address to the internal address used by the + iProc PCIe core (not the PCIe address) + + msi: + type: object + properties: + compatible: + items: + - const: brcm,iproc-msi + + msi-parent: true + + msi-controller: true + + brcm,pcie-msi-inten: + type: boolean + description: > + Needs to be present for some older iProc platforms that require the + interrupt enable registers to be set explicitly to enable MSI + +dependencies: + brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"] + brcm,pcie-msi-inten: [msi-controller] + +required: + - compatible + - reg + - ranges + +if: + properties: + compatible: + contains: + enum: + - brcm,iproc-pcie +then: + required: + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include + + bus { + #address-cells = <1>; + #size-cells = <1>; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + phys = <&phy 0 5>; + phy-names = "pcie-phy"; + + brcm,pcie-ob; + brcm,pcie-ob-axi-offset = <0x00000000>; + + msi-parent = <&msi0>; + + /* iProc event queue based MSI */ + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + phys = <&phy 1 6>; + phy-names = "pcie-phy"; + }; + };