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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:42 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Marcel Ziswiler Subject: [PATCH v7 01/31] doc: Add documentation about devicetree usage Date: Mon, 6 Dec 2021 17:11:39 -0700 Message-Id: <20211207001209.3467163-2-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean At present some of the ideas and techniques behind devicetree in U-Boot are assumed, implied or unsaid. Add some documentation to cover how devicetree is build, how it can be modified and the rules about using the various CONFIG_OF_... options. Signed-off-by: Simon Glass Reviewed-by: Marcel Ziswiler --- This patch attracted quite a bit of discussion here: https://patchwork.ozlabs.org/project/uboot/patch/20210909201033.755713-4-sjg@chromium.org/ I have not included the text suggested by François. While I agree that it would be useful to have an introduction in this space, I do not agree that we should have two devicetrees or that U-Boot should not have its own things in the devicetree, so it is not clear to me what we should actually write. The 'Devicetree Control in U-Boot' docs were recently merged and these provide some base info, for now. Changes in v7: - Fix 'linst' typo Changes in v6: - Fix description of OF_BOARD so it refers just to the current state - Explain that the 'two devicetrees' refers to two *control* devicetrees Changes in v5: - Bring into the OF_BOARD series - Rebase to master and drop mention of OF_PRIOR_STAGE, since removed - Refer to the 'control' DTB in the first paragraph - Use QEMU instead of qemu Changes in v3: - Clarify the 'bug' refered to at the top - Reword 'This means that there' paragraph to explain U-Boot-specific things - Move to doc/develop/devicetree now that OF_CONTROL is in the docs Changes in v2: - Fix typos per Sean (thank you!) and a few others - Add a 'Use of U-Boot /config node' section - Drop mention of dm-verity since that actually uses the kernel cmdline - Explain that OF_BOARD will still work after these changes (in 'Once this bug is fixed...' paragraph) - Expand a bit on the reason why the 'Current situation' is bad - Clarify in a second place that Linux and U-Boot use the same devicetree in 'To be clear, while U-Boot...' - Expand on why we should have rules for other projects in 'Devicetree in another project' - Add a comment as to why devicetree in U-Boot is not 'bad design' - Reword 'in-tree U-Boot devicetree' to 'devicetree source in U-Boot' - Rewrite 'Devicetree generated on-the-fly in another project' to cover points raised on v1 - Add 'Why does U-Boot have its nodes and properties?' - Add 'Why not have two devicetrees?' doc/develop/devicetree/dt_update.rst | 555 +++++++++++++++++++++++++++ doc/develop/devicetree/index.rst | 1 + 2 files changed, 556 insertions(+) create mode 100644 doc/develop/devicetree/dt_update.rst diff --git a/doc/develop/devicetree/dt_update.rst b/doc/develop/devicetree/dt_update.rst new file mode 100644 index 00000000000..e3b65f6fa66 --- /dev/null +++ b/doc/develop/devicetree/dt_update.rst @@ -0,0 +1,555 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Updating the devicetree +======================= + +U-Boot uses devicetree for runtime configuration and storing required blobs or +any other information it needs to operate. This is called the 'control' +devicetree since it controls U-Boot. It is possible to update the control +devicetree separately from actually building U-Boot. This provides a good degree +of control and flexibility for firmware that uses U-Boot in conjunction with +other project. + +There are many reasons why it is useful to modify the devicetree after building +it: + +- Configuration can be changed, e.g. which UART to use +- A serial number can be added +- Public keys can be added to allow image verification +- Console output can be changed (e.g. to select serial or vidconsole) + +This section describes how to work with devicetree to accomplish your goals. + +See also :doc:`../devicetree/control` for a basic summary of the available +features. + + +Devicetree source +----------------- + +Every board in U-Boot must include a devicetree sufficient to build and boot +that board on suitable hardware (or emulation). This is specified using the +`CONFIG DEFAULT_DEVICE_TREE` option. + + +Current situation (October 2021) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +As an aside, at present U-Boot allows `CONFIG_DEFAULT_DEVICE_TREE` to be empty, +e.g. if `CONFIG_OF_BOARD` is used. This has unfortunately created an enormous +amount of confusion and some wasted effort. This was not intended. Support for +an empty `CONFIG_DEFAULT_DEVICE_TREE` will be dropped soon. + +Some of the problems created are: + +- It is not obvious that the devicetree is coming from another project + +- There is no way to see even a sample devicetree for these platform in U-Boot, + so it is hard to know what is going on, e.g. which devices are typically + present + +- The other project may not provide a way to support U-Boot's requirements for + devicetree, such as the /config node. Note: On the U-Boot mailing list, this + was only discovered after weeks of discussion and confusion + +- For QEMU specifically, consulting two QEMU source files is required, for which + there are no references in U-Boot documentation. The code is generating a + devicetree, but it is not clear what controls affect this generation. + +Specifically on the changes in U-Bootm `CONFIG_OF_BOARD` was added in +rpi_patch_ for Raspberry Pi, which does have an in-tree devicetree, but this +feature has since been used for boards that don't + +Once this bug is fixed, CONFIG_OF_BOARD will override (at runtime) the +evicetree suppled with U-Boot, but will otherwise use CONFIG_OF_SEPARATE for the +in-tree build. So these two will become options, moving out of the 'choice' in +`dts/Kconfig`. + +This means that there is a basic devicetree build in the U-Boot tree, for +build-testing, consistency and documentation purposes, but at runtime U-Boot can +accept its devicetree from another source. The in-tree devicetree may contain +U-Boot-specific features (in u-boot*.dtsi files) and this may prove useful for +the other project, so it can ensure that U-Boot functions correctly and supports +all its expected features. + +To be clear, while U-Boot has its own copy of the devicetree source for each +board, this must match the Linux source, perhaps with some u-boot.dtsi +additions. The intent here is not to create a separate binding, just to provide +a representative devicetree in U-Boot. + +Offending boards are: + +- rpi_4 and rpi_4_32b (other rpi boards do have an in-tree devicetree) +- qemu_arm64 +- qemu_arm +- qemu-ppce500 +- qemu-riscv32 +- qemu-riscv32_smode +- qemu-riscv64 +- qemu-riscv64_smode + +All of these need to have a devicetree added in-tree. This is targeted to be +fixed in the 2022.01 release. + + +Building the devicetree +----------------------- + +U-Boot automatically builds the devicetree for a board, from the +`arch//dts` directory. The Makefile in those directories has rules for +building devicetree files. It is preferable to avoid target-specific rules in +those files: i.e. all boards for a particular SoC should be built at once, +where practical. Apart from simplifying the Makefile, this helps to efficiently +(and immediately) ensure that changes in one board's DT do not break others that +are related. Building devicetrees is fast, so performance is seldom a concern +here. + + +Overriding the default devicetree +--------------------------------- + +When building U-Boot, the `DEVICE_TREE` environment variable allows the +default devicetree file to be overridden at build time. This can be useful if +modifications have to be made to the in-tree devicetree file, for the benefit +of a downstream build system. Note that the in-tree devicetree must be +sufficient to build and boot, so this is not a way to bypass that requirement. + + +Modifying the devicetree after building +--------------------------------------- + +While it is generally painful and hacky to modify the code or rodata of a +program after it is built, in many cases it is useful to do so, e.g. to add +configuration information like serial numbers, enabling/disabling features, etc. + +Devicetree provides a very nice solution to these problems since it is +structured data and it is relatively easy to change it, even in binary form +(see fdtput). + +U-Boot takes care that the devicetree is easily accessible after the build +process. In fact it is placed in a separate file called `u-boot.dtb`. If the +build system wants to modify or replace that file, it can do so. Then all that +is needed is to run `binman update` to update the file inside the image. If +binman is not used, then `u-boot-nodtb.bin` and the new `u-boot.dtb` can simply +be concatenated to achieve the desired result. U-Boot happily copes with the +devicetree growing or shrinking. + +The `u-boot.bin` image contains both pieces. While it is possible to locate the +devicetree within the image using the signature at the start of the file, this +is a bit messy. + +This is why `CONFIG_OF_SEPARATE` should always be used when building U-Boot. +The `CONFIG_OF_EMBED` option embeds the devicetree somewhere in the U-Boot ELF +image as rodata, meaning that it is hard to find it and it cannot increase in +size. + +When modifying the devicetree, the different cases to consider are as follows: + +- CONFIG_OF_SEPARATE + This is easy, described above. Just change, replace or rebuild the + devicetree so it suits your needs, then rerun binman or redo the `cat` + operation to join `u-boot-nodtb.bin` and the new `u-boot.dtb` + +- CONFIG_OF_EMBED + This is tricky, since the devicetree cannot easily be located. If the EFL + file is available, then the _dtb_dt_begin and __dtb_dt_end symbols can be + examined to find it. While it is possible to contract the file, it is not + possible to expand the file since that would involve re-linking + +- CONFIG_OF_BOARD + This is a board-specific situation, so needs to be considered on a + case-by-case base. + + +Use of U-Boot /config node +-------------------------- + +A common problem with firmware is that many builds are needed to deal with the +slight variations between different, related models. For example, one model may +have a TPM and another may not. Devicetree provides an excellent solution to +this problem, in that the devicetree to actually use on a platform can be +injected in the factory based on which model is being manufactured at the time. + +A related problem causing build proliferation is dealing with the differences +between development firmware, developer-friendly firmware (e.g. with all +security features present but with the ability to access the command line), +test firmware (which runs tests used in the factory), final production firmware +(before signing), signed firmware (where the signatures have been inserted) and +the like. Ideally all or most of these should use the same U-Boot build, with +just some options to determine the features available. For example, being able +to control whether the UART console or JTAG are available, on any image, is a +great debugging aid. + +When the firmware consists of multiple parts, it is helpful that all operate +the same way at runtime, regardless of how they were built. This can be achieved +by passing the runtime configuration (e.g. 'enable UART console) along the chain +through each firmware stage. It is frustrating to have to replicate a bug on +production firmware which does happen on developer firmware, because they are +completely different builds. + +The /config node provides useful functionality for this. It allows the different +controls to be 'factored out' of the U-Boot binary, so they can be controlled +separately from the initial source-code build. The node can be easily updated by +a build or factory tool and can control various features in U-Boot. It is +similar in concept to a Kconfig option, except that it can be changed after +U-Boot is built. + +The /config node is similar in concept to the `/chosen node`_ except that it is +for passing information *into* firmware instead of from firmware to the +Operating System. Also, while Linux has a (sometimes extremely long) command +line, U-Boot does not support this. The devicetree provides a more structured +approach in any case. + + +Devicetree in another project +----------------------------- + +In some cases U-Boot receive its devicetree at runtime from a program that calls +it. For example ARM's Trusted Firmware A (`TF-A`_) may have a devicetree that it +passes to U-Boot. This overrides any devicetree build by U-Boot. When packaging +the firmware, the U-Boot devicetree may in fact be left out if it can be +guaranteed that it will receive one from another project. + +In this case, the devicetree in the other project must track U-Boot's use of +device tree, for the following reasons: + +- U-Boot only has one devicetree. See `Why not have two devicetrees?`_. +- For a consistent firmware build, decisions made in early stages should be + communicated to later ones at runtime. For example, if the serial console is + enabled in an early stage, it should be enabled in U-Boot too. +- U-Boot is quite capable of managing its own copy of the devicetree. If + another project wants to bypass this (often for good reason), it is reasonable + that it should take on the (fairly small) requirements that U-Boot features + that rely on devicetree are still available +- The point here is not that *U-Boot needs this extra node*, or *U-Boot needs + to have this public key*. These features are present in U-Boot in service of + the entire firmware system. If the U-Boot features are used, but cannot be + supported in the normal way, then there is pressure to implement these + features in other ways. In the end, we would have a different mechanism for + every other project that uses U-Boot. This introduces duplicate ways of doing + the same thing, needlessly increases the complexity of the U-Boot source code, + forces authors to consider parallel implementations when writing new features, + makes U-Boot harder to test, complicates documentation and confuses the + runtime flow of U-Boot. If every board did things its own way rather than + contributing to the common code, U-Boot would lose a lot of its cross-platform + value. + +The above does not indicate *bad design* within U-Boot. Devicetree is a core +component of U-Boot and U-Boot makes use of it to the full. It solves a myriad +of problems that would otherwise need their own special C struct, binary format, +special property, tooling for viewing and updating, etc. + +Specifically, the other project must provide a way to add configuration and +other information to the devicetree for use by U-Boot, such as the /config node. +Note that the U-Boot in-tree devicetree source must be sufficient to build and +boot, so this is not a way to bypass that requirement. + +If binman is used, the devicetree source in U-Boot must contain the binman +definition so that a valid image can be build. This helps people discover what +other firmware components are needed and seek out appropriate documentation. + +If verified boot is used, the project must provide a way to inject a public key, +certificate or other material into the U-Boot devicetree so that it is available +to U-Boot at runtime. See `Signing with U-Boot devicetree`_. This may be +through tooling in the project itself or by making use of U-Boot's tooling. + + +Devicetree generated on-the-fly in another project +-------------------------------------------------- + +In some rare cases, another project may wish to create a devicetree for U-Boot +entirely on-the-fly, then pass it to U-Boot at runtime. The only known example +of this at the time of writing (2021) is QEMU, for ARM (`QEMU ARM`_) and +RISC-V (`QEMU RISC-V`_). + +In effect, when the board boots, U-Boot is *downstream* of the other project. +It is entirely reliant on that project for its correct operation. + +This does not mean to imply that the other project is creating its own, +incompatible devicetree. In fact QEMU generates a valid devicetree which is +suitable for both U-Boot and Linux. It is quite normal for a devicetree to be +present in flash and be made available to U-Boot at runtime. What matters is +where the devicetree comes from. If the other project builds a devicetree for +U-Boot then it needs to support adding the things needed by U-Boot features. +Without them, for example: + +- U-Boot may not boot because too many devices are enabled before relocation +- U-Boot may not have access to the developer or production public keys used for + signing +- U-Boot may not support controlling whether the console is enabled +- U-Boot may not be know which MMC device to boot from +- U-Boot may not be able to find other firmware components that it needs to load + +Normally, supporting U-Boot's features is trivial, since the devicetree compiler +(dtc) can compile the source, including any U-Boot pieces. So the burden is +extremely low. + +In this case, the devicetree in the other project must track U-Boot's use of +device tree, so that it remains compatible. See `Devicetree in another project`_ +for reasons why. + +If a particular version of the project is needed for a particular version of +U-Boot, that must be documented in both projects. + +Further, it must provide a way to add configuration and other information to +the devicetree for use by U-Boot, such as the `/config` node and the tags used +by driver model. Note that the U-Boot in-tree devicetree must be sufficient to +build and boot, so this is not a way to bypass that requirement. + +More specifically, tooling or command-line arguments must provide a way to +add a `/config` node or items within that node, so that U-Boot can receive a +suitable configuration. It must provide a way of adding `u-boot,dm-...` tags for +correct operation of driver model. These options can then be used as part of the +build process, which puts the firmware image together. For binman, a way must be +provided to add the binman definition into the devicetree in the same way. + +One way to do this is to allow a .dtsi file to be merged in with the generated +devicetree. + +Note that the burden goes both ways. If a new feature is added to U-Boot which +needs support in another project, then the author of the U-Boot patch must add +any required support to the other project. + + +Passing the devicetree through to Linux +--------------------------------------- + +Ideally U-Boot and Linux use the same devicetree source, even though it is +hosted in separate projects. U-Boot adds some extra pieces, such as the +`config/` node and tags like `u-boot,dm-spl`. Linux adds some extra pieces, such +as `linux,default-trigger` and `linux,code`. This should not interfere with +each other. + +In principle it is possible for U-Boot's control devicetree to be passed to +Linux. This is, after all, one of the goals of devicetree and the original +Open Firmware project, to have the firmware provide the hardware description to +the Operating System. + +For boards where this approach is used, care must be taken. U-Boot typically +needs to 'fix up' the devicetree before passing it to Linux, e.g. to add +information about the memory map, about which serial console is used, provide +the kernel address space layout randomization (KASLR) seed or select whether the +console should be silenced for a faster boot. + +Fix-ups involve modifying the devicetree. If the control devicetree is used, +that means the control devicetree could be modified, while U-Boot is using it. +Removing a device and reinserting it can cause problems if the devicetree offset +has changed, for example, since the device will be unable to locates its +devicetree properties at the expected devicetree offset, which is a fixed +integer. + +To deal with this, it is recommended to employ one or more of the following +approaches: + +- Make a copy of the devicetree and 'fix up' the copy, leaving the control + devicetree alone +- Enable `CONFIG_OF_LIVE` so that U-Boot makes its own copy of the devicetree + during relocation; fixups then happen on the original flat tree +- Ensure that fix-ups happen after all loading has happened and U-Boot has + completed image verification + +In practice,the last point is typically observed, since boot_prep_linux() is +called just before jumping to Linux, long after signature verification, for +example. But it is important to make sure that this line is not blurred, +particularly if untrusted user data is involved. + + +Devicetree use cases that must be supported +------------------------------------------- + +Regardless of how the devicetree is provided to U-Boot at runtime, various +U-Boot features must be fully supported. This section describes some of these +features and the implications for other projects. + +If U-Boot uses its own in-tree devicetree these features are supported +automatically. + + +Signing with U-Boot devicetree +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +U-Boot supports signing a payload so that it can be verified to have been +created by a party owning a private key. This is called verified boot in U-Boot +(see doc/uImage.FIT/verified-boot.txt). + +Typically this works by creating a FIT and then running the `mkimage` tool to +add signatures for particular images. As part of this process, `mkimage` writes +a public key to the U-Boot devicetree, although this can be done separately. +See fdt_add_pubkey_ for patches for a suitable tool, for example. + +As with all configuration information, if another project is providing the +devicetree to U-Boot, it must provide a way to add this public key into the +devicetree it passes to U-Boot. This could be via a tooling option, making use +of `mkimage`, or allowing a .dtsi file to be merged in with what is generated in +the other project. + + +Providing the binman image definition +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In complex systems U-Boot must locate and make use of other firmware components, +such as images for the user interface, files containing peripheral firmware, +multiple copies of U-Boot for use with A/B boot, etc. U-Boot uses +:doc:`Binman <../package/binman>` as a standard way of putting an image +together. + +Typically this works by running binman with the devicetree as an input, to +create the file image. Binman then outputs an updated devicetree which is +packed in the firmware image, so U-Boot can access the binman definition and +locate all the components. + +As with all configuration information, if another project is providing the +devicetree to U-Boot, it must provide a way to add this binman definition into +the devicetree it passes to U-Boot. This could be via a tooling option, making +use of `binman`, or alowing a .dtsi file to be merged in with what is generated +in the other project. + + +Protecting the devicetree +------------------------- + +U-Boot relies heavily on devicetree for correct operation. A corrupt or invalid +device can cause U-Boot to fail to start, behave incorrectly, crash (e.g. if +`CONFIG_OF_LIBFDT_ASSUME_MASK` is adjusted, or fail to boot an Operating System. +Within U-Boot, the devicetree is as important as any other part of the source +code. At ruuntime, the devicetree can be considered to be structured rodata. + +With secure systems, care must be taken that the devicetree is valid: + +- If the code / rodata has a hash or signature, the devicetree should also, if + they are packaged separately. +- If the code / rodata is write-protected when running, the devicetree should be + also. Note that U-Boot relocates its code and devicetree, so this is not as + simple as it sounds. U-Boot must write-protect these items after relocating. + + +Why does U-Boot have its nodes and properties? +---------------------------------------------- + +See also :doc:`../devicetree/intro`. + +There has been pushback at the concept that U-Boot dares have its own nodes and +properties in the devicetree. + +Apart from these nodes and properties, U-Boot uses the same bindings as Linux. +A `u-boot.dtsi` file helps to keep U-Boot-specific changes in separate files, +making it easier to keep devicetree source files in U-Boot in sync with Linux. + +As a counter-example, the Zephyr OS project takes a different approach. It uses +entirely different bindings, in general, making no effort to sync devicetree +source files with Linux. U-Boot strives to be compatible with Linux in a number +of ways, such as source code style and common APIs, to aid porting of code +between the projects. Devicetree is another way where U-Boot and Linux follow a +similar approach. + +Fundamentally, the idea that U-Boot cannot have its own tags flies in the face +of the devicetree specification (see dtspec_), which says: + + Nonstandard property names should specify a **unique string prefix**, such as + a stock ticker symbol, identifying the name of the company **or organization** + that defined the property. Examples: + + - fsl,channel-fifo-len + - ibm,ppc-interrupt-server#s + - **linux**,network-index + +It is also fundamentally unbalanced. Linux has many tags of its own (some 36 in +version 5.13) and at least one Linux-specific node, even if you ignore things +like flash partitions which clearly provide configuration information to Linux. + +Practically speaking there are many reasons why U-Boot has its own nodes and +properties. Some examples: + +- Binding every device before relocation even if it won't be used, consumes time + and memory: tags on each node can specify which are needed in SPL or before + relocation. Linux has no such constraints. + +- Requiring the full clock tree to be up and running just to get the debug UART + running is inefficient. It is also and self-defeating, since if that much + code is working properly, you probably don't need the debug UART. A devicetree + property to provide the UART input-clock frequency is a simple solution. + +- U-Boot does not have a user space to provide policy and configuration. It + cannot do what Linux does and run programs and look up filesystems to figure + out how to boot. + + +Why not have two devicetrees? +----------------------------- + +Setting aside the argument for restricting U-Boot from having its own nodes and +properties, another idea proposed is to have two devicetrees, one for the +U-Boot-specific bits (here called `special`) and one for everything else (here +called `linux`). This would mean that U-Boot would be controlled by two +devicetrees, i.e. OF_CONTROL would require/allow two devicetrees in order to +work. + +On the positive side, it might quieten the discussion alluded to in the section +above. But there are many negatives to consider and many open questions to +resolve. + +- **Bindings** - Presumably the special devicetree would have its own bindings. + It would not be necessary to put a `u-boot,` prefix on anything. People coming + across the devicetree source would wonder how it fits in with the Linux + devicetree. + +- **Access** - U-Boot has a nice `ofnode` API for accessing the devicetree. This + would need to be expanded to support two trees. Features which need to access + both (such as a device driver which reads the special devicetree to get some + configuration info) could become quite confusing to read and write. + +- **Merging** - Can the two devicetree be merged if a platform desires it? If + so, how is this managed in tooling? Does it happen during the build, in which + case they are not really separate at all. Or does U-Boot merge them at + runtime, in which case this adds time and memory? + +- **Efficiency** - A second device tree adds more code and more code paths. It + requires that both be made available to the code in U-Boot, e.g. via a + separate pointer or argument or API. Overall the separation would certainly + not speed up U-Boot, nor decrease its size. + +- **Source code** - At present `u-boot.dtsi` files provide the pieces needed for + U-Boot for a particular board. Would we use these same files for the special + devicetree? + +- **Complexity** - Two devicetrees complicates the build system since it must + build and package them both. Errors must be reported in such a way that it + is obvious which one is failing. + +- **Referencing each other** - The `u-boot,dm-xxx` tags used by driver model + are currently placed in the nodes they relate to. How would these tags + reference a node that is in a separate devicetree? What extra validation would + be needed? + +- **Storage** - How would the two devicetrees be stored in the image? At present + we simply concatenate the U-Boot binary and the devicetree. We could add the + special devicetree before the Linux one, so two are concatenated, but it is + not pretty. We could use binman to support more complex arrangements, but only + some boards use this at present, so it would be a big change. + +- **API** - How would another project provide two devicetree files to U-Boot at + runtime? Presumably this would just be too painful. But if it doesn't, it + would be unable to configure run-time features of U-Boot during the boot. + +- **Confusion** - No other project has two devicetrees used for controlling its + operation (although having multiple devicetrees to pass on to the OS is + common). U-Boot would be in the unfortunate position of having to describe + the purpose of the two control devicetrees fact to new users, along with the + (arguably contrived) reason for the arrangement. + +- **Signing flow** - The current signing flow is simple as it involves running + `mkimage` with the U-Boot devicetree. This would have to be updated to use the + special devicetree. Some way of telling the user that they have done it wrong + would have to be invented. + +Overall, adding a second devicetree would create enormous confusion and +complexity. It seems a lot cheaper to solve this by a change of attitude. + + +.. _rpi_patch: https://patchwork.ozlabs.org/project/uboot/patch/20170402082520.32546-1-deymo@google.com/ +.. _`TF-A`: https://www.trustedfirmware.org/projects/tf-a +.. _`QEMU ARM`: https://github.com/qemu/qemu/blob/master/hw/arm/virt.c +.. _`QEMU RISC-V`: https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c +.. _`/chosen node`: https://www.kernel.org/doc/Documentation/devicetree/bindings/chosen.txt +.. _fdt_add_pubkey: https://patchwork.ozlabs.org/project/uboot/list/?series=157843&state=* +.. _dtspec: https://www.devicetree.org/specifications/ diff --git a/doc/develop/devicetree/index.rst b/doc/develop/devicetree/index.rst index fa5db3eb76e..b5b33dfea0f 100644 --- a/doc/develop/devicetree/index.rst +++ b/doc/develop/devicetree/index.rst @@ -11,3 +11,4 @@ build-time and runtime configuration. intro control + dt_update From patchwork Tue Dec 7 00:11:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564411 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=b567GbGK; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LNW6dr3z9sCD for ; Tue, 7 Dec 2021 11:12:58 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 95E46830BB; Tue, 7 Dec 2021 01:12:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="b567GbGK"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D658083090; Tue, 7 Dec 2021 01:12:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 374EC83090 for ; Tue, 7 Dec 2021 01:12:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x32e.google.com with SMTP id n104-20020a9d2071000000b005799790cf0bso15869148ota.5 for ; Mon, 06 Dec 2021 16:12:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IBZ5+jwDs0WEkFP4WUuukvfsmEulflYVtmxnqKafLi4=; b=b567GbGKXNIVpClcLHFrcphze3XdQxfQqvuX3Q4SPZMQoPJWvV5bhGahg05p145FrE lM8wDjq55EEl/lh9ijy/cYp46cdZ6VCAXA490xPCkQm+WglFdnKCFtOk/DgZ8LYqjZ/5 EhkTNdeLEcJWkRJm7h7ixPZDq4gXy2mmRey9M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IBZ5+jwDs0WEkFP4WUuukvfsmEulflYVtmxnqKafLi4=; b=4Ij5kmdFf1MQj7ven4zzNRy2k404tAOZ62klqC8EcN4pJBu21Ot43slqGxv3QeXdDM s64Ibbka1tzfB8XFDbnAhhFBflLjMiK6Xj7KPX6bpA7K/bn6z/YtRI+0BgIDA3lQQGjy g+9w2YrB+NlaP9pyA/OdLtmdmbEX5IiJ/FZ9WCRpsm6zWdctHGXYLC0b5X7SUCpjpULc QJuqBdJdorJdU33z6EWPzkT97iM7FWAxPDvXFmfJcG7Ngg411ieZPqEFbsq9QyS1XzIT gaWNctVGu2iu0hsqP2AZGpNO36CGn+ie6x2Fe9fQ47ykGMq6Wg6xVqxz6fiIkloqGu8w X4Aw== X-Gm-Message-State: AOAM532zpYVMCW3NeqAxKqlLne24yh/A6K1uc/u/seXGiDQrqxrubZ0n FB9FlcWSckPvBBC7UD/Q9kkUbZoMSQN4Dw== X-Google-Smtp-Source: ABdhPJy0g3qCe9MbLnl/Gb7niHxeKanvU3m0iCCAdOU3oaF0xiQ4bCIvLNvdVYh8dUEqmXomvnXF1w== X-Received: by 2002:a9d:6854:: with SMTP id c20mr33120034oto.190.1638835964381; Mon, 06 Dec 2021 16:12:44 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:43 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud Subject: [PATCH v7 02/31] arm: qemu: Mention -nographic in the docs Date: Mon, 6 Dec 2021 17:11:40 -0700 Message-Id: <20211207001209.3467163-3-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Without this option QEMU appears to hang. Add it to avoid confusion. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- (no changes since v1) doc/board/emulation/qemu-arm.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 584ef0a7e15..8bd7b60cdb4 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -41,14 +41,15 @@ The minimal QEMU command line to get U-Boot up and running is: - For ARM:: - qemu-system-arm -machine virt -bios u-boot.bin + qemu-system-arm -machine virt -nographic -bios u-boot.bin - For AArch64:: - qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin + qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 -bios u-boot.bin Note that for some odd reason qemu-system-aarch64 needs to be explicitly -told to use a 64-bit CPU or it will boot in 32-bit mode. +told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument +ensures that output appears on the terminal. Use Ctrl-A X to quit. Additional persistent U-boot environment support can be added as follows: From patchwork Tue Dec 7 00:11:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564416 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=mOFWN2Z0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LPN6NMgz9sCD for ; Tue, 7 Dec 2021 11:13:44 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CD0F2830CE; Tue, 7 Dec 2021 01:13:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="mOFWN2Z0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A8469830CB; Tue, 7 Dec 2021 01:12:59 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7C716830A1 for ; Tue, 7 Dec 2021 01:12:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x32c.google.com with SMTP id x3-20020a05683000c300b0057a5318c517so15771567oto.13 for ; Mon, 06 Dec 2021 16:12:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=faeE37utE+jmk8F12ZyHzkyxCpJ89LFtQUBS6cCjquo=; b=mOFWN2Z0ZZrooOEyA9JCfj8RNNAjvjOhq65NbjA8ZSg0yMazA+sbgjeLIbW6sVbXok IZEOX9Oamy0BdiKBu8YL07wgLdceCNm9s0icWve8Jn1yBeOcdRcZYFDk0KzbR0Up+75T Wqcu8qZcWao1dKdjXY9ovBe3A2R3lKFol3mtw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=faeE37utE+jmk8F12ZyHzkyxCpJ89LFtQUBS6cCjquo=; b=S9/lS4Jx6UNUdGGfU//8+2rNyVXv8vTrXka6rt9lS7g5ot6lb/QCTCr8uiKrx5+GsS kkGu33gP/EVkA9f31Z/5lpTAHNMgDIotGDlwUEqEEJk4r42uhykeW1Vqdw3Al3JSqboy Y6Zc6w21yJKPs65Wa7AlQ/Qqovhe7FURSKzj+EzP4Ava+VF/bAePxLrFNz4GsiABB8QD mo1zkdJMHhwjZunXrwmEq72Lf8gSVyzbJvNEJYtgfehdjJ2SxawRv5pyc8eQksCwGAd+ ARUCuV+CNurPWQ6UEFzwdtvU76HG9KApRNz47tWrq9kBxTVY/hdEGtZB3P8dTe545/xp xuqA== X-Gm-Message-State: AOAM531LJ1oBUIznIfnhQj+UmZo0nK5ugIC1d3mdvER3be9YT1WwR2k+ 5DD8VrVlSCvd4DaNkKVRZXmEsoRFikyWuw== X-Google-Smtp-Source: ABdhPJxShMEZK+vVuXqitHpBW/XslLoeS3TrUNk/PK9YHW5Vs5W/lwfZWDsr06cffXpX1ReF1Q4zCQ== X-Received: by 2002:a05:6830:1da:: with SMTP id r26mr32221728ota.73.1638835965603; Mon, 06 Dec 2021 16:12:45 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:45 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud Subject: [PATCH v7 03/31] arm: riscv: qemu: Explain how to extract the generated dt Date: Mon, 6 Dec 2021 17:11:41 -0700 Message-Id: <20211207001209.3467163-4-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean QEMU currently generates a devicetree for use with U-Boot. Explain how to obtain it. Also explain how to merge it to produce a devicetree with the U-Boot features included. Signed-off-by: Simon Glass --- (no changes since v5) Changes in v5: - Merge RISC-V and ARM patches since they are similar doc/board/emulation/qemu-arm.rst | 3 ++ doc/board/emulation/qemu-riscv.rst | 3 ++ doc/develop/devicetree/dt_qemu.rst | 48 ++++++++++++++++++++++++++++++ doc/develop/devicetree/index.rst | 1 + 4 files changed, 55 insertions(+) create mode 100644 doc/develop/devicetree/dt_qemu.rst diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 8bd7b60cdb4..ff64ec08c3e 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -21,6 +21,9 @@ The 'virt' platform provides the following as the basic functionality: Additionally, a number of optional peripherals can be added to the PCI bus. +See :doc:`../../develop/devicetree/dt_qemu` for information on how to see +the devicetree actually generated by QEMU. + Building U-Boot --------------- Set the CROSS_COMPILE environment variable as usual, and run: diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index 4b8e104a215..3409fff8117 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -13,6 +13,9 @@ The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged + +See :doc:`../../develop/devicetree/dt_qemu` for information on how to see +the devicetree actually generated by QEMU. architecture spec v1.10. Building U-Boot diff --git a/doc/develop/devicetree/dt_qemu.rst b/doc/develop/devicetree/dt_qemu.rst new file mode 100644 index 00000000000..1392a2cae97 --- /dev/null +++ b/doc/develop/devicetree/dt_qemu.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Devicetree in QEMU +================== + +For QEMU on ARM, RISC-V and one PPC target, the devicetree is created on the +fly by QEMU. It is intended for use in Linux but can be used by U-Boot also, +so long as any nodes/properties needed by U-Boot are merged in. + +When `CONFIG_OF_BOARD` is enabled + + +Obtaining the QEMU devicetree +----------------------------- + +Where QEMU generates its own devicetree to pass to U-Boot tou can use +`-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version. + +To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`, +e.g.:: + + qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb + + qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb + + qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb + + +Merging in U-Boot nodes/properties +---------------------------------- + +Various U-Boot features require nodes and properties in the U-Boot devicetree +and at present QEMU is unaware of these. To use these you must manually merge +in the appropriate pieces. + +One way to do this is with dtc. This command runs dtc on each .dtb file in turn, +to produce a text file. It drops the duplicate header on the qemu one. Then it +joins them up and runs them through dtc to compile the output:: + + qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb + cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb u-boot.dtb |grep -v /dts-v1/) |dtc - -o merged.dtb + +You can then run qemu with the merged devicetree, e.g.:: + + qemu-system-arm -machine virt -nographic -bios u-boot.bin -dtb merged.dtb + +Note that there seems to be a bug in some versions of qemu where the output of +dumpdtb does not quite match what is provided to U-Boot. diff --git a/doc/develop/devicetree/index.rst b/doc/develop/devicetree/index.rst index b5b33dfea0f..fc2fb41b1bb 100644 --- a/doc/develop/devicetree/index.rst +++ b/doc/develop/devicetree/index.rst @@ -12,3 +12,4 @@ build-time and runtime configuration. intro control dt_update + dt_qemu From patchwork Tue Dec 7 00:11:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564417 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=jAx1w8qF; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LPn1BTXz9sCD for ; Tue, 7 Dec 2021 11:14:05 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C9204830C5; Tue, 7 Dec 2021 01:13:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="jAx1w8qF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 391CE830C5; Tue, 7 Dec 2021 01:12:59 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 94CAD830A8 for ; Tue, 7 Dec 2021 01:12:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-oi1-x234.google.com with SMTP id bk14so24550954oib.7 for ; Mon, 06 Dec 2021 16:12:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wwr+Ewj4Z2VAY0luQAeawL4iEaEq4PzVqU5h/uQlyiw=; b=jAx1w8qF57YPKFf76VL3udGax9OtKwG5i0324Ekjn38b5P6ARbH74hC0K3BCmscs1L Z58f7lVUkDgN8AEXq2uYXbB9r2j7k0KgIyJNa5b28UcDQS7O+rgpaDK9/44dUovjCW++ GHYksCpjjCQjU03GsXyxeWAOoXJhB1+whla5A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wwr+Ewj4Z2VAY0luQAeawL4iEaEq4PzVqU5h/uQlyiw=; b=cloGjoGoCqrDfoekrX+M09uB2rl4sRuPIYJ1a99NCeNI5hB4x8DwhAUKL9j4SBCotk cWxxUlDvsGW8kuz6n1bjESb4ksero7imdeuj/zHt+7W+lhKEYxGF8F8GdjcdN49/M09H CeACcM+RDi4d5di+U0C7wFpUq/6gEST4Xnr5E/kmyLI5H0rL8atNTfMBxs72EnGwET0k z5+UcI4CM7ucSvea7u5v24eeuVss/chKJi83+97hRpy1HbpoCid4tdjgVtoLZx1qyXTo 63w8/OFpQJsjKEcqNdKgS+dHBZsNOfDathRVvM45sfy5i/SJ7s7fdew/DFKb0SyatR7r ZsxQ== X-Gm-Message-State: AOAM530VOpSFhpJMggBOA3dHrBvvWoYGPl83zyqqknloXtZ5kBOo6Nej 5q99Y7d1VHD3DC4Hh38KXmGQwwF3vDiQiA== X-Google-Smtp-Source: ABdhPJzCfdgTKm39BsOyF7qQHgcRYYsWtK4ZQ4eYD55i6rMbzrZXY0D4/bmf1LTNod7WIm0Y6V7NnA== X-Received: by 2002:a05:6808:23c3:: with SMTP id bq3mr2075358oib.124.1638835966928; Mon, 06 Dec 2021 16:12:46 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:46 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Heinrich Schuchardt , Albert Aribaud , Tuomas Tynkkynen Subject: [PATCH v7 04/31] arm: qemu: Add a devicetree file for qemu_arm Date: Mon, 6 Dec 2021 17:11:42 -0700 Message-Id: <20211207001209.3467163-5-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This uses QEMU virt which creates its own devicetree. Add an empty version of this file, so that we can at least build this board when devicetrees are required. Tested-by: Heinrich Schuchardt Signed-off-by: Simon Glass --- Changes in v7: - Switch to using an empty file for qemu virt Changes in v6: - Expand the commit message based on comments arch/arm/dts/Makefile | 2 ++ arch/arm/dts/qemu-arm.dts | 11 +++++++++++ configs/qemu_arm_defconfig | 1 + 3 files changed, 14 insertions(+) create mode 100644 arch/arm/dts/qemu-arm.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7f622fedbda..eaad3b679cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1162,6 +1162,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb +dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/qemu-arm.dts b/arch/arm/dts/qemu-arm.dts new file mode 100644 index 00000000000..230c630f04f --- /dev/null +++ b/arch/arm/dts/qemu-arm.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for qemu_arm + + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index d4f6d0b4373..a644a5f3e79 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-arm" CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_DEBUG_UART_BASE=0x9000000 CONFIG_DEBUG_UART_CLOCK=0 From patchwork Tue Dec 7 00:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564415 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=fQF1Z5LA; dkim-atps=neutral Authentication-Results: ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:47 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Heinrich Schuchardt , Albert Aribaud , Tuomas Tynkkynen Subject: [PATCH v7 05/31] arm: qemu: Add a devicetree file for qemu_arm64 virt Date: Mon, 6 Dec 2021 17:11:43 -0700 Message-Id: <20211207001209.3467163-6-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This uses QEMU virt which creates its own devicetree. Add an empty version of this file, so that we can at least build this board when devicetrees are required. Tested-by: Heinrich Schuchardt Signed-off-by: Simon Glass --- Changes in v7: - Switch to using an empty file for qemu virt Changes in v6: - Expand the commit message based on comments arch/arm/dts/Makefile | 2 +- arch/arm/dts/qemu-arm64.dts | 11 +++++++++++ configs/qemu_arm64_defconfig | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/qemu-arm64.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eaad3b679cc..2d92b2f940d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1162,7 +1162,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb -dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb +dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/qemu-arm64.dts b/arch/arm/dts/qemu-arm64.dts new file mode 100644 index 00000000000..096b3910728 --- /dev/null +++ b/arch/arm/dts/qemu-arm64.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for qemu_arm64 + + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 02a5e940c41..a8652f871ca 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEBUG_UART_BASE=0x9000000 CONFIG_DEBUG_UART_CLOCK=0 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x40200000 From patchwork Tue Dec 7 00:11:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564414 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=SZCeZoz5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:48 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Heinrich Schuchardt , Bin Meng Subject: [PATCH v7 06/31] riscv: qemu: Split devicetree files for qemu_riscv32/64 Date: Mon, 6 Dec 2021 17:11:44 -0700 Message-Id: <20211207001209.3467163-7-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This uses QEMU virt which creates its own devicetree. Copy the existing empty version of this file, so splitting the existing qemu-virt into two, since anyone actually trying to use this will need a different devicetree for 32- and 64-bit machines. Tested-by: Heinrich Schuchardt Signed-off-by: Simon Glass --- Changes in v7: - Switch to using an empty file for qemu virt - Reword commit message arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/{qemu-virt.dts => qemu-virt32.dts} | 3 +++ arch/riscv/dts/qemu-virt64.dts | 11 +++++++++++ configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 2 +- configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 2 +- 9 files changed, 21 insertions(+), 3 deletions(-) rename arch/riscv/dts/{qemu-virt.dts => qemu-virt32.dts} (94%) create mode 100644 arch/riscv/dts/qemu-virt64.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index b6e9166767b..90d3f35e6e3 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,7 +2,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb -dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt32.dts similarity index 94% rename from arch/riscv/dts/qemu-virt.dts rename to arch/riscv/dts/qemu-virt32.dts index fecff542b91..17e2f0dea41 100644 --- a/arch/riscv/dts/qemu-virt.dts +++ b/arch/riscv/dts/qemu-virt32.dts @@ -6,3 +6,6 @@ /dts-v1/; #include "binman.dtsi" + +/ { +}; diff --git a/arch/riscv/dts/qemu-virt64.dts b/arch/riscv/dts/qemu-virt64.dts new file mode 100644 index 00000000000..17e2f0dea41 --- /dev/null +++ b/arch/riscv/dts/qemu-virt64.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng + */ + +/dts-v1/; + +#include "binman.dtsi" + +/ { +}; diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 0b8cd191618..4c0f51bd2aa 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_TARGET_QEMU_VIRT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x80200000 diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 4d65104f7b4..19406080100 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index eb64c51a214..c4422969c61 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -2,7 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 4faa6dad8d6..cba975d703d 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index f575c127b7c..6b7771488fe 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 0fbdb7564c6..e02ca3a1465 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -2,7 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y From patchwork Tue Dec 7 00:11:45 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:50 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Matthias Brugger , Stephen Warren , Stephen Warren Subject: [PATCH v7 07/31] arm: rpi: Sync rpi dts files from Linux Date: Mon, 6 Dec 2021 17:11:45 -0700 Message-Id: <20211207001209.3467163-8-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Sync these files, obtained from Linux v5.15. This adds a devicetree file for rpi_4 which was not there before. Testing shows no change so far as I can see: - boots to U-Boot prompt on rpi0, rpi2 - boots to distro on rpi3 - boots to distro on rpi4 I am assuming that syncing with Linux is safe, but the maintainer should know for sure. Signed-off-by: Simon Glass --- Changes in v7: - Bring in files from Linux instead arch/arm/dts/Makefile | 3 +- arch/arm/dts/bcm2711-rpi-4-b.dts | 262 +++++ arch/arm/dts/bcm2711-rpi.dtsi | 74 ++ arch/arm/dts/bcm2711.dtsi | 1100 ++++++++++++++++++ arch/arm/dts/bcm2835-common.dtsi | 207 ++++ arch/arm/dts/bcm2835-rpi-a-plus.dts | 18 +- arch/arm/dts/bcm2835-rpi-a.dts | 16 +- arch/arm/dts/bcm2835-rpi-b-plus.dts | 18 +- arch/arm/dts/bcm2835-rpi-b-rev2.dts | 16 +- arch/arm/dts/bcm2835-rpi-b.dts | 16 +- arch/arm/dts/bcm2835-rpi-cm1-io1.dts | 9 + arch/arm/dts/bcm2835-rpi-cm1.dtsi | 7 +- arch/arm/dts/bcm2835-rpi-common.dtsi | 12 + arch/arm/dts/bcm2835-rpi-zero-w.dts | 20 +- arch/arm/dts/bcm2835-rpi-zero.dts | 16 +- arch/arm/dts/bcm2835-rpi.dtsi | 35 +- arch/arm/dts/bcm2835.dtsi | 2 + arch/arm/dts/bcm2836-rpi-2-b.dts | 14 +- arch/arm/dts/bcm2836.dtsi | 2 + arch/arm/dts/bcm2837-rpi-3-a-plus.dts | 9 +- arch/arm/dts/bcm2837-rpi-3-b-plus.dts | 9 +- arch/arm/dts/bcm2837-rpi-3-b.dts | 5 +- arch/arm/dts/bcm2837-rpi-cm3-io3.dts | 9 + arch/arm/dts/bcm2837-rpi-cm3.dtsi | 9 + arch/arm/dts/bcm2837.dtsi | 2 + arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi | 7 + arch/arm/dts/bcm283x.dtsi | 224 +--- configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + include/dt-bindings/clock/bcm2835.h | 2 + 31 files changed, 1878 insertions(+), 248 deletions(-) create mode 100644 arch/arm/dts/bcm2711-rpi-4-b.dts create mode 100644 arch/arm/dts/bcm2711-rpi.dtsi create mode 100644 arch/arm/dts/bcm2711.dtsi create mode 100644 arch/arm/dts/bcm2835-common.dtsi create mode 100644 arch/arm/dts/bcm2835-rpi-common.dtsi create mode 100644 arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2d92b2f940d..9cddab37207 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1077,7 +1077,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb + bcm2837-rpi-cm3-io3.dtb \ + bcm2711-rpi-4-b.dtb dtb-$(CONFIG_ARCH_BCM63158) += \ bcm963158.dtb diff --git a/arch/arm/dts/bcm2711-rpi-4-b.dts b/arch/arm/dts/bcm2711-rpi-4-b.dts new file mode 100644 index 00000000000..72ce80fbf26 --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi-4-b.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711.dtsi" +#include "bcm2711-rpi.dtsi" +#include "bcm283x-rpi-usb-peripheral.dtsi" + +/ { + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; + model = "Raspberry Pi 4 Model B"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + led-act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; + }; + + sd_io_1v8_reg: sd_io_1v8_reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + status = "okay"; + }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + ""; +}; + +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; + status = "okay"; +}; + +/* SDHCI is used to control the SDIO for wireless */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* EMMC2 is used to drive the SD card */ +&emmc2 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + broken-cd; + status = "okay"; +}; + +&genet { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&genet_mdio { + phy1: ethernet-phy@1 { + /* No PHY interrupt */ + reg = <0x1>; + }; +}; + +&pcie0 { + pci@0,0 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reg = <0 0 0 0 0>; + + usb@0,0 { + reg = <0 0 0 0 0>; + resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; + }; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi new file mode 100644 index 00000000000..ca266c5d9f9 --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +#include + +/ { + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0>; + }; + + aliases { + emmc2bus = &emmc2bus; + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; + }; +}; + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&vchiq { + interrupts = ; +}; diff --git a/arch/arm/dts/bcm2711.dtsi b/arch/arm/dts/bcm2711.dtsi new file mode 100644 index 00000000000..3b60297af7f --- /dev/null +++ b/arch/arm/dts/bcm2711.dtsi @@ -0,0 +1,1100 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm283x.dtsi" + +#include +#include + +/ { + compatible = "brcm,bcm2711"; + + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gicv2>; + + vc4: gpu { + compatible = "brcm,bcm2711-vc5"; + status = "disabled"; + }; + + clk_27MHz: clk-27M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "27MHz-clock"; + }; + + clk_108MHz: clk-108M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <108000000>; + clock-output-names = "108MHz-clock"; + }; + + soc { + /* + * Defined ranges: + * Common BCM283x peripherals + * BCM2711-specific peripherals + * ARM-local peripherals + */ + ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, + <0x7c000000 0x0 0xfc000000 0x02000000>, + <0x40000000 0x0 0xff800000 0x00800000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; + + /* + * This node is the provider for the enable-method for + * bringing up secondary cores. + */ + local_intc: local_intc@40000000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + }; + + gicv2: interrupt-controller@40041000 { + interrupt-controller; + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + reg = <0x40041000 0x1000>, + <0x40042000 0x2000>, + <0x40044000 0x2000>, + <0x40046000 0x2000>; + interrupts = ; + }; + + avs_monitor: avs-monitor@7d5d2000 { + compatible = "brcm,bcm2711-avs-monitor", + "syscon", "simple-mfd"; + reg = <0x7d5d2000 0xf00>; + + thermal: thermal { + compatible = "brcm,bcm2711-thermal"; + #thermal-sensor-cells = <0>; + }; + }; + + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xb00>; + interrupts = , + , + , + , + , + , + , + /* DMA lite 7 - 10 */ + , + , + , + ; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x07f5>; + }; + + pm: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>, + <0x7ec11000 0x20>; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; + + rng@7e104000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7e104000 0x28>; + }; + + uart2: serial@7e201400 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201400 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart3: serial@7e201600 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201600 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart4: serial@7e201800 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201800 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart5: serial@7e201a00 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201a00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + spi3: spi@7e204600 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204600 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@7e204800 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204800 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@7e204a00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204a00 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@7e204c00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204c00 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@7e205600 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205600 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@7e205800 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205800 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@7e205a00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205a00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@7e205c00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205c00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pixelvalve0: pixelvalve@7e206000 { + compatible = "brcm,bcm2711-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7e207000 { + compatible = "brcm,bcm2711-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve2: pixelvalve@7e20a000 { + compatible = "brcm,bcm2711-pixelvalve2"; + reg = <0x7e20a000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pwm1: pwm@7e20c800 { + compatible = "brcm,bcm2835-pwm"; + reg = <0x7e20c800 0x28>; + clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clock-rates = <10000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pixelvalve4: pixelvalve@7e216000 { + compatible = "brcm,bcm2711-pixelvalve4"; + reg = <0x7e216000 0x100>; + interrupts = ; + status = "disabled"; + }; + + hvs: hvs@7e400000 { + compatible = "brcm,bcm2711-hvs"; + interrupts = ; + }; + + pixelvalve3: pixelvalve@7ec12000 { + compatible = "brcm,bcm2711-pixelvalve3"; + reg = <0x7ec12000 0x100>; + interrupts = ; + status = "disabled"; + }; + + vec: vec@7ec13000 { + compatible = "brcm,bcm2711-vec"; + reg = <0x7ec13000 0x1000>; + clocks = <&clocks BCM2835_CLOCK_VEC>; + interrupts = ; + status = "disabled"; + }; + + dvp: clock@7ef00000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7ef00000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aon_intr: interrupt-controller@7ef00100 { + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg = <0x7ef00100 0x30>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + hdmi0: hdmi@7ef00700 { + compatible = "brcm,bcm2711-hdmi0"; + reg = <0x7ef00700 0x300>, + <0x7ef00300 0x200>, + <0x7ef00f00 0x80>, + <0x7ef00f80 0x80>, + <0x7ef01b00 0x200>, + <0x7ef01f00 0x400>, + <0x7ef00200 0x80>, + <0x7ef04300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 0>; + interrupt-parent = <&aon_intr>; + interrupts = <0>, <1>, <2>, + <3>, <4>, <5>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "wakeup", "hpd-connected", "hpd-removed"; + ddc = <&ddc0>; + dmas = <&dma 10>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc0: i2c@7ef04500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + + hdmi1: hdmi@7ef05700 { + compatible = "brcm,bcm2711-hdmi1"; + reg = <0x7ef05700 0x300>, + <0x7ef05300 0x200>, + <0x7ef05f00 0x80>, + <0x7ef05f80 0x80>, + <0x7ef06b00 0x200>, + <0x7ef06f00 0x400>, + <0x7ef00280 0x80>, + <0x7ef09300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + ddc = <&ddc1>; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 1>; + interrupt-parent = <&aon_intr>; + interrupts = <8>, <7>, <6>, + <9>, <10>, <11>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "wakeup", "hpd-connected", "hpd-removed"; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc1: i2c@7ef09500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + }; + + /* + * emmc2 has different DMA constraints based on SoC revisions. It was + * moved into its own bus, so as for RPi4's firmware to update them. + * The firmware will find whether the emmc2bus alias is defined, and if + * so, it'll edit the dma-ranges property below accordingly. + */ + emmc2bus: emmc2bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; + dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; + + emmc2: mmc@7e340000 { + compatible = "brcm,bcm2711-emmc2"; + reg = <0x0 0x7e340000 0x100>; + interrupts = ; + clocks = <&clocks BCM2711_CLOCK_EMMC2>; + status = "disabled"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + /* This only applies to the ARMv7 stub */ + arm,cpu-registers-not-fw-configured; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000d8>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e8>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000f0>; + }; + }; + + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH>; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0xc0000000>; + brcm,enable-ssc; + }; + + genet: ethernet@7d580000 { + compatible = "brcm,bcm2711-genet-v5"; + reg = <0x0 0x7d580000 0x10000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + interrupts = , + ; + status = "disabled"; + + genet_mdio: mdio@e14 { + compatible = "brcm,genet-mdio-v5"; + reg = <0xe14 0x8>; + reg-names = "mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + }; +}; + +&clk_osc { + clock-frequency = <54000000>; +}; + +&clocks { + compatible = "brcm,bcm2711-cprman"; +}; + +&cpu_thermal { + coefficients = <(-487) 410040>; + thermal-sensors = <&thermal>; +}; + +&dsi0 { + interrupts = ; +}; + +&dsi1 { + interrupts = ; + compatible = "brcm,bcm2711-dsi1"; +}; + +&gpio { + compatible = "brcm,bcm2711-gpio"; + interrupts = , + , + , + ; + + gpclk0_gpio49: gpclk0_gpio49 { + pin-gpclk { + pins = "gpio49"; + function = "alt1"; + bias-disable; + }; + }; + gpclk1_gpio50: gpclk1_gpio50 { + pin-gpclk { + pins = "gpio50"; + function = "alt1"; + bias-disable; + }; + }; + gpclk2_gpio51: gpclk2_gpio51 { + pin-gpclk { + pins = "gpio51"; + function = "alt1"; + bias-disable; + }; + }; + + i2c0_gpio46: i2c0_gpio46 { + pin-sda { + function = "alt0"; + pins = "gpio46"; + bias-pull-up; + }; + pin-scl { + function = "alt0"; + pins = "gpio47"; + bias-disable; + }; + }; + i2c1_gpio46: i2c1_gpio46 { + pin-sda { + function = "alt1"; + pins = "gpio46"; + bias-pull-up; + }; + pin-scl { + function = "alt1"; + pins = "gpio47"; + bias-disable; + }; + }; + i2c3_gpio2: i2c3_gpio2 { + pin-sda { + function = "alt5"; + pins = "gpio2"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio3"; + bias-disable; + }; + }; + i2c3_gpio4: i2c3_gpio4 { + pin-sda { + function = "alt5"; + pins = "gpio4"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio5"; + bias-disable; + }; + }; + i2c4_gpio6: i2c4_gpio6 { + pin-sda { + function = "alt5"; + pins = "gpio6"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio7"; + bias-disable; + }; + }; + i2c4_gpio8: i2c4_gpio8 { + pin-sda { + function = "alt5"; + pins = "gpio8"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio9"; + bias-disable; + }; + }; + i2c5_gpio10: i2c5_gpio10 { + pin-sda { + function = "alt5"; + pins = "gpio10"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio11"; + bias-disable; + }; + }; + i2c5_gpio12: i2c5_gpio12 { + pin-sda { + function = "alt5"; + pins = "gpio12"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio13"; + bias-disable; + }; + }; + i2c6_gpio0: i2c6_gpio0 { + pin-sda { + function = "alt5"; + pins = "gpio0"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio1"; + bias-disable; + }; + }; + i2c6_gpio22: i2c6_gpio22 { + pin-sda { + function = "alt5"; + pins = "gpio22"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio23"; + bias-disable; + }; + }; + i2c_slave_gpio8: i2c_slave_gpio8 { + pins-i2c-slave { + pins = "gpio8", + "gpio9", + "gpio10", + "gpio11"; + function = "alt3"; + }; + }; + + jtag_gpio48: jtag_gpio48 { + pins-jtag { + pins = "gpio48", + "gpio49", + "gpio50", + "gpio51", + "gpio52", + "gpio53"; + function = "alt4"; + }; + }; + + mii_gpio28: mii_gpio28 { + pins-mii { + pins = "gpio28", + "gpio29", + "gpio30", + "gpio31"; + function = "alt4"; + }; + }; + mii_gpio36: mii_gpio36 { + pins-mii { + pins = "gpio36", + "gpio37", + "gpio38", + "gpio39"; + function = "alt5"; + }; + }; + + pcm_gpio50: pcm_gpio50 { + pins-pcm { + pins = "gpio50", + "gpio51", + "gpio52", + "gpio53"; + function = "alt2"; + }; + }; + + pwm0_0_gpio12: pwm0_0_gpio12 { + pin-pwm { + pins = "gpio12"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_0_gpio18: pwm0_0_gpio18 { + pin-pwm { + pins = "gpio18"; + function = "alt5"; + bias-disable; + }; + }; + pwm1_0_gpio40: pwm1_0_gpio40 { + pin-pwm { + pins = "gpio40"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio13: pwm0_1_gpio13 { + pin-pwm { + pins = "gpio13"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio19: pwm0_1_gpio19 { + pin-pwm { + pins = "gpio19"; + function = "alt5"; + bias-disable; + }; + }; + pwm1_1_gpio41: pwm1_1_gpio41 { + pin-pwm { + pins = "gpio41"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio45: pwm0_1_gpio45 { + pin-pwm { + pins = "gpio45"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_0_gpio52: pwm0_0_gpio52 { + pin-pwm { + pins = "gpio52"; + function = "alt1"; + bias-disable; + }; + }; + pwm0_1_gpio53: pwm0_1_gpio53 { + pin-pwm { + pins = "gpio53"; + function = "alt1"; + bias-disable; + }; + }; + + rgmii_gpio35: rgmii_gpio35 { + pin-start-stop { + pins = "gpio35"; + function = "alt4"; + }; + pin-rx-ok { + pins = "gpio36"; + function = "alt4"; + }; + }; + rgmii_irq_gpio34: rgmii_irq_gpio34 { + pin-irq { + pins = "gpio34"; + function = "alt5"; + }; + }; + rgmii_irq_gpio39: rgmii_irq_gpio39 { + pin-irq { + pins = "gpio39"; + function = "alt4"; + }; + }; + rgmii_mdio_gpio28: rgmii_mdio_gpio28 { + pins-mdio { + pins = "gpio28", + "gpio29"; + function = "alt5"; + }; + }; + rgmii_mdio_gpio37: rgmii_mdio_gpio37 { + pins-mdio { + pins = "gpio37", + "gpio38"; + function = "alt4"; + }; + }; + + spi0_gpio46: spi0_gpio46 { + pins-spi { + pins = "gpio46", + "gpio47", + "gpio48", + "gpio49"; + function = "alt2"; + }; + }; + spi2_gpio46: spi2_gpio46 { + pins-spi { + pins = "gpio46", + "gpio47", + "gpio48", + "gpio49", + "gpio50"; + function = "alt5"; + }; + }; + spi3_gpio0: spi3_gpio0 { + pins-spi { + pins = "gpio0", + "gpio1", + "gpio2", + "gpio3"; + function = "alt3"; + }; + }; + spi4_gpio4: spi4_gpio4 { + pins-spi { + pins = "gpio4", + "gpio5", + "gpio6", + "gpio7"; + function = "alt3"; + }; + }; + spi5_gpio12: spi5_gpio12 { + pins-spi { + pins = "gpio12", + "gpio13", + "gpio14", + "gpio15"; + function = "alt3"; + }; + }; + spi6_gpio18: spi6_gpio18 { + pins-spi { + pins = "gpio18", + "gpio19", + "gpio20", + "gpio21"; + function = "alt3"; + }; + }; + + uart2_gpio0: uart2_gpio0 { + pin-tx { + pins = "gpio0"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio1"; + function = "alt4"; + bias-pull-up; + }; + }; + uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { + pin-cts { + pins = "gpio2"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio3"; + function = "alt4"; + bias-disable; + }; + }; + uart3_gpio4: uart3_gpio4 { + pin-tx { + pins = "gpio4"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio5"; + function = "alt4"; + bias-pull-up; + }; + }; + uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { + pin-cts { + pins = "gpio6"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio7"; + function = "alt4"; + bias-disable; + }; + }; + uart4_gpio8: uart4_gpio8 { + pin-tx { + pins = "gpio8"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio9"; + function = "alt4"; + bias-pull-up; + }; + }; + uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { + pin-cts { + pins = "gpio10"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio11"; + function = "alt4"; + bias-disable; + }; + }; + uart5_gpio12: uart5_gpio12 { + pin-tx { + pins = "gpio12"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio13"; + function = "alt4"; + bias-pull-up; + }; + }; + uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { + pin-cts { + pins = "gpio14"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio15"; + function = "alt4"; + bias-disable; + }; + }; +}; + +&rmem { + #address-cells = <2>; +}; + +&cma { + /* + * arm64 reserves the CMA by default somewhere in ZONE_DMA32, + * that's not good enough for the BCM2711 as some devices can + * only address the lower 1G of memory (ZONE_DMA). + */ + alloc-ranges = <0x0 0x00000000 0x40000000>; +}; + +&i2c0 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + interrupts = ; +}; + +&i2c1 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + interrupts = ; +}; + +&mailbox { + interrupts = ; +}; + +&sdhci { + interrupts = ; +}; + +&sdhost { + interrupts = ; +}; + +&spi { + interrupts = ; +}; + +&spi1 { + interrupts = ; +}; + +&spi2 { + interrupts = ; +}; + +&system_timer { + interrupts = , + , + , + ; +}; + +&txp { + interrupts = ; +}; + +&uart0 { + interrupts = ; +}; + +&uart1 { + interrupts = ; +}; + +&usb { + interrupts = ; +}; + +&vec { + compatible = "brcm,bcm2711-vec"; + interrupts = ; +}; diff --git a/arch/arm/dts/bcm2835-common.dtsi b/arch/arm/dts/bcm2835-common.dtsi new file mode 100644 index 00000000000..c25e797b906 --- /dev/null +++ b/arch/arm/dts/bcm2835-common.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations. + */ + +/ { + interrupt-parent = <&intc>; + + soc { + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16>, + <1 17>, + <1 18>, + <1 19>, + <1 20>, + <1 21>, + <1 22>, + <1 23>, + <1 24>, + <1 25>, + <1 26>, + /* dma channel 11-14 share one irq */ + <1 27>, + <1 27>, + <1 27>, + <1 27>, + /* unused shared irq for all channels */ + <1 28>; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10", + "dma11", + "dma12", + "dma13", + "dma14", + "dma-shared-all"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7f35>; + }; + + intc: interrupt-controller@7e00b200 { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; + + rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; + }; + + pixelvalve@7e206000 { + compatible = "brcm,bcm2835-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = <2 13>; /* pwa0 */ + }; + + pixelvalve@7e207000 { + compatible = "brcm,bcm2835-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = <2 14>; /* pwa1 */ + }; + + thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@7e805000 { + compatible = "brcm,bcm2835-i2c"; + reg = <0x7e805000 0x1000>; + interrupts = <2 21>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + vec: vec@7e806000 { + compatible = "brcm,bcm2835-vec"; + reg = <0x7e806000 0x1000>; + clocks = <&clocks BCM2835_CLOCK_VEC>; + interrupts = <2 27>; + status = "disabled"; + }; + + pixelvalve@7e807000 { + compatible = "brcm,bcm2835-pixelvalve2"; + reg = <0x7e807000 0x100>; + interrupts = <2 10>; /* pixelvalve */ + }; + + hdmi: hdmi@7e902000 { + compatible = "brcm,bcm2835-hdmi"; + reg = <0x7e902000 0x600>, + <0x7e808000 0x100>; + interrupts = <2 8>, <2 9>; + ddc = <&i2c2>; + clocks = <&clocks BCM2835_PLLH_PIX>, + <&clocks BCM2835_CLOCK_HSM>; + clock-names = "pixel", "hdmi"; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + v3d: v3d@7ec00000 { + compatible = "brcm,bcm2835-v3d"; + reg = <0x7ec00000 0x1000>; + interrupts = <1 10>; + }; + + vc4: gpu { + compatible = "brcm,bcm2835-vc4"; + }; + }; +}; + +&cpu_thermal { + thermal-sensors = <&thermal>; +}; + +&gpio { + i2c_slave_gpio18: i2c_slave_gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + + jtag_gpio4: jtag_gpio4 { + brcm,pins = <4 5 6 12 13>; + brcm,function = ; + }; + + pwm0_gpio12: pwm0_gpio12 { + brcm,pins = <12>; + brcm,function = ; + }; + pwm0_gpio18: pwm0_gpio18 { + brcm,pins = <18>; + brcm,function = ; + }; + pwm0_gpio40: pwm0_gpio40 { + brcm,pins = <40>; + brcm,function = ; + }; + pwm1_gpio13: pwm1_gpio13 { + brcm,pins = <13>; + brcm,function = ; + }; + pwm1_gpio19: pwm1_gpio19 { + brcm,pins = <19>; + brcm,function = ; + }; + pwm1_gpio41: pwm1_gpio41 { + brcm,pins = <41>; + brcm,function = ; + }; + pwm1_gpio45: pwm1_gpio45 { + brcm,pins = <45>; + brcm,function = ; + }; +}; + +&i2s { + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; +}; + +&sdhost { + dmas = <&dma 13>; + dma-names = "rx-tx"; +}; + +&spi { + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; +}; diff --git a/arch/arm/dts/bcm2835-rpi-a-plus.dts b/arch/arm/dts/bcm2835-rpi-a-plus.dts index db8a6017f22..40b9405f1a8 100644 --- a/arch/arm/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/dts/bcm2835-rpi-a-plus.dts @@ -8,12 +8,17 @@ compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; model = "Raspberry Pi Model A+"; + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; + leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; @@ -99,6 +104,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -107,6 +114,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-a.dts b/arch/arm/dts/bcm2835-rpi-a.dts index 067d1f07a2d..11edb581dba 100644 --- a/arch/arm/dts/bcm2835-rpi-a.dts +++ b/arch/arm/dts/bcm2835-rpi-a.dts @@ -8,8 +8,13 @@ compatible = "raspberrypi,model-a", "brcm,bcm2835"; model = "Raspberry Pi Model A"; + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; + leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; @@ -94,6 +99,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -102,6 +109,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-b-plus.dts b/arch/arm/dts/bcm2835-rpi-b-plus.dts index 1e40d672b05..1b435c64bd9 100644 --- a/arch/arm/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/dts/bcm2835-rpi-b-plus.dts @@ -9,12 +9,17 @@ compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; model = "Raspberry Pi Model B+"; + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; @@ -101,6 +106,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -109,6 +116,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/dts/bcm2835-rpi-b-rev2.dts index 28e7513ce61..a23c25c00ee 100644 --- a/arch/arm/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/dts/bcm2835-rpi-b-rev2.dts @@ -9,8 +9,13 @@ compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; model = "Raspberry Pi Model B rev2"; + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; + leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; @@ -94,6 +99,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -102,6 +109,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-b.dts b/arch/arm/dts/bcm2835-rpi-b.dts index 31ff602e2cd..1b63d6b1975 100644 --- a/arch/arm/dts/bcm2835-rpi-b.dts +++ b/arch/arm/dts/bcm2835-rpi-b.dts @@ -9,8 +9,13 @@ compatible = "raspberrypi,model-b", "brcm,bcm2835"; model = "Raspberry Pi Model B"; + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; + leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; @@ -89,6 +94,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -97,6 +104,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts index 4764a25585a..a75c882e657 100644 --- a/arch/arm/dts/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts @@ -79,6 +79,15 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/dts/bcm2835-rpi-cm1.dtsi index ef22c2da783..e4e6b6abbfc 100644 --- a/arch/arm/dts/bcm2835-rpi-cm1.dtsi +++ b/arch/arm/dts/bcm2835-rpi-cm1.dtsi @@ -5,11 +5,16 @@ / { leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + reg_3v3: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "3V3"; diff --git a/arch/arm/dts/bcm2835-rpi-common.dtsi b/arch/arm/dts/bcm2835-rpi-common.dtsi new file mode 100644 index 00000000000..8a55b6cded5 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-common.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's + * firmware interface. + */ + +#include + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts b/arch/arm/dts/bcm2835-rpi-zero-w.dts index ba0167df6c5..33b2b77aa47 100644 --- a/arch/arm/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts @@ -12,14 +12,19 @@ compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; model = "Raspberry Pi Zero W"; + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + chosen { /* 8250 auxiliary UART instead of pl011 */ stdout-path = "serial1:115200n8"; }; leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; + led-act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; @@ -100,12 +105,16 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &sdhci { #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; + bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; non-removable; status = "okay"; @@ -116,6 +125,13 @@ }; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; diff --git a/arch/arm/dts/bcm2835-rpi-zero.dts b/arch/arm/dts/bcm2835-rpi-zero.dts index 3b35a8a4a55..6f9b3a908f2 100644 --- a/arch/arm/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/dts/bcm2835-rpi-zero.dts @@ -12,8 +12,13 @@ compatible = "raspberrypi,model-zero", "brcm,bcm2835"; model = "Raspberry Pi Zero"; + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; @@ -96,6 +101,15 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/dts/bcm2835-rpi.dtsi b/arch/arm/dts/bcm2835-rpi.dtsi index 715d50c6452..87ddcad7608 100644 --- a/arch/arm/dts/bcm2835-rpi.dtsi +++ b/arch/arm/dts/bcm2835-rpi.dtsi @@ -1,15 +1,10 @@ #include / { - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; - leds { compatible = "gpio-leds"; - act { + led-act { label = "ACT"; default-state = "keep"; linux,default-trigger = "heartbeat"; @@ -18,8 +13,12 @@ soc { firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mailbox>; + dma-ranges; }; power: power { @@ -64,32 +63,10 @@ clock-frequency = <100000>; }; -&i2c2 { - status = "okay"; -}; - -&sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio48>; - bus-width = <4>; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - &usb { power-domains = <&power RPI_POWER_DOMAIN_USB>; }; -&hdmi { - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - &vec { power-domains = <&power RPI_POWER_DOMAIN_VEC>; status = "okay"; diff --git a/arch/arm/dts/bcm2835.dtsi b/arch/arm/dts/bcm2835.dtsi index a5c3824c805..0549686134e 100644 --- a/arch/arm/dts/bcm2835.dtsi +++ b/arch/arm/dts/bcm2835.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2835"; diff --git a/arch/arm/dts/bcm2836-rpi-2-b.dts b/arch/arm/dts/bcm2836-rpi-2-b.dts index 7b4e651bafd..d8af8eeac7b 100644 --- a/arch/arm/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/dts/bcm2836-rpi-2-b.dts @@ -10,15 +10,16 @@ model = "Raspberry Pi 2 Model B"; memory@0 { + device_type = "memory"; reg = <0 0x40000000>; }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; @@ -105,6 +106,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -113,6 +116,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/dts/bcm2836.dtsi b/arch/arm/dts/bcm2836.dtsi index c933e841388..b390006aef7 100644 --- a/arch/arm/dts/bcm2836.dtsi +++ b/arch/arm/dts/bcm2836.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2836"; diff --git a/arch/arm/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts index 7f4437a8eed..77099a7871b 100644 --- a/arch/arm/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts @@ -14,17 +14,20 @@ }; memory@0 { + device_type = "memory"; reg = <0 0x20000000>; }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; }; @@ -117,6 +120,8 @@ &hdmi { hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { diff --git a/arch/arm/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts index c6fa34c2410..61010266ca9 100644 --- a/arch/arm/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts @@ -15,17 +15,20 @@ }; memory@0 { + device_type = "memory"; reg = <0 0x40000000>; }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; @@ -124,6 +127,8 @@ &hdmi { hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { diff --git a/arch/arm/dts/bcm2837-rpi-3-b.dts b/arch/arm/dts/bcm2837-rpi-3-b.dts index ce71f578c51..dd4a4860409 100644 --- a/arch/arm/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/dts/bcm2837-rpi-3-b.dts @@ -15,11 +15,12 @@ }; memory@0 { + device_type = "memory"; reg = <0 0x40000000>; }; leds { - act { + led-act { gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; }; }; @@ -125,6 +126,8 @@ &hdmi { hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; /* uart0 communicates with the BT module */ diff --git a/arch/arm/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts index 6c8233a36d8..588d9411ceb 100644 --- a/arch/arm/dts/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts @@ -78,6 +78,15 @@ &hdmi { hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/dts/bcm2837-rpi-cm3.dtsi index 81399b2c5af..828a20561b9 100644 --- a/arch/arm/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/dts/bcm2837-rpi-cm3.dtsi @@ -5,9 +5,18 @@ / { memory@0 { + device_type = "memory"; reg = <0 0x40000000>; }; + leds { + /* + * Since there is no upstream GPIO driver yet, + * remove the incomplete node. + */ + /delete-node/ led-act; + }; + reg_3v3: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "3V3"; diff --git a/arch/arm/dts/bcm2837.dtsi b/arch/arm/dts/bcm2837.dtsi index beb6c502dad..0199ec98cd6 100644 --- a/arch/arm/dts/bcm2837.dtsi +++ b/arch/arm/dts/bcm2837.dtsi @@ -1,4 +1,6 @@ #include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2837"; diff --git a/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi new file mode 100644 index 00000000000..0ff0e9e2532 --- /dev/null +++ b/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +&usb { + dr_mode = "peripheral"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 256 512 512 512 768 768>; +}; diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi index 9777644c6c2..a3e06b68094 100644 --- a/arch/arm/dts/bcm283x.dtsi +++ b/arch/arm/dts/bcm283x.dtsi @@ -18,7 +18,6 @@ / { compatible = "brcm,bcm2835"; model = "BCM2835"; - interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; @@ -31,16 +30,27 @@ stdout-path = "serial0:115200n8"; }; + rmem: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + }; + }; + thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; polling-delay = <1000>; - thermal-sensors = <&thermal>; - trips { cpu-crit { - temperature = <80000>; + temperature = <90000>; hysteresis = <0>; type = "critical"; }; @@ -56,7 +66,7 @@ #address-cells = <1>; #size-cells = <1>; - timer@7e003000 { + system_timer: timer@7e003000 { compatible = "brcm,bcm2835-system-timer"; reg = <0x7e003000 0x1000>; interrupts = <1 0>, <1 1>, <1 2>, <1 3>; @@ -67,74 +77,12 @@ clock-frequency = <1000000>; }; - txp@7e004000 { + txp: txp@7e004000 { compatible = "brcm,bcm2835-txp"; reg = <0x7e004000 0x20>; interrupts = <1 11>; }; - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; - }; - - intc: interrupt-controller@7e00b200 { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; - }; - clocks: cprman@7e101000 { compatible = "brcm,bcm2835-cprman"; #clock-cells = <1>; @@ -149,12 +97,6 @@ <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; }; - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; - }; - mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; @@ -184,8 +126,7 @@ interrupt-controller; #interrupt-cells = <2>; - /* Defines pin muxing groups according to - * BCM2835-ARM-Peripherals.pdf page 102. + /* Defines common pin muxing groups * * While each pin can have its mux selected * for various functions individually, some @@ -263,15 +204,7 @@ brcm,pins = <44 45>; brcm,function = ; }; - i2c_slave_gpio18: i2c_slave_gpio18 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; - jtag_gpio4: jtag_gpio4 { - brcm,pins = <4 5 6 12 13>; - brcm,function = ; - }; jtag_gpio22: jtag_gpio22 { brcm,pins = <22 23 24 25 26 27>; brcm,function = ; @@ -286,35 +219,6 @@ brcm,function = ; }; - pwm0_gpio12: pwm0_gpio12 { - brcm,pins = <12>; - brcm,function = ; - }; - pwm0_gpio18: pwm0_gpio18 { - brcm,pins = <18>; - brcm,function = ; - }; - pwm0_gpio40: pwm0_gpio40 { - brcm,pins = <40>; - brcm,function = ; - }; - pwm1_gpio13: pwm1_gpio13 { - brcm,pins = <13>; - brcm,function = ; - }; - pwm1_gpio19: pwm1_gpio19 { - brcm,pins = <19>; - brcm,function = ; - }; - pwm1_gpio41: pwm1_gpio41 { - brcm,pins = <41>; - brcm,function = ; - }; - pwm1_gpio45: pwm1_gpio45 { - brcm,pins = <45>; - brcm,function = ; - }; - sdhost_gpio48: sdhost_gpio48 { brcm,pins = <48 49 50 51 52 53>; brcm,function = ; @@ -396,8 +300,8 @@ }; uart0: serial@7e201000 { - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x1000>; + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x200>; interrupts = <2 25>; clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; @@ -410,8 +314,6 @@ reg = <0x7e202000 0x100>; interrupts = <2 24>; clocks = <&clocks BCM2835_CLOCK_VPU>; - dmas = <&dma 13>; - dma-names = "rx-tx"; status = "disabled"; }; @@ -419,16 +321,12 @@ compatible = "brcm,bcm2835-i2s"; reg = <0x7e203000 0x24>; clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; status = "disabled"; }; spi: spi@7e204000 { compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; + reg = <0x7e204000 0x200>; interrupts = <2 22>; clocks = <&clocks BCM2835_CLOCK_VPU>; #address-cells = <1>; @@ -438,7 +336,7 @@ i2c0: i2c@7e205000 { compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; + reg = <0x7e205000 0x200>; interrupts = <2 21>; clocks = <&clocks BCM2835_CLOCK_VPU>; #address-cells = <1>; @@ -446,18 +344,6 @@ status = "disabled"; }; - pixelvalve@7e206000 { - compatible = "brcm,bcm2835-pixelvalve0"; - reg = <0x7e206000 0x100>; - interrupts = <2 13>; /* pwa0 */ - }; - - pixelvalve@7e207000 { - compatible = "brcm,bcm2835-pixelvalve1"; - reg = <0x7e207000 0x100>; - interrupts = <2 14>; /* pwa1 */ - }; - dpi: dpi@7e208000 { compatible = "brcm,bcm2835-dpi"; reg = <0x7e208000 0x8c>; @@ -486,13 +372,6 @@ "dsi0_ddr2", "dsi0_ddr"; - }; - - thermal: thermal@7e212000 { - compatible = "brcm,bcm2835-thermal"; - reg = <0x7e212000 0x8>; - clocks = <&clocks BCM2835_CLOCK_TSENS>; - #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -541,7 +420,7 @@ status = "disabled"; }; - sdhci: sdhci@7e300000 { + sdhci: mmc@7e300000 { compatible = "brcm,bcm2835-sdhci"; reg = <0x7e300000 0x100>; interrupts = <2 30>; @@ -585,44 +464,6 @@ status = "disabled"; }; - i2c2: i2c@7e805000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vec: vec@7e806000 { - compatible = "brcm,bcm2835-vec"; - reg = <0x7e806000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = <2 27>; - status = "disabled"; - }; - - pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; - interrupts = <2 10>; /* pixelvalve */ - }; - - hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; - clocks = <&clocks BCM2835_PLLH_PIX>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; - dmas = <&dma 17>; - dma-names = "audio-rx"; - status = "disabled"; - }; - usb: usb@7e980000 { compatible = "brcm,bcm2835-usb"; reg = <0x7e980000 0x10000>; @@ -634,36 +475,19 @@ phys = <&usbphy>; phy-names = "usb2-phy"; }; - - v3d: v3d@7ec00000 { - compatible = "brcm,bcm2835-v3d"; - reg = <0x7ec00000 0x1000>; - interrupts = <1 10>; - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; - }; - - vc4: gpu { - compatible = "brcm,bcm2835-vc4"; - }; }; clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - /* The oscillator is the root of the clock tree. */ - clk_osc: clock@3 { + clk_osc: clk-osc { compatible = "fixed-clock"; - reg = <3>; #clock-cells = <0>; clock-output-names = "osc"; clock-frequency = <19200000>; }; - clk_usb: clock@4 { + clk_usb: clk-usb { compatible = "fixed-clock"; - reg = <4>; #clock-cells = <0>; clock-output-names = "otg"; clock-frequency = <480000000>; diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 88f7504a60f..0d534b8a28d 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_RPI_4_32B=y CONFIG_ENV_SIZE=0x4000 +CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 59a71031540..0b3cadaced2 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_RPI_4=y CONFIG_ENV_SIZE=0x4000 +CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 67dbf094ef7..07f67394ac2 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_RPI_ARM64=y CONFIG_ENV_SIZE=0x4000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 2cec01f9689..b60c03430cf 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -58,3 +58,5 @@ #define BCM2835_CLOCK_DSI1E 48 #define BCM2835_CLOCK_DSI0P 49 #define BCM2835_CLOCK_DSI1P 50 + +#define BCM2711_CLOCK_EMMC2 51 From patchwork Tue Dec 7 00:11:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564423 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=V2Yv8fGb; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Linus Walleij Subject: [PATCH v7 08/31] arm: vexpress: Add a devicetree files for juno Date: Mon, 6 Dec 2021 17:11:46 -0700 Message-Id: <20211207001209.3467163-9-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Sync these file, obtained from Linux v5.15. Add a note for the maintainer, and SPDX lines where they are missing. The added lines are: SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause Note, this matches the text in those files, but is not the same as the GPL-2.0 of some files. [1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/ Signed-off-by: Simon Glass --- Changes in v7: - Bring in files from Linux instead - Rewrite the commit message arch/arm/dts/Makefile | 3 + arch/arm/dts/juno-base.dtsi | 831 +++++++++++++++++++++++++ arch/arm/dts/juno-clocks.dtsi | 46 ++ arch/arm/dts/juno-cs-r1r2.dtsi | 85 +++ arch/arm/dts/juno-motherboard.dtsi | 303 +++++++++ arch/arm/dts/juno-r2.dts | 322 ++++++++++ configs/vexpress_aemv8a_juno_defconfig | 1 + 7 files changed, 1591 insertions(+) create mode 100644 arch/arm/dts/juno-base.dtsi create mode 100644 arch/arm/dts/juno-clocks.dtsi create mode 100644 arch/arm/dts/juno-cs-r1r2.dtsi create mode 100644 arch/arm/dts/juno-motherboard.dtsi create mode 100644 arch/arm/dts/juno-r2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9cddab37207..d53bae2c350 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1149,7 +1149,10 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \ dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb +# TODO(Linus Walleij ): Should us a single vexpress +# Kconfig option to build all of these. See examples above. dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb diff --git a/arch/arm/dts/juno-base.dtsi b/arch/arm/dts/juno-base.dtsi new file mode 100644 index 00000000000..6288e104a08 --- /dev/null +++ b/arch/arm/dts/juno-base.dtsi @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "juno-clocks.dtsi" +#include "juno-motherboard.dtsi" + +/ { + /* + * Devices shared by all Juno boards + */ + + memtimer: timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2a820000 0x20000>; + status = "disabled"; + frame@2a830000 { + frame-number = <1>; + interrupts = ; + reg = <0x10000 0x10000>; + }; + }; + + mailbox: mhu@2b1f0000 { + compatible = "arm,mhu", "arm,primecell"; + reg = <0x0 0x2b1f0000 0x0 0x1000>; + interrupts = , + ; + #mbox-cells = <1>; + clocks = <&soc_refclk100mhz>; + clock-names = "apb_pclk"; + }; + + smmu_gpu: iommu@2b400000 { + compatible = "arm,mmu-400", "arm,smmu-v1"; + reg = <0x0 0x2b400000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + status = "disabled"; + }; + + smmu_pcie: iommu@2b500000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x2b500000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + status = "disabled"; + }; + + smmu_etr: iommu@2b600000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x2b600000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + power-domains = <&scpi_devpd 0>; + }; + + gic: interrupt-controller@2c010000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + reg = <0x0 0x2c010000 0 0x1000>, + <0x0 0x2c02f000 0 0x2000>, + <0x0 0x2c04f000 0 0x2000>, + <0x0 0x2c06f000 0 0x2000>; + #address-cells = <1>; + #interrupt-cells = <3>; + #size-cells = <1>; + interrupt-controller; + interrupts = ; + ranges = <0 0 0x2c1c0000 0x40000>; + + v2m_0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0 0x10000>; + }; + + v2m@10000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x10000 0x10000>; + }; + + v2m@20000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x20000 0x10000>; + }; + + v2m@30000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x30000 0x10000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + /* + * Juno TRMs specify the size for these coresight components as 64K. + * The actual size is just 4K though 64K is reserved. Access to the + * unmapped reserved region results in a DECERR response. + */ + etf@20010000 { /* etf0 */ + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + in-ports { + port { + etf0_in_port: endpoint { + remote-endpoint = <&main_funnel_out_port>; + }; + }; + }; + + out-ports { + port { + etf0_out_port: endpoint { + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ + main_funnel: funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + out-ports { + port { + main_funnel_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + }; + + main_funnel_in_ports: in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + main_funnel_in_port0: endpoint { + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@1 { + reg = <1>; + main_funnel_in_port1: endpoint { + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + iommus = <&smmu_etr 0>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + arm,scatter-gather; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x1000000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + stm_out_port: endpoint { + }; + }; + }; + }; + + replicator@20120000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x20120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port0: endpoint { + }; + }; + }; + }; + + cpu_debug0: cpu-debug@22010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x22010000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm0: etm@22040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x22040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster0_etm0_out_port: endpoint { + remote-endpoint = <&cluster0_funnel_in_port0>; + }; + }; + }; + }; + + funnel@220c0000 { /* cluster0 funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x220c0000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster0_funnel_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster0_funnel_in_port0: endpoint { + remote-endpoint = <&cluster0_etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + cluster0_funnel_in_port1: endpoint { + remote-endpoint = <&cluster0_etm1_out_port>; + }; + }; + }; + }; + + cpu_debug1: cpu-debug@22110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x22110000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm1: etm@22140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x22140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster0_etm1_out_port: endpoint { + remote-endpoint = <&cluster0_funnel_in_port1>; + }; + }; + }; + }; + + cpu_debug2: cpu-debug@23010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23010000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm2: etm@23040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster1_etm0_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port0>; + }; + }; + }; + }; + + funnel@230c0000 { /* cluster1 funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x230c0000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster1_funnel_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster1_funnel_in_port0: endpoint { + remote-endpoint = <&cluster1_etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + cluster1_funnel_in_port1: endpoint { + remote-endpoint = <&cluster1_etm1_out_port>; + }; + }; + port@2 { + reg = <2>; + cluster1_funnel_in_port2: endpoint { + remote-endpoint = <&cluster1_etm2_out_port>; + }; + }; + port@3 { + reg = <3>; + cluster1_funnel_in_port3: endpoint { + remote-endpoint = <&cluster1_etm3_out_port>; + }; + }; + }; + }; + + cpu_debug3: cpu-debug@23110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23110000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm3: etm@23140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster1_etm1_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port1>; + }; + }; + }; + }; + + cpu_debug4: cpu-debug@23210000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23210000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm4: etm@23240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23240000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster1_etm2_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port2>; + }; + }; + }; + }; + + cpu_debug5: cpu-debug@23310000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23310000 0x0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + }; + + etm5: etm@23340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23340000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + cluster1_etm3_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port3>; + }; + }; + }; + }; + + gpu: gpu@2d000000 { + compatible = "arm,juno-mali", "arm,mali-t624"; + reg = <0 0x2d000000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scpi_dvfs 2>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + /* The SMMU is only really of interest to bare-metal hypervisors */ + /* iommus = <&smmu_gpu 0>; */ + status = "disabled"; + }; + + sram: sram@2e000000 { + compatible = "arm,juno-sram-ns", "mmio-sram"; + reg = <0x0 0x2e000000 0x0 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2e000000 0x8000>; + + cpu_scp_lpri: scp-sram@0 { + compatible = "arm,juno-scp-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-sram@200 { + compatible = "arm,juno-scp-shmem"; + reg = <0x200 0x200>; + }; + }; + + pcie_ctlr: pcie@40000000 { + compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, + <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, + <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; + /* Standard AXI Translation entries as programmed by EDK2 */ + dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, + <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&v2m_0>; + status = "disabled"; + iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ + iommu-map = <0x0 &smmu_pcie 0x0 0x1>; + }; + + scpi { + compatible = "arm,scpi"; + mboxes = <&mailbox 1>; + shmem = <&cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clocks-0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "atlclk", "aplclk","gpuclk"; + }; + scpi_clk: clocks-1 { + compatible = "arm,scpi-variable-clocks"; + #clock-cells = <1>; + clock-indices = <3>; + clock-output-names = "pxlclk"; + }; + }; + + scpi_devpd: power-controller { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; + + scpi_sensors0: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + pmic { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 0>; + }; + + soc { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 3>; + }; + + big_cluster_thermal_zone: big-cluster { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 21>; + status = "disabled"; + }; + + little_cluster_thermal_zone: little-cluster { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 22>; + status = "disabled"; + }; + + gpu0_thermal_zone: gpu0 { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 23>; + status = "disabled"; + }; + + gpu1_thermal_zone: gpu1 { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 24>; + status = "disabled"; + }; + }; + + smmu_dma: iommu@7fb00000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb00000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + }; + + smmu_hdlcd1: iommu@7fb10000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb10000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + }; + + smmu_hdlcd0: iommu@7fb20000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb20000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + }; + + smmu_usb: iommu@7fb30000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb30000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + }; + + dma@7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x7ff00000 0 0x1000>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + interrupts = , + , + , + , + , + , + , + , + ; + iommus = <&smmu_dma 0>, + <&smmu_dma 1>, + <&smmu_dma 2>, + <&smmu_dma 3>, + <&smmu_dma 4>, + <&smmu_dma 5>, + <&smmu_dma 6>, + <&smmu_dma 7>, + <&smmu_dma 8>; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + }; + + hdlcd@7ff50000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff50000 0 0x1000>; + interrupts = ; + iommus = <&smmu_hdlcd1 0>; + clocks = <&scpi_clk 3>; + clock-names = "pxlclk"; + + port { + hdlcd1_output: endpoint { + remote-endpoint = <&tda998x_1_input>; + }; + }; + }; + + hdlcd@7ff60000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff60000 0 0x1000>; + interrupts = ; + iommus = <&smmu_hdlcd0 0>; + clocks = <&scpi_clk 3>; + clock-names = "pxlclk"; + + port { + hdlcd0_output: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + + soc_uart0: serial@7ff80000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff80000 0x0 0x1000>; + interrupts = ; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + i2c@7ffa0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x7ffa0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <500>; + clocks = <&soc_smc50mhz>; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&hdlcd0_output>; + }; + }; + }; + + hdmi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + port { + tda998x_1_input: endpoint { + remote-endpoint = <&hdlcd1_output>; + }; + }; + }; + }; + + usb@7ffb0000 { + compatible = "generic-ohci"; + reg = <0x0 0x7ffb0000 0x0 0x10000>; + interrupts = ; + iommus = <&smmu_usb 0>; + clocks = <&soc_usb48mhz>; + }; + + usb@7ffc0000 { + compatible = "generic-ehci"; + reg = <0x0 0x7ffc0000 0x0 0x10000>; + interrupts = ; + iommus = <&smmu_usb 0>; + clocks = <&soc_usb48mhz>; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = , + ; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + + memory@80000000 { + device_type = "memory"; + /* last 16MB of the first memory area is reserved for secure world use by firmware */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>, + <0x00000008 0x80000000 0x1 0x80000000>; + }; + + bus@8000000 { + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 15>; + interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + }; + + site2: tlx-bus@60000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60000000 0x10000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0>; + interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/dts/juno-clocks.dtsi b/arch/arm/dts/juno-clocks.dtsi new file mode 100644 index 00000000000..b0f8ccaac9e --- /dev/null +++ b/arch/arm/dts/juno-clocks.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * ARM Juno Platform clocks + * + * Copyright (c) 2013-2014 ARM Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ +/ { + /* SoC fixed clocks */ + soc_uartclk: refclk7372800hz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7372800>; + clock-output-names = "juno:uartclk"; + }; + + soc_usb48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "clk48mhz"; + }; + + soc_smc50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "smc_clk"; + }; + + soc_refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_faxiclk: refclk400mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "faxi_clk"; + }; +}; diff --git a/arch/arm/dts/juno-cs-r1r2.dtsi b/arch/arm/dts/juno-cs-r1r2.dtsi new file mode 100644 index 00000000000..eda3d9e18af --- /dev/null +++ b/arch/arm/dts/juno-cs-r1r2.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + funnel@20130000 { /* cssys1 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x20130000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + csys1_funnel_out_port: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + in-ports { + port { + csys1_funnel_in_port0: endpoint { + }; + }; + + }; + }; + + etf@20140000 { /* etf1 */ + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + in-ports { + port { + etf1_in_port: endpoint { + remote-endpoint = <&csys1_funnel_out_port>; + }; + }; + }; + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&csys2_funnel_in_port1>; + }; + }; + }; + }; + + funnel@20150000 { /* cssys2 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x20150000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + out-ports { + port { + csys2_funnel_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csys2_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf0_out_port>; + }; + }; + + port@1 { + reg = <1>; + csys2_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etf1_out_port>; + }; + }; + + }; + }; +}; diff --git a/arch/arm/dts/juno-motherboard.dtsi b/arch/arm/dts/juno-motherboard.dtsi new file mode 100644 index 00000000000..42b17542ab1 --- /dev/null +++ b/arch/arm/dts/juno-motherboard.dtsi @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * ARM Juno Platform motherboard peripherals + * + * Copyright (c) 2013-2014 ARM Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ + +/ { + mb_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "juno_mb:clk24mhz"; + }; + + mb_clk25mhz: clk25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "juno_mb:clk25mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "juno_mb:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "juno_mb:refclk32khz"; + }; + + mb_fixed_3v3: mcc-sb-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MCC_SB_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + home-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + rlock-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + vol-up-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + vol-down-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + nmi-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; + + motherboard-bus@8000000 { + compatible = "arm,vexpress,v2p-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + arm,hbi = <0x252>; + arm,vexpress,site = <0>; + + flash@0 { + /* 2 * 32MiB NOR Flash memory mounted on CS0 */ + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <4>; + /* + * Unfortunately, accessing the flash disturbs + * the CPU idle states (suspend) and CPU + * hotplug of the platform. For this reason, + * flash hardware access is disabled by default. + */ + status = "disabled"; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + ethernet@200000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x00000000 0x10000>; + interrupts = <3>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + clocks = <&mb_clk25mhz>; + vdd33a-supply = <&mb_fixed_3v3>; + vddvario-supply = <&mb_fixed_3v3>; + }; + + iofpga-bus@300000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + apbregs@10000 { + compatible = "syscon", "simple-mfd"; + reg = <0x010000 0x1000>; + + led0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "vexpress:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "vexpress:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "vexpress:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "vexpress:3"; + linux,default-trigger = "cpu1"; + default-state = "off"; + }; + led4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "vexpress:4"; + linux,default-trigger = "cpu2"; + default-state = "off"; + }; + led5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "vexpress:5"; + linux,default-trigger = "cpu3"; + default-state = "off"; + }; + led6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "vexpress:6"; + default-state = "off"; + }; + led7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "vexpress:7"; + default-state = "off"; + }; + }; + + mmc@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <5>; + /* cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; */ + max-frequency = <12000000>; + vmmc-supply = <&mb_fixed_3v3>; + clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <8>; + clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <8>; + clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + watchdog@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x10000>; + interrupts = <7>; + clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x10000>; + interrupts = <9>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x10000>; + interrupts = <9>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x10000>; + interrupts = <0>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + + iofpga_gpio0: gpio@1d0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1d0000 0x1000>; + interrupts = <6>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/juno-r2.dts b/arch/arm/dts/juno-r2.dts new file mode 100644 index 00000000000..52a6517d165 --- /dev/null +++ b/arch/arm/dts/juno-r2.dts @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * ARM Ltd. Juno Platform + * + * Copyright (c) 2015 ARM Ltd. + * + * This file is licensed under a dual GPLv2 or BSD license. + */ + +/dts-v1/; + +#include +#include "juno-base.dtsi" +#include "juno-cs-r1r2.dtsi" + +/ { + model = "ARM Juno development board (r2)"; + compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + + A72_0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&A72_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <450>; + }; + + A72_1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&A72_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <450>; + }; + + A53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; + }; + + A53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; + }; + + A53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; + }; + + A53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; + }; + + A72_L2: l2-cache0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + A53_L2: l2-cache1 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + }; + + pmu-a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = , + ; + interrupt-affinity = <&A72_0>, + <&A72_1>; + }; + + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&A53_0>, + <&A53_1>, + <&A53_2>, + <&A53_3>; + }; +}; + +&memtimer { + status = "okay"; +}; + +&pcie_ctlr { + status = "okay"; +}; + +&smmu_pcie { + status = "okay"; +}; + +&etm0 { + cpu = <&A72_0>; +}; + +&etm1 { + cpu = <&A72_1>; +}; + +&etm2 { + cpu = <&A53_0>; +}; + +&etm3 { + cpu = <&A53_1>; +}; + +&etm4 { + cpu = <&A53_2>; +}; + +&etm5 { + cpu = <&A53_3>; +}; + +&big_cluster_thermal_zone { + status = "okay"; +}; + +&little_cluster_thermal_zone { + status = "okay"; +}; + +&gpu0_thermal_zone { + status = "okay"; +}; + +&gpu1_thermal_zone { + status = "okay"; +}; + +&etf0_out_port { + remote-endpoint = <&csys2_funnel_in_port0>; +}; + +&replicator_in_port0 { + remote-endpoint = <&csys2_funnel_out_port>; +}; + +&csys1_funnel_in_port0 { + remote-endpoint = <&stm_out_port>; +}; + +&stm_out_port { + remote-endpoint = <&csys1_funnel_in_port0>; +}; + +&cpu_debug0 { + cpu = <&A72_0>; +}; + +&cpu_debug1 { + cpu = <&A72_1>; +}; + +&cpu_debug2 { + cpu = <&A53_0>; +}; + +&cpu_debug3 { + cpu = <&A53_1>; +}; + +&cpu_debug4 { + cpu = <&A53_2>; +}; + +&cpu_debug5 { + cpu = <&A53_3>; +}; diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index f6ff0e0a569..0d9914c32bf 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -51,3 +51,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="juno-r2" From patchwork Tue Dec 7 00:11:47 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:52 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Anastasiia Lukianenko , Oleksandr Andrushchenko Subject: [PATCH v7 09/31] arm: xenguest_arm64: Add a empty devicetree file Date: Mon, 6 Dec 2021 17:11:47 -0700 Message-Id: <20211207001209.3467163-10-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add an empty file to prevent build errors when building with CONFIG_OF_SEPARATE enabled. The build instructions in U-Boot do not provide enough detail to build a useful devicetree, unfortunately. Signed-off-by: Simon Glass --- Changes in v7: - Use 'empty' instead of 'fake' arch/arm/dts/Makefile | 2 ++ arch/arm/dts/xenguest-arm64.dts | 15 +++++++++++++++ configs/xenguest_arm64_defconfig | 2 +- 3 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/xenguest-arm64.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d53bae2c350..f6345988c8c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1140,6 +1140,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb +dtb-$(CONFIG_XEN) += xenguest-arm64.dtb + dtb-$(CONFIG_TARGET_GE_BX50V3) += \ imx6q-bx50v3.dtb \ imx6q-b850v3.dtb \ diff --git a/arch/arm/dts/xenguest-arm64.dts b/arch/arm/dts/xenguest-arm64.dts new file mode 100644 index 00000000000..d8734433763 --- /dev/null +++ b/arch/arm/dts/xenguest-arm64.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Empty devicetree file for xenguest_arm64 + * + * This is required to make the board build with CONFIG OF_SEPARATE + * Build instructions at xenguest_arm64.rst are inadequate for obtaining a real + * devicetree. + * + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index 8d9d9133a2e..edce34346d3 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -3,7 +3,7 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_TARGET_XENGUEST_ARM64=y CONFIG_SYS_TEXT_BASE=0x40080000 CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64" CONFIG_IDENT_STRING=" xenguest" CONFIG_SYS_LOAD_ADDR=0x40000000 CONFIG_BOOTDELAY=10 From patchwork Tue Dec 7 00:11:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564419 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=NZOeVf2j; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:54 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Aaron Williams , Albert Aribaud Subject: [PATCH v7 10/31] arm: octeontx: Add an empty devicetree file Date: Mon, 6 Dec 2021 17:11:48 -0700 Message-Id: <20211207001209.3467163-11-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add an empty file to prevent build errors when building with CONFIG_OF_SEPARATE enabled. Unfortunately there are no build instructions in the U-Boot tree to enable a real file to be created. Signed-off-by: Simon Glass --- Changes in v7: - Use 'empty' instead of 'fake' arch/arm/dts/Makefile | 3 +++ arch/arm/dts/octeontx.dts | 14 ++++++++++++++ configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + 6 files changed, 21 insertions(+) create mode 100644 arch/arm/dts/octeontx.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f6345988c8c..91302118598 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1142,6 +1142,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_XEN) += xenguest-arm64.dtb +dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb +dtb-$(CONFIG_ARCH_OCTEONTX2) += octeontx.dtb + dtb-$(CONFIG_TARGET_GE_BX50V3) += \ imx6q-bx50v3.dtb \ imx6q-b850v3.dtb \ diff --git a/arch/arm/dts/octeontx.dts b/arch/arm/dts/octeontx.dts new file mode 100644 index 00000000000..60a15f5df23 --- /dev/null +++ b/arch/arm/dts/octeontx.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Dummy devicetre file for octeontx2 boards + * + * This is required to make the board build with CONFIG OF_SEPARATE + * I could not find any in-tree documentation at all so this is a dummy file. + * + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index e1b86a5a8b6..e3df390c94b 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX2_95XX=y CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="octeontx" CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index ec03d959771..0478b3068a6 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX2_96XX=y CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="octeontx" CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index d0728ac3c67..d871be8f812 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX_81XX=y CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="octeontx" CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 6c9609b0cd3..94b072bf6fa 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX_83XX=y CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="octeontx" CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y From patchwork Tue Dec 7 00:11:49 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Michal Simek Subject: [PATCH v7 11/31] arm: xilinx_versal_virt: Add a devicetree file Date: Mon, 6 Dec 2021 17:11:49 -0700 Message-Id: <20211207001209.3467163-12-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add an empty file to prevent build errors when building with CONFIG_OF_SEPARATE enabled. Signed-off-by: Simon Glass --- (no changes since v1) arch/arm/dts/Makefile | 3 ++- arch/arm/dts/xilinx-versal-virt.dts | 11 +++++++++++ configs/xilinx_versal_virt_defconfig | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/xilinx-versal-virt.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 91302118598..b07a1b3378e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -360,7 +360,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ versal-mini-emmc0.dtb \ - versal-mini-emmc1.dtb + versal-mini-emmc1.dtb \ + xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += \ diff --git a/arch/arm/dts/xilinx-versal-virt.dts b/arch/arm/dts/xilinx-versal-virt.dts new file mode 100644 index 00000000000..733e532f987 --- /dev/null +++ b/arch/arm/dts/xilinx-versal-virt.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for versal-virt board + * + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 11598623954..f0ec2639a38 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_COUNTER_FREQUENCY=100000000 From patchwork Tue Dec 7 00:11:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564421 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=A3F5O9g1; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:56 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Thomas Fitzsimmons Subject: [PATCH v7 12/31] arm: bcm7xxx: Add a devicetree file Date: Mon, 6 Dec 2021 17:11:50 -0700 Message-Id: <20211207001209.3467163-13-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add a dummy devicetree file for these boards. It seems to be possible to obtain a real one from another bootloader called 'bolt' but I will leave this to the maintainer. Signed-off-by: Simon Glass --- (no changes since v1) arch/arm/dts/Makefile | 2 ++ arch/arm/dts/bcm7xxx.dts | 15 +++++++++++++++ configs/bcm7260_defconfig | 1 + configs/bcm7445_defconfig | 1 + 4 files changed, 19 insertions(+) create mode 100644 arch/arm/dts/bcm7xxx.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b07a1b3378e..8bb15b96cc7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1092,6 +1092,8 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb +dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb + dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb diff --git a/arch/arm/dts/bcm7xxx.dts b/arch/arm/dts/bcm7xxx.dts new file mode 100644 index 00000000000..786ce3ff959 --- /dev/null +++ b/arch/arm/dts/bcm7xxx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Empty devicetre file for bcm7260 board + * + * This is required to make the board build with CONFIG OF_SEPARATE + * In-tree document explains how to obtain a real devicetree using 'bolt' but + * I did not attempt this. + * + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { +}; diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 257d81052a8..2b527b65770 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_BCM7260=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x814800 +CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx" CONFIG_ENV_OFFSET_REDUND=0x824800 CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 9ffa436e454..3ae678ba56e 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1E0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx" CONFIG_ENV_OFFSET_REDUND=0x1F0000 CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y From patchwork Tue Dec 7 00:11:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564422 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:57 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Alexander Graf , Bin Meng Subject: [PATCH v7 13/31] arm: qemu-ppce500: Add a devicetree file Date: Mon, 6 Dec 2021 17:11:51 -0700 Message-Id: <20211207001209.3467163-14-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This uses QEMU virt which creates its own devicetree. Add an empty version of this file, so that we can at least build this board when devicetrees are required. Signed-off-by: Simon Glass --- Changes in v7: - Switch to using an empty file for qemu virt arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/qemu-ppce500.dts | 10 ++++++++++ configs/qemu-ppce500_defconfig | 1 + 3 files changed, 12 insertions(+) create mode 100644 arch/powerpc/dts/qemu-ppce500.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index ceaa8ce5c82..66d22ae8a45 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb +dtb-$(CONFIG_TARGET_QEMU_PPCE500) += qemu-ppce500.dtb dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb diff --git a/arch/powerpc/dts/qemu-ppce500.dts b/arch/powerpc/dts/qemu-ppce500.dts new file mode 100644 index 00000000000..e88e09e1796 --- /dev/null +++ b/arch/powerpc/dts/qemu-ppce500.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for qemu-ppce400 + * + * Copyright 2021 Google LLC + */ +/dts-v1/; + +/ { +}; diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index f386f526548..ae4cd8b9618 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xf01000 CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_QEMU_PPCE500=y From patchwork Tue Dec 7 00:11:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564424 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=BO4I3rA+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:12:59 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Albert Aribaud , Andre Przywara Subject: [PATCH v7 14/31] arm: highbank: Add devicetree files Date: Mon, 6 Dec 2021 17:11:52 -0700 Message-Id: <20211207001209.3467163-15-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Sync these files, obtained from Linux v5.15. Signed-off-by: Simon Glass --- Changes in v7: - Bring in files from Linux instead arch/arm/dts/Makefile | 2 + arch/arm/dts/ecx-common.dtsi | 231 +++++++++++++++++++++++++++++++++++ arch/arm/dts/highbank.dts | 158 ++++++++++++++++++++++++ configs/highbank_defconfig | 2 +- 4 files changed, 392 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ecx-common.dtsi create mode 100644 arch/arm/dts/highbank.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8bb15b96cc7..453e2fd1a98 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -871,6 +871,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb + dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ diff --git a/arch/arm/dts/ecx-common.dtsi b/arch/arm/dts/ecx-common.dtsi new file mode 100644 index 00000000000..57a028a6937 --- /dev/null +++ b/arch/arm/dts/ecx-common.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2011-2012 Calxeda, Inc. + */ + +/ { + chosen { + bootargs = "console=ttyAMA0"; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000002>; + cpu_off = <0x84000004>; + cpu_on = <0x84000006>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <0 83 4>; + dma-coherent; + calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, + <&combophy0 1>, <&combophy0 2>, + <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, + <&gpioh 7 1>; + calxeda,led-order = <4 0 1 2 3>; + }; + + sdhci@ffe0e000 { + compatible = "calxeda,hb-sdhci"; + reg = <0xffe0e000 0x1000>; + interrupts = <0 90 4>; + clocks = <&eclk>; + status = "disabled"; + }; + + ipc@fff20000 { + compatible = "arm,pl320", "arm,primecell"; + reg = <0xfff20000 0x1000>; + interrupts = <0 7 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpioe: gpio@fff30000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff30000 0x1000>; + interrupts = <0 14 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpiof: gpio@fff31000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff31000 0x1000>; + interrupts = <0 15 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpiog: gpio@fff32000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff32000 0x1000>; + interrupts = <0 16 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpioh: gpio@fff33000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff33000 0x1000>; + interrupts = <0 17 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + timer@fff34000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfff34000 0x1000>; + interrupts = <0 18 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + rtc@fff35000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0xfff35000 0x1000>; + interrupts = <0 19 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xfff36000 0x1000>; + interrupts = <0 20 4>; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; + + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + a9bclk: a9bclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9bus-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + emmcpll: emmcpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x10C>; + }; + + eclk: eclk { + #clock-cells = <0>; + compatible = "calxeda,hb-emmc-clock"; + clocks = <&emmcpll>; + reg = <0x114>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <150000000>; + }; + }; + }; + + dma@fff3d000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfff3d000 0x1000>; + interrupts = <0 92 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; + dma-coherent; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4>, <0 81 4>, <0 82 4>; + dma-coherent; + }; + + combophy0: combo-phy@fff58000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff58000 0x1000>; + phydev = <5>; + }; + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; + }; +}; diff --git a/arch/arm/dts/highbank.dts b/arch/arm/dts/highbank.dts new file mode 100644 index 00000000000..b6b0225a769 --- /dev/null +++ b/arch/arm/dts/highbank.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2011-2012 Calxeda, Inc. + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x900>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@901 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x901>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@902 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x902>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@903 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x903>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + soc { + ranges = <0x00000000 0x00000000 0xffffffff>; + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; + + timer@fff10600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfff10600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&a9periphclk>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xfff10620 0x20>; + interrupts = <1 14 0xf01>; + clocks = <&a9periphclk>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <0 70 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; + }; + + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; + + }; +}; + +/include/ "ecx-common.dtsi" diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 85b42c70f55..3e8bfcf73a6 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="highbank" CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_DISTRO_DEFAULTS=y @@ -21,7 +22,6 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_BOARD=y CONFIG_ENV_IS_IN_NVRAM=y CONFIG_ENV_ADDR=0xFFF88000 CONFIG_SCSI_AHCI=y From patchwork Tue Dec 7 00:11:53 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:00 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 15/31] fdt: Make OF_BOARD a bool option Date: Mon, 6 Dec 2021 17:11:53 -0700 Message-Id: <20211207001209.3467163-16-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This should not be a separate option from OF_SEPARATE. It is a run-time option to override the devicetree, even if present. Move the option out of the choice. Disable BINMAN_FDT for a few boards which don't actually use it. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-ppce500_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 2 ++ configs/qemu-riscv64_spl_defconfig | 1 + dts/Kconfig | 11 ++++++----- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index ae4cd8b9618..81d12d5f3c1 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -56,4 +56,5 @@ CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_ADDR_MAP=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index c4422969c61..8889b028c6b 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y +# CONFIG_OF_BOARD_FIXUP is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y @@ -18,3 +19,4 @@ CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y +# CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index e02ca3a1465..8f875949ec0 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -19,3 +19,4 @@ CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y +# CONFIG_BINMAN_FDT is not set diff --git a/dts/Kconfig b/dts/Kconfig index b7c4a2fec03..9994ab13dcb 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -97,11 +97,9 @@ config OF_LIVE choice prompt "Provider of DTB for DT control" depends on OF_CONTROL - default OF_BOARD if SANDBOX config OF_SEPARATE bool "Separate DTB for DT control" - depends on !SANDBOX help If this option is enabled, the device tree will be built and placed as a separate u-boot.dtb file alongside the U-Boot image. @@ -114,14 +112,17 @@ config OF_EMBED and development only and is not recommended for production devices. Boards in the mainline U-Boot tree should not use it. +endchoice + config OF_BOARD bool "Provided by the board (e.g a previous loader) at runtime" + default y if SANDBOX help If this option is enabled, the device tree will be provided by - the board at runtime if the board supports it, instead of being - bundled with the image. + the board at runtime if the board supports it. The device tree bundled + with the image (if any) will be overridden / ignored. -endchoice + A device tree file must be provided in the tree. config DEFAULT_DEVICE_TREE string "Default Device Tree for DT control" From patchwork Tue Dec 7 00:11:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564427 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=FGHYGwrd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LS767h7z9sCD for ; Tue, 7 Dec 2021 11:16:07 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5859483433; Tue, 7 Dec 2021 01:14:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="FGHYGwrd"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 68D1D830C4; Tue, 7 Dec 2021 01:13:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3ED9A830CB for ; Tue, 7 Dec 2021 01:13:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-oi1-x22a.google.com with SMTP id 7so24512560oip.12 for ; Mon, 06 Dec 2021 16:13:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4NfxC28CbRN1c/ciQ0T8VK5cTpb/LF/vkeqQS+NlYwM=; b=FGHYGwrdUKdk8gXPGgCJ9tEQKMDfU4eDVagvy1W3ptl8884830M2T/rIfNqFiusuYH EiMq3rJ0kLpT5kNknDKZHklf/zj49sbIUpsDb40WlVAtspuDbjcZ5na4WI5fvbjkdIsG Bbc9fIq4HOjNdZafz0BZmPcnJO0k0cL1rXfqU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4NfxC28CbRN1c/ciQ0T8VK5cTpb/LF/vkeqQS+NlYwM=; b=dV64yLVPvOwBOPwMQvgTrHmr0o0JAouVIAYPeR15FsWotFZD8QoVqN1H3uYSlzwkXG 4XwNZumny3aZbwD6SDpnn6556TrHJQnUuOjO5ySVj4jheAR5XCffcJ3VvPqOrFI7fgZw K0TFX5wAEhO+bteimg897DO8ahrQq4+7k5MTHArLEuK02kIhbyKfcY/KUeSm5JCEwTw6 sGAdikRxN7ysiTwPfn1r9Ln21lCn1WSfW0xc4p87A3ALik4YYpIHxIiKxTt7+q96wvRc w4EHSThTt+WLn2Q7+BCQqsifbO5OxTNHFiozyiOL5NOoSrfw33sYIXTfdDfZkBxDOvOC 4mXQ== X-Gm-Message-State: AOAM530n3o03Vk35NvsqE1k+SYThpZekef7H7G7/rlHmSEnkL7nfys+t YyBbWJY8vL2YsGrwGw7deh9xrOWvWO/O1A== X-Google-Smtp-Source: ABdhPJxtAqsUtxTk0XH6hR+YvdroSQI6Vr0M5QpE682T1RM03CTgU9VhdMgtnYEhtwI5tZw8Vkn0Cg== X-Received: by 2002:aca:1a05:: with SMTP id a5mr2125233oia.146.1638835981692; Mon, 06 Dec 2021 16:13:01 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:01 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass Subject: [PATCH v7 16/31] Drop CONFIG_BINMAN_STANDALONE_FDT Date: Mon, 6 Dec 2021 17:11:54 -0700 Message-Id: <20211207001209.3467163-17-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This was added as a hack to work around not having an in-tree devicetree. Now that this is fixed it is not needed. Drop it. Signed-off-by: Simon Glass --- (no changes since v1) Makefile | 3 +-- dts/Kconfig | 18 ------------------ tools/binman/binman.rst | 20 -------------------- 3 files changed, 1 insertion(+), 40 deletions(-) diff --git a/Makefile b/Makefile index 043af9a5dcd..6671c5d9e2f 100644 --- a/Makefile +++ b/Makefile @@ -953,7 +953,6 @@ endif endif INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb -INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img endif @@ -1427,7 +1426,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \ ,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) diff --git a/dts/Kconfig b/dts/Kconfig index 9994ab13dcb..6ebbac2a649 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -16,24 +16,6 @@ config BINMAN bool select DTOC -config BINMAN_STANDALONE_FDT - bool - depends on BINMAN - default y if OF_BOARD - help - This option tells U-Boot build system that a standalone device tree - source is explicitly required when using binman to package U-Boot. - - This is not necessary in a common scenario where a device tree source - that contains the binman node is provided in the arch//dts - directory for a specific board. Such device tree sources are built for - OF_SEPARATE or OF_EMBED. However for a scenario like the board device - tree blob is not provided in the U-Boot build tree, but fed to U-Boot - in the runtime, e.g.: in the OF_BOARD case that it is passed by - a prior stage bootloader. For such scenario, a standalone device tree - blob containing binman node to describe how to package U-Boot should - be provided explicitly. - menu "Device Tree Control" depends on SUPPORT_OF_CONTROL diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 10389a52c4b..56f865800e6 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -232,26 +232,6 @@ You can use other, more specific CONFIG options - see 'Automatic .dtsi inclusion' below. -Using binman with OF_BOARD --------------------------------------------- - -Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED. -This is a typical scenario where a device tree source that contains the binman -node is provided in the arch//dts directory for a specific board. - -However for a board configured with OF_BOARD, no device tree blob is provided -in the U-Boot build phase hence the binman node information is not available. -In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT -is introduced, to tell the build system that a standalone device tree blob -containing binman node is explicitly required. - -Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to -access information about binman entries, stored in the device tree in a binman -node. Generally speaking, this option makes sense for OF_SEPARATE or OF_EMBED. -For the other OF_CONTROL methods, it's quite possible binman node is not -available as binman is invoked during the build phase, thus this option is not -turned on by default for these OF_CONTROL methods. - Access to binman entry offsets at run time (symbols) ---------------------------------------------------- From patchwork Tue Dec 7 00:11:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564433 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Qz9ODuh9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LTL3bTNz9sCD for ; Tue, 7 Dec 2021 11:17:10 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E702083575; Tue, 7 Dec 2021 01:14:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Qz9ODuh9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DFED283178; Tue, 7 Dec 2021 01:13:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 98C27830DB for ; Tue, 7 Dec 2021 01:13:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x332.google.com with SMTP id h19-20020a9d3e53000000b0056547b797b2so15816519otg.4 for ; Mon, 06 Dec 2021 16:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nPKoRnJvQLV+XvLrecMl2gElBxXm3HBpD2Xt/8tDLak=; b=Qz9ODuh9smDrM0FJaxW/OOCGqffqGIuPkkwwMSOTnauif7ORqze5xjlgvMLsG6fFP7 mLJOkXwwBFIyjyz7IRW8z7vIVdYC/T8fKx4n1SKTwUIDUqzEom1dCCvwqd1IBSJl6V8F EOt6E5UAiNwCoJvkFDKZJ5dg2v3nnzLhDum08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nPKoRnJvQLV+XvLrecMl2gElBxXm3HBpD2Xt/8tDLak=; b=sLJiiardqp2qPhBNMVhWM4DBNhbVkQgmksI7QpBcnTC0jPm3h5sauFcv6JSoYQakmA oLeAVPlHtrOmXgmeQpwoMp3KlxpjLDVHwscasrRc1BAS0tYcpn7inhAJA9wH0NnHg7YI 9kbPvVNR94l9C/PWW4cbZ+HDrcsAFbIr+4VlcKUQTFvY7X/xnaYpCdkPIL/mn/MahRjK 3YvU523vhp0SVrVZ31HgOZsntabPFTiXRYR70s2GJb8k0ZFKsW0Wri6EMUnvRUa83tvO 0T0dcHJaYZGvz7qLxCBM8RJg8BDE2D+FlMMgdsSesIrMxtaELwqzmd2rRXvNTjrsOb5t Vkmw== X-Gm-Message-State: AOAM531jRi6U09y6qQEVv7C83HPfqC15qjF0mJ4W53Jlr3ALXfXsD6RM mzJXOp4svw5MsVsoLVcKr6MOrgTXt0zmLg== X-Google-Smtp-Source: ABdhPJz3Cw9OOYHW6uCMEQoE8dmrTZdUReYTgJczhWLYwsgWs7wzb2zwpBIVAYGUVfUYSpLH4ceGIA== X-Received: by 2002:a9d:5190:: with SMTP id y16mr33396213otg.364.1638835982774; Mon, 06 Dec 2021 16:13:02 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:02 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass Subject: [PATCH v7 17/31] doc: Update info on devicetree update Date: Mon, 6 Dec 2021 17:11:55 -0700 Message-Id: <20211207001209.3467163-18-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Since OF_BOARD has been corrected to be a run-time option, we can drop the historical info from this documentation. Signed-off-by: Simon Glass --- (no changes since v1) doc/develop/devicetree/dt_update.rst | 74 +++------------------------- 1 file changed, 7 insertions(+), 67 deletions(-) diff --git a/doc/develop/devicetree/dt_update.rst b/doc/develop/devicetree/dt_update.rst index e3b65f6fa66..10a2dfcfd39 100644 --- a/doc/develop/devicetree/dt_update.rst +++ b/doc/develop/devicetree/dt_update.rst @@ -32,66 +32,6 @@ that board on suitable hardware (or emulation). This is specified using the `CONFIG DEFAULT_DEVICE_TREE` option. -Current situation (October 2021) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -As an aside, at present U-Boot allows `CONFIG_DEFAULT_DEVICE_TREE` to be empty, -e.g. if `CONFIG_OF_BOARD` is used. This has unfortunately created an enormous -amount of confusion and some wasted effort. This was not intended. Support for -an empty `CONFIG_DEFAULT_DEVICE_TREE` will be dropped soon. - -Some of the problems created are: - -- It is not obvious that the devicetree is coming from another project - -- There is no way to see even a sample devicetree for these platform in U-Boot, - so it is hard to know what is going on, e.g. which devices are typically - present - -- The other project may not provide a way to support U-Boot's requirements for - devicetree, such as the /config node. Note: On the U-Boot mailing list, this - was only discovered after weeks of discussion and confusion - -- For QEMU specifically, consulting two QEMU source files is required, for which - there are no references in U-Boot documentation. The code is generating a - devicetree, but it is not clear what controls affect this generation. - -Specifically on the changes in U-Bootm `CONFIG_OF_BOARD` was added in -rpi_patch_ for Raspberry Pi, which does have an in-tree devicetree, but this -feature has since been used for boards that don't - -Once this bug is fixed, CONFIG_OF_BOARD will override (at runtime) the -evicetree suppled with U-Boot, but will otherwise use CONFIG_OF_SEPARATE for the -in-tree build. So these two will become options, moving out of the 'choice' in -`dts/Kconfig`. - -This means that there is a basic devicetree build in the U-Boot tree, for -build-testing, consistency and documentation purposes, but at runtime U-Boot can -accept its devicetree from another source. The in-tree devicetree may contain -U-Boot-specific features (in u-boot*.dtsi files) and this may prove useful for -the other project, so it can ensure that U-Boot functions correctly and supports -all its expected features. - -To be clear, while U-Boot has its own copy of the devicetree source for each -board, this must match the Linux source, perhaps with some u-boot.dtsi -additions. The intent here is not to create a separate binding, just to provide -a representative devicetree in U-Boot. - -Offending boards are: - -- rpi_4 and rpi_4_32b (other rpi boards do have an in-tree devicetree) -- qemu_arm64 -- qemu_arm -- qemu-ppce500 -- qemu-riscv32 -- qemu-riscv32_smode -- qemu-riscv64 -- qemu-riscv64_smode - -All of these need to have a devicetree added in-tree. This is targeted to be -fixed in the 2022.01 release. - - Building the devicetree ----------------------- @@ -198,17 +138,18 @@ The /config node is similar in concept to the `/chosen node`_ except that it is for passing information *into* firmware instead of from firmware to the Operating System. Also, while Linux has a (sometimes extremely long) command line, U-Boot does not support this. The devicetree provides a more structured -approach in any case. +approach in any case. Upstreaming of this node (as /options) has begun as of +November 2021. Devicetree in another project ----------------------------- -In some cases U-Boot receive its devicetree at runtime from a program that calls -it. For example ARM's Trusted Firmware A (`TF-A`_) may have a devicetree that it -passes to U-Boot. This overrides any devicetree build by U-Boot. When packaging -the firmware, the U-Boot devicetree may in fact be left out if it can be -guaranteed that it will receive one from another project. +In some cases U-Boot receives its devicetree at runtime from a program that +calls it. For example ARM's Trusted Firmware A (`TF-A`_) may have a devicetree +that it passes to U-Boot. This overrides any devicetree build by U-Boot. When +packaging the firmware, the U-Boot devicetree may in fact be left out if it can +be guaranteed that it will receive one from another project. In this case, the devicetree in the other project must track U-Boot's use of device tree, for the following reasons: @@ -546,7 +487,6 @@ Overall, adding a second devicetree would create enormous confusion and complexity. It seems a lot cheaper to solve this by a change of attitude. -.. _rpi_patch: https://patchwork.ozlabs.org/project/uboot/patch/20170402082520.32546-1-deymo@google.com/ .. _`TF-A`: https://www.trustedfirmware.org/projects/tf-a .. _`QEMU ARM`: https://github.com/qemu/qemu/blob/master/hw/arm/virt.c .. _`QEMU RISC-V`: https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c From patchwork Tue Dec 7 00:11:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564428 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=BwtfP1dZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LSL2dKqz9sCD for ; Tue, 7 Dec 2021 11:16:18 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 884D4830C3; Tue, 7 Dec 2021 01:14:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="BwtfP1dZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 55000830C8; Tue, 7 Dec 2021 01:13:29 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8CE7B830CA for ; Tue, 7 Dec 2021 01:13:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x333.google.com with SMTP id h19-20020a9d3e53000000b0056547b797b2so15816557otg.4 for ; Mon, 06 Dec 2021 16:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OzUbFLdXacSSwGt+D6IUePwZ7PfhVUUChqBowWm0xdA=; b=BwtfP1dZdt5YszNgq1zzTSZzUBC939gp4uagf71ziUJcmX0hrR7uqcHiBEnGzw3mTM q2fVI1ba/c0iORwuOHyJdTUvsu9M/03Te2ulBLlN4sLJ1g1Cj2E0wbHSTnXzjrfNAEr/ 8HqgNTjya9ce21b+pLZ+Low9vMuu+jQOAcbmY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OzUbFLdXacSSwGt+D6IUePwZ7PfhVUUChqBowWm0xdA=; b=aDo7p+1or/E7q2R4XQYhFEFhe02ShtT5txF24KnuSF5a5uUA1cbwq+R62d/IFwdmko nBIwUezVaNMxCFyCctjFac0JsXSgLWdXTYF7OitlAtfILQ4fAsb2NaTLteZ+bdUnFkTy WjkTTGdwFPlFDWweMAJZM58Kj5Mlo+fH3t9VEkItihze2v08nAQZDk2KMMF6laV21bUu 7liNNwrDEZQwYPfvxhI5BEuJHjGYAL7hCkg8h83sZWzckqLesoUJd/gtpmvnTjyusZC0 GFh3YzO5un0NdbArLn/OSFnxm5C4Ho4Dmf9eSTeQx4dUuD9ZoWTaHu1gja/2ujT+zYb2 P1WQ== X-Gm-Message-State: AOAM531eKCRYcp9Ufg9NIfAbwkcHPJw5jflKGlHzgn+L/iyNI8hVK4Au 0gxASv7x6WMJCYqBKKdGXHAF8n9uBBLukA== X-Google-Smtp-Source: ABdhPJwLUZntgw2LI4XZlXYGV4YabnxdYTx4m7cLWOWt7cyp4ZDCtFNeUa3GIzojWHUkz7lfv2/JCw== X-Received: by 2002:a05:6830:3113:: with SMTP id b19mr32282490ots.9.1638835984058; Mon, 06 Dec 2021 16:13:04 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:03 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 18/31] fdt: Move MULTI_DTB_FIT handling out of fdtdec_setup() Date: Mon, 6 Dec 2021 17:11:56 -0700 Message-Id: <20211207001209.3467163-19-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This logic is a bit convoluted for one function. Move the mulit-FIT part into its own function. Signed-off-by: Simon Glass Reviewed-by: Ilias Apalodimas --- (no changes since v1) lib/fdtdec.c | 62 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 24 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 7681f272d27..e0ce2532f95 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1594,13 +1594,46 @@ __weak int fdtdec_board_setup(const void *fdt_blob) return 0; } +/** + * setup_multi_dtb_fit() - locate the correct dtb from a FIT + * + * This supports the CONFIG_MULTI_DTB_FIT feature, looking for the dtb in a + * supplied FIT + * + * It accepts the current value of gd->fdt_blob, which points to the FIT, then + * updates that gd->fdt_blob, to point to the chosen dtb so that U-Boot uses the + * correct one + */ +static void setup_multi_dtb_fit(void) +{ +# if CONFIG_IS_ENABLED(MULTI_DTB_FIT) + void *blob; + + /* + * Try and uncompress the blob. + * Unfortunately there is no way to know how big the input blob really + * is. So let us set the maximum input size arbitrarily high. 16MB + * ought to be more than enough for packed DTBs. + */ + if (uncompress_blob(gd->fdt_blob, 0x1000000, &blob) == 0) + gd->fdt_blob = blob; + + /* + * Check if blob is a FIT images containings DTBs. + * If so, pick the most relevant + */ + blob = locate_dtb_in_fit(gd->fdt_blob); + if (blob) { + gd->multi_dtb_fit = gd->fdt_blob; + gd->fdt_blob = blob; + } +#endif /* # MULTI_DTB_FIT */ +} + int fdtdec_setup(void) { int ret; #if CONFIG_IS_ENABLED(OF_CONTROL) -# if CONFIG_IS_ENABLED(MULTI_DTB_FIT) - void *fdt_blob; -# endif # ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ # ifdef CONFIG_SPL_BUILD @@ -1621,27 +1654,8 @@ int fdtdec_setup(void) (unsigned long)map_to_sysmem(gd->fdt_blob)), 0); # endif -# if CONFIG_IS_ENABLED(MULTI_DTB_FIT) - /* - * Try and uncompress the blob. - * Unfortunately there is no way to know how big the input blob really - * is. So let us set the maximum input size arbitrarily high. 16MB - * ought to be more than enough for packed DTBs. - */ - if (uncompress_blob(gd->fdt_blob, 0x1000000, &fdt_blob) == 0) - gd->fdt_blob = fdt_blob; - - /* - * Check if blob is a FIT images containings DTBs. - * If so, pick the most relevant - */ - fdt_blob = locate_dtb_in_fit(gd->fdt_blob); - if (fdt_blob) { - gd->multi_dtb_fit = gd->fdt_blob; - gd->fdt_blob = fdt_blob; - } - -# endif + if (CONFIG_IS_ENABLED(MULTI_DTB_FIT)) + setup_multi_dtb_fit(); #endif ret = fdtdec_prepare_fdt(); From patchwork Tue Dec 7 00:11:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564431 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=VKbF92U3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LSx0Qyqz9sCD for ; Tue, 7 Dec 2021 11:16:49 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 87D18834E4; Tue, 7 Dec 2021 01:14:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="VKbF92U3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 44F09833BC; Tue, 7 Dec 2021 01:13:32 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D25AD830BD for ; Tue, 7 Dec 2021 01:13:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x32a.google.com with SMTP id i5-20020a05683033e500b0057a369ac614so15814778otu.10 for ; Mon, 06 Dec 2021 16:13:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iQ60UMX7zDfk5O4ySI4zICPN8m7h1SqhzeaneyuHrn8=; b=VKbF92U35CbSNiCVfXquHt+fMaguHt5hu6rB3nLC7oyPSsE2ssrjaLoUR1Y08KLzgr ljtEqbiSc/96wJeNrKQXLd/QCe22n1p57BOuJfmy6wRFfdJh4ByvkO0EY09mJYtP7Pbu LR5iNLXVqSelpdK1ZvuL5i3T/51ujlPS0ctZQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iQ60UMX7zDfk5O4ySI4zICPN8m7h1SqhzeaneyuHrn8=; b=3YmL1H5Oy5cpkpqpjT3zdGrnQffBIDY71YD+W9vr8Wqe1ctvRR6flRuNJyZNikNXFa 3FpXmX8tI38PSF1ERpQr7sB1+Evjc5jUZOI9rzNQxg9Q/ImO+D3rfeme2350YvLVpC2Q RJCK1SBxfi2gc0PSs6la9/oWQIXgG4URgWc0pqf6fL8cyE+hF9RCYax5PFEpYrHlXmEV hLAiVorzwIlf8Hjz3MxO3J+pyeV2Z70OGTPBAN06kuICtmAz2g739EGdAmeI8gXYGq3v J2P/aR0k+9+cz4x9NbFjYoedck+wvcc9wCyotjbMjvT4NPHpULBv1oBb7yP4uK784pdQ HEUQ== X-Gm-Message-State: AOAM533rpkzxrzPNXSIT8vuTZwzI76aHPhO8ifZMk+SMUZ3TphRcqyU1 TpQ7Bux21fOy5/A/Mu2Qrn20jIcUgpyDeA== X-Google-Smtp-Source: ABdhPJyIrhBl6nf+8Qoy3/ogACG8Ngvh7V5Ok7qWSqMQxFe29i5BT9wHIfJkmzfCg5bNlnbaJ5D9Bg== X-Received: by 2002:a9d:6854:: with SMTP id c20mr33121259oto.190.1638835985186; Mon, 06 Dec 2021 16:13:05 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:04 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 19/31] fdt: Drop #ifdefs with MULTI_DTB_FIT Date: Mon, 6 Dec 2021 17:11:57 -0700 Message-Id: <20211207001209.3467163-20-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Refactor the code to drop the #ifdefs for this feature. Signed-off-by: Simon Glass --- (no changes since v1) dts/Kconfig | 1 - include/asm-generic/global_data.h | 8 ++++++++ lib/fdtdec.c | 31 +++++++++++-------------------- 3 files changed, 19 insertions(+), 21 deletions(-) diff --git a/dts/Kconfig b/dts/Kconfig index 6ebbac2a649..5dcc79d5192 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -177,7 +177,6 @@ endchoice config MULTI_DTB_FIT_UNCOMPRESS_SZ hex "Size of memory reserved to uncompress the DTBs" - depends on (MULTI_DTB_FIT_GZIP || MULTI_DTB_FIT_LZO) default 0x8000 help This is the size of this area where the DTBs are uncompressed. diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 16fd305a65c..99daa20c765 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -512,6 +512,14 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_acpi_ctx() NULL #endif +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) +#define gd_multi_dtb_fit() gd->multi_dtb_fit +#define gd_set_multi_dtb_fit(_dtb) gd->multi_dtb_fit = _dtb +#else +#define gd_multi_dtb_fit() NULL +#define gd_set_multi_dtb_fit(_dtb) +#endif + /** * enum gd_flags - global data flags * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index e0ce2532f95..4967ab87075 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1146,11 +1146,10 @@ int fdtdec_setup_mem_size_base_lowest(void) return 0; } -#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) -# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\ - CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO) static int uncompress_blob(const void *src, ulong sz_src, void **dstp) { +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\ + CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO) size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ); bool gzip = 0, lzo = 0; ulong sz_in = sz_src; @@ -1175,11 +1174,11 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp) return -ENOMEM; } } else { -# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA) +# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA) dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR); -# else +# else return -ENOTSUPP; -# endif +# endif } if (CONFIG_IS_ENABLED(GZIP) && gzip) @@ -1197,16 +1196,12 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp) return -EBADMSG; } *dstp = dst; - return 0; -} -# else -static int uncompress_blob(const void *src, ulong sz_src, void **dstp) -{ +#else + *dstp = (void *)src; *dstp = (void *)src; +#endif return 0; } -# endif -#endif #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) /* @@ -1606,7 +1601,6 @@ __weak int fdtdec_board_setup(const void *fdt_blob) */ static void setup_multi_dtb_fit(void) { -# if CONFIG_IS_ENABLED(MULTI_DTB_FIT) void *blob; /* @@ -1624,10 +1618,9 @@ static void setup_multi_dtb_fit(void) */ blob = locate_dtb_in_fit(gd->fdt_blob); if (blob) { - gd->multi_dtb_fit = gd->fdt_blob; + gd_set_multi_dtb_fit(gd->fdt_blob); gd->fdt_blob = blob; } -#endif /* # MULTI_DTB_FIT */ } int fdtdec_setup(void) @@ -1664,7 +1657,6 @@ int fdtdec_setup(void) return ret; } -#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) int fdtdec_resetup(int *rescan) { void *fdt_blob; @@ -1675,8 +1667,8 @@ int fdtdec_resetup(int *rescan) * FIT image stillpresent there. Save the time and space * required to uncompress it again. */ - if (gd->multi_dtb_fit) { - fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit); + if (gd_multi_dtb_fit()) { + fdt_blob = locate_dtb_in_fit(gd_multi_dtb_fit()); if (fdt_blob == gd->fdt_blob) { /* @@ -1700,7 +1692,6 @@ int fdtdec_resetup(int *rescan) *rescan = 0; return 0; } -#endif int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, From patchwork Tue Dec 7 00:11:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564429 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=iWJOC92O; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LSY05yzz9sCD for ; Tue, 7 Dec 2021 11:16:28 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 53BC1834E6; Tue, 7 Dec 2021 01:14:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="iWJOC92O"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9F8A0830DC; Tue, 7 Dec 2021 01:13:30 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F035D830C5 for ; Tue, 7 Dec 2021 01:13:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x335.google.com with SMTP id x43-20020a056830246b00b00570d09d34ebso15864628otr.2 for ; Mon, 06 Dec 2021 16:13:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XZnp+w6kXLquv/pv588ZLdIWOMoe/x4ctprXZQfzpMM=; b=iWJOC92OyUzcgJNH75Nwc9EZVve23g+tU9WjU3VC1eof2WLtQFX71mjdgX0SogmYJd M3TCLJGk5khXk1m60GFOWb5MED7nKOXyC/rU2lMI5me+z7Fer2ZXu3ZxAx6f06hWtkJV QYbm/NI2Wn8+nSVX0Pi8GSCnbaaki6jFooDpo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XZnp+w6kXLquv/pv588ZLdIWOMoe/x4ctprXZQfzpMM=; b=3pnazJp979Rcy1gsqc2+Z3BZ92FpKO6In0/9E+otd1Z/jUXDv7wKFP15jukGb0Eofg iPT6NnllR3vKa4fqRUwwk3kn2vam1+iZjTaRWn3JQK9YvC0p0L72z0/ymdxrrwA2b4sT EAQnb8eUKIAmKmhOEVwWwyfNrtQa3GMUgcXTDqvIEZAAYaWQYdR8svErpLwZROzVqLbS SVnA2UVTrkW+MiFIhQ479M7qhn0EWzO7M9UpRvCJmeL+0x1NuySIekF+ymfADzjiy4XK a0oOKXCpqPj+/TmLcEyYX2UHBMVamWR04hPkZG0uu3K6KRzsxnudm6vdvQFcD+1bR56e Q8oA== X-Gm-Message-State: AOAM532oFMAAU0HUSU9QIfC7SmN4xZFIHPrvhpeYqTHtNoruP1ltkys2 cek9t7L1MZJ/zHfpdPDM/WLW+nhl07NlnA== X-Google-Smtp-Source: ABdhPJyxXNbCRO8TwuOl1sd0F1ZHssK/Mn3tYrOrRAZ53RHhBno/T0FdmP1uzvm6VozBAhTlRsxDBQ== X-Received: by 2002:a05:6830:1da:: with SMTP id r26mr32222926ota.73.1638835986344; Mon, 06 Dec 2021 16:13:06 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:05 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 20/31] fdt: Drop CONFIG_SPL_BUILD check in fdtdec_setup() Date: Mon, 6 Dec 2021 17:11:58 -0700 Message-Id: <20211207001209.3467163-21-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Move this to the header file to clean up the C code. Signed-off-by: Simon Glass --- (no changes since v1) include/fdtdec.h | 14 ++++++++++++++ lib/fdtdec.c | 6 +----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 6c7ab887b20..68786111a44 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -111,6 +111,20 @@ struct fdt_pci_addr { extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ +/* Get a pointer to the embedded devicetree, if there is one, else NULL */ +static inline u8 *dtb_dt_embedded(void) +{ +#ifdef CONFIG_OF_EMBED +# ifdef CONFIG_SPL_BUILD + return __dtb_dt_spl_begin; +# else + return __dtb_dt_begin; +# endif +#else + return NULL; +#endif +} + /** * Compute the size of a resource. * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4967ab87075..fbdc92c0813 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1629,11 +1629,7 @@ int fdtdec_setup(void) #if CONFIG_IS_ENABLED(OF_CONTROL) # ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ -# ifdef CONFIG_SPL_BUILD - gd->fdt_blob = __dtb_dt_spl_begin; -# else - gd->fdt_blob = __dtb_dt_begin; -# endif + gd->fdt_blob = dtb_dt_embedded(); # elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) /* Allow the board to override the fdt address. */ gd->fdt_blob = board_fdt_blob_setup(&ret); From patchwork Tue Dec 7 00:11:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564430 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=IMBlktIe; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LSl0jDgz9sCD for ; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:07 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 21/31] fdt: Drop #ifdef around board_fdt_blob_setup() Date: Mon, 6 Dec 2021 17:11:59 -0700 Message-Id: <20211207001209.3467163-22-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This serves no purpose. Drop it. Signed-off-by: Simon Glass --- (no changes since v1) lib/fdtdec.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index fbdc92c0813..299a2c3a32f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1203,7 +1203,6 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp) return 0; } -#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) /* * For CONFIG_OF_SEPARATE, the board may optionally implement this to * provide and/or fixup the fdt. @@ -1226,7 +1225,6 @@ __weak void *board_fdt_blob_setup(int *err) return fdt_blob; } -#endif int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size) { From patchwork Tue Dec 7 00:12:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564432 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=VkVAQeQa; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LT73ZkMz9sCD for ; Tue, 7 Dec 2021 11:16:59 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1D0FC8361E; Tue, 7 Dec 2021 01:14:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="VkVAQeQa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3C42983095; Tue, 7 Dec 2021 01:13:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0B4CA830DD for ; Tue, 7 Dec 2021 01:13:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x32e.google.com with SMTP id i5-20020a05683033e500b0057a369ac614so15814940otu.10 for ; Mon, 06 Dec 2021 16:13:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/QLKlN640lGwIHFGyTJw9DBMrKNULJX4jga8HNn3IX0=; b=VkVAQeQaWH2udWO36I1nC45c+VCSx6LtS80tJ/jyrZ+uCNcxbejFK3CosNoRgU9E1c nuAAulrOUDFRNlXGaLMa+caxc3yJ41nO03QaV8JBtzMe2k/nSaxeVyBSQ1s5NKYu1kzO 1wAh3HUOAxd2UzmAfHL9NoDm7iN6082z/f9Ig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/QLKlN640lGwIHFGyTJw9DBMrKNULJX4jga8HNn3IX0=; b=NkyPdRRlYBGHeCo11pEEEQUjdZxdCa8mjOTQuEFkH6mD7HPDOFEj2x4GDSLShnoZYz mdyB6Ng4ECTCrrfGqS9KM8hCywxHA/dYt0vdxNldLjQE9O5yDfxN9Oim9dMZ7FXVnW5x s+L/uwhV1SHxgAku+Y2fFd33RTebO9qjXGZsvogbPbefJwr/AQHnzK2A00D/k4xZTBvY wQbjFSKrIT00BdUY+w+xjL9zkSPrmZqphBF5mCtZgBxefk5PcG5THDgdvIPXlweVA6EJ yq9LhhNrtn7MNgwu/TJdX5nMJMAo/hRVxkUfBByA70MCjD+fUmQ3FMeDsYxZKPFeCaHI maLA== X-Gm-Message-State: AOAM531hiHXTsFC+j+DF55kevjOWcJ03JzVVellRvSNl9ucxv2Wa/7wq Y9B0iFHNwKv4DkdqoSsFPXy06voXPiksqA== X-Google-Smtp-Source: ABdhPJwfj8dKzoDHQyiv47xsnRQTDQaOgYjUoT7Ser37FFs0rhdnlfuBNdg1+oRQupG0rQNCrJOYqg== X-Received: by 2002:a05:6830:22ca:: with SMTP id q10mr33149131otc.275.1638835988527; Mon, 06 Dec 2021 16:13:08 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:08 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 22/31] fdt: Use if() for fdtcontroladdr check Date: Mon, 6 Dec 2021 17:12:00 -0700 Message-Id: <20211207001209.3467163-23-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Change this to use if() instead of #if Signed-off-by: Simon Glass --- (no changes since v1) lib/fdtdec.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 299a2c3a32f..659aeffd82e 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1634,12 +1634,11 @@ int fdtdec_setup(void) if (ret) return ret; # endif -# ifndef CONFIG_SPL_BUILD - /* Allow the early environment to override the fdt address */ - gd->fdt_blob = map_sysmem - (env_get_ulong("fdtcontroladdr", 16, + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Allow the early environment to override the fdt address */ + gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16, (unsigned long)map_to_sysmem(gd->fdt_blob)), 0); -# endif + } if (CONFIG_IS_ENABLED(MULTI_DTB_FIT)) setup_multi_dtb_fit(); From patchwork Tue Dec 7 00:12:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564435 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=W+goFSLL; dkim-atps=neutral Authentication-Results: ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:09 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 23/31] fdt: Drop OF_CONTROL check in fdtdec_setup() Date: Mon, 6 Dec 2021 17:12:01 -0700 Message-Id: <20211207001209.3467163-24-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This function should only be called when OF_CONTROL is enabled. It fails in fdtdec_prepare_fdt() anyway, since gd->fdt_blob stays as NULL if OF_CONTROL is not enabled. Drop this useless check. Signed-off-by: Simon Glass --- (no changes since v1) lib/fdtdec.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 659aeffd82e..5b31064cee2 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1624,16 +1624,15 @@ static void setup_multi_dtb_fit(void) int fdtdec_setup(void) { int ret; -#if CONFIG_IS_ENABLED(OF_CONTROL) -# ifdef CONFIG_OF_EMBED +#ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ gd->fdt_blob = dtb_dt_embedded(); -# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) +#elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) /* Allow the board to override the fdt address. */ gd->fdt_blob = board_fdt_blob_setup(&ret); if (ret) return ret; -# endif +#endif if (!IS_ENABLED(CONFIG_SPL_BUILD)) { /* Allow the early environment to override the fdt address */ gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16, @@ -1642,7 +1641,6 @@ int fdtdec_setup(void) if (CONFIG_IS_ENABLED(MULTI_DTB_FIT)) setup_multi_dtb_fit(); -#endif ret = fdtdec_prepare_fdt(); if (!ret) From patchwork Tue Dec 7 00:12:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564434 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=kKF4pjZP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LTZ3Bs5z9sCD for ; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:10 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 24/31] fdt: Drop remaining preprocessor macros in fdtdec_setup() Date: Mon, 6 Dec 2021 17:12:02 -0700 Message-Id: <20211207001209.3467163-25-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean We only have two choices for obtaining the devicetree. Simplify the code to make that clear. Signed-off-by: Simon Glass --- (no changes since v1) lib/fdtdec.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5b31064cee2..a7f62123a94 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1624,15 +1624,17 @@ static void setup_multi_dtb_fit(void) int fdtdec_setup(void) { int ret; -#ifdef CONFIG_OF_EMBED - /* Get a pointer to the FDT */ - gd->fdt_blob = dtb_dt_embedded(); -#elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) - /* Allow the board to override the fdt address. */ - gd->fdt_blob = board_fdt_blob_setup(&ret); - if (ret) - return ret; -#endif + + /* The devicetree is typically appended to U-Boot */ + if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { + /* Allow the board to override the fdt address. */ + gd->fdt_blob = board_fdt_blob_setup(&ret); + if (ret) + return ret; + } else { /* embed dtb in ELF file for testing / development */ + gd->fdt_blob = dtb_dt_embedded(); + } + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { /* Allow the early environment to override the fdt address */ gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16, From patchwork Tue Dec 7 00:12:03 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:11 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 25/31] fdt: Don't call board_fdt_blob_setup() without OF_BOARD Date: Mon, 6 Dec 2021 17:12:03 -0700 Message-Id: <20211207001209.3467163-26-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean At present this override function is called even when OF_BOARD is not enabled. This makes it impossible to disable this feature and in fact makes the OF_BOARD option useless. Reinstate its intended purpose, so that it is possible to switch between the appended devicetree and one provided by the board's custom function. Signed-off-by: Simon Glass --- Changes in v7: - Fix 'Is' typo in commit message Changes in v5: - Add new patches to clean up fdtdec_setup() and surrounds include/fdtdec.h | 7 +++++-- lib/fdtdec.c | 21 ++++++++++++--------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 68786111a44..68a36f10583 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1170,10 +1170,13 @@ int fdtdec_resetup(int *rescan); /** * Board-specific FDT initialization. Returns the address to a device tree blob. - * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined - * and the board implements it. + * + * Called when CONFIG_OF_BOARD is defined. + * + * The existing devicetree is available at gd->fdt_blob * * @err internal error code if we fail to setup a DTB + * @returns new devicetree blob pointer */ void *board_fdt_blob_setup(int *err); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index a7f62123a94..31a509bc221 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1203,15 +1203,15 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp) return 0; } -/* - * For CONFIG_OF_SEPARATE, the board may optionally implement this to - * provide and/or fixup the fdt. +/** + * fdt_find_separate() - Find a devicetree at the end of the image + * + * @return pointer to FDT blob */ -__weak void *board_fdt_blob_setup(int *err) +static void *fdt_find_separate(void) { void *fdt_blob = NULL; - *err = 0; #ifdef CONFIG_SPL_BUILD /* FDT is at end of BSS unless it is in a different memory region */ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) @@ -1626,13 +1626,16 @@ int fdtdec_setup(void) int ret; /* The devicetree is typically appended to U-Boot */ - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - /* Allow the board to override the fdt address. */ + if (IS_ENABLED(CONFIG_OF_SEPARATE)) + gd->fdt_blob = fdt_find_separate(); + else /* embed dtb in ELF file for testing / development */ + gd->fdt_blob = dtb_dt_embedded(); + + /* Allow the board to override the fdt address. */ + if (IS_ENABLED(CONFIG_OF_BOARD)) { gd->fdt_blob = board_fdt_blob_setup(&ret); if (ret) return ret; - } else { /* embed dtb in ELF file for testing / development */ - gd->fdt_blob = dtb_dt_embedded(); } if (!IS_ENABLED(CONFIG_SPL_BUILD)) { From patchwork Tue Dec 7 00:12:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564440 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:12 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Marek Vasut , Pavel Herrmann Subject: [PATCH v7 26/31] dm: core: Allow getting some basic stats Date: Mon, 6 Dec 2021 17:12:04 -0700 Message-Id: <20211207001209.3467163-27-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add a function that returns some basic stats about driver model. For now we only have two. Signed-off-by: Simon Glass --- (no changes since v1) drivers/core/device.c | 11 ++++++++++ drivers/core/root.c | 7 ++++++ drivers/core/uclass.c | 13 ++++++++++++ include/dm/device.h | 11 +++++++++- include/dm/root.h | 8 +++++++ include/dm/uclass-internal.h | 7 ++++++ test/dm/core.c | 41 ++++++++++++++++++++++++++++++++++++ 7 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/core/device.c b/drivers/core/device.c index 74374ff881c..4873c47d10b 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -739,6 +739,17 @@ int device_get_child_count(const struct udevice *parent) return count; } +int device_get_decendent_count(const struct udevice *parent) +{ + const struct udevice *dev; + int count = 1; + + list_for_each_entry(dev, &parent->child_head, sibling_node) + count += device_get_decendent_count(dev); + + return count; +} + int device_find_child_by_seq(const struct udevice *parent, int seq, struct udevice **devp) { diff --git a/drivers/core/root.c b/drivers/core/root.c index 26b8195faa3..815173f86eb 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -407,6 +408,12 @@ int dm_init_and_scan(bool pre_reloc_only) return 0; } +void dm_get_stats(int *device_countp, int *uclass_countp) +{ + *device_countp = device_get_decendent_count(gd->dm_root); + *uclass_countp = uclass_get_count(); +} + #ifdef CONFIG_ACPIGEN static int root_acpi_get_name(const struct udevice *dev, char *out_name) { diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 2aa21430775..336ea8d243d 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -643,6 +643,19 @@ int uclass_next_device_check(struct udevice **devp) return device_probe(*devp); } +int uclass_get_count(void) +{ + const struct uclass *uc; + int count = 0; + + if (gd->dm_root) { + list_for_each_entry(uc, gd->uclass_root, sibling_node) + count++; + } + + return count; +} + int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data, struct udevice **devp) { diff --git a/include/dm/device.h b/include/dm/device.h index daf28a0a457..19d37e0e76c 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -593,7 +593,7 @@ int device_get_child(const struct udevice *parent, int index, struct udevice **devp); /** - * device_get_child_count() - Get the available child count of a device + * device_get_child_count() - Get the child count of a device * * Returns the number of children to a device. * @@ -601,6 +601,15 @@ int device_get_child(const struct udevice *parent, int index, */ int device_get_child_count(const struct udevice *parent); +/** + * device_get_decendent_count() - Get the total number of decendents of a device + * + * Returns the total number of decendents, including all children + * + * @parent: Parent device to check + */ +int device_get_decendent_count(const struct udevice *parent); + /** * device_find_child_by_seq() - Find a child device based on a sequence * diff --git a/include/dm/root.h b/include/dm/root.h index 42510b106ab..780f269db65 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -131,4 +131,12 @@ int dm_remove_devices_flags(uint flags); static inline int dm_remove_devices_flags(uint flags) { return 0; } #endif +/** + * dm_get_stats() - Get some stats for driver mode + * + * @device_countp: Returns total number of devices that are bound + * @uclass_countp: Returns total number of uclasses in use + */ +void dm_get_stats(int *device_countp, int *uclass_countp); + #endif diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index 49808c5c856..fb0edcc2969 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -306,6 +306,13 @@ int uclass_pre_remove_device(struct udevice *dev); static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; } #endif +/** + * uclass_get_count() - Get the number of uclasses + * + * Returns the number of uclasses instantiated in driver model + */ +int uclass_get_count(void); + /** * uclass_find() - Find uclass by its id * diff --git a/test/dm/core.c b/test/dm/core.c index c9a7606666c..c76dfdb1651 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -307,11 +307,15 @@ static int dm_test_lifecycle(struct unit_test_state *uts) { int op_count[DM_TEST_OP_COUNT]; struct udevice *dev, *test_dev; + int start_dev_count, start_uc_count; + int dev_count, uc_count; int pingret; int ret; memcpy(op_count, dm_testdrv_op_count, sizeof(op_count)); + dm_get_stats(&start_dev_count, &start_uc_count); + ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual, &dev)); ut_assert(dev); @@ -319,6 +323,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts) == op_count[DM_TEST_OP_BIND] + 1); ut_assert(!dev_get_priv(dev)); + /* We should have one more device */ + dm_get_stats(&dev_count, &uc_count); + ut_asserteq(start_dev_count + 1, dev_count); + ut_asserteq(start_uc_count, uc_count); + /* Probe the device - it should fail allocating private data */ uts->force_fail_alloc = 1; ret = device_probe(dev); @@ -353,6 +362,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts) ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]); + /* We should have one less device */ + dm_get_stats(&dev_count, &uc_count); + ut_asserteq(start_dev_count, dev_count); + ut_asserteq(start_uc_count, uc_count); + return 0; } DM_TEST(dm_test_lifecycle, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST); @@ -526,17 +540,31 @@ DM_TEST(dm_test_leak, 0); /* Test uclass init/destroy methods */ static int dm_test_uclass(struct unit_test_state *uts) { + int dev_count, uc_count; struct uclass *uc; + /* We should have just the root device and uclass */ + dm_get_stats(&dev_count, &uc_count); + ut_asserteq(1, dev_count); + ut_asserteq(1, uc_count); + ut_assertok(uclass_get(UCLASS_TEST, &uc)); ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); ut_assert(uclass_get_priv(uc)); + dm_get_stats(&dev_count, &uc_count); + ut_asserteq(1, dev_count); + ut_asserteq(2, uc_count); + ut_assertok(uclass_destroy(uc)); ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); + dm_get_stats(&dev_count, &uc_count); + ut_asserteq(1, dev_count); + ut_asserteq(1, uc_count); + return 0; } DM_TEST(dm_test_uclass, 0); @@ -1217,3 +1245,16 @@ static int dm_test_dma_offset(struct unit_test_state *uts) } DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); #endif + +/* Test dm_get_stats() */ +static int dm_test_get_stats(struct unit_test_state *uts) +{ + int dev_count, uc_count; + + dm_get_stats(&dev_count, &uc_count); + ut_assert(dev_count > 50); + ut_assert(uc_count > 30); + + return 0; +} +DM_TEST(dm_test_get_stats, UT_TESTF_SCAN_FDT); From patchwork Tue Dec 7 00:12:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564439 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=CYMXG4HX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:13 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 27/31] fdt: Record where the devicetree came from Date: Mon, 6 Dec 2021 17:12:05 -0700 Message-Id: <20211206171107.v7.27.I60f02bbc201166267fc11bf3159d1a93764d201f@changeid> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Keep track of where the devicetree came from, so we can report this later. Signed-off-by: Simon Glass --- Changes in v7: - Drop FDTSRC_PASSAGE for now include/asm-generic/global_data.h | 4 ++++ include/fdtdec.h | 32 +++++++++++++++++++++++++++++++ lib/fdtdec.c | 20 ++++++++++++++----- 3 files changed, 51 insertions(+), 5 deletions(-) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 99daa20c765..104282bd479 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -244,6 +244,10 @@ struct global_data { * @fdt_size: space reserved for relocated device space */ unsigned long fdt_size; + /** + * @fdt_src: Source of FDT + */ + enum fdt_source_t fdt_src; #if CONFIG_IS_ENABLED(OF_LIVE) /** * @of_root: root node of the live tree diff --git a/include/fdtdec.h b/include/fdtdec.h index 68a36f10583..09525ce510a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -55,6 +55,31 @@ struct bd_info; #define SPL_BUILD 0 #endif +/** + * enum fdt_source_t - indicates where the devicetree came from + * + * These are listed in approximate order of desirability after FDTSRC_NONE + * + * @FDTSRC_SEPARATE: Appended to U-Boot. This is the normal approach if U-Boot + * is the only firmware being booted + * @FDTSRC_FIT: Found in a multi-dtb FIT. This should be used when U-Boot must + * select a devicetree from many options + * @FDTSRC_BOARD: Located by custom board code. This should only be used when + * the prior stage does not support FDTSRC_PASSAGE + * @FDTSRC_EMBED: Embedded into U-Boot executable. This should onyl be used when + * U-Boot is packaged as an ELF file, e.g. for debugging purposes + * @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should + * be used for debugging/development only + * @FDTSRC_NONE: No devicetree at all + */ +enum fdt_source_t { + FDTSRC_SEPARATE, + FDTSRC_FIT, + FDTSRC_BOARD, + FDTSRC_EMBED, + FDTSRC_ENV, +}; + /* * Information about a resource. start is the first address of the resource * and end is the last address (inclusive). The length of the resource will @@ -1215,4 +1240,11 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, struct bd_info *bd); +/** + * fdtdec_get_srcname() - Get the name of where the devicetree comes from + * + * @return source name + */ +const char *fdtdec_get_srcname(void); + #endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 31a509bc221..8cfa958fb96 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1618,6 +1618,7 @@ static void setup_multi_dtb_fit(void) if (blob) { gd_set_multi_dtb_fit(gd->fdt_blob); gd->fdt_blob = blob; + gd->fdt_src = FDTSRC_FIT; } } @@ -1626,22 +1627,31 @@ int fdtdec_setup(void) int ret; /* The devicetree is typically appended to U-Boot */ - if (IS_ENABLED(CONFIG_OF_SEPARATE)) + if (IS_ENABLED(CONFIG_OF_SEPARATE)) { gd->fdt_blob = fdt_find_separate(); - else /* embed dtb in ELF file for testing / development */ + gd->fdt_src = FDTSRC_SEPARATE; + } else { /* embed dtb in ELF file for testing / development */ gd->fdt_blob = dtb_dt_embedded(); + gd->fdt_src = FDTSRC_EMBED; + } /* Allow the board to override the fdt address. */ if (IS_ENABLED(CONFIG_OF_BOARD)) { gd->fdt_blob = board_fdt_blob_setup(&ret); if (ret) return ret; + gd->fdt_src = FDTSRC_BOARD; } + /* Allow the early environment to override the fdt address */ if (!IS_ENABLED(CONFIG_SPL_BUILD)) { - /* Allow the early environment to override the fdt address */ - gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16, - (unsigned long)map_to_sysmem(gd->fdt_blob)), 0); + ulong addr; + + addr = env_get_hex("fdtcontroladdr", 0); + if (addr) { + gd->fdt_blob = map_sysmem(addr, 0); + gd->fdt_src = FDTSRC_ENV; + } } if (CONFIG_IS_ENABLED(MULTI_DTB_FIT)) From patchwork Tue Dec 7 00:12:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564436 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:15 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 28/31] fdt: Report the devicetree source Date: Mon, 6 Dec 2021 17:12:06 -0700 Message-Id: <20211207001209.3467163-28-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean It can be confusing to figure out where the devicetree came from. It seems important enough to warrant a message during boot. Add information about the number of devices and uclasses too since it is helpful to have some idea what is going on with driver model. Report the devicetree source in bdinfo too. This looks something like this, with > marking the new line. U-Boot 2021.10-00190 (Oct 30 2021 - 09:01:29 -0600) DRAM: 128 MiB > Core: 42 devices, 11 uclasses, devicetree: passage Flash: 64 MiB Signed-off-by: Simon Glass --- Changes in v7: - Drop FDTSRC_PASSAGE for now cmd/bdinfo.c | 2 ++ common/board_r.c | 18 ++++++++++++++++++ lib/fdtdec.c | 13 +++++++++++++ 3 files changed, 33 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index bf63cc6d649..c56b3f4f6ec 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -128,6 +128,8 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); lmb_dump_all_force(&lmb); + if (IS_ENABLED(CONFIG_OF_REAL)) + printf("devicetree = %s\n", fdtdec_get_srcname()); } arch_print_bdinfo(); diff --git a/common/board_r.c b/common/board_r.c index 31a59c585a8..99adff14b39 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -586,6 +586,23 @@ int initr_mem(void) } #endif +static int dm_announce(void) +{ + int device_count; + int uclass_count; + + if (IS_ENABLED(CONFIG_DM)) { + dm_get_stats(&device_count, &uclass_count); + printf("Core: %d devices, %d uclasses", device_count, + uclass_count); + if (CONFIG_IS_ENABLED(OF_REAL)) + printf(", devicetree: %s", fdtdec_get_srcname()); + printf("\n"); + } + + return 0; +} + static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -661,6 +678,7 @@ static init_fnc_t init_sequence_r[] = { stdio_init_tables, serial_initialize, initr_announce, + dm_announce, #if CONFIG_IS_ENABLED(WDT) initr_watchdog, #endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 8cfa958fb96..118c100b389 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -76,6 +76,19 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init") }; +static const char *const fdt_src_name[] = { + [FDTSRC_SEPARATE] = "separate", + [FDTSRC_FIT] = "fit", + [FDTSRC_BOARD] = "board", + [FDTSRC_EMBED] = "embed", + [FDTSRC_ENV] = "env", +}; + +const char *fdtdec_get_srcname(void) +{ + return fdt_src_name[gd->fdt_src]; +} + const char *fdtdec_get_compatible(enum fdt_compat_id id) { /* We allow reading of the 'unknown' ID for testing purposes */ From patchwork Tue Dec 7 00:12:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564438 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Q+7Da/Uv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LVQ2cLNz9sCD for ; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:16 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 29/31] fdt: Add a Kconfig for boards with a prior stage Date: Mon, 6 Dec 2021 17:12:07 -0700 Message-Id: <20211207001209.3467163-29-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean When U-Boot is started from another firmware program, not just a prior phase of U-Boot, special behaviour is typically used. In particular, the device tree may come from that prior stage. At present this is sort-of indicated by OF_BOARD, although the correlation is not 1:1, since that option simply means that the board has a custom mechanism for obtaining the device tree. For example, sandbox defines OF_BOARD. Also the board_fdt_blob_setup() function can in fact make use of the devicetree in U-Boot if it wishes, as used by dragonboard410c until very recently. Add an explicit Kconfig for this situation. Define it for boards which use this feature. Update the OF_BOARD option to more-accurately reflect what it is doing, e.g. for sandbox. Signed-off-by: Simon Glass --- Changes in v7: - Add new patch to add a Kconfig for boards with a prior stage arch/arm/Kconfig | 8 ++++++++ arch/arm/mach-bcm283x/Kconfig | 1 + board/emulation/qemu-riscv/Kconfig | 1 + dts/Kconfig | 31 ++++++++++++++++++++++++++---- lib/fdtdec.c | 1 + 5 files changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eed27af74e8..d26461029af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -635,6 +635,7 @@ config ARCH_BCMSTB select GPIO_EXTRA_HEADER select OF_CONTROL imply CMD_DM + imply OF_HAS_PRIOR_STAGE help This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips. @@ -713,6 +714,7 @@ config ARCH_HIGHBANK select AHCI select DM_ETH select PHYS_64BIT + imply OF_HAS_PRIOR_STAGE config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" @@ -966,6 +968,7 @@ config ARCH_QEMU imply DM_RNG imply DM_RTC imply RTC_PL031 + imply OF_HAS_PRIOR_STAGE config ARCH_RMOBILE bool "Renesas ARM SoCs" @@ -1251,6 +1254,7 @@ config TARGET_VEXPRESS64_JUNO select DM_ETH select BLK select USB + imply OF_HAS_PRIOR_STAGE config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" @@ -1907,6 +1911,7 @@ config ARCH_OCTEONTX select OF_LIVE select BOARD_LATE_INIT select SYS_CACHE_SHIFT_7 + imply OF_HAS_PRIOR_STAGE config ARCH_OCTEONTX2 bool "Support OcteonTX2 SoCs" @@ -1918,6 +1923,7 @@ config ARCH_OCTEONTX2 select OF_LIVE select BOARD_LATE_INIT select SYS_CACHE_SHIFT_7 + imply OF_HAS_PRIOR_STAGE config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" @@ -1954,6 +1960,8 @@ config TARGET_XENGUEST_ARM64 select LINUX_KERNEL_IMAGE_HEADER select XEN_SERIAL select SSCANF + imply OF_HAS_PRIOR_STAGE + endchoice config SUPPORT_PASSING_ATAGS diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index b3287ce8bce..2eb3802d9ae 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -188,6 +188,7 @@ config TARGET_RPI_4 This option creates a build targeting the ARMv8/AArch64 ISA. select BCM2711_64B + imply OF_HAS_PRIOR_STAGE config TARGET_RPI_ARM64 bool "Raspberry Pi one binary 64-bit build" diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 1bbf1bc84af..a380db61a0f 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -65,5 +65,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply VIRTIO_BLK imply MTD_NOR_FLASH imply CFI_FLASH + imply OF_HAS_PRIOR_STAGE endif diff --git a/dts/Kconfig b/dts/Kconfig index 5dcc79d5192..803d0899556 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -100,11 +100,34 @@ config OF_BOARD bool "Provided by the board (e.g a previous loader) at runtime" default y if SANDBOX help - If this option is enabled, the device tree will be provided by - the board at runtime if the board supports it. The device tree bundled - with the image (if any) will be overridden / ignored. + If this option is enabled, the device tree is provided at runtime by + a custom function called board_fdt_blob_setup(). The board must + implement this function if it wishes to provide special behaviour. - A device tree file must be provided in the tree. + With this option, the device tree build by U-Boot may be overridden or + ignored. See OF_HAS_PRIOR_STAGE. + + Note: Boards which use this to handle a device tree passed from an + earlier stage should enable OF_HAS_PRIOR_STAGE. + +config OF_HAS_PRIOR_STAGE + bool + help + Indicates that a prior stage of the firmware (before U-Boot proper) + makes use of device tree and this board normally boots with that prior + stage, that provides a devicetree to U-Boot. + + This means that the device tree built in U-Boot should not be packaged + in the firmware image. Instead, the prior stage's device tree should + be so packaged. At runtime, the prior stage reads this, does any + necessary fix-ups, then passes it to U-Boot. See OF_BOARD. + + This option does not preclude using the U-Boot device tree, e.g. for + development purposes, but it is not recommended, and likely will not + even work, for production systems. + + Note: This option must be set in Kconfig and cannot be enabled or + disabled in the board's defconfig file. config DEFAULT_DEVICE_TREE string "Default Device Tree for DT control" diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 118c100b389..280cda61a72 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1595,6 +1595,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, return 0; } +/* TODO(sjg@chromium.org): This function should not be weak */ __weak int fdtdec_board_setup(const void *fdt_blob) { return 0; From patchwork Tue Dec 7 00:12:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564441 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=RQDJU90/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LW62Fbdz9sCD for ; Tue, 7 Dec 2021 11:18:42 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AAEAB8376D; Tue, 7 Dec 2021 01:15:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="RQDJU90/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3A40B83093; Tue, 7 Dec 2021 01:13:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3AFD9830B7 for ; Tue, 7 Dec 2021 01:13:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-ot1-x32c.google.com with SMTP id h19-20020a9d3e53000000b0056547b797b2so15817172otg.4 for ; Mon, 06 Dec 2021 16:13:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XsSvHFo0P+Jddocb1rOmLF9vxeDqzIOOa55PsmqPWyE=; b=RQDJU90/V58+qYy0G8pzuJiRIm1BFtGkH+nzCG4RQ5+0qJE09Kvjcxws5fsG2Xsnvq fYSL4L8mebMdZLrYSlCblAnKiwQj8CMLz1OpO9cjHciO/TstCXXnbtCIa6FckvccwblL cpf+2OmFLLzF5mafw3yusQSj6cImVa5A9b62E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XsSvHFo0P+Jddocb1rOmLF9vxeDqzIOOa55PsmqPWyE=; b=R3gvc42krFbSWYgsTDqlZH9gMxPP9qgILlIJndhDlgYkBLPiaGCqhdr9hHnJqug4cg rdTZOodn5cEL9kbnVzPcTWSTejvsCY7j610AmqZEiYRrasyjXUjJYTupOH6kaQCp1gkc 0M/bgBWci/+SAUQrULCR0Ik4RsOCt4WsNy54pYZ+TplR+lHApKvjFcRBYu5p8WgUnYc2 GrRwAZ286vR3ZdALq3pvhVSSxDYBvkF/vlidcBBCi86nRTPVfx9oXVvDNh+Mav0ENoiU wJI1C1gMryhTej0TH2V7JNw6okHea+KoXwIJAyZyoS7+iaO60r7RoPdU7HAOGn8Ekw05 H/sg== X-Gm-Message-State: AOAM533YhG44LmT3WwCeGof8hgLRaq2QPgaSsBxf1ZzD4FaMyqiw1QaR aRreyMpcrvNAQTGKF2EgF9THeTJnSN2bYA== X-Google-Smtp-Source: ABdhPJxGEvjvfr6/zsMJdxOSPkAC2Gr7miupu5TICQy+phJUR2CPafpm9nJ9R+UtRxzsrU2Vgry4UQ== X-Received: by 2002:a9d:d08:: with SMTP id 8mr33266329oti.334.1638835997755; Mon, 06 Dec 2021 16:13:17 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:17 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 30/31] fdt: Avoid emitting an device tree when not needed Date: Mon, 6 Dec 2021 17:12:08 -0700 Message-Id: <20211207001209.3467163-30-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean U-Boot always needs some sort of a device tree. Some boards never actually use this, at least in production systems, since a prior firmware stage sets one up and passes it to U-Boot. At present the only mechanism to do that is with custom function (OF_BOARD), but future work will include a standard way of doing this ('standard passage'). It can be confusing to see a device tree emitted from the U-Boot build in this situation. Add an option to drop it. Signed-off-by: Simon Glass --- (no changes since v1) Makefile | 6 +++++- dts/Kconfig | 10 ++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6671c5d9e2f..a3f018f01e0 100644 --- a/Makefile +++ b/Makefile @@ -952,7 +952,11 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img endif endif INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin + +# Allow omitting the .dtb output if it is not normally used +ifndef CONFIG_OF_OMIT_DTB INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb +endif ifeq ($(CONFIG_SPL_FRAMEWORK),y) INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img endif @@ -1192,7 +1196,7 @@ u-boot.bin: u-boot-fit-dtb.bin FORCE u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE $(call if_changed,cat) -else ifeq ($(CONFIG_OF_SEPARATE),y) +else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.) u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE $(call if_changed,cat) diff --git a/dts/Kconfig b/dts/Kconfig index 803d0899556..fd2829ad708 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -129,6 +129,16 @@ config OF_HAS_PRIOR_STAGE Note: This option must be set in Kconfig and cannot be enabled or disabled in the board's defconfig file. +config OF_OMIT_DTB + bool "Omit the device tree output when building" + default y if OF_HAS_PRIOR_STAGE && !BINMAN + help + As a special case, avoid writing a device tree file u-boot.dtb when + building. Also don't include that file in u-boot.bin + + This is used for boards which normally provide a devicetree via a + runtime mechanism (such as OF_BOARD), to avoid confusion. + config DEFAULT_DEVICE_TREE string "Default Device Tree for DT control" depends on OF_CONTROL From patchwork Tue Dec 7 00:12:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1564442 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=IMr0lktL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7LWK6w3Nz9sCD for ; Tue, 7 Dec 2021 11:18:53 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BB18C8375A; Tue, 7 Dec 2021 01:15:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="IMr0lktL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 55DB2830BA; Tue, 7 Dec 2021 01:13:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 441418307A for ; Tue, 7 Dec 2021 01:13:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-oi1-x230.google.com with SMTP id u74so24515208oie.8 for ; Mon, 06 Dec 2021 16:13:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8BsipBuooq2r371qHnt9OlAvSzgtARTo4U46ih5UF/c=; b=IMr0lktLYuXeWpjEkkz5ZphJWSGmNwNqokh3krtfdKM3Q9vlS989bF5ZLqQiT/CGiE dh2r6jxzQoi6etzNbLrVf2DXA9IBFjFvdrOvZoCQVoh9DY/RPH0jV3s0pP/UBeGjg+lW goAE7PS9BuHsjSjrHKfpSLUevgL+3SUY4MuDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8BsipBuooq2r371qHnt9OlAvSzgtARTo4U46ih5UF/c=; b=lu8nfqjmwswTKf0FYF9uAZzdUq0Jhc3C7ZNzm0qQ7sTwH9bZNdjQgsSL4QQEvPuH9F +EjKqRALKlaIENNAqmFFISU0GBHKvZa1tVBsk1qnhQK7FnSItk3sDBFSN6HlOxKRksk9 FhgAW4rvjWzPheajRigwKdCrDi7RvSh+BNdrLGLg2GCuIDjpQo3RgE+Nklq9IRoYh4Ks qy/xsSyQRe4Su009lpcoyWHm10JgqfWvGC+8AOVxMyzk0W0tPx5PK/xLUJT4MQ7TMnb/ Bcpv4YsBjdYcbZN7p/ILm7QuuoaQrQxtopPHRYPFVfcHiYxA2jJ8W8WSV2cqiXXmD11A XoZA== X-Gm-Message-State: AOAM531aKDOx4LUc6DMW1uySEM8p1Q4fKm1AxJI2NqOJrnbERgSKa8rk ysaArrNYfS2CUolRgclzoGAUSdKKgwchDQ== X-Google-Smtp-Source: ABdhPJzyt7XXtoKf+E3tTqVr0SUvHz+WgxXnfljdU0CIdVhbrDX88bv6wvfyR4eS1RnH2oYnD2391Q== X-Received: by 2002:a05:6808:1903:: with SMTP id bf3mr2063318oib.7.1638835998833; Mon, 06 Dec 2021 16:13:18 -0800 (PST) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id g7sm2466410oon.27.2021.12.06.16.13.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 16:13:18 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Sean Anderson , Heinrich Schuchardt , Mark Kettenis , Tom Rini , =?utf-8?q?Fran=C3=A7ois_Ozog?= , Ilias Apalodimas , Simon Glass , Jerry Van Baren Subject: [PATCH v7 31/31] fdt: Show build/runtime warnings based on devicetree source Date: Mon, 6 Dec 2021 17:12:09 -0700 Message-Id: <20211207001209.3467163-31-sjg@chromium.org> X-Mailer: git-send-email 2.34.1.400.ga245620fadb-goog In-Reply-To: <20211207001209.3467163-1-sjg@chromium.org> References: <20211207001209.3467163-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Show a warning at build time if the devicetree is built for a board which normally should get it from a prior stage: Warning: Devicetree was built but is not normally used on this board When running, if the devicetree failed to come from the expected source, show a warning then also, e.g: U-Boot ... DRAM: 128 MiB Core: 42 devices, 11 uclasses, devicetree: separate Warning: Unexpected devicetree source (not from a prior stage) Warning: U-Boot may not function properly Flash: 64 MiB ... These warnings should only appear if the board config has been changed, or the prior stage is broken. Signed-off-by: Simon Glass --- (no changes since v1) Makefile | 3 +++ common/board_r.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/Makefile b/Makefile index a3f018f01e0..0059f10cbca 100644 --- a/Makefile +++ b/Makefile @@ -1107,6 +1107,9 @@ endif ifeq ($(CONFIG_DEPRECATED),y) $(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.") endif +ifeq ($(CONFIG_OF_HAS_PRIOR_STAGE).$(CONFIG_OF_OMIT_DTB),y.) + @echo >&2 "Warning: Devicetree was built but is not normally used on this board" +endif ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y) @echo >&2 "===================== WARNING ======================" @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only" diff --git a/common/board_r.c b/common/board_r.c index 99adff14b39..6d520662dbb 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -598,6 +598,12 @@ static int dm_announce(void) if (CONFIG_IS_ENABLED(OF_REAL)) printf(", devicetree: %s", fdtdec_get_srcname()); printf("\n"); + if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) && + (gd->fdt_src == FDTSRC_SEPARATE || + gd->fdt_src == FDTSRC_EMBED)) { + printf("Warning: Unexpected devicetree source (not from a prior stage)"); + printf("Warning: U-Boot may not function properly\n"); + } } return 0;