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[220.135.95.34]) by smtp.gmail.com with ESMTPSA id 130sm10557820pfu.13.2021.12.05.21.57.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Dec 2021 21:57:14 -0800 (PST) From: AceLan Kao To: kernel-team@lists.ubuntu.com Subject: [RESEND][PATCH 1/1][SRU][H][I] UBUNTU: SAUCE: watchdog: f71808e_wdt: Add F81966 support Date: Mon, 6 Dec 2021 13:57:10 +0800 Message-Id: <20211206055710.348049-2-acelan.kao@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211206055710.348049-1-acelan.kao@canonical.com> References: <20211206055710.348049-1-acelan.kao@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.172; envelope-from=acelan@gmail.com; helo=mail-pf1-f172.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: AaeonIot BugLink: https://bugs.launchpad.net/bugs/1949063 This adds watchdog support the Fintek F81966 Super I/O chip. Testing was done on the Aaeon SSE-OPTI Signed-off-by: AaeonIot Signed-off-by: Chia-Lin Kao (AceLan) --- drivers/watchdog/f71808e_wdt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) mode change 100644 => 100755 drivers/watchdog/f71808e_wdt.c diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c old mode 100644 new mode 100755 index f60beec1bbae..0e009d167964 --- a/drivers/watchdog/f71808e_wdt.c +++ b/drivers/watchdog/f71808e_wdt.c @@ -54,6 +54,7 @@ #define SIO_F81803_ID 0x1210 /* Chipset ID */ #define SIO_F81865_ID 0x0704 /* Chipset ID */ #define SIO_F81866_ID 0x1010 /* Chipset ID */ +#define SIO_F81966_ID 0x1502 /* F81804 chipset ID, same for f81966 */ #define F71808FG_REG_WDO_CONF 0xf0 #define F71808FG_REG_WDT_CONF 0xf5 @@ -111,7 +112,7 @@ MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with" " given initial timeout. Zero (default) disables this feature."); enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg, - f81803, f81865, f81866}; + f81803, f81865, f81866, f81966}; static const char *f71808e_names[] = { "f71808fg", @@ -124,6 +125,7 @@ static const char *f71808e_names[] = { "f81803", "f81865", "f81866", + "f81966" }; /* Super-I/O Function prototypes */ @@ -371,6 +373,7 @@ static int watchdog_start(void) break; case f81866: + case f81966: /* * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0. * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch: @@ -397,7 +400,7 @@ static int watchdog_start(void) superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0); - if (watchdog.type == f81865 || watchdog.type == f81866) + if (watchdog.type == f81865 || watchdog.type == f81866 || watchdog.type == f81966) superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF, F81865_FLAG_WDOUT_EN); else @@ -820,6 +823,9 @@ static int __init f71808e_find(int sioaddr) case SIO_F81866_ID: watchdog.type = f81866; break; + case SIO_F81966_ID: + watchdog.type = f81966; + break; default: pr_info("Unrecognized Fintek device: %04x\n", (unsigned int)devid);