From patchwork Thu Dec 2 00:00:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 1562482 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=ak9cw5YM; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J4GNQ58Rvz9sRN for ; Thu, 2 Dec 2021 11:02:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353951AbhLBAFN (ORCPT ); Wed, 1 Dec 2021 19:05:13 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:3936 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353979AbhLBAEX (ORCPT ); Wed, 1 Dec 2021 19:04:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1638403263; x=1669939263; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=JGow5gSyCVGGIvARjpIWCWieeUWr8i3gh6AHITcaPMM=; b=ak9cw5YMd5IuHfCLxosGdMnYb405LnUF61ka1ywtUWH1VIxKgh4AbYv0 35/1foUcZURIX/Pv4CyNUQfqlkK/Vy4C+LLdx2x1wwDeNXOvZ9ztC4+6C boNCmGMvCIFY6puyLhyJcEFvxOjUaUjDr0T7+8eWoGTtF4jzubdoeltyS 8=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 01 Dec 2021 16:01:02 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2021 16:01:02 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:01:01 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:00:58 -0800 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , CC: , , , , Subject: [RESEND PATCH v3 07/10] bindings: spmi: spmi-pmic-arb: mark interrupt properties as optional Date: Thu, 2 Dec 2021 08:00:09 +0800 Message-ID: <1638403212-29265-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> References: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: David Collins Mark all interrupt related properties as optional instead of required. Some boards do not required PMIC IRQ support and it isn't needed to handle SPMI bus transactions, so specify it as optional. Signed-off-by: David Collins Signed-off-by: Fenglin Wu Acked-by: Rob Herring --- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt index ca645e2..6332507 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -29,6 +29,8 @@ Required properties: - #size-cells : must be set to 0 - qcom,ee : indicates the active Execution Environment identifier (0-5) - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) + +Optional properties: - interrupts : interrupt list for the PMIC Arb controller, must contain a single interrupt entry for the peripheral interrupt - interrupt-names : corresponding interrupt names for the interrupts From patchwork Thu Dec 2 00:00:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 1562483 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=ZNENtuc/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J4GP00D6gz9sRN for ; Thu, 2 Dec 2021 11:02:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353997AbhLBAGC (ORCPT ); Wed, 1 Dec 2021 19:06:02 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:20583 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354002AbhLBAEe (ORCPT ); Wed, 1 Dec 2021 19:04:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1638403273; x=1669939273; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=f2yYHDXNl3uhD7HN2SXULZcfY2DXP5daCOiiMrMpBQ4=; b=ZNENtuc/SDrOtaFVSzt+Aco7aoQHopr/N52yY5y4F2leQfKhHNLbz1Tv U+A1HKBCKScKiwhCJTvK2kOBKF2Y11kA+j55TE+GjAqeggMPFFMRLdwze dyZM0IMY0yTqrk8AYpBs2/dJErdIsCUAOCzdG9Z+8LqWrZx8lfBCM1nHR I=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 01 Dec 2021 16:01:13 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2021 16:01:12 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:01:12 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 1 Dec 2021 16:01:08 -0800 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , Fenglin Wu , Subbaraman Narayanamurthy , CC: , , , Subject: [RESEND PATCH v3 10/10] dt-bindings: convert qcom,spmi-pmic-arb binding to YAML format Date: Thu, 2 Dec 2021 08:00:12 +0800 Message-ID: <1638403212-29265-11-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> References: <1638403212-29265-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the SPMI PMIC arbiter documentation to JSON/yaml. While at it, update SPMI bus "reg" items constraint for SPMI PMIC arbiter to carry it and update it with a smaller range. Signed-off-by: Fenglin Wu Reviewed-by: Rob Herring --- .../bindings/spmi/qcom,spmi-pmic-arb.txt | 67 ----------- .../bindings/spmi/qcom,spmi-pmic-arb.yaml | 128 +++++++++++++++++++++ Documentation/devicetree/bindings/spmi/spmi.yaml | 3 +- 3 files changed, 130 insertions(+), 68 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt deleted file mode 100644 index 6332507..0000000 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ /dev/null @@ -1,67 +0,0 @@ -Qualcomm SPMI Controller (PMIC Arbiter) - -The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI -controller with wrapping arbitration logic to allow for multiple on-chip -devices to control a single SPMI master. - -The PMIC Arbiter can also act as an interrupt controller, providing interrupts -to slave devices. - -See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI -controller binding requirements for child nodes. - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -generic interrupt controller binding documentation. - -Required properties: -- compatible : should be "qcom,spmi-pmic-arb". -- reg-names : must contain: - "core" - core registers - "intr" - interrupt controller registers - "cnfg" - configuration registers - Registers used only for V2 PMIC Arbiter: - "chnls" - tx-channel per virtual slave registers. - "obsrvr" - rx-channel (called observer) per virtual slave registers. - -- reg : address + size pairs describing the PMIC arb register sets; order must - correspond with the order of entries in reg-names -- #address-cells : must be set to 2 -- #size-cells : must be set to 0 -- qcom,ee : indicates the active Execution Environment identifier (0-5) -- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) - -Optional properties: -- interrupts : interrupt list for the PMIC Arb controller, must contain a - single interrupt entry for the peripheral interrupt -- interrupt-names : corresponding interrupt names for the interrupts - listed in the 'interrupts' property, must contain: - "periph_irq" - summary interrupt for PMIC peripherals -- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller -- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: - cell 1: slave ID for the requested interrupt (0-15) - cell 2: peripheral ID for requested interrupt (0-255) - cell 3: the requested peripheral interrupt (0-7) - cell 4: interrupt flags indicating level-sense information, as defined in - dt-bindings/interrupt-controller/irq.h - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - - interrupt-names = "periph_irq"; - interrupts = <0 190 0>; - - qcom,ee = <0>; - qcom,channel = <0>; - - #address-cells = <2>; - #size-cells = <0>; - - interrupt-controller; - #interrupt-cells = <4>; - }; diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml new file mode 100644 index 0000000..3f0bea2 --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC Arbiter + +maintainers: + - Fenglin Wu + - Subbaraman Narayanamurthy + +description: | + The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI + controller with wrapping arbitration logic to allow for multiple + on-chip devices to control a single SPMI master. + + The PMIC Arbiter can also act as an interrupt controller, providing + interrupts to slave devices. + + See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic + SPMI controller binding requirements for child nodes. + +allOf: + - $ref: spmi.yaml# + +properties: + $nodename: + pattern: "^spmi@.*" + + compatible: + const: qcom,spmi-pmic-arb + + reg-names: + oneOf: + - items: + - const: core + - const: intr + - const: cnfg + - items: + - const: core + - const: intr + - const: cnfg + - const: chnls + - const: obsrvr + + reg: + minItems: 3 + maxItems: 5 + description: | + Specifies base physical address and size of the registers in SPMI PMIC + Arbiter HW module, with the following order. + - SPMI PMIC arbiter core registers (core) + - SPMI PMIC arbiter interrupt controller registers (intr) + - SPMI PMIC arbiter configuration registers (cnfg) + - SPMI PMIC arbiter tx-channel per virtual slave registers (chnls) + - SPMI PMIC arbiter rx-channel per virtual slave registers (obsrvr). + Register for "chnls" and "obsrvr" are only applicable for PMIC arbiter + with HW version greater than V2. + + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + interrupts: + description: The summary interrupt for the PMIC Arb controller. + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + "#interrupt-cells": + const: 4 + description: | + Specifies the number of cells needed to encode any interrupt source. + The 1st cell is the slave ID for the requested interrupt, its valid + range is [0-15]. + The 2nd cell is the peripheral ID for requested interrupt, its valid + range is [0-255]. + The 3rd cell is the requested peripheral interrupt, its valid range + is [0-7]. + The 4th cell is interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + + qcom,ee: + description: the active Execution Environment identifier + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5] + + qcom,channel: + description: which of the PMIC Arbiter provided channels to use for accesses + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5] + +required: + - compatible + - reg-names + - reg + - "#address-cells" + - "#size-cells" + - qcom,ee + - qcom,channel + +additionalProperties: false + +examples: + - | + spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml index 1d243fae..d7d9345 100644 --- a/Documentation/devicetree/bindings/spmi/spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/spmi.yaml @@ -25,7 +25,8 @@ properties: pattern: "^spmi@.*" reg: - maxItems: 1 + minItems: 1 + maxItems: 5 "#address-cells": const: 2