From patchwork Sun Nov 28 02:53:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1560821 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=CHA+e5QH; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=MomG1e3c; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J1tMy6HCwz9sVk for ; Sun, 28 Nov 2021 13:53:34 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A001382BA5; Sun, 28 Nov 2021 03:53:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1638068003; bh=CaItL0W0XWs6c8aYxCYF1rxEf/ccV9nDLpB/NwvQZYU=; h=From:To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=CHA+e5QHpwC1xUg7TfQiHqPVFASnvicnmo2fgPPKE7foUXWavGaf/GXNj0VQBsclu kY77XYrpTVhoSo6M/TBFRmLN/K6VLL0QrvmHnaRJOIgE8LzIbwek/S2OGljLggzgyO OZTNsXxtFoBiBXZL7A09mKGj8hT6Ynnz2KJHpupRm4fiXh2tXewDMnYgPtR4lCz3j9 DLSlAmlk0NGIcX3yiWH+1b1Q7EDhKZ+dglnhIEqx8EjYGZJQspMsb2Gu+sQsgN0oM5 Ast3bvVTMpurqKYS9DvTs6nzWwUuMaICIHIE+olSPcx6NDxrhZG55z1Io4kaVbLmqF HNXU+PkVoxAJw== Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id BA73580F9C; Sun, 28 Nov 2021 03:53:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1638068002; bh=CaItL0W0XWs6c8aYxCYF1rxEf/ccV9nDLpB/NwvQZYU=; h=From:To:Cc:Subject:Date:From; b=MomG1e3cUbGvPceXgaVwiY+K/TBaMgzFGn5se1xo2B8UIpWekdu3v145VYAgJNAc9 EtdIDQY2DcAO2iBq1NPuXgQI51adVEdkNsPruABvM2KNbuFv8Ql20E+jNpG+mKOodv YuTGZSzrnGpAevKZQHLNS0G6Y9knMizd/K7gYIAqbJtxJ1ILRsNjtiD71aPjMCjF1B 4bN1yTo03KKqSOm/2wMYIeShK/7KVKd2NJmiIaO2PUl8D0xrCmZD9DGnXHNcYY1goo +6uPlvsR+T/ZS5bFGG96GijXXEuAhXZaajCqVs/QrAYT0gGTF5zNof7f7gWDfxmEZ1 UrJ0YMijMEkxg== From: Marek Vasut To: u-boot@lists.denx.de Cc: Christoph Niedermaier , Marek Vasut , Stefano Babic Subject: [PATCH] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board Date: Sun, 28 Nov 2021 03:53:18 +0100 Message-Id: <20211128025318.367051-1-marex@denx.de> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Christoph Niedermaier The PDK2 board is capable of running both 100M and 1G ethernet. However, the i.MX6 has only one ethernet MAC, so it is possible to configure either 100M or 1G Ethernet. In case of 100M option, the PHY is on the SoM and the signals are routed to a RJ45 port. For 1G the PHY is on the PDK2 board with another RJ45 port. 100M and 1G ethernet use different signal pins from the i.MX6, but share the MDIO bus. This SoM board combination is used to demonstrate how to enable 1G ethernet configuration. Signed-off-by: Christoph Niedermaier Signed-off-by: Marek Vasut Cc: Christoph Niedermaier Cc: Stefano Babic --- NOTE: Adapted from Linux 298591bf725a ("ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board") --- arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi | 2 +- arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi | 50 +++++++++++++++++++-- include/configs/dh_imx6.h | 4 +- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi index 32128d4d2ab..a1ffb1d6fc5 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -15,7 +15,7 @@ }; &fec { - phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; phy-reset-post-delay = <10>; diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi index af4719aaeba..d8772a98966 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi @@ -38,6 +38,45 @@ status = "okay"; }; +/* 1G ethernet */ +/delete-node/ ðphy0; +&fec { + phy-mode = "rgmii"; + phy-handle = <ðphy7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1G>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy7: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy7>; + pinctrl-names = "default"; + reg = <7>; + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + &hdmi { ddc-i2c-bus = <&i2c2>; status = "okay"; @@ -113,9 +152,14 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 + >; + }; + + pinctrl_ethphy7: ethphy7-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ >; }; diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 8183e7debd4..3cf0578b5e1 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,9 +32,9 @@ /* FEC ethernet */ #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_MXC_PHYADDR 7 #define CONFIG_ARP_TIMEOUT 200UL /* MMC Configs */