From patchwork Fri Nov 19 19:37:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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[176.63.2.222]) by smtp.googlemail.com with ESMTPSA id sb19sm327521ejc.120.2021.11.19.11.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 11:39:22 -0800 (PST) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Bolarinwa O. Saheed" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Subject: [RFC PATCH v5 1/4] PCI/ASPM: Move pci_function_0() upward Date: Fri, 19 Nov 2021 20:37:29 +0100 Message-Id: <20211119193732.12343-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211119193732.12343-1-refactormyself@gmail.com> References: <20211119193732.12343-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Bolarinwa O. Saheed" To call pci_function_0() directly from other functions, move its definition upward to a more accessible location. Reviewed-by: Christoph Hellwig Signed-off-by: Bolarinwa O. Saheed --- drivers/pci/pcie/aspm.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 52c74682601a..6f128b654730 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -105,6 +105,20 @@ static const char *policy_str[] = { #define LINK_RETRAIN_TIMEOUT HZ +/* + * The L1 PM substate capability is only implemented in function 0 in a + * multi function device. + */ +static struct pci_dev *pci_function_0(struct pci_bus *linkbus) +{ + struct pci_dev *child; + + list_for_each_entry(child, &linkbus->devices, bus_list) + if (PCI_FUNC(child->devfn) == 0) + return child; + return NULL; +} + static int policy_to_aspm_state(struct pcie_link_state *link) { switch (aspm_policy) { @@ -423,20 +437,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) } } -/* - * The L1 PM substate capability is only implemented in function 0 in a - * multi function device. - */ -static struct pci_dev *pci_function_0(struct pci_bus *linkbus) -{ - struct pci_dev *child; - - list_for_each_entry(child, &linkbus->devices, bus_list) - if (PCI_FUNC(child->devfn) == 0) - return child; - return NULL; -} - static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, u32 clear, u32 set) { From patchwork Fri Nov 19 19:37:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1557374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=foRvEjki; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Hwn706TxWz9sRK for ; Sat, 20 Nov 2021 06:39:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233316AbhKSTmi (ORCPT ); Fri, 19 Nov 2021 14:42:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235324AbhKSTmf (ORCPT ); Fri, 19 Nov 2021 14:42:35 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C173BC061748; Fri, 19 Nov 2021 11:39:24 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id l25so30491416eda.11; Fri, 19 Nov 2021 11:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lEUVIidb26P1etOScGhyEwiMqag493M5Iw91U7Op3Z4=; b=foRvEjkibnTriH+7Du9LiMvshA1zgwBeURU/LzlqpZ980L8ex4A262f36noM3k+zaK Jl/vVUgBRywY3TsC2UA5/lxDiClWix2nHehiG05pIVEa69wFBsaMfs89vBVqGLTMIWnN t451KY/YrFzfQlGS5T+73Wf0YcYMqKx1rDOL8VVP94Kc7B5X9L33pS1NCS3q0G0/uH7Q hG37JM0MaL5QBSBimi6Ieqf60Wnb7qET4THav4HxbVPecModD6nwZees4YsmRTF8OQha W3RQCyrLpgvTOzES2PrPGuqlImTdgLeXnJf2YlSyQGjleVcraFmHyoU7Sg0kIZksQ42G eOWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lEUVIidb26P1etOScGhyEwiMqag493M5Iw91U7Op3Z4=; b=Z2MUWlLk/waliQnf/LLNXhDtOge7e0cJWLOKdmOUJ59njSiqN68Lw2oQMDbJSA3VOt PtTy1ZUrYKCpEZYhxerSQXGvnTKprtW6W/ul0n9bz/dAtKhTCYiutvAmKfpPvYNtqcnw yk+Zt/viVGErFHSDjdgkpJRNyiy8YhjGoX8MMQ2U0yUdErBdceNBiCo/ngo5hpMZO6Ge F17h7lb8k9lDsyM2bNegkfOZMevQ51hNwhIhCH9acmcVydV539Qyi/PdrIi+DHLjmHvQ Z+R/jdURMkh6VEZAFX0HWJ6N8IBRmiD1t+pbAyhwm6h9tElsrK0dstaxPCwVXEzAyf03 KhpA== X-Gm-Message-State: AOAM532VSppewH4lJvboDKj4/4WYS+U6zo72vAO3k8Io705wQFtg08sq 6Ig53s5lG0rLvZkssvj9hOg= X-Google-Smtp-Source: ABdhPJyS+huF4Vf7cuGqBz7aOTYQEzp+lhaEYxjCQo2miCpX+Gj6r874ITLAYBTquAJrs1kAxW1NAA== X-Received: by 2002:a05:6402:4407:: with SMTP id y7mr28718591eda.140.1637350763365; Fri, 19 Nov 2021 11:39:23 -0800 (PST) Received: from localhost.localdomain (catv-176-63-2-222.catv.broadband.hu. [176.63.2.222]) by smtp.googlemail.com with ESMTPSA id sb19sm327521ejc.120.2021.11.19.11.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 11:39:23 -0800 (PST) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Subject: [RFC PATCH v5 2/4] PCI/ASPM: Do not cache link latencies Date: Fri, 19 Nov 2021 20:37:30 +0100 Message-Id: <20211119193732.12343-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211119193732.12343-1-refactormyself@gmail.com> References: <20211119193732.12343-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The latencies of the upstream and downstream are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.latency_* These values are only used in pcie_aspm_check_latency() where they are compared with the acceptable latencies on the link. - remove `latency_*` entries from struct pcie_link_state. - calculate the latencies directly where they are needed. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 6f128b654730..1b8933e0afb2 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -66,9 +66,6 @@ struct pcie_link_state { u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - /* Exit latencies */ - struct aspm_latency latency_up; /* Upstream direction exit latency */ - struct aspm_latency latency_dw; /* Downstream direction exit latency */ /* * Endpoint acceptable latencies. A pcie downstream port only * has one slot under it, so at most there are 8 functions. @@ -392,7 +389,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, l1_switch_latency = 0; + u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; struct pcie_link_state *link; @@ -405,14 +403,29 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; while (link) { + struct pci_dev *dev = pci_function_0( + link->pdev->subordinate); + + /* Read direction exit latencies */ + pcie_capability_read_dword(link->pdev, + PCI_EXP_LNKCAP, + &lnkcap_up); + pcie_capability_read_dword(dev, + PCI_EXP_LNKCAP, + &lnkcap_dw); + latency_up.l0s = calc_l0s_latency(lnkcap_up); + latency_up.l1 = calc_l1_latency(lnkcap_up); + latency_dw.l0s = calc_l0s_latency(lnkcap_dw); + latency_dw.l1 = calc_l1_latency(lnkcap_dw); + /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (link->latency_up.l0s > acceptable->l0s)) + (latency_up.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (link->latency_dw.l0s > acceptable->l0s)) + (latency_dw.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -427,7 +440,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); + latency = max_t(u32, latency_up.l1, latency_dw.l1); if ((link->aspm_capable & ASPM_STATE_L1) && (latency + l1_switch_latency > acceptable->l1)) link->aspm_capable &= ~ASPM_STATE_L1; @@ -593,8 +606,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(parent_lnkcap); - link->latency_dw.l0s = calc_l0s_latency(child_lnkcap); /* Setup L1 state */ if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) @@ -602,8 +613,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(parent_lnkcap); - link->latency_dw.l1 = calc_l1_latency(child_lnkcap); /* Setup L1 substate */ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, From patchwork Fri Nov 19 19:37:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1557372 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=OU6etl9K; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Hwn6w37xzz9sRK for ; Sat, 20 Nov 2021 06:39:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235775AbhKSTmg (ORCPT ); Fri, 19 Nov 2021 14:42:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236002AbhKSTmf (ORCPT ); Fri, 19 Nov 2021 14:42:35 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97293C061574; Fri, 19 Nov 2021 11:39:25 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id o20so2527987eds.10; Fri, 19 Nov 2021 11:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rj93QcILIz19ZRcferyP1zIgd4/v1Pg6xmThPg4ZhjY=; b=OU6etl9KFjHr03VjZ6y6xiPNTKIUTGC1OzimdFOyNhldGtfHxGyfGZLape0ShqVD9V kNow3h9taNCWnzGBwquufYv0aVYj9gfNNmFV/z/0ZL8UcF37P2dXybEVOWs9+Omxg60L ZqT+QCmDOMBenEukECm98y6TbGcLXP2yBh07Qi3M6QLxMOcoDCTSgcp5tT44pucyPSc7 uf195PY2MrUI8QmmIuBjR6cTT9i7uaWjpuw1+Y/lxkVCak54rV1mB+XDxi3nW5rKC1Ln uaUv1nlHnTm8axfBAqdjMp8YwsUB8ZRDdhi9M5kJyIqsSvi+ALzQ43e0QyFTpTahYh4v DvXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rj93QcILIz19ZRcferyP1zIgd4/v1Pg6xmThPg4ZhjY=; b=JT/NxNgYX9GxF/ANykyf6av6PyEwnX7LDjhab0oPG8wADszHYmczkd8X1WzQhBhdYx JRtVoVWo7qi7vPF7fjh2lN4dUs6kfXRjSTIaD4IKykGauihugIPjoCMVC4DLACCaZE52 Zz4hk04id5ua2tgW0LJh47Fl9IEuIZ3x0n1GMuCg0y76wR3mLpZfOKPI+z+sbBl76gWP XS0mlqKHG8Wx5Y01iekuK0fRaJErI7So2XKwMi9mP1PQK3WQsfSzrnsbXc1FIdzhSLrK D0+g+oYafSeQ+o8S1Yc5YrXA/6fOFzcBlmnhfTR/nldKMu1GVc4ZKANmNz05NsJZCldm kt7g== X-Gm-Message-State: AOAM533n++dFxtkcfbqeGtr06zOtLukzkWrYgnTotY27WreGGQ5rEkrI S5x7PMFxEtm1Znr4X4u3CR8x0+YhTdI= X-Google-Smtp-Source: ABdhPJxsnLHK8nf41r2F1legqgBx8dyP3FklJ4cjYLXI7yNFdoPkh1ZO6mfE9M+YPWzbRNyDlR7utw== X-Received: by 2002:a17:907:764b:: with SMTP id kj11mr81552ejc.307.1637350764197; Fri, 19 Nov 2021 11:39:24 -0800 (PST) Received: from localhost.localdomain (catv-176-63-2-222.catv.broadband.hu. [176.63.2.222]) by smtp.googlemail.com with ESMTPSA id sb19sm327521ejc.120.2021.11.19.11.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 11:39:23 -0800 (PST) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Subject: [RFC PATCH v5 3/4] PCI/ASPM: Remove struct pcie_link_state.acceptable Date: Fri, 19 Nov 2021 20:37:31 +0100 Message-Id: <20211119193732.12343-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211119193732.12343-1-refactormyself@gmail.com> References: <20211119193732.12343-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The acceptable latencies for each device on the bus are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.acceptable. They are only used within pcie_aspm_check_latency() to validate actual latencies. Thus, it is possible to avoid caching these values. - remove `acceptable` from struct pcie_link_state - calculate the acceptable latency for individual device directly - remove the calculations done within pcie_aspm_cap_init() Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 1b8933e0afb2..a8821fe1ffe7 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -65,12 +65,6 @@ struct pcie_link_state { u32 clkpm_enabled:1; /* Current Clock PM state */ u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - - /* - * Endpoint acceptable latencies. A pcie downstream port only - * has one slot under it, so at most there are 8 functions. - */ - struct aspm_latency acceptable[8]; }; static int aspm_disabled, aspm_force; @@ -389,7 +383,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw; + u32 l1_switch_latency = 0; struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; struct pcie_link_state *link; @@ -400,7 +395,13 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) return; link = endpoint->bus->self->link_state; - acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; + pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); + /* Calculate endpoint L0s acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; + acceptable->l0s = calc_l0s_acceptable(encoding); + /* Calculate endpoint L1 acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; + acceptable->l1 = calc_l1_acceptable(encoding); while (link) { struct pci_dev *dev = pci_function_0( @@ -669,22 +670,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - u32 reg32, encoding; - struct aspm_latency *acceptable = - &link->acceptable[PCI_FUNC(child->devfn)]; if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue; - pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); - /* Calculate endpoint L0s acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); - /* Calculate endpoint L1 acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); - pcie_aspm_check_latency(child); } } From patchwork Fri Nov 19 19:37:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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[176.63.2.222]) by smtp.googlemail.com with ESMTPSA id sb19sm327521ejc.120.2021.11.19.11.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 11:39:24 -0800 (PST) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Subject: [RFC PATCH v5 4/4] PCI/ASPM: Remove struct aspm_latency Date: Fri, 19 Nov 2021 20:37:32 +0100 Message-Id: <20211119193732.12343-5-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211119193732.12343-1-refactormyself@gmail.com> References: <20211119193732.12343-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The struct aspm_latency is now used only inside pcie_aspm_check_latency(). - replace struct aspm_latency variables with u32 variables - remove struct aspm_latency Reviewed-by: Christoph Hellwig Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index a8821fe1ffe7..e29611080a90 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -41,11 +41,6 @@ #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ ASPM_STATE_L1SS) -struct aspm_latency { - u32 l0s; /* L0s latency (nsec) */ - u32 l1; /* L1 latency (nsec) */ -}; - struct pcie_link_state { struct pci_dev *pdev; /* Upstream component of the Link */ struct pci_dev *downstream; /* Downstream component, function 0 */ @@ -384,9 +379,9 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw; - u32 l1_switch_latency = 0; - struct aspm_latency latency_up, latency_dw; - struct aspm_latency *acceptable; + u32 l1_switch_latency = 0, latency_up_l0s; + u32 latency_up_l1, latency_dw_l0s, latency_dw_l1; + u32 acceptable_l0s, acceptable_l1; struct pcie_link_state *link; /* Device not in D0 doesn't need latency check */ @@ -398,10 +393,10 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); /* Calculate endpoint L0s acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); + acceptable_l0s = calc_l0s_acceptable(encoding); /* Calculate endpoint L1 acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); + acceptable_l1 = calc_l1_acceptable(encoding); while (link) { struct pci_dev *dev = pci_function_0( @@ -414,19 +409,19 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap_dw); - latency_up.l0s = calc_l0s_latency(lnkcap_up); - latency_up.l1 = calc_l1_latency(lnkcap_up); - latency_dw.l0s = calc_l0s_latency(lnkcap_dw); - latency_dw.l1 = calc_l1_latency(lnkcap_dw); + latency_up_l0s = calc_l0s_latency(lnkcap_up); + latency_up_l1 = calc_l1_latency(lnkcap_up); + latency_dw_l0s = calc_l0s_latency(lnkcap_dw); + latency_dw_l1 = calc_l1_latency(lnkcap_dw); /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (latency_up.l0s > acceptable->l0s)) + (latency_up_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (latency_dw.l0s > acceptable->l0s)) + (latency_dw_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -441,9 +436,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, latency_up.l1, latency_dw.l1); + latency = max_t(u32, latency_up_l1, latency_dw_l1); if ((link->aspm_capable & ASPM_STATE_L1) && - (latency + l1_switch_latency > acceptable->l1)) + (latency + l1_switch_latency > acceptable_l1)) link->aspm_capable &= ~ASPM_STATE_L1; l1_switch_latency += 1000; @@ -670,7 +665,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue;