From patchwork Fri Nov 19 14:38:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557153 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=E8MR4yPt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfRt72zPz9sS8 for ; Sat, 20 Nov 2021 01:38:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235410AbhKSOlv (ORCPT ); Fri, 19 Nov 2021 09:41:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOlv (ORCPT ); Fri, 19 Nov 2021 09:41:51 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66BB2C061574; Fri, 19 Nov 2021 06:38:49 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id w29so18497510wra.12; Fri, 19 Nov 2021 06:38:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VypbopsrzjbLiXpW/5jIEdbTxIotLoER2uda7Lkx/6Q=; b=E8MR4yPts33q6YqyiWoLW3QODea4CH6/S3ndVqJH0rfWK4gj1wxg0gI8LZqwUPPdMg wKn2VOT1SOkoVBNhTrqTq/WMMpTd8rfQwgLxJ0r+/GKYKpC2araL3RKK9+xeo1AehVOL c3EnX63s+QTizlMCSWigcT2kRJtS7EROqYRKfDxIm3t+KUk7MPNMcZBlYSvPPhDWRlzT T7KejXwbuiezJKJ/Jy0CojeaQwLbueSLF1AmTjmUe92RGvmJ/HLFLxuPsLqNCivyg2M6 GlYII7JCEyHqk8efiH4Fe/ObnUinQzRTXHWkRCUnc/5GdWIAsFWGevNroYSwOPNVmlnq 9THw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VypbopsrzjbLiXpW/5jIEdbTxIotLoER2uda7Lkx/6Q=; b=owHr1yiFThy99jhjrG8egR4xLzN0bewPpar7zWtRwj/Y2ZxiHOXJwvQaG/wcPG4Lz/ lGw7HBo83JL0pnb/0EyqTDjZJEe25O+r3UIX0pFZ3kDUecE+p8k5SM4TUv//MXRnTV2G yCDPb9phcvVvDmhXsNVpvQ5kJqSmTAnfVSWFsUEb0EIvHCM6sjyX7PoZYH/0DJEBjHre dA1yMZrl2g5ygobMIY5FRyXmC2I4mX2CgQ3+B4hbWh+cEeUMn8SkKw+qbC1u5LBkaaCn jaah2STNG92z7GtKT0pbiJ+ktXHNXRKUoLVGRARhJHWvTMq8PO9r6e6YbBvzdESHbonf 0wDQ== X-Gm-Message-State: AOAM531d/mEXf0PzsQ4IoKtddFccPQKj+HpAXiwZ6E//fGr3HhrJkebL TA5uVbaPuu0cAj60OSqdpa0= X-Google-Smtp-Source: ABdhPJzFs74+on7xCkmOV3NoFwJXILBSdfsRXBmcHap2Fx8sQB13xc4R+z3tf9yIfAA24S17dO0D8Q== X-Received: by 2002:a5d:6dc3:: with SMTP id d3mr7881950wrz.159.1637332727926; Fri, 19 Nov 2021 06:38:47 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id 138sm7496538wma.17.2021.11.19.06.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:38:47 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC to json-schema Date: Fri, 19 Nov 2021 15:38:24 +0100 Message-Id: <20211119143839.1950739-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../bindings/misc/nvidia,tegra186-misc.txt | 14 ----- .../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 ------- .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++ 4 files changed, 94 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt deleted file mode 100644 index 43d777ed8316..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra186 (and later) MISC register block - -The MISC register block found on Tegra186 and later SoCs contains registers -that can be used to identify a given chip and various strapping options. - -Required properties: -- compatible: Must be: - - Tegra186: "nvidia,tegra186-misc" - - Tegra194: "nvidia,tegra194-misc" - - Tegra234: "nvidia,tegra234-misc" -- reg: Should contain 2 entries: The first entry gives the physical address - and length of the register region which contains revision and debug - features. The second entry specifies the physical address and length - of the register region indicating the strapping options. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml new file mode 100644 index 000000000000..cacb845868f4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) MISC register block + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The MISC register block found on Tegra186 and later SoCs contains + registers that can be used to identify a given chip and various strapping + options. + +properties: + compatible: + enum: + - nvidia,tegra186-misc + - nvidia,tegra194-misc + - nvidia,tegra234-misc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + misc@100000 { + compatible = "nvidia,tegra186-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt deleted file mode 100644 index 83f6a251ba3e..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra APBMISC block - -Required properties: -- compatible: Must be: - - Tegra20: "nvidia,tegra20-apbmisc" - - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" -- reg: Should contain 2 entries: the first entry gives the physical address - and length of the registers which contain revision and debug features. - The second entry gives the physical address and length of the - registers indicating the strapping options. - -Optional properties: -- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml new file mode 100644 index 000000000000..6f504fa74007 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APBMISC block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra210-apbmisc + - nvidia,tegra124-apbmisc + - nvidia,tegra114-apbmisc + - nvidia,tegra30-apbmisc + - const: nvidia,tegra20-apbmisc + + - items: + - const: nvidia,tegra20-apbmisc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + + nvidia,long-ram-code: + description: If present, the RAM code is long (4 bit). If not, short + (2 bit). + type: boolean + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; From patchwork Fri Nov 19 14:38:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557155 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=mf7qKqG5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfRx6J3zz9sS8 for ; Sat, 20 Nov 2021 01:38:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235943AbhKSOly (ORCPT ); Fri, 19 Nov 2021 09:41:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOly (ORCPT ); Fri, 19 Nov 2021 09:41:54 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FA7FC061574; Fri, 19 Nov 2021 06:38:52 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id z1-20020a05600c220100b00337f97d2464so7841625wml.1; Fri, 19 Nov 2021 06:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S3sjksDIQ9MKliIa1LJLuy02teNrCGoXHUHhRkTM9zo=; b=mf7qKqG5lWJmPEraoiVdQjoZs9eVlYwsa1XrvpppLBiuLPSsjBSk3pyL2TlhBEjPhY S8dPaNwAtf4UQgMlVLzpsKTU8wdRd+hJ3OcBPRxO5S6xmEQwo7XoeNgpZQvA9F+M0Rdu pe5SJKQYhJOIIR7gze7XysoTU1o4T6BtsCbnZ7pLuvZfW77Trcu8nDebcbggPz5Wj4tb 1b+Tya9JuKSywje3+XKZlrDBZmm/RWRhoJusJW0kbOwi1MK7rAVckCpZ6UmRkhNohiO4 q6JKFL9Da6pnx4fb9ASk6uOh28JaEtlPqpz/KVj7iGhIEMs+ZZDryLwHaQU4tn3z3R/C kofg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S3sjksDIQ9MKliIa1LJLuy02teNrCGoXHUHhRkTM9zo=; b=WrBJ9H5m6rS8aneL7BFFZXmSCl2UrzVcWR9QDJSasSyqc9lix2OdyTYmupuaKAwFl9 kTPfGJD+xEhVN5Hqq6RLjyiRYnJGQpP3e136cnk5Kn/3nmFAmBLwVNNfDqqzomL3qdeM vMIcIM3kZaUvzSfmEImuURw6++xVYuN4dvpBhtK/3WwQPaOxp1usSzmge++qIwiCKUz6 AmND1gsnafMvAg4D0Ufulszpp7seQ28EckMHbcAINLuKiqVzSsQHWMUpbwT88kwV/t/x JUmxQ1o/4UeeSu0WvNDh3eJ7D/W4BKOs0Y4jYCLZ6z2izmyYFKffvwAnB5Lg8h3q3PwE nB8Q== X-Gm-Message-State: AOAM532nj7fAFbe1rxNR5cN/sCNsxWkhp02kbnOshjvXUmUYpq7+dKLD b4WTlKt0eeY/pCfRsYPTm3aSJ2qGvl+fsA== X-Google-Smtp-Source: ABdhPJwRddkEmPE7G7dRobIU8x8u11AKArJ1syal6v5N+V0qkDCuZENC+mqv5Wxx4meXSJrgvTWCSA== X-Received: by 2002:a1c:a592:: with SMTP id o140mr199279wme.10.1637332730595; Fri, 19 Nov 2021 06:38:50 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id c16sm2950095wrx.96.2021.11.19.06.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:38:49 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:25 +0100 Message-Id: <20211119143839.1950739-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra SDHCI bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - drop redundant $ref properties, add missing maxItems .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 --------- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 294 ++++++++++++++++++ 2 files changed, 294 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index 96c0b1440c9c..000000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null @@ -1,143 +0,0 @@ -* NVIDIA Tegra Secure Digital Host Controller - -This controller on Tegra family SoCs provides an interface for MMC, SD, -and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-tegra driver. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra20-sdhci": for Tegra20 - - "nvidia,tegra30-sdhci": for Tegra30 - - "nvidia,tegra114-sdhci": for Tegra114 - - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - - "nvidia,tegra210-sdhci": for Tegra210 - - "nvidia,tegra186-sdhci": for Tegra186 - - "nvidia,tegra194-sdhci": for Tegra194 -- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. - One for the module clock and one for the timeout clock. - For all other Tegra devices, must contain a single entry for - the module clock. See ../clocks/clock-bindings.txt for details. -- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the - strings 'sdhci' and 'tmclk' to represent the module and - the timeout clocks, respectively. - For all other Tegra devices must contain the string 'sdhci' - to represent the module clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sdhci - -Optional properties: -- power-gpios : Specify GPIOs for power control - -Example: - -sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = <47>; - clocks = <&tegra_car 14>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <8>; -}; - -Optional properties for Tegra210, Tegra186 and Tegra194: -- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage - configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" - for controllers supporting multiple voltage levels. The order of names - should correspond to the pin configuration states in pinctrl-0 and - pinctrl-1. -- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for - Tegra210 where pad config registers are in the pinmux register domain - for pull-up-strength and pull-down-strength values configuration when - using pads at 3V3 and 1V8 levels. -- nvidia,only-1-8-v : The presence of this property indicates that the - controller operates at a 1.8 V fixed I/O voltage. -- nvidia,pad-autocal-pull-up-offset-3v3, - nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength - calibration offsets for 3.3 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-1v8, - nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength - calibration offsets for 1.8 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-3v3-timeout, - nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 3.3 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-1v8-timeout, - nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 1.8 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-sdr104, - nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength - calibration offsets for SDR104 mode. -- nvidia,pad-autocal-pull-up-offset-hs400, - nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength - calibration offsets for HS400 mode. -- nvidia,default-tap : Specify the default inbound sampling clock - trimmer value for non-tunable modes. -- nvidia,default-trim : Specify the default outbound clock trimmer - value. -- nvidia,dqs-trim : Specify DQS trim value for HS400 timing - - Notes on the pad calibration pull up and pulldown offset values: - - The property values are drive codes which are programmed into the - PD_OFFSET and PU_OFFSET sections of the - SDHCI_TEGRA_AUTO_CAL_CONFIG register. - - A higher value corresponds to higher drive strength. Please refer - to the reference manual of the SoC for correct values. - - The SDR104 and HS400 timing specific values are used in - corresponding modes if specified. - - Notes on tap and trim values: - - The values are used for compensating trace length differences - by adjusting the sampling point. - - The values are programmed to the Vendor Clock Control Register. - Please refer to the reference manual of the SoC for correct - values. - - The DQS trim values are only used on controllers which support - HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports - HS400. - -Example: -sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; - -sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml new file mode 100644 index 000000000000..1c3b9bbea6b4 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -0,0 +1,294 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Secure Digital Host Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + This controller on Tegra family SoCs provides an interface for MMC, SD, and + SDIO types of memory cards. + + This file documents differences between the core properties described by + mmc-controller.yaml and the properties for the Tegra SDHCI controller. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + - nvidia,tegra210-sdhci + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + + - items: + - const: nvidia,tegra132-sdhci + - const: nvidia,tegra124-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + assigned-clocks: true + assigned-clock-parents: true + assigned-clock-rates: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: sdhci + + power-gpios: + description: specify GPIOs for power control + maxItems: 1 + + iommus: + maxItems: 1 + + nvidia,default-tap: + description: Specify the default inbound sampling clock trimmer value for + non-tunable modes. + + The values are used for compensating trace length differences by + adjusting the sampling point. The values are programmed to the Vendor + Clock Control Register. Please refer to the reference manual of the SoC + for correct values. + + The DQS trim values are only used on controllers which support HS400 + timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,default-trim: + description: Specify the default outbound clock trimmer value. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,dqs-trim: + description: Specify DQS trim value for HS400 timing. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + + The property values are drive codes which are programmed into the + PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG + register. A higher value corresponds to higher drive strength. Please + refer to the reference manual of the SoC for correct values. The SDR104 + and HS400 timing specific values are used in corresponding modes if + specified. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,only-1-8v: + description: The presence of this property indicates that the controller + operates at a 1.8 V fixed I/O voltage. + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + +allOf: + - $ref: "mmc-controller.yaml" + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + clocks: + items: + - description: module clock + minItems: 1 + maxItems: 1 + else: + properties: + clocks: + items: + - description: module clock + - description: timeout clock + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: sdhci + - const: tmclk + minItems: 2 + maxItems: 2 + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-sdhci + then: + properties: + pinctrl-names: + oneOf: + - items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + then: + properties: + pinctrl-names: + items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mmc@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = <47>; + clocks = <&tegra_car 14>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <8>; + }; + + - | + #include + #include + + mmc@700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; + nvidia,default-tap = <0x2>; + nvidia,default-trim = <0x4>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_C4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; + }; From patchwork Fri Nov 19 14:38:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557157 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=lXzASvGz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; 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Fri, 19 Nov 2021 06:38:53 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id z14sm3387551wrp.70.2021.11.19.06.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:38:52 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 03/16] dt-bindings: mailbox: tegra: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:26 +0100 Message-Id: <20211119143839.1950739-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra HSP bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - add missing additionalProperties: false .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------ .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 ++++++++++++++++++ 2 files changed, 111 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt deleted file mode 100644 index ff3eafc5a882..000000000000 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ /dev/null @@ -1,72 +0,0 @@ -NVIDIA Tegra Hardware Synchronization Primitives (HSP) - -The HSP modules are used for the processors to share resources and communicate -together. It provides a set of hardware synchronization primitives for -interprocessor communication. So the interprocessor communication (IPC) -protocols can use hardware synchronization primitives, when operating between -two processors not in an SMP relationship. - -The features that HSP supported are shared mailboxes, shared semaphores, -arbitrated semaphores and doorbells. - -Required properties: -- name : Should be hsp -- compatible - Array of strings. - one of: - - "nvidia,tegra186-hsp" - - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" -- reg : Offset and length of the register set for the device. -- interrupt-names - Array of strings. - Contains a list of names for the interrupts described by the interrupt - property. May contain the following entries, in any order: - - "doorbell" - - "sharedN", where 'N' is a number from zero up to the number of - external interrupts supported by the HSP instance minus one. - Users of this binding MUST look up entries in the interrupt property - by name, using this interrupt-names property to do so. -- interrupts - Array of interrupt specifiers. - Must contain one entry per entry in the interrupt-names property, - in a matching order. -- #mbox-cells : Should be 2. - -The mbox specifier of the "mboxes" property in the client node should contain -two cells. The first cell determines the HSP type and the second cell is used -to identify the mailbox that the client is going to use. - -For doorbells, the second cell specifies the index of the doorbell to use. - -For shared mailboxes, the second cell is composed of two fields: -- bits 31..24: - A bit mask of flags that further specify how the shared mailbox will be - used. Valid flags are: - - bit 31: - Defines the direction of the mailbox. If set, the mailbox will be used - as a producer (i.e. used to send data). If cleared, the mailbox is the - consumer of data sent by a producer. - -- bits 23.. 0: - The index of the shared mailbox to use. The number of available mailboxes - may vary by instance of the HSP block and SoC generation. - -The following file contains definitions that can be used to construct mailbox -specifiers: - - - -Example: - -hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; -}; - -client { - ... - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml new file mode 100644 index 000000000000..c43fc4c56f77 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The HSP modules are used for the processors to share resources and + communicate together. It provides a set of hardware synchronization + primitives for interprocessor communication. So the interprocessor + communication (IPC) protocols can use hardware synchronization + primitives, when operating between two processors not in an SMP + relationship. + + The features that HSP supported are shared mailboxes, shared + semaphores, arbitrated semaphores and doorbells. + + The mbox specifier of the "mboxes" property in the client node should + contain two cells. The first cell determines the HSP type and the + second cell is used to identify the mailbox that the client is going + to use. + + For doorbells, the second cell specifies the index of the doorbell to + use. + + For shared mailboxes, the second cell is composed of two fields: + - bits 31..24: + A bit mask of flags that further specify how the shared mailbox + will be used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox + will be used as a producer (i.e. used to send data). If + cleared, the mailbox is the consumer of data sent by a + producer. + + - bits 23..0: + The index of the shared mailbox to use. The number of available + mailboxes may vary by instance of the HSP block and SoC + generation. + + The following file contains definitions that can be used to + construct mailbox specifiers: + + + +properties: + $nodename: + pattern: "^hsp@[0-9a-f]+$" + + compatible: + oneOf: + - const: nvidia,tegra186-hsp + - const: nvidia,tegra194-hsp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 9 + + interrupt-names: + oneOf: + # shared interrupts are optional + - items: + - const: doorbell + + - items: + - const: doorbell + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + - items: + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + "#mbox-cells": + const: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + client { + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>; + }; From patchwork Fri Nov 19 14:38:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557159 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=TcRYy4Dd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfS23f0rz9sS8 for ; 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Fri, 19 Nov 2021 06:38:54 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 04/16] dt-bindings: mailbox: tegra: Document Tegra234 HSP Date: Fri, 19 Nov 2021 15:38:27 +0100 Message-Id: <20211119143839.1950739-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the HSP block found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index c43fc4c56f77..9f7a7296b57f 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -57,6 +57,9 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - items: + - const: nvidia,tegra234-hsp + - const: nvidia,tegra194-hsp reg: maxItems: 1 From patchwork Fri Nov 19 14:38:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557161 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=SkxF/i1j; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfS516Vrz9sS8 for ; Sat, 20 Nov 2021 01:39:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235898AbhKSOmB (ORCPT ); Fri, 19 Nov 2021 09:42:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOmB (ORCPT ); Fri, 19 Nov 2021 09:42:01 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF2BEC061574; Fri, 19 Nov 2021 06:38:59 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id b184-20020a1c1bc1000000b0033140bf8dd5so7659685wmb.5; Fri, 19 Nov 2021 06:38:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VOjo5CXprhYwBXJymhhEQ4r0sW37uqRZzASN8wfkw40=; b=SkxF/i1jAMZbRjF5Uphejn89VxK1uRz4pvidf4wW0a0YnEkista/KoARU1m6WpiyDz ME+EAMUPskNheRzi4fuxEfY5q2Lfdg5TPu0wG9vOTMZXVZDEbO2UOfPTLIENrnMhYCTG 1UOFw6VJ/ZTottpVk4OO3k/ad1TVjvzqTW+IIMkFk2SIO6pWFlTOLR6CPhHIQfQrjI7v uXaMiWy47AVynGmAlArzQMtmSczVC0r8cW5eEmmuSkiPah3V9XHCKQ8PJDWF08wDho2M q2qNcGiIHPMoS/SqQH0ijgtgvohuEKJTiZOitBrr0luKFBu2mmw2ENL4/ZiiHI3L4T6p A7kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VOjo5CXprhYwBXJymhhEQ4r0sW37uqRZzASN8wfkw40=; b=MZioZsu5w+voGZox6tVhgut9eupAmzn5UzkzYhbtzBxmN2UI/VXMMFyUV5LuBV2otT Xv/rODYg7033rwo9iqUfUjYiSWXfxpwPNa20YXh563KS8Rke9iq00VOWb+QI5x4JOfU3 AhPDWjT2yejiZzRTCuVpt4ad5Preo/D0xRPxV2pgtfky5lMoRJzPURwNWHTCrYfZg+/1 j1BgwmeXDkX25Ye1+MT2RsF0AuHoqOUjNXmdefePY68j8iZ+NocPpIuUmT1AWLWSn3kt OED90bMbsCDO6csyw4l7TkMa5I0hSekJsvCioQpHqDq8g8V9MHNROF2a6XHucR6wIvKH He9g== X-Gm-Message-State: AOAM530Swe7SQ/n2p8aHgm6Z7hz6qzT6gxCfG0adBPr9+0mCaYHNkhdM AKOG660UazI04qGcClZHGbM= X-Google-Smtp-Source: ABdhPJxrPb6iNG9iY5P5J25oC7V9i2TxSW/PRV12I9csDupZjmY6CsvXP+FfCDm6EcPgpmv/roYBUQ== X-Received: by 2002:a1c:8015:: with SMTP id b21mr79343wmd.161.1637332738186; Fri, 19 Nov 2021 06:38:58 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h15sm3153814wml.9.2021.11.19.06.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:38:57 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:28 +0100 Message-Id: <20211119143839.1950739-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra RTC bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - document clock-names property and add additionalProperties: false .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 -------- .../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e098..000000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,-rtc", "nvidia,tegra20-rtc"', where - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml new file mode 100644 index 000000000000..94266de73cb9 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra real-time clock + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra RTC maintains seconds and milliseconds counters, and five + alarm registers. The alarms and other interrupts may wake the system + from low-power state. + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-rtc + - items: + - enum: + - nvidia,tegra30-rtc + - nvidia,tegra114-rtc + - nvidia,tegra124-rtc + - nvidia,tegra210-rtc + - nvidia,tegra186-rtc + - nvidia,tegra194-rtc + - const: nvidia,tegra20-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + timer@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; + }; From patchwork Fri Nov 19 14:38:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557163 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=O6K596yW; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfS73MMrz9sS8 for ; Sat, 20 Nov 2021 01:39:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235962AbhKSOmE (ORCPT ); Fri, 19 Nov 2021 09:42:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOmE (ORCPT ); Fri, 19 Nov 2021 09:42:04 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18BE4C061574; Fri, 19 Nov 2021 06:39:02 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id a9so18540513wrr.8; Fri, 19 Nov 2021 06:39:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RVh2KvmWaXSrzgI1sSlud1jjLQ6p4L1rLolhS5vwJb8=; b=O6K596yWMS2nsG/LR2+7pdf0h3mdaBjQ9suOuHbbr7BYXTjdAtPXd+GF0Up6bw3sHu Owy/1c8JW9SqktScF8YYIfTUFY6pk5KdSPnWoGySQIkn1ZnNUjj5wQQn271EeCEumkW4 7eZ11OLjMHAra8B0phkqCuuuxYtBBjD+UQ3x1BQXIY1TNAEXsA1LwQXhgAe1LBmqHD54 rbZKeuG4mmgF1fk72X+aiXE+nLeXKuoIoSUH2lrJTM5eIj77s54awRx/qXiDhQfUZtj1 Kk6OJ7/biQ2SedlmsStzl1PVwE1RfynFW5IQJQCYysYBCyGtn4OCYH/+u/0PouuPauNk GI+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RVh2KvmWaXSrzgI1sSlud1jjLQ6p4L1rLolhS5vwJb8=; b=rvqQHFBq024PmeoiyYdv51B1px6G+fuPV12TpuDI4W0PZxDQA5rq2NK6sICdYy2Vlh +LWXj0EP1jEs9XoghkNsi6baW7vzMDJYTA9lZ/Qw82pNPulbxmtn78eai7/+8NzeH7Cl AGyg/dTAsapvg21H35ANiGJ1l5y7Iy1+hoInk3z8ehpAQ7v2JLdtFjowDsUchukWoD2I TRt80qX4M2eGoEBhF6kkhgMxTJ6VWY6Uh5sjaB+p+5+cv0yYRRy8xX//CLyhAJptN7O+ ukBo5CyQd7crKiRGT7Hoew27Qf0bCGXZGtIdTj/+CAVSpl4LT3iVu30FBOStOCeFqARp KTIA== X-Gm-Message-State: AOAM532rtQ89iK7rKEoQmJRdSIFcaSQ7AxS0S4oc9hEhuILx5t/GrgAI iOcf0snyZOjY2ycowKFPC64= X-Google-Smtp-Source: ABdhPJzjGQ5cR3UNBSuKToI93jmDRFTdW2NdPvANlHWV/PoaQYz5997qnivD6f3btDjIcEeaZWtSOA== X-Received: by 2002:a5d:400e:: with SMTP id n14mr7658411wrp.368.1637332740578; Fri, 19 Nov 2021 06:39:00 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l15sm3042986wme.47.2021.11.19.06.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:38:59 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 06/16] dt-bindings: rtc: tegra: Document Tegra234 RTC Date: Fri, 19 Nov 2021 15:38:29 +0100 Message-Id: <20211119143839.1950739-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the RTC block found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml index 94266de73cb9..17d6280e5515 100644 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-rtc - nvidia,tegra186-rtc - nvidia,tegra194-rtc + - nvidia,tegra234-rtc - const: nvidia,tegra20-rtc reg: From patchwork Fri Nov 19 14:38:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557165 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Gci5VyVH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSB1ZBxz9sS8 for ; Sat, 20 Nov 2021 01:39:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235968AbhKSOmH (ORCPT ); Fri, 19 Nov 2021 09:42:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOmG (ORCPT ); Fri, 19 Nov 2021 09:42:06 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95EF7C061574; Fri, 19 Nov 2021 06:39:04 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id y196so8708220wmc.3; Fri, 19 Nov 2021 06:39:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CQxCnPcAPbozA2Unzyb1BDSDrGy+z8YGUBHGD0vjHKA=; b=Gci5VyVHTqf1lB328y24FBP7t8yi7uP18OIw71G4rDqcHzQzV47zsBtjZ3hw+kDJWf pC/FwJsNs5Vat0o+l5ks74qdZtTkKf/Pl1xIIdqpop6esB/mPyrGb2pbQH8ngNlxUWjP mBHbRUazjBoDg+FRDmyh25qnfxU0Y+PgfPGvtEkwHf3QWTWDEgSktp6P6LYpJNk7qVBn 4WR903htchz63AgSpuUAw9gQOM8aAr4X7/JVvOpv/TVp/NEmNY5IAIycFPDF50i1MvFJ 1JL6tU+JZw2vdt/IedLEBVIAAwlEhXUt+2aiPoP9SscSiHR6UdMTTEa9T7wC0+O4B9zw maRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CQxCnPcAPbozA2Unzyb1BDSDrGy+z8YGUBHGD0vjHKA=; b=FaDESd20d85ubgVSeGXKLoNFOjtZ8J5FA/U6KjYCq2khBJCHSeEySFmJ8pOPU2FP9i 6zCSFJfQqm6hvzIZzXtT8RDcaxv+PiY9N09m6eNMnW+xGyMat5dFDrbh36IUgwIfn93e 8iFAP7LXie6hZPnbvvyGiSir5vbifO2xCIlci7Z8iwjzyObQDoysEGjC3JVe2JOzJung WVl5J9tksnDUL9lh0GEMMaK2hS+T/3to0cxX9SRpBNf1PzOC+6P+8iWAottt9tkM7aHT vebe72L5Fe8OFBHFWhPNmKDAkt1x5KxuRII9jS3juhR239Gei6RcBADckRxn9J0qid9i tijg== X-Gm-Message-State: AOAM532fijRxY8JTPOvXgwSdq63p9nKQaNER5Avm15KlKtReQNKtsPhd Hv0uYuEP4C+NB+OMM/bZJa4= X-Google-Smtp-Source: ABdhPJxhdNtCfz2zPSLVc8pZFLWoFagwwEYOpBucfpd3lI7H7Ty//JolA4XHo2ZA/dI4WFlD7m7sRA== X-Received: by 2002:a1c:4d15:: with SMTP id o21mr76615wmh.171.1637332743117; Fri, 19 Nov 2021 06:39:03 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id p12sm3208028wro.33.2021.11.19.06.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:02 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:30 +0100 Message-Id: <20211119143839.1950739-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - add missing additionalProperties: false .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ---------- .../bindings/fuse/nvidia,tegra20-fuse.yaml | 81 +++++++++++++++++++ 2 files changed, 81 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index b109911669e4..000000000000 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". - For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain - "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". - For Tegra234 must contain "nvidia,tegra234-efuse". - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml new file mode 100644 index 000000000000..8d608e722ab2 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra FUSE block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra210-efuse + - nvidia,tegra186-efuse + - nvidia,tegra194-efuse + + - items: + - const: nvidia,tegra132-efuse + - const: nvidia,tegra124-efuse + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fuse + + resets: + maxItems: 1 + + reset-names: + items: + - const: fuse + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra132-efuse + - nvidia,tegra210-efuse +then: + required: + - resets + - reset-names + +examples: + - | + #include + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; From patchwork Fri Nov 19 14:38:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557167 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=kPhthXKw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSD6NNnz9sS8 for ; Sat, 20 Nov 2021 01:39:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235971AbhKSOmJ (ORCPT ); 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Fri, 19 Nov 2021 06:39:04 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 08/16] dt-bindings: fuse: tegra: Document Tegra234 FUSE Date: Fri, 19 Nov 2021 15:38:31 +0100 Message-Id: <20211119143839.1950739-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the FUSE block found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 8d608e722ab2..ce1056174778 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -21,6 +21,7 @@ properties: - nvidia,tegra210-efuse - nvidia,tegra186-efuse - nvidia,tegra194-efuse + - nvidia,tegra234-efuse - items: - const: nvidia,tegra132-efuse From patchwork Fri Nov 19 14:38:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557169 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=kJdlkr7/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSG71CKz9sS8 for ; Sat, 20 Nov 2021 01:39:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235975AbhKSOmL (ORCPT ); Fri, 19 Nov 2021 09:42:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbhKSOmL (ORCPT ); Fri, 19 Nov 2021 09:42:11 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D0ACC061748; Fri, 19 Nov 2021 06:39:09 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id b12so18529960wrh.4; Fri, 19 Nov 2021 06:39:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jQt3bGvPXR3AJH0Wpc4Hw/qwqDdumuScQ+nidDp9608=; b=kJdlkr7/0xGuBZqPdpB6AUoLVwI1+5hmjBWwFpwYuKCmZyAzOGNSqSnjk96I+S9PZJ ip0FX0OUAJEyYH5e6le1mzSba4jz+kLefESPgqVhy1iy2/lrPU7Z+nOnKqugxoy/FbcS mMrhku/2UCQWbwTD06kXcy0jsUwUvvw2IL73XOtOK+msryL+piBayoBqk4fjxRATv39P S3JVwFpJSC93IwACRL4c1sWzDBZesaZ0zuYxHaJ21cNVH4AN7EC9KHSgYHEkekrfSR75 Mg/N9b4qtplmRYJ+6p13ar61ytmzfnfsAYoFKApd0yC6tF7CTkKsG0p91pUYSahcVwg3 3vEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jQt3bGvPXR3AJH0Wpc4Hw/qwqDdumuScQ+nidDp9608=; b=EySjo7gEPzt8GswwQM7FHBNNkNxmcLqiqpEW2ZauhrmK8gsqHQN55ps+5rYirVuOai wiaQEuHfAhp0b08LvhPc2L4sZHZX/GJo8rMl3VEKNYpdlICYINnC1r2fnCRVfwXE6/99 uI87YL17hkN1jeeupMxlrM4/R2rO8hTRAkoWSA7eRGQQtvZsfZvs8qTFN2pKbw97fJJs LclKkFpBKwHPXpzh1T+SMvUyl7f5IT4/v+lWAwJ+K5DbNTrN1K0fo/Sj+rM5+Ju+gsfX RKjWX135JeFbYk+TvimwGCpvVnKoJHRir3biLkSrGGrc7LikAnIeJChJndTpJ8GmG0T9 kgSA== X-Gm-Message-State: AOAM5329jjYZaZftwJFcqhb1rmrf495JHRlg/UXKjDDMd81xnbBi6vjT Us5Q9LN9PX9ThJRnDIj4EgXXCwyTjFLvgw== X-Google-Smtp-Source: ABdhPJyV02yiQs9fkib5ZsBclMYwhGNrHe9lu0/MEjKpSnSjn9Pa1VVgpWMKEZt+RA+GrqsVgC5OTQ== X-Received: by 2002:adf:d20e:: with SMTP id j14mr7904920wrh.220.1637332748044; Fri, 19 Nov 2021 06:39:08 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h2sm2999388wrz.23.2021.11.19.06.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:07 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 09/16] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Date: Fri, 19 Nov 2021 15:38:32 +0100 Message-Id: <20211119143839.1950739-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the SDHCI block found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index 1c3b9bbea6b4..a361896323d0 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -33,6 +33,12 @@ properties: - const: nvidia,tegra132-sdhci - const: nvidia,tegra124-sdhci + - items: + - enum: + - nvidia,tegra194-sdhci + - nvidia,tegra234-sdhci + - const: nvidia,tegra186-sdhci + reg: maxItems: 1 From patchwork Fri Nov 19 14:38:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557171 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=YnIyeLQN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSK36bWz9sS8 for ; Sat, 20 Nov 2021 01:39:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235976AbhKSOmO (ORCPT ); Fri, 19 Nov 2021 09:42:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235977AbhKSOmN (ORCPT ); Fri, 19 Nov 2021 09:42:13 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0384AC06174A; Fri, 19 Nov 2021 06:39:12 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id u1so18504468wru.13; Fri, 19 Nov 2021 06:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DvmflS0p1AV4yRC5qHHwVEmvP4IwgGTcmBAOtxdyyHA=; b=YnIyeLQNANbl/vDEO/LLBsH4mxXppiXaKuHyK8pttF2oMieJYDf1R0FpRaphZUDsqK PSldtjUgyAumZQZctIH323lnP/YIsUCDPjA1NODbuvQ0qTLtpmwqFQj6UvNT99M+HaYr bB6ow0Z67axt6SK9Qu/ZHvqQql3vkjyuFodZauP/eFyuxIVlzvqFFBhrQ+dZp18KnyO/ XGxEKavf7NSLtfYjo9UQm+aW4aysfMqu6ehG/2juJH/XYKr8zZqHay5R5XDuwHbGhLlU ZhnbA6J6eXhPOwEF/q0fvwRrvZShtl2D1f8UZerQEgO80i98RyCiGzmK2IJUycB1DcGK xhVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DvmflS0p1AV4yRC5qHHwVEmvP4IwgGTcmBAOtxdyyHA=; b=rzsezQAzY3135TiGbFbS9U6N7GbRjSJYXpCdfdXSs//6HsLlA2eJ1wNdYeZVRxNl9k szuMjQMNE1y6dtIu3NhDR8jqtGVf95J5yE2VfFeXkb75KT0SzPswWzLzElK13Mb2NbkN kDoVX1l3KaLFWQuV2voDRL7o3XismiF7Z/VXPWndLocL78SIgc9RMYs/lK1PLcVkt6jj gTcDEltCz2itcwoba2waLWrK9QgmZpsFZMtABY5K3VEIWbTz+YK9NIuR4Wqw4pRhoN77 dRY5M3hsp49Y/FppOlmMdpq6LoM363QAAdVahn7aZE/ukyrd8hq1A/PqYEOQO+TOP23A bfNw== X-Gm-Message-State: AOAM533GusSIMNJ+xLZredgn9GAFEWJ8HOLJ5a8fHmk5wHbIIS3jvct3 J0vchGcoo+5PlW+LdybQ+mo= X-Google-Smtp-Source: ABdhPJxMAeWWROc8t0vYKK6KckmT3grqLiEK1hwMS+u0HqeWoPlfNntjaOvvuKWMdYkF12EdSB5NLA== X-Received: by 2002:a5d:648e:: with SMTP id o14mr8153037wri.69.1637332750553; Fri, 19 Nov 2021 06:39:10 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h13sm3109588wrx.82.2021.11.19.06.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:09 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 10/16] dt-bindings: serial: 8250: Document Tegra234 UART Date: Fri, 19 Nov 2021 15:38:33 +0100 Message-Id: <20211119143839.1950739-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the UART found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/8250.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index fa767440f281..3bab2f27b970 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -113,9 +113,10 @@ properties: - nvidia,tegra30-uart - nvidia,tegra114-uart - nvidia,tegra124-uart + - nvidia,tegra210-uart - nvidia,tegra186-uart - nvidia,tegra194-uart - - nvidia,tegra210-uart + - nvidia,tegra234-uart - const: nvidia,tegra20-uart reg: From patchwork Fri Nov 19 14:38:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557173 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=M7MyIHvg; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSN5XPrz9sS8 for ; Sat, 20 Nov 2021 01:39:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235981AbhKSOmR (ORCPT ); Fri, 19 Nov 2021 09:42:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233963AbhKSOmQ (ORCPT ); Fri, 19 Nov 2021 09:42:16 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B290C061574; Fri, 19 Nov 2021 06:39:14 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id b184-20020a1c1bc1000000b0033140bf8dd5so7660171wmb.5; Fri, 19 Nov 2021 06:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P/7ztmZKHyyKzC/vfI/wZjARcBDSSOm3pOkQTYjxERE=; b=M7MyIHvggnK5ua5LQI2jD/8ckS9Te/5c8rz0AlD4ik7yeOMZMab5H8lI84b0y4FT78 YVFERicKTVE92xWQKd0Lmi2TKnda7ayOu0hukLbqkR23BKWbu/M7zM+vcSr7aTcYMGTq Id+E4acwQ9WN8fr8KPmEUMeWsMUHFYxOLZRfBzoudNmJa3avINnF5MxyL8LMWPHKaKHJ tLuesrCg3Mt9b12WJLZhIpgSAQ1umysrbXBeP43PYtB5/2IK0pkblbDhLbMv7UxlYSu0 +ytwVE75gfhK6PAP7DeJZkTQd/5QKQFDGxY5wTge+FrhmPoSeDpyffDJge0xwY6gmK8/ tIRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P/7ztmZKHyyKzC/vfI/wZjARcBDSSOm3pOkQTYjxERE=; b=scClj8jWwW1XGqmKOthIFDLlSY+CGa4TgzbEmu7GN96RYV41ugF733XWbI+0175iRW rQiZ/qZrLjI1h4iMWfQZGFw5rH77TcnRjKfwj+D0o/sKQ4pWrD8c9lq7a9amlMC6Glxz 1Gu73v+xdOQl951P4NVI4je+Xyemln/eV/D7CEC4+tXyx+SuSKZC9k62Z1TYPYf/QClg DQN+36FDtNaVszDCoe35rzEh8zja6efWq5pJu8cWYZTy2KmOVt3/Nj4I6FA638ixd95M Ojhqmr4trx8rkdXyjG8dlTTEwvBXG9/mJWeZKTfCoWjPAAQx4Mpb8g0KlfFBbYqloD3w ScqA== X-Gm-Message-State: AOAM531IYC3ouVpmV1nbI/7tIVOIvdUKuhfu0Uxc+//idCbyvI0H7bRK itqyx12KR4bXsLjzlo922To= X-Google-Smtp-Source: ABdhPJxDBepXBQeTrrzh05hq3lfqZSaxNaj8I9+OCTbpkFyNu3VoaZS35YhV+8FVJCTywd3UmVXg/Q== X-Received: by 2002:a1c:a984:: with SMTP id s126mr149402wme.156.1637332752761; Fri, 19 Nov 2021 06:39:12 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l15sm3043451wme.47.2021.11.19.06.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:12 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:34 +0100 Message-Id: <20211119143839.1950739-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------ .../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++++++++ 2 files changed, 199 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 576462fae27f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,133 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 - - "nvidia,tegra234-pmc": for Tegra234 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194 and later) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -Pad configurations are described with pin configuration nodes which -are placed under the pmc node and they are referred to by the pinctrl -client properties. For more information see -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - -The following pads are present on Tegra186: -csia csib dsi mipi-bias -pex-clk-bias pex-clk3 pex-clk2 pex-clk1 -usb0 usb1 usb2 usb-bias -uart audio hsic dbg -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv -sdmmc4 cam dsib dsic -dsid csic csid csie -dsif spi ufs dmic-hv -edp sdmmc1-hv sdmmc3-hv conn -audio-hv ao-hv - -Required pin configuration properties: - - pins: A list of strings, each of which contains the name of a pad - to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the above pads except - for ao-hv. Following pads have software configurable signaling - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, - ao-hv. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@3400000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - - ... - - sor0: sor@15540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml new file mode 100644 index 000000000000..6946df96ec81 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + enum: + - nvidia,tegra186-pmc + - nvidia,tegra194-pmc + - nvidia,tegra234-pmc + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + maxItems: 5 + items: + - const: pmc + - const: wake + - const: aotag + - const: scratch + - const: misc + + interrupt-controller: true + + "#interrupt-cells": + description: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + const: 2 + + nvidia,invert-interrupt: + description: If present, inverts the PMU interrupt signal. + $ref: /schemas/types.yaml#/definitions/flag + +if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc +then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 +else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + +patternProperties: + "^[a-z0-9]+-[a-z0-9]+$": + if: + type: object + then: + description: | + These are pad configuration nodes. On Tegra SoCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power + state and signaling voltage. A pad can be either in active or + power down mode. The support for power state and signaling voltage + configuration varies depending on the pad in question. 3.3 V and + 1.8 V signaling voltages are supported on pins where software + controllable signaling voltage switching is available. + + Pad configurations are described with pin configuration nodes + which are placed under the pmc node and they are referred to by + the pinctrl client properties. For more information see + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The following pads are present on Tegra186: + + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv + + The following pads are present on Tegra194: + + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, + audio-hv, ao-hv + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain the name of the pad(s) to be + configured. + + low-power-enable: + description: Configure the pad into power down mode. + $ref: /schemas/types.yaml#/definitions/flag + + low-power-disable: + description: Configure the pad into active mode. + $ref: /schemas/types.yaml#/definitions/flag + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling + voltages. + + The values are defined in + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + The power state can be configured on all of the above pads + except for ao-hv. Following pads have software configurable + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, + audio-hv, ao-hv. + + phandle: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +dependencies: + interrupt-controller: ['#interrupt-cells'] + "#interrupt-cells": + required: + - interrupt-controller + +examples: + - | + #include + #include + #include + #include + #include + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + nvidia,invert-interrupt; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + }; + + sdmmc1: mmc@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; From patchwork Fri Nov 19 14:38:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557175 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=BXYeS1y/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Fri, 19 Nov 2021 06:39:15 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id 10sm4221586wrb.75.2021.11.19.06.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:14 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 12/16] dt-bindings: firmware: tegra: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:35 +0100 Message-Id: <20211119143839.1950739-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - add some missing properties and set additionalProperties to false .../firmware/nvidia,tegra186-bpmp.txt | 107 ---------- .../firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++++++++ 2 files changed, 186 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index e44a13bc06ed..000000000000 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- -- ../power/power-domain.yaml -- -- .../reset/reset.txt -- - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml new file mode 100644 index 000000000000..833c07f1685c --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The BPMP is a specific processor in Tegra chip, which is designed for + booting process handling and offloading the power management, clock + management, and reset control tasks from the CPU. The binding document + defines the resources that would be used by the BPMP firmware driver, + which can create the interprocessor communication (IPC) between the + CPU and BPMP. + + This node is a mailbox consumer. See the following files for details + of the mailbox subsystem, and the specifiers implemented by the + relevant provider(s): + + - .../mailbox/mailbox.txt + - .../mailbox/nvidia,tegra186-hsp.yaml + + This node is a clock, power domain, and reset provider. See the + following files for general documentation of those features, and the + specifiers implemented by this node: + + - .../clock/clock-bindings.txt + - + - ../power/power-domain.yaml + - + - .../reset/reset.txt + - + + The BPMP implements some services which must be represented by + separate nodes. For example, it can provide access to certain I2C + controllers, and the I2C bindings represent each I2C controller as a + device tree node. Such nodes should be nested directly inside the main + BPMP node. + + Software can determine whether a child node of the BPMP node + represents a device by checking for a compatible property. Any node + with a compatible property represents a device that can be + instantiated. Nodes without a compatible property may be used to + provide configuration information regarding the BPMP itself, although + no such configuration nodes are currently defined by this binding. + + The BPMP firmware defines no single global name-/numbering-space for + such services. Put another way, the numbering scheme for I2C buses is + distinct from the numbering scheme for any other service the BPMP may + provide (e.g. a future hypothetical SPI bus service). As such, child + device nodes will have no reg property, and the BPMP node will have no + "#address-cells" or "#size-cells" property. + + The shared memory area for the IPC TX and RX between CPU and BPMP are + predefined and work on top of sysram, which is an SRAM inside the + chip. See ".../sram/sram.yaml" for the bindings. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra194-bpmp + - nvidia,tegra234-bpmp + - const: nvidia,tegra186-bpmp + - const: nvidia,tegra186-bpmp + + mboxes: + description: A phandle and channel specifier for the mailbox used to + communicate with the BPMP. + maxItems: 1 + + shmem: + description: List of the phandle to the TX and RX shared memory area + that the IPC between CPU and BPMP is based on. + minItems: 2 + maxItems: 2 + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + - description: DMA read client + - description: DMA write client + + interconnect-names: + items: + - const: read + - const: write + - const: dma-mem # dma-read + - const: dma-write + + iommus: + maxItems: 1 + + i2c: + type: object + + thermal: + type: object + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + - "#clock-cells" + - "#power-domain-cells" + - "#reset-cells" + +examples: + - | + #include + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + sram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x30000000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000000 0x50000>; + + cpu_bpmp_tx: sram@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: sram@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; From patchwork Fri Nov 19 14:38:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557177 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Be5MYLq0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSS6qdqz9sS8 for ; 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Fri, 19 Nov 2021 06:39:17 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:36 +0100 Message-Id: <20211119143839.1950739-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding --- Changes in v2: - add missing additionalProperties: false .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 ------------------- .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt deleted file mode 100644 index ab240e10debc..000000000000 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra186 BPMP I2C controller - -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW -devices, such as the I2C controller for the power management I2C bus. Software -running on other CPUs must perform IPC to the BPMP in order to execute -transactions on that I2C bus. This binding describes an I2C bus that is -accessed in such a fashion. - -The BPMP I2C node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents an I2C controller. See ../i2c/i2c.txt for details of the -core I2C binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-i2c". -- #address-cells: Address cells for I2C device address. - Single-cell integer. - Must be <1>. -- #size-cells: - Single-cell integer. - Must be <0>. -- nvidia,bpmp-bus-id: - Single-cell integer. - Indicates the I2C bus number this DT node represent, as defined by the - BPMP firmware. - -Example: - -bpmp { - ... - - i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - #address-cells = <1>; - #size-cells = <0>; - nvidia,bpmp-bus-id = <5>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml new file mode 100644 index 000000000000..351e12124959 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) BPMP I2C controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + In Tegra186 and later, the BPMP (Boot and Power Management Processor) + owns certain HW devices, such as the I2C controller for the power + management I2C bus. Software running on other CPUs must perform IPC to + the BPMP in order to execute transactions on that I2C bus. This + binding describes an I2C bus that is accessed in such a fashion. + + The BPMP I2C node must be located directly inside the main BPMP node. + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP + binding. + + This node represents an I2C controller. See ../i2c/i2c.txt for details + of the core I2C binding. + +properties: + compatible: + const: nvidia,tegra186-bpmp-i2c + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + nvidia,bpmp-bus-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Indicates the I2C bus number this DT node represents, + as defined by the BPMP firmware. + +additionalProperties: false From patchwork Fri Nov 19 14:38:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557179 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Gh3PkeeZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSX1bHgz9sR4 for ; Sat, 20 Nov 2021 01:39:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235249AbhKSOmY (ORCPT ); Fri, 19 Nov 2021 09:42:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233963AbhKSOmY (ORCPT ); Fri, 19 Nov 2021 09:42:24 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28E62C061574; Fri, 19 Nov 2021 06:39:22 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id c4so18513286wrd.9; Fri, 19 Nov 2021 06:39:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Npk8T09MN3u7MPB/kTqp1CMriQODziO/BDGRUCLRDHg=; b=Gh3PkeeZL/gj5+pnoDmcs86bzqehgJ7giTtUokIwqiW+bbevRAH3ofCcrr5b/Iqczs VPpqce/BofQh023pvGr5ByNXw1YklQXkKg0QgwF89rrCoerd0USWSl7bABLPRuY2ShyD +kUNzOfmJwpK3AaEqjspd/5BbL9l/0eKNKX5zt90J54U9bxfQO7aG2K3U28/hXXQunLc 8qUsmgs+HyXdc0ChqeeSVAQPHgKQ5LxQC50KixaiqFsipE3RK3buw5T8/l4KUSKavNvn Irwk6i2urrdKFXxdfg3BNLEzRT0xIeqQl/sjejCRZubEDoFlTY/VtqqPapLxxD0CKCIN y94Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Npk8T09MN3u7MPB/kTqp1CMriQODziO/BDGRUCLRDHg=; b=ql6V9EciQfZcKx/0jGd7KnXXJArk4qhvhn4VBj4Y15X4IBK1ITPaCeb5lOG7lI/+DP iD9lcvjs4qGM6p/bR+GYZvyDxb/0a1YXhutKznWdss0y4AnwgaseHi7955VYxAfYvXCz HmVGyV+rBh3p01Xj5YrGtj2rqHTbCfgXNmFvyG+Nuy1mRENyFOMiZjeQtXYddHo45VhV 3gwU+jxV6MLvRbm/4zr4r7GPqg1X9YiTtVdNBJqm6gZkvGIduIaAap1/ECE6PdqFnpUv DcrpBUx3u2Yv+7w0+oNfa3Jr7fhF3yRqdLMGsgyW4nnecueZhOoHkDPsEgWvI++3CxwR i49Q== X-Gm-Message-State: AOAM532wA91pYymk9DKg4nCN7SXBQNMGxa+DWzPISHY1LuvvnCuz5JyR NmUeKDJYIS3kw6Cwubju19kM2DxsLUpO/g== X-Google-Smtp-Source: ABdhPJzsEgjlrZDt9AzKuHvWrRW6Y6rapVr6FtfNi6HqQqW6VdEzp6fnnGIjspLTKxPMR7MZnwJFAA== X-Received: by 2002:a5d:6702:: with SMTP id o2mr7849359wru.108.1637332760691; Fri, 19 Nov 2021 06:39:20 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id j17sm4490850wmq.41.2021.11.19.06.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:19 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:37 +0100 Message-Id: <20211119143839.1950739-15-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the Tegra186 (and later) BPMP thermal device tree bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 --------------- .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt deleted file mode 100644 index fc87f6aa1b8f..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ /dev/null @@ -1,33 +0,0 @@ -NVIDIA Tegra186 BPMP thermal sensor - -In Tegra186, the BPMP (Boot and Power Management Processor) implements an -interface that is used to read system temperatures, including CPU cluster -and GPU temperatures. This binding describes the thermal sensor that is -exposed by BPMP. - -The BPMP thermal node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the -core thermal binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-thermal" - - "nvidia,tegra194-bpmp-thermal" -- #thermal-sensor-cells: Cell for sensor index. - Single-cell integer. - Must be <1>. - -Example: - -bpmp { - ... - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml new file mode 100644 index 000000000000..c91fd07e4061 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) BPMP thermal sensor + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + In Tegra186, the BPMP (Boot and Power Management Processor) implements + an interface that is used to read system temperatures, including CPU + cluster and GPU temperatures. This binding describes the thermal + sensor that is exposed by BPMP. + + The BPMP thermal node must be located directly inside the main BPMP + node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the + BPMP binding. + + This node represents a thermal sensor. See + + Documentation/devicetree/bindings/thermal/thermal-sensor.yaml + + for details of the core thermal binding. + +properties: + compatible: + enum: + - nvidia,tegra186-bpmp-thermal + - nvidia,tegra194-bpmp-thermal + + '#thermal-sensor-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of cells needed in the phandle specifier to + identify a given sensor. Must be 1 and the single cell specifies + the sensor index. + const: 1 + +additionalProperties: false From patchwork Fri Nov 19 14:38:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557181 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=DObCJ8XE; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSb3FDTz9sS8 for ; Sat, 20 Nov 2021 01:39:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235988AbhKSOm2 (ORCPT ); Fri, 19 Nov 2021 09:42:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233963AbhKSOm0 (ORCPT ); Fri, 19 Nov 2021 09:42:26 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E155BC061574; Fri, 19 Nov 2021 06:39:24 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id s13so18568883wrb.3; Fri, 19 Nov 2021 06:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b8xXQKtUyU9ebK+LdHYtVXL4JcEXXJuMuyVb0n2sCgQ=; b=DObCJ8XEVvjACTO8d5Gkj0R8aQ7Toyurl1GVbrXLA3KtxFPx1XWWpzFYKlYrmvmCIb +tP3Rk3zhr+zlyNwumSevEWmj1zL1uDCSp4aduwwvGsUUvJ+oE/6maiae2dx30nqJMFH lQGpBN42RI9HQXjOc5brB0NTy3bXsIKhWgBCz+xAjOfgqDh6+W+JCoXh+x5PekDDigQX GiVR5lCssRvuvAsASHH1b+wazQXd/ydPbp3rv6TZnH2CONXB33gyU0NOlOov7HzBb6yB oY/LC+HsheU0fsoY82LwZWbqyINpk9yErEoI/NvZBBfPwCmh8Nqk66rEsbpAWX2yMSvr drjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b8xXQKtUyU9ebK+LdHYtVXL4JcEXXJuMuyVb0n2sCgQ=; b=Cy8QC2E0IKD8FAnVj7RBOPie31e1HqFi0Ccw8ICnJom4nM2tZbnkAUIJzuX3qxag6z ht6BKnQZzXxvY/zD9Il32Ew10htHFhGPoDw52yyVyF8PFYDfTTKNzkIob2BB6CAIc+n2 whL2CqlYctSi+Z0XCwIB725KRgFLRfdBfCmTfIEz3dpDMVvbDpAaTEIBswFtcVuhPywV 4UqyQHhBqlFPBKbxdwFOsZT4zZAOmv6smE2fVvT+ZHa1FahHNayXjGoEdjs3UejGmAMu 8H9CXqfEyIIqgKO/7V8o+bCu2vKusZ+p5FHo8ScTZyvUTsnSAOx1rOthuq49qEX3OMkW dJ1A== X-Gm-Message-State: AOAM5306WTgnb2D6f/1y2oheU9gHJLtTJ0vARxMGK4Q0L+N0dnCxjdk1 vwNVqW9FHZ65LPxtNLnYbjE= X-Google-Smtp-Source: ABdhPJyZGTWEsSVQz6DxxMnET1TZxQNmGYr5raFuoEHzMUAom+FilekC6qNFWg7yl7PQnfFIhavquw== X-Received: by 2002:a5d:5385:: with SMTP id d5mr7923432wrv.132.1637332763380; Fri, 19 Nov 2021 06:39:23 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id q123sm12226713wma.30.2021.11.19.06.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:22 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: Convert to json-schema Date: Fri, 19 Nov 2021 15:38:38 +0100 Message-Id: <20211119143839.1950739-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Convert the Tegra TCU device tree bindings to json-schema. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------ .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt deleted file mode 100644 index 085a8591accd..000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt +++ /dev/null @@ -1,35 +0,0 @@ -NVIDIA Tegra Combined UART (TCU) - -The TCU is a system for sharing a hardware UART instance among multiple -systems within the Tegra SoC. It is implemented through a mailbox- -based protocol where each "virtual UART" has a pair of mailboxes, one -for transmitting and one for receiving, that is used to communicate -with the hardware implementing the TCU. - -Required properties: -- name : Should be tcu -- compatible - Array of strings - One of: - - "nvidia,tegra194-tcu" -- mbox-names: - "rx" - Mailbox for receiving data from hardware UART - "tx" - Mailbox for transmitting data to hardware UART -- mboxes: Mailboxes corresponding to the mbox-names. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -Example bindings: ------------------ - -tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; - mbox-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml new file mode 100644 index 000000000000..7987eca0bb52 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Combined UART (TCU) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: + The TCU is a system for sharing a hardware UART instance among multiple + systems within the Tegra SoC. It is implemented through a mailbox- + based protocol where each "virtual UART" has a pair of mailboxes, one + for transmitting and one for receiving, that is used to communicate + with the hardware implementing the TCU. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + const: nvidia,tegra194-tcu + + mbox-names: + items: + - const: rx + - const: tx + + mboxes: + description: | + List of phandles to mailbox channels used for receiving and + transmitting data from and to the hardware UART. + items: + - description: mailbox for receiving data from hardware UART + - description: mailbox for transmitting data to hardware UART + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include + + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; From patchwork Fri Nov 19 14:38:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1557183 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=e/hYgUIN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HwfSd14JYz9sS8 for ; Sat, 20 Nov 2021 01:39:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235991AbhKSOm3 (ORCPT ); Fri, 19 Nov 2021 09:42:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233963AbhKSOm3 (ORCPT ); Fri, 19 Nov 2021 09:42:29 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C59DC061574; Fri, 19 Nov 2021 06:39:27 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id u1so18505769wru.13; Fri, 19 Nov 2021 06:39:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zeKFXDCOK1JKP/WgTGfGZCqCINDxzG0cnQHN+HuP6jE=; b=e/hYgUINDWKWu+hunJDTboMvSEFWzMucP05H+3J9UZq9X5Uz5h1ZZZH6KacL07Kev/ 2F7LnONvLEZMytV2wkduOfzkVac8mFokfMuZRH29qM676ACVYV/bEmtIS060f0m8VB9E 3yx7aXPCcpZC1TOBh70yUgeIg+TfFbWmaYJTKjBMu2elhgVvl+kbiHKDhbEM4AxpC6/n QdlamVxZPdqe4DXgiMYurm7Lt6CWcPvrHel18yMJ8Bhob0K7rRuzh0TPLlVDuZgkKc2F 7EUM8hZvFPCbHjUroIAHcklJGqBHEHahT4MuUAInwEWIcfZfWrthNkJs+P61uTbrqmDZ 5r8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zeKFXDCOK1JKP/WgTGfGZCqCINDxzG0cnQHN+HuP6jE=; b=pNICT+Mo/bTKf8vOEAc9zT+O2P8qYWobi/EAWjZ1MfUZZrR5ucq86i6tfwo5NWSTFZ zV4xclef5Rt+pGlIR555JZyvLq90bl8QpEZMAtgpg92nUDfEGSM96adpBB/zeMJcr/MG oMENYMF0hXQM5yjmHRoBeAg6cxxfF/ufqrIdPH3rVtEd0DdkTrdJ0DHMlzKyOmUVy3uU TO4+KWZ7ovgyuSzElnrB+pSwafnimZ1hPD/P1nWfomvSI6Kuaj1MayZ31rIpGtR9fLap 389KxAqUts6meCGSUFmhu37PAJFRU71pVvM/L2YVxA6twRS8fCACKtAtezA+lZRcYV0I tuDg== X-Gm-Message-State: AOAM532jiomoMz3H5WREP2ZaXtmwlDObYUKVGNmNNi/qOeREX84CpSjN himdbEP2J7I3wAc8dauH51k= X-Google-Smtp-Source: ABdhPJyYTRYl13JhHgXfELFbTAtF7IJlLsIIuP26yEa72zdkGK8O1XtC0z8IUQqcw0DadVfuZdZfMA== X-Received: by 2002:adf:a194:: with SMTP id u20mr7790281wru.153.1637332766134; Fri, 19 Nov 2021 06:39:26 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id d7sm3031770wrw.87.2021.11.19.06.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 06:39:25 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU Date: Fri, 19 Nov 2021 15:38:39 +0100 Message-Id: <20211119143839.1950739-17-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211119143839.1950739-1-thierry.reding@gmail.com> References: <20211119143839.1950739-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the compatible string for the TCU found on the Tegra234 SoC. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml index 7987eca0bb52..e2d111b3e0b0 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -22,7 +22,12 @@ properties: pattern: "^serial(@.*)?$" compatible: - const: nvidia,tegra194-tcu + oneOf: + - const: nvidia,tegra194-tcu + - items: + - enum: + - nvidia,tegra234-tcu + - const: nvidia,tegra194-tcu mbox-names: items: