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Fri, 19 Nov 2021 13:46:13 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 19 Nov 2021 05:46:11 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 19 Nov 2021 05:46:11 -0800 Envelope-to: git@xilinx.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Received: from [172.23.64.8] (port=38273 helo=xhdvnc108.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mo4DS-0006h0-Sn; Fri, 19 Nov 2021 05:46:11 -0800 Received: by xhdvnc108.xilinx.com (Postfix, from userid 16987) id 14856604A7; Fri, 19 Nov 2021 19:16:10 +0530 (IST) From: Manish Narani To: , , , CC: , , , , Subject: [PATCH] dt-bindings: usb: dwc3-xilinx: Convert USB DWC3 bindings Date: Fri, 19 Nov 2021 19:16:08 +0530 Message-ID: <1637329568-31756-1-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b3aab792-3783-4549-07db-08d9ab62f3a7 X-MS-TrafficTypeDiagnostic: BN6PR02MB3234: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2021 13:46:13.1680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3aab792-3783-4549-07db-08d9ab62f3a7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT057.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB3234 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert USB DWC3 bindings to DT schema format using json-schema. Signed-off-by: Manish Narani --- .../devicetree/bindings/usb/dwc3-xilinx.txt | 56 ---------- .../devicetree/bindings/usb/dwc3-xilinx.yaml | 119 +++++++++++++++++++++ 2 files changed, 119 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/dwc3-xilinx.txt create mode 100644 Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt deleted file mode 100644 index 04813a4..00000000 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt +++ /dev/null @@ -1,56 +0,0 @@ -Xilinx SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3" -- reg: Base address and length of the register control block -- clocks: A list of phandles for the clocks listed in clock-names -- clock-names: Should contain the following: - "bus_clk" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - - "ref_clk" Clock source to core during PHY power down -- resets: A list of phandles for resets listed in reset-names -- reset-names: - "usb_crst" USB core reset - "usb_hibrst" USB hibernation reset - "usb_apbrst" USB APB reset - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Optional properties for snps,dwc3: -- dma-coherent: Enable this flag if CCI is enabled in design. Adding this - flag configures Global SoC bus Configuration Register and - Xilinx USB 3.0 IP - USB coherency register to enable CCI. -- interrupt-names: Should contain the following: - "dwc_usb3" USB gadget mode interrupts - "otg" USB OTG mode interrupts - "hiber" USB hibernation interrupts - -Example device node: - - usb@0 { - #address-cells = <0x2>; - #size-cells = <0x1>; - compatible = "xlnx,zynqmp-dwc3"; - reg = <0x0 0xff9d0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; - clocks = <&clk125>, <&clk125>; - resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; - reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; - ranges; - - dwc3@fe200000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe200000 0x40000>; - interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 65 4>, <0 69 4>, <0 75 4>; - phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; - phy-names = "usb3-phy"; - dr_mode = "host"; - dma-coherent; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml new file mode 100644 index 00000000..193c69a6 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manish Narani + +properties: + compatible: + items: + - enum: + - xlnx,zynqmp-dwc3 + - xlnx,versal-dwc3 + reg: + maxItems: 1 + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: Clock source to core during PHY power down. + + clock-names: + items: + - const: bus_clk + - const: ref_clk + + resets: + description: + A list of phandles for resets listed in reset-names. + + items: + - description: USB core reset + - description: USB hibernation reset + - description: USB APB reset + + reset-names: + items: + - const: usb_crst + - const: usb_hibrst + - const: usb_apbrst + +# Required child node: + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - power-domains + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + axi { + #address-cells = <2>; + #size-cells = <2>; + + usb@0 { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clock-names = "bus_clk", "ref_clk"; + power-domains = <&zynqmp_firmware PD_USB_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + ranges; + + usb@fe200000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe200000 0x0 0x40000>; + interrupt-names = "dwc_usb3"; + interrupts = <0 65 4>; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + phy-names = "usb3-phy"; + dr_mode = "host"; + dma-coherent; + }; + }; + };