From patchwork Wed Nov 17 09:56:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1556131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=RSJ6bF4E; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HvJH32vLRz9sCD for ; Wed, 17 Nov 2021 20:56:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235719AbhKQJ71 (ORCPT ); Wed, 17 Nov 2021 04:59:27 -0500 Received: from mail-sn1anam02on2076.outbound.protection.outlook.com ([40.107.96.76]:10433 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235741AbhKQJ70 (ORCPT ); Wed, 17 Nov 2021 04:59:26 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mzj7ajbWhfNxmW91bm3+lwT/0BoaOrv0ym63zG9fTNvhulYc8T5qifmpflUHubYBG9iXYHivhur3xGeCrZ5GjfB+jqrsXBGbgKXc/ztGK7oDDsh07bFro2iPehXYfFEa1Hb6TnnqqZjHBTh+VI52L3W3yIBwRFvijDxiQvlg0CrmrIFMvlmaCXmJSFTJ3dWsmX+F6d1oBaNCYb2E2jNsfzjKUREC+sTub3fEX+Sg7n0RaUl+jFxLv6zFl3ezRPd0CzPCh0VTsV4+Z1Ru513S+fX730tiNFRndIDk5qW7rlK0bnaS2Rm+vFEpLXEb/Mdh5+BSnwyoxQGg+Azyp755iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IX46un4wkzovF72nSCtTQmW5ENCaTcrFLgi9cGA+kl8=; b=l4H6RuJzd/Pey1SE1HG46f9owprTVEecD81XZc8z+9JHjSIIt0mN4xIj3uDjegz2UB49BiJzIR/UY8hkzOFwn0cC8RoKONtUBJac/WaSpb70Pw0i/sGTwmFpuJneAd5mcSmwai+fVBw9SXHABJus9oUL9KN2dNDBmAov+gwBDfEaTrzkqo/SOaBAC8epfvCRdRGbH9yvHJzO6hNaiOHN5rqeWZSAnBAR241oZEe9RkUSLL4AonEKkBMQGYswnIwTTnJMUxg0dVtv3Lrt/CgsjKO7gvYb24Lw07errbQOYHHep0fZxco1lc4s5OyP5OF5vx4WaEnWhSx0UptOxHnRuw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.36) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IX46un4wkzovF72nSCtTQmW5ENCaTcrFLgi9cGA+kl8=; b=RSJ6bF4EwYSgUk4mkuCTHkl1NHfojT6ZM+qNPoVnqlGfAi496QfqZj2jaTnfNZMMKvx22JTjuivF901/RCw/PRzxJLAAF5zGWXaJ7r/TpfljKVfqolPFuVSCMXeP4mhY8M7fHajPJoG7pdoFeKhomH+Irg3qoVMiDKdsn7VHDwgb06U44i8tG8vRlpj1EEQni4ol0q80CkkCvgmZXLcb0LaQR3OFgRoYxcxQCjyz59IhvnqzitSVAdgmr9nJha4vNWU/c0zftrdjcZ4RHktKZ+82cH8QmFvMwbtcMH6RFwPQDhrGhOUuxvbLRs+eZNmxgQ1QQMTI+Lm2rlu2xEhPKA== Received: from BN0PR10CA0008.namprd10.prod.outlook.com (2603:10b6:408:143::27) by MN2PR12MB4143.namprd12.prod.outlook.com (2603:10b6:208:1d0::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Wed, 17 Nov 2021 09:56:25 +0000 Received: from BN8NAM11FT040.eop-nam11.prod.protection.outlook.com (2603:10b6:408:143:cafe::3e) by BN0PR10CA0008.outlook.office365.com (2603:10b6:408:143::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21 via Frontend Transport; Wed, 17 Nov 2021 09:56:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.36) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by BN8NAM11FT040.mail.protection.outlook.com (10.13.177.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Wed, 17 Nov 2021 09:56:24 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 17 Nov 2021 09:56:20 +0000 Received: from moonraker.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 17 Nov 2021 09:56:18 +0000 From: Jon Hunter To: Rob Herring , Thierry Reding , Mikko Perttunen CC: , , , Jon Hunter Subject: [PATCH V3 1/2] dt-bindings: Add YAML bindings for NVENC and NVJPG Date: Wed, 17 Nov 2021 09:56:07 +0000 Message-ID: <20211117095608.60415-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3353121b-ed78-4207-0211-08d9a9b084a8 X-MS-TrafficTypeDiagnostic: MN2PR12MB4143: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Mawl7PRPj53qkMjNOtVFMFDFY8Rm18gorc3lmDv1Xf/IwzfnljjNgYr5460c0qsb0r9pume7cXol99rvOk1zdwYQaYOpqk1kU1FoHMgsgj7b4e+4uLbi3AoQAGAGKQfPYPbl8UAjuLBjEbLBmEifLBypflNxwULCfs7oSlVpcDeN64ePUiboGt4oCkH/vrWn3+zsjcKuDcLcvW2I5D0dD840ToEsjg/vtZtqr6mBDZimpmCZm/Uk7crYVr5EUw2zCzk+nyrb93nGa38bTPaKHFQRHu9r9iTBxTUDivfs6bkn9JCxAmClnzPBAVq152G1eNICtH9vm4XoVj9GG/rvq63ZcsG0ULUunssgQW1Ti18qn2DHKv3Vx2jjREPUNOgl3XUieEkRRVmJ2F1ALX1X8tlpY4qGOalib9ek13e9Yy1SdeyFMyXkxflsat5JTYyIR7GGXMBa95SqTQR2TPH+bFxgV+6QVs7ZtJwtHFq+dsCsrpYTbLAj5UelWXPj/oTTvGKTE4Fsr8Uuz06NhtpTjbux0jNWnIdN0fAj7bfLthCGNPKzeXexKgDcaViK36d35kTuMGMapJkwnecVe8GNb+1Im7K7zLdoDD5vVeEQZWoMYD4Kdg+fV/xo0D36UEWWN/JEq1+aaZHkb0tIPFnpQPTriRasAMN8mf2X+c8ThRsUQ8jhAxPdpqPwB0FaAlGAzBllABnWRgTH4lgQJx2zxvk8KHo9Y2P4cMGUsjagbUuRW1jXP94ptHcvdcCIMLoE99qevlHk0WytnMo2SegECNBRbCLIlfBbPil5PYUd2jwPrzMQBu/8XS52BPYIZXJ24nJvJl/5CRycTW+ANybXqg== X-Forefront-Antispam-Report: CIP:216.228.112.36;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid05.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(70586007)(107886003)(4326008)(8676002)(7636003)(7696005)(5660300002)(1076003)(336012)(36860700001)(6636002)(86362001)(8936002)(47076005)(186003)(26005)(356005)(70206006)(508600001)(83380400001)(2906002)(54906003)(110136005)(6666004)(82310400003)(316002)(426003)(36756003)(2616005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2021 09:56:24.8170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3353121b-ed78-4207-0211-08d9a9b084a8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4143 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter Reviewed-by: Rob Herring --- Changes since V2: - Fixed indentation Changes since V1: - Fixed errors reported by Rob's bot .../gpu/host1x/nvidia,tegra210-nvenc.yaml | 135 ++++++++++++++++++ .../gpu/host1x/nvidia,tegra210-nvjpg.yaml | 94 ++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml new file mode 100644 index 000000000000..e63ae1a00818 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVENC + +description: | + NVENC is the hardware video encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvenc@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + - nvidia,tegra194-nvenc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvenc + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + maxItems: 3 + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0x21 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - if: + properties: + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: write + - if: + properties: + compatible: + enum: + - nvidia,tegra194-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml new file mode 100644 index 000000000000..8647404d67e4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVJPG + +description: | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically programmed + through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvjpg@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvjpg + - nvidia,tegra186-nvjpg + - nvidia,tegra194-nvjpg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvjpg + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvjpg + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; From patchwork Wed Nov 17 09:56:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1556129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=iWNSep2j; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HvJH11S4tz9s5P for ; Wed, 17 Nov 2021 20:56:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235720AbhKQJ7Y (ORCPT ); Wed, 17 Nov 2021 04:59:24 -0500 Received: from mail-dm6nam11on2087.outbound.protection.outlook.com ([40.107.223.87]:35456 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235719AbhKQJ7X (ORCPT ); Wed, 17 Nov 2021 04:59:23 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kei0xEHvHbfrAHIUnBxTHi+S3kenv2GZS2u5uQU7/JBXqxoYZ/jJX1cdvbm2tx7oKURES4Sh3n2AN+NLrjKidKR6AeYzviRnc0w44IH8zLpEzle7ZMmKmAQn37+caPiFytkfUb0Ykb7jLU68bNHyg/n2FvIOgiyGwR75+m7SBayQElYwUD2yosRUPKuY+QZc9ENpEGdqQGGGaJ9h9/7fu+B5iv8IurvAVNii2y0ywQ+Lpwp5xRPBY5WY5FWnAcMPT5afQSYGQWIf5VRIqO44vDbwEZOkNTMPdo6YbYl9BdHuP1yA/Z7+BoYYj6syACm5h1sGYymCi02RoVTWcd3Meg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Zn5Q8bh8jYStsvRCO/wZ+ql/12lFOmpC5TY/9K6oM/0=; b=RypWQkAnOXYX3THKpQ6Wq+G5N7x8zOswPKWKXL2g4EwvOaHmy6aFBVCdSSikheUA+Qu/IqFSxdAi36yK18wYpQIeF+jwQANHaxortr8Gfky9bWRMNtVQ+2tnegGAD3ryvfJuRV+FrJnAx9nAUVaD/guovdc+gUGe/FAn7feLAabi0WL9sJ9KrJKjGlDg+5wp+ImmKfwLe/1S5uTwTHIVo+/J+JEMY9MgH3JUzoWHRAn61vsLk3QKckhpjc0YGb1nmmwpK/Gf1gG4ScZUlXjB7bjbiS7CMpwGI+xVjFyl8Js0R9VcI+ivKCjHzRQGsP0v5biSm//LaoNil9dCZNRZNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Zn5Q8bh8jYStsvRCO/wZ+ql/12lFOmpC5TY/9K6oM/0=; b=iWNSep2jTWvZFxn870/rBnE7Bq3Dggrb9x1Mje9JUqnjXaL5BJOSTu4hizKObM9QJ+OnnMDiMkA5+3GmoiXyE+HeyuhBnrp+6lCw61KezAizN7HC4hL7L7J3di5Ee1w8XR78fbvwHHjV2qTDiqJVHi+wir56ELxO16x3Kw9JLMFplA7EvmohmX4jTLmJqFgBAlgbd+j4gj4LkGo46VjQjj6WA8lJl6v+IxPfYTI+505seGxdGhKlluX49U5X8ln4Js5mn2QdvqSUwMPyLSmksjFGCw33HkttJk9ibhMg2TzZWm51bdMgU2b9JwPnFgugYoNvgCUCNFv6rzD1x3vUUg== Received: from BN0PR03CA0039.namprd03.prod.outlook.com (2603:10b6:408:e7::14) by BY5PR12MB4115.namprd12.prod.outlook.com (2603:10b6:a03:20f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Wed, 17 Nov 2021 09:56:23 +0000 Received: from BN8NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e7:cafe::7f) by BN0PR03CA0039.outlook.office365.com (2603:10b6:408:e7::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.26 via Frontend Transport; Wed, 17 Nov 2021 09:56:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT032.mail.protection.outlook.com (10.13.177.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Wed, 17 Nov 2021 09:56:23 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 17 Nov 2021 09:56:22 +0000 Received: from moonraker.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 17 Nov 2021 09:56:20 +0000 From: Jon Hunter To: Rob Herring , Thierry Reding , Mikko Perttunen CC: , , , Jon Hunter Subject: [PATCH V3 2/2] arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194 Date: Wed, 17 Nov 2021 09:56:08 +0000 Message-ID: <20211117095608.60415-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211117095608.60415-1-jonathanh@nvidia.com> References: <20211117095608.60415-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a734b90b-6208-4bcf-5834-08d9a9b08360 X-MS-TrafficTypeDiagnostic: BY5PR12MB4115: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AwAJHm3+SMly8l6s2y4HiuwvjaS5ByFmMoeFuPWz9yJ0s+FQarfg+vNyJRSESBm1RVPk3HhiM7fJ1gys/85FRKlg+LIM7MCRjgEES5lJSynv+uewHsYaWOelHzFVu8qtoh9VUZHIv9OsCN4KXuhFUIFyKTIlyclplOnnX5NeWAeVcTvbfo5nfNi1QhFyjGx3xRA9M1qTF99NJ4To4NsO+JK8Mmzd73XxJGxmEsPKBSD8TgyqQC8w74QcwyMjbsnuF3MSn2MLqnhB5XTN9DMmqq0jlxvK/33g4Y4KTsEohUGOWdM7w4VTkYbd9QEQlFiFc336FT7y4QgFl36rdfHZy2yVZdnPlrLCdk/L8vS7T5J0nS80wtCkwD5ULdfdeKCkpvFLpHXSUttCr2z18ibUK767gdmus0DM4147ZD4Oo8MuNtw1b6Nu+57Fs4fpCA4NIaOC1XYgjqu6E1vXvgNb+fH9bK4MMUCUXesDfb9E9U4bpEjPhaawGoj/24GMa2xKz0Ah3ASJL8UIgs5nh0G+YSUn6pnB977fWa3M+0LBaBOmUZGSBKWLyvpCo+LnZkZ8EMlRXRr6NaWBdFbC3YgjJj3/NMg8BEExtCLFUOdq/jyPr2g5dbBAXxPokgxwEnqj1bVQGlednhxVNJxpfC/Jc9bQ6e0K4X57vAOpv/rm6Toh6Ey0vb+/j8O8RYEwy1fiuXiKlHZ9m9HtVwUSC0Pd1A== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(6666004)(70586007)(107886003)(36756003)(36906005)(4326008)(316002)(336012)(186003)(426003)(47076005)(8936002)(7696005)(508600001)(36860700001)(2906002)(70206006)(54906003)(110136005)(86362001)(5660300002)(8676002)(2616005)(82310400003)(26005)(1076003)(83380400001)(7636003)(6636002)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2021 09:56:23.1244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a734b90b-6208-4bcf-5834-08d9a9b08360 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4115 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter --- Changes since V1: - None arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 +++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 54 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9ac4f0140700..f21cfcaab2a6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1538,6 +1538,21 @@ vic@15340000 { iommus = <&smmu TEGRA186_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; + dsib: dsi@15400000 { compatible = "nvidia,tegra186-dsi"; reg = <0x15400000 0x10000>; @@ -1569,6 +1584,21 @@ nvdec@15480000 { iommus = <&smmu TEGRA186_SID_NVDEC>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; + sor0: sor@15540000 { compatible = "nvidia,tegra186-sor"; reg = <0x15540000 0x10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1adf076526c8..9586af9a100b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1782,6 +1782,22 @@ vic@15340000 { dma-coherent; }; + nvjpg@15380000 { + compatible = "nvidia,tegra194-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA194_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_NVJPG>; + dma-coherent; + }; + nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; reg = <0x15480000 0x00040000>; @@ -1801,6 +1817,25 @@ nvdec@15480000 { nvidia,host1x-class = <0xf0>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC>; + dma-coherent; + + nvidia,host1x-class = <0x21>; + }; + dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; reg = <0x155c0000 0x10000>; @@ -1937,6 +1972,25 @@ i2c-bus { }; }; + nvenc@15a80000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x15a80000 0x00040000>; + clocks = <&bpmp TEGRA194_CLK_NVENC1>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC1>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC1>; + dma-coherent; + + nvidia,host1x-class = <0x22>; + }; + sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; reg = <0x15b00000 0x40000>;