From patchwork Fri Nov 12 05:54:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Lo X-Patchwork-Id: 1554153 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Hr78055YZz9s5P for ; Fri, 12 Nov 2021 16:54:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231888AbhKLF5L (ORCPT ); Fri, 12 Nov 2021 00:57:11 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:42648 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231713AbhKLF5I (ORCPT ); Fri, 12 Nov 2021 00:57:08 -0500 X-UUID: 14228c4ded3a4d2cba7b17f2a6fe71af-20211112 X-UUID: 14228c4ded3a4d2cba7b17f2a6fe71af-20211112 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 386747951; Fri, 12 Nov 2021 13:54:13 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 12 Nov 2021 13:54:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 12 Nov 2021 13:54:12 +0800 From: James Lo To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , James Lo , , , , , , Subject: [RESEND, v14 1/3] dt-bindings: spmi: modify the constraint of reg property Date: Fri, 12 Nov 2021 13:54:08 +0800 Message-ID: <20211112055410.21418-2-james.lo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211112055410.21418-1-james.lo@mediatek.com> References: <20211112055410.21418-1-james.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The constraint of reg may larger than 1, so we modify to 'minItem: 1' and 'maxItem: 2'. And adds documentation for the SPMI controller found on Mediatek SoCs. Merge [RESEND,v13,2/4] into [RESEND,v13,1/4] for fix yaml error. [RESEND,v13,1/4] : dt-bindings: spmi: modify the constraint of reg property [RESEND,v13,2/4] : dt-bindings: spmi: document binding for the Mediatek SPMI controller Signed-off-by: James Lo Signed-off-by: Hsin-Hsiung Wang --- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 76 +++++++++++++++++++ .../devicetree/bindings/spmi/spmi.yaml | 3 +- 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..2445c5e0b0ef --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Hsin-Hsiung Wang + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +allOf: + - $ref: "spmi.yaml" + +properties: + compatible: + enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + + reg: + maxItems: 2 + + reg-names: + items: + - const: pmif + - const: spmimst + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: pmif_sys_ck + - const: pmif_tmr_ck + - const: spmimst_clk_mux + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0x10027000 0xe00>, + <0x10029000 0x100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +... diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml index 1d243faef2f8..f29183a45adc 100644 --- a/Documentation/devicetree/bindings/spmi/spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/spmi.yaml @@ -25,7 +25,8 @@ properties: pattern: "^spmi@.*" reg: - maxItems: 1 + maxItems: 2 + minItems: 1 "#address-cells": const: 2