From patchwork Fri Oct 22 06:05:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1544790 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HbDjd54gFz9sRN for ; Fri, 22 Oct 2021 17:20:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbhJVGWg (ORCPT ); Fri, 22 Oct 2021 02:22:36 -0400 Received: from [113.204.237.245] ([113.204.237.245]:45628 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229484AbhJVGWg (ORCPT ); Fri, 22 Oct 2021 02:22:36 -0400 X-MailGates: (compute_score:DELIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10974:0:AUTH_RELAY) (envelope-from ); Fri, 22 Oct 2021 14:05:50 +0800 (CST) From: qinjian To: robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, qinjian Subject: [PATCH 1/4] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Date: Fri, 22 Oct 2021 14:05:07 +0800 Message-Id: <20211022060507.280329-1-qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This introduces bindings for boards based Sunplus SP7021 SoC. Signed-off-by: qinjian Reviewed-by: Rob Herring --- .../bindings/arm/sunplus,sp7021.yaml | 26 +++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ MAINTAINERS | 6 +++++ 3 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml diff --git a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file mode 100644 index 000000000..3b0089981 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sunplus,sp7021-achip + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a867f7102..50d4ee5ac 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1131,6 +1131,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sunplus,.*": + description: Sunplus Technology Co., Ltd. "^SUNW,.*": description: Sun Microsystems, Inc "^supermicro,.*": diff --git a/MAINTAINERS b/MAINTAINERS index e0bca0de0..7a78b1bbe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2655,6 +2655,12 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian +L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang M: Sebastian Hesselbarth From patchwork Fri Oct 22 06:07:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1544791 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HbDjf0Glvz9sXN for ; Fri, 22 Oct 2021 17:20:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229484AbhJVGWg (ORCPT ); Fri, 22 Oct 2021 02:22:36 -0400 Received: from [113.204.237.245] ([113.204.237.245]:45636 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230238AbhJVGWg (ORCPT ); Fri, 22 Oct 2021 02:22:36 -0400 X-MailGates: (compute_score:DELIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10980:0:AUTH_RELAY) (envelope-from ); Fri, 22 Oct 2021 14:08:10 +0800 (CST) From: qinjian To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, qinjian Subject: [PATCH 2/4] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Date: Fri, 22 Oct 2021 14:07:37 +0800 Message-Id: <20211022060737.281116-1-qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 interrupt controller bindings. Signed-off-by: qinjian --- .../sunplus,sp7021-intc.yaml | 69 +++++++++++++++++++ MAINTAINERS | 2 + .../interrupt-controller/sp7021-intc.h | 24 +++++++ 3 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml create mode 100644 include/dt-bindings/interrupt-controller/sp7021-intc.h diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file mode 100644 index 000000000..73719f65b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + interrupts: + description: + Interrupts references to primary interrupt controller + + ext0-mask: + description: + cpu affinity of EXT_INT0. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 16 + + ext1-mask: + description: + cpu affinity of EXT_INT1. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 16 + +required: + - compatible + - interrupt-controller + - "#interrupt-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + intc: interrupt-controller@9c000780 { + compatible = "sunplus,sp7021-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-parent = <&gic>; + interrupts = , /* EXT_INT0 */ + ; /* EXT_INT1 */ + ext0-mask = <0xf>; /* core0-3 */ + ext1-mask = <0xe>; /* core1-3 */ + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7a78b1bbe..065da0846 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2660,6 +2660,8 @@ M: Qin Jian L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml +F: include/dt-bindings/interrupt-controller/sp7021-intc.h ARM/Synaptics SoC support M: Jisheng Zhang diff --git a/include/dt-bindings/interrupt-controller/sp7021-intc.h b/include/dt-bindings/interrupt-controller/sp7021-intc.h new file mode 100644 index 000000000..8f36e262e --- /dev/null +++ b/include/dt-bindings/interrupt-controller/sp7021-intc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + * + * + * This header provides constants for the SP7021 INTC + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_SP7021_INTC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_SP7021_INTC_H + +#include + +/* + * Interrupt specifier cell 1. + * The flags in irq.h are valid, plus those below. + */ +#define SP_INTC_EXT_INT0 0x00000 +#define SP_INTC_EXT_INT1 0x01000 +#define SP_INTC_EXT_INT_MASK 0xff000 +#define SP_INTC_EXT_INT_SHFIT 12 + +#endif From patchwork Fri Oct 22 06:11:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1544788 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HbDZn4jvWz9sRN for ; Fri, 22 Oct 2021 17:14:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbhJVGQk (ORCPT ); Fri, 22 Oct 2021 02:16:40 -0400 Received: from [113.204.237.245] ([113.204.237.245]:45560 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229484AbhJVGQk (ORCPT ); Fri, 22 Oct 2021 02:16:40 -0400 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10964:0:AUTH_RELAY) (envelope-from ); Fri, 22 Oct 2021 14:11:33 +0800 (CST) From: qinjian To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, qinjian Subject: [PATCH 3/4] dt-bindings: clock: Add bindings for SP7021 clock driver Date: Fri, 22 Oct 2021 14:11:05 +0800 Message-Id: <20211022061105.281807-1-qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: qinjian Reviewed-by: Rob Herring --- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000..5b3c0881b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x80>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 065da0846..474544db2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2660,7 +2660,9 @@ M: Qin Jian L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/interrupt-controller/sp7021-intc.h ARM/Synaptics SoC support diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/clock/sp-sp7021.h new file mode 100644 index 000000000..98c3feba1 --- /dev/null +++ b/include/dt-bindings/clock/sp-sp7021.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H + +#define XTAL 27000000 + +/* plls */ +#define PLL_A 0 +#define PLL_E 1 +#define PLL_E_2P5 2 +#define PLL_E_25 3 +#define PLL_E_112P5 4 +#define PLL_F 5 +#define PLL_TV 6 +#define PLL_TV_A 7 +#define PLL_SYS 8 + +/* gates: mo_clken0 ~ mo_clken9 */ +#define SYSTEM 0x10 +#define RTC 0x12 +#define IOCTL 0x13 +#define IOP 0x14 +#define OTPRX 0x15 +#define NOC 0x16 +#define BR 0x17 +#define RBUS_L00 0x18 +#define SPIFL 0x19 +#define SDCTRL0 0x1a +#define PERI0 0x1b +#define A926 0x1d +#define UMCTL2 0x1e +#define PERI1 0x1f + +#define DDR_PHY0 0x20 +#define ACHIP 0x22 +#define STC0 0x24 +#define STC_AV0 0x25 +#define STC_AV1 0x26 +#define STC_AV2 0x27 +#define UA0 0x28 +#define UA1 0x29 +#define UA2 0x2a +#define UA3 0x2b +#define UA4 0x2c +#define HWUA 0x2d +#define DDC0 0x2e +#define UADMA 0x2f + +#define CBDMA0 0x30 +#define CBDMA1 0x31 +#define SPI_COMBO_0 0x32 +#define SPI_COMBO_1 0x33 +#define SPI_COMBO_2 0x34 +#define SPI_COMBO_3 0x35 +#define AUD 0x36 +#define USBC0 0x3a +#define USBC1 0x3b +#define UPHY0 0x3d +#define UPHY1 0x3e + +#define I2CM0 0x40 +#define I2CM1 0x41 +#define I2CM2 0x42 +#define I2CM3 0x43 +#define PMC 0x4d +#define CARD_CTL0 0x4e +#define CARD_CTL1 0x4f + +#define CARD_CTL4 0x52 +#define BCH 0x54 +#define DDFCH 0x5b +#define CSIIW0 0x5c +#define CSIIW1 0x5d +#define MIPICSI0 0x5e +#define MIPICSI1 0x5f + +#define HDMI_TX 0x60 +#define VPOST 0x65 + +#define TGEN 0x70 +#define DMIX 0x71 +#define TCON 0x7a +#define INTERRUPT 0x7f + +#define RGST 0x80 +#define GPIO 0x83 +#define RBUS_TOP 0x84 + +#define MAILBOX 0x96 +#define SPIND 0x9a +#define I2C2CBUS 0x9b +#define SEC 0x9d +#define DVE 0x9e +#define GPOST0 0x9f + +#define OSD0 0xa0 +#define DISP_PWM 0xa2 +#define UADBG 0xa3 +#define DUMMY_MASTER 0xa4 +#define FIO_CTL 0xa5 +#define FPGA 0xa6 +#define L2SW 0xa7 +#define ICM 0xa8 +#define AXI_GLOBAL 0xa9 + +#define CLK_MAX 0xb0 + +#endif From patchwork Fri Oct 22 06:12:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qin Jian X-Patchwork-Id: 1544786 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HbDYM3Yn4z9sRN for ; Fri, 22 Oct 2021 17:13:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230393AbhJVGP0 (ORCPT ); Fri, 22 Oct 2021 02:15:26 -0400 Received: from [113.204.237.245] ([113.204.237.245]:45518 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229484AbhJVGP0 (ORCPT ); Fri, 22 Oct 2021 02:15:26 -0400 X-Greylist: delayed 403 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Oct 2021 02:15:25 EDT X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10970:0:AUTH_RELAY) (envelope-from ); Fri, 22 Oct 2021 14:12:44 +0800 (CST) From: qinjian To: p.zabel@pengutronix.de Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, qinjian Subject: [PATCH 4/4] dt-bindings: clock: Add bindings for SP7021 reset driver Date: Fri, 22 Oct 2021 14:12:16 +0800 Message-Id: <20211022061216.281903-1-qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Sunplus SP7021 reset driver bindings. Signed-off-by: qinjian Reviewed-by: Rob Herring --- .../bindings/reset/sunplus,reset.yaml | 40 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 99 +++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml create mode 100644 include/dt-bindings/reset/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/reset/sunplus,reset.yaml b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file mode 100644 index 000000000..bf55f4ee2 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian + +properties: + compatible: + enum: + - sunplus,sp7021-reset # Reset Controller on SP7021 and compatible SoCs + - sunplus,q645-reset # Reset Controller on Q645 and compatible SoCs + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#reset-cells" + - reg + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + #reset-cells = <1>; + reg = <0x9c000054 0x28>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 474544db2..123616bb9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2662,8 +2662,10 @@ S: Maintained F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/interrupt-controller/sp7021-intc.h +F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support M: Jisheng Zhang diff --git a/include/dt-bindings/reset/sp-sp7021.h b/include/dt-bindings/reset/sp-sp7021.h new file mode 100644 index 000000000..a08fd6231 --- /dev/null +++ b/include/dt-bindings/reset/sp-sp7021.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H +#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H + +/* mo_reset0 ~ mo_reset9 */ +#define RST_SYSTEM 0x00 +#define RST_RTC 0x02 +#define RST_IOCTL 0x03 +#define RST_IOP 0x04 +#define RST_OTPRX 0x05 +#define RST_NOC 0x06 +#define RST_BR 0x07 +#define RST_RBUS_L00 0x08 +#define RST_SPIFL 0x09 +#define RST_SDCTRL0 0x0a +#define RST_PERI0 0x0b +#define RST_A926 0x0d +#define RST_UMCTL2 0x0e +#define RST_PERI1 0x0f + +#define RST_DDR_PHY0 0x10 +#define RST_ACHIP 0x12 +#define RST_STC0 0x14 +#define RST_STC_AV0 0x15 +#define RST_STC_AV1 0x16 +#define RST_STC_AV2 0x17 +#define RST_UA0 0x18 +#define RST_UA1 0x19 +#define RST_UA2 0x1a +#define RST_UA3 0x1b +#define RST_UA4 0x1c +#define RST_HWUA 0x1d +#define RST_DDC0 0x1e +#define RST_UADMA 0x1f + +#define RST_CBDMA0 0x20 +#define RST_CBDMA1 0x21 +#define RST_SPI_COMBO_0 0x22 +#define RST_SPI_COMBO_1 0x23 +#define RST_SPI_COMBO_2 0x24 +#define RST_SPI_COMBO_3 0x25 +#define RST_AUD 0x26 +#define RST_USBC0 0x2a +#define RST_USBC1 0x2b +#define RST_UPHY0 0x2d +#define RST_UPHY1 0x2e + +#define RST_I2CM0 0x30 +#define RST_I2CM1 0x31 +#define RST_I2CM2 0x32 +#define RST_I2CM3 0x33 +#define RST_PMC 0x3d +#define RST_CARD_CTL0 0x3e +#define RST_CARD_CTL1 0x3f + +#define RST_CARD_CTL4 0x42 +#define RST_BCH 0x44 +#define RST_DDFCH 0x4b +#define RST_CSIIW0 0x4c +#define RST_CSIIW1 0x4d +#define RST_MIPICSI0 0x4e +#define RST_MIPICSI1 0x4f + +#define RST_HDMI_TX 0x50 +#define RST_VPOST 0x55 + +#define RST_TGEN 0x60 +#define RST_DMIX 0x61 +#define RST_TCON 0x6a +#define RST_INTERRUPT 0x6f + +#define RST_RGST 0x70 +#define RST_GPIO 0x73 +#define RST_RBUS_TOP 0x74 + +#define RST_MAILBOX 0x86 +#define RST_SPIND 0x8a +#define RST_I2C2CBUS 0x8b +#define RST_SEC 0x8d +#define RST_DVE 0x8e +#define RST_GPOST0 0x8f + +#define RST_OSD0 0x90 +#define RST_DISP_PWM 0x92 +#define RST_UADBG 0x93 +#define RST_DUMMY_MASTER 0x94 +#define RST_FIO_CTL 0x95 +#define RST_FPGA 0x96 +#define RST_L2SW 0x97 +#define RST_ICM 0x98 +#define RST_AXI_GLOBAL 0x99 + +#define RST_MAX 0xA0 + +#endif