From patchwork Wed Oct 13 10:19:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifeng Zhao X-Patchwork-Id: 1540357 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HTpSD1PPqz9t0T for ; Wed, 13 Oct 2021 21:19:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239316AbhJMKV5 (ORCPT ); Wed, 13 Oct 2021 06:21:57 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:48636 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239144AbhJMKV4 (ORCPT ); Wed, 13 Oct 2021 06:21:56 -0400 Received: from localhost (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id A0AA9D81F3; Wed, 13 Oct 2021 18:19:48 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P26701T140614792369920S1634120379732571_; Wed, 13 Oct 2021 18:19:48 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: zyf@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: zyf@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 12 X-LOCAL-RCPT-COUNT: 1 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: <8d4e248f2d49e39adc1c985533a7c26a> X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, Yifeng Zhao Subject: [PATCH v2 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings Date: Wed, 13 Oct 2021 18:19:36 +0800 Message-Id: <20211013101938.28061-2-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211013101938.28061-1-yifeng.zhao@rock-chips.com> References: <20211013101938.28061-1-yifeng.zhao@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Signed-off-by: Yifeng Zhao --- Changes in v2: - Fix dtschema/dtc warnings/errors .../phy/phy-rockchip-naneng-combphy.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..55ad33d902ec --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + minItems: 1 + items: + - const: ref + - const: apb + - const: pipe + + '#phy-cells': + const: 1 + + resets: + minItems: 1 + items: + - description: exclusive apb reset line + - description: exclusive PHY reset line + + reset-names: + minItems: 1 + items: + - const: combphy-apb + - const: combphy + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are access through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are access through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#phy-cells' + - resets + - reset-names + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + +additionalProperties: false + +examples: + - | + + #include + + pipegrf: syscon@fdc50000 { + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + reg = <0xfdc70000 0x1000>; + }; + + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + };