From patchwork Fri Oct 8 09:31:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 1538281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=kzwMFqvZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HQjd26JY9z9sR4 for ; Fri, 8 Oct 2021 20:31:49 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 333873857C62 for ; Fri, 8 Oct 2021 09:31:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 333873857C62 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1633685506; bh=BYInQJlMLyCRD7QX2zDubnJNbTK6m0T91EYQ9p8fHdQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=kzwMFqvZb9+XhYFKj872D2siKLppGDwtk4ihbMxdjE6cPX3O1D6wB2sri6IyjH2Ik uLrkblehnlJKGsaZCBQ7kvs3yPWZCO0zjp0donhgF2OjiOBKgbcbI4ht8uxjjYkhvD VwZt1CD3whRUP2b7Erw4QKj2l6t2El2BKailMMX8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 030B23858431 for ; Fri, 8 Oct 2021 09:31:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 030B23858431 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225248161" X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="225248161" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 02:31:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="561266680" Received: from scymds01.sc.intel.com ([10.148.94.138]) by FMSMGA003.fm.intel.com with ESMTP; 08 Oct 2021 02:31:23 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1989VLuD025887; Fri, 8 Oct 2021 02:31:22 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Refine movhfcc. Date: Fri, 8 Oct 2021 17:31:21 +0800 Message-Id: <20211008093121.88264-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" For AVX512-FP16, HFmode only supports vcmpsh whose dest is mask register, so for movhfcc, it's vcmpsh op2, op1, %k1 vmovsh op1, op2{%k1} mov op2, dest gcc/ChangeLog: PR target/102639 * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Handle HFmode. (ix86_use_mask_cmp_p): Ditto. (ix86_expand_sse_movcc): Ditto. * config/i386/i386.md (setcc_hf_mask): New define_insn. (movhf_mask): Ditto. (UNSPEC_MOVCC_MASK): New unspec. * config/i386/sse.md (UNSPEC_PCMP): Move to i386.md. gcc/testsuite/ChangeLog: * g++.target/i386/pr102639.C: New test. --- gcc/config/i386/i386-expand.c | 19 ++++++++++--- gcc/config/i386/i386.md | 34 +++++++++++++++++++++++- gcc/config/i386/sse.md | 1 - gcc/testsuite/g++.target/i386/pr102639.C | 19 +++++++++++++ 4 files changed, 67 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/g++.target/i386/pr102639.C diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 4780b993917..3c4a07d4d7d 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -3613,6 +3613,10 @@ ix86_valid_mask_cmp_mode (machine_mode mode) if (TARGET_XOP && !TARGET_AVX512F) return false; + /* HFmode only supports vcmpsh whose dest is mask register. */ + if (TARGET_AVX512FP16 && mode == HFmode) + return true; + /* AVX512F is needed for mask operation. */ if (!(TARGET_AVX512F && VECTOR_MODE_P (mode))) return false; @@ -3634,7 +3638,9 @@ ix86_use_mask_cmp_p (machine_mode mode, machine_mode cmp_mode, { int vector_size = GET_MODE_SIZE (mode); - if (vector_size < 16) + if (cmp_mode == HFmode) + return true; + else if (vector_size < 16) return false; else if (vector_size == 64) return true; @@ -3750,7 +3756,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) && GET_MODE_CLASS (cmpmode) == MODE_INT) { gcc_assert (ix86_valid_mask_cmp_mode (mode)); - /* Using vector move with mask register. */ + /* Using scalar/vector move with mask register. */ cmp = force_reg (cmpmode, cmp); /* Optimize for mask zero. */ op_true = (op_true != CONST0_RTX (mode) @@ -3769,8 +3775,13 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) std::swap (op_true, op_false); } - rtx vec_merge = gen_rtx_VEC_MERGE (mode, op_true, op_false, cmp); - emit_insn (gen_rtx_SET (dest, vec_merge)); + if (mode == HFmode) + emit_insn (gen_movhf_mask (dest, op_true, op_false, cmp)); + else + { + rtx vec_merge = gen_rtx_VEC_MERGE (mode, op_true, op_false, cmp); + emit_insn (gen_rtx_SET (dest, vec_merge)); + } return; } else if (vector_all_ones_operand (op_true, mode) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 04cb3bf6a33..c7ae4ac5fbc 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -117,6 +117,7 @@ (define_c_enum "unspec" [ ;; For SSE/MMX support: UNSPEC_FIX_NOTRUNC UNSPEC_MASKMOV + UNSPEC_MOVCC_MASK UNSPEC_MOVMSK UNSPEC_BLENDV UNSPEC_PSHUFB @@ -125,8 +126,9 @@ (define_c_enum "unspec" [ UNSPEC_RSQRT UNSPEC_PSADBW - ;; For AVX512F support + ;; For AVX/AVX512F support UNSPEC_SCALEF + UNSPEC_PCMP ;; Generic math support UNSPEC_IEEE_MIN ; not commutative @@ -13608,6 +13610,20 @@ (define_insn "setcc__sse" (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) + +(define_insn "setcc_hf_mask" + [(set (match_operand:QI 0 "register_operand" "=k") + (unspec:QI + [(match_operand:HF 1 "register_operand" "v") + (match_operand:HF 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_31_operand" "n")] + UNSPEC_PCMP))] + "TARGET_AVX512FP16" + "vcmpsh\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "prefix" "evex") + (set_attr "mode" "HF")]) + ;; Basic conditional jump instructions. @@ -19841,6 +19857,22 @@ (define_peephole2 operands[9] = replace_rtx (operands[6], operands[0], operands[1], true); }) +(define_insn "movhf_mask" + [(set (match_operand:HF 0 "nonimmediate_operand" "=v,m,v") + (unspec:HF + [(match_operand:HF 1 "nonimmediate_operand" "m,v,v") + (match_operand:HF 2 "nonimm_or_0_operand" "0C,0C,0C") + (match_operand:QI 3 "register_operand" "Yk,Yk,Yk")] + UNSPEC_MOVCC_MASK))] + "TARGET_AVX512FP16" + "@ + vmovsh\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1} + vmovsh\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1} + vmovsh\t{%d1, %0%{%3%}%N2|%0%{%3%}%N2, %d1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "HF")]) + (define_expand "movhfcc" [(set (match_operand:HF 0 "register_operand") (if_then_else:HF diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4559b0ce9c9..a3c4a3f1e62 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -67,7 +67,6 @@ (define_c_enum "unspec" [ UNSPEC_PCLMUL ;; For AVX support - UNSPEC_PCMP UNSPEC_VPERMIL UNSPEC_VPERMIL2 UNSPEC_VPERMIL2F128 diff --git a/gcc/testsuite/g++.target/i386/pr102639.C b/gcc/testsuite/g++.target/i386/pr102639.C new file mode 100644 index 00000000000..f094e4d1b43 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr102639.C @@ -0,0 +1,19 @@ +/* PR target/102639 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -std=c++14 -mavx512fp16" } */ +/* { dg-final { scan-assembler-times "vminsh" 1 } } */ + +typedef _Float16 v16hf __attribute__((vector_size(2))); +v16hf vcond_v16hfv16hfge_b, vcond_v16hfv16hfge_c, vcond_v16hfv16hfge_d, + __attribute__vcond_v16hfv16hfge_a; +v16hf __attribute__vcond_v16hfv16hfge() { + return __attribute__vcond_v16hfv16hfge_a >= vcond_v16hfv16hfge_b + ? vcond_v16hfv16hfge_c + : vcond_v16hfv16hfge_d; +} + +v16hf __attribute__vcond_v16hfv16hfmax() { + return __attribute__vcond_v16hfv16hfge_a < vcond_v16hfv16hfge_b + ? __attribute__vcond_v16hfv16hfge_a + : vcond_v16hfv16hfge_b; +}