From patchwork Thu Oct 7 12:48:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 1537681 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HQB3D3Wn9z9sPB for ; Thu, 7 Oct 2021 23:49:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241407AbhJGMvE (ORCPT ); Thu, 7 Oct 2021 08:51:04 -0400 Received: from muru.com ([72.249.23.125]:41860 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233158AbhJGMvE (ORCPT ); Thu, 7 Oct 2021 08:51:04 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 77FB58131; Thu, 7 Oct 2021 12:49:39 +0000 (UTC) From: Tony Lindgren To: linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Geert Uytterhoeven , Rob Herring , Simon Horman , Suman Anna Subject: [PATCH 1/3] dt-bindings: bus: simple-pm-bus: Make clocks and power-domains optional Date: Thu, 7 Oct 2021 15:48:56 +0300 Message-Id: <20211007124858.44011-2-tony@atomide.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211007124858.44011-1-tony@atomide.com> References: <20211007124858.44011-1-tony@atomide.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clocks and power domains are not required by the simple-pm-bus driver. There are buses with read-only registers for clocks and power domains that are always on. Even without clocks and power domains configured, simple-pm-bus is still different from simple-bus as simple-pm-bus enables runtime PM for the bus driver. Let's update the binding accordingly as this remove the related warnings for dt_binding_check for omaps. Cc: Geert Uytterhoeven Cc: Rob Herring Cc: Simon Horman Cc: Suman Anna Signed-off-by: Tony Lindgren --- .../devicetree/bindings/bus/simple-pm-bus.yaml | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml --- a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml @@ -13,10 +13,9 @@ description: | A Simple Power-Managed Bus is a transparent bus that doesn't need a real driver, as it's typically initialized by the boot loader. - However, its bus controller is part of a PM domain, or under the control - of a functional clock. Hence, the bus controller's PM domain and/or - clock must be enabled for child devices connected to the bus (either - on-SoC or externally) to function. + However, its bus controller is typically part of a PM domain, or under + the control of a functional clock. Without PM domain or functional clock, + it still enables runtime PM for the bus driver unlike "simple-bus". While "simple-pm-bus" follows the "simple-bus" set of properties, as specified in the Devicetree Specification, it is not an extension of @@ -43,10 +42,10 @@ properties: clocks: true # Functional clocks - # Required if power-domains is absent, optional otherwise + # Typically used if power-domains is absent power-domains: - # Required if clocks is absent, optional otherwise + # Typically used if clocks is absent minItems: 1 required: @@ -55,12 +54,6 @@ required: - '#size-cells' - ranges -anyOf: - - required: - - clocks - - required: - - power-domains - additionalProperties: true examples: From patchwork Thu Oct 7 12:48:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 1537682 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HQB3K4pQrz9sPB for ; Thu, 7 Oct 2021 23:49:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241502AbhJGMvJ (ORCPT ); Thu, 7 Oct 2021 08:51:09 -0400 Received: from muru.com ([72.249.23.125]:41866 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241492AbhJGMvJ (ORCPT ); Thu, 7 Oct 2021 08:51:09 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id D8C188206; Thu, 7 Oct 2021 12:49:44 +0000 (UTC) From: Tony Lindgren To: linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Geert Uytterhoeven , Rob Herring , Simon Horman , Suman Anna Subject: [PATCH 2/3] dt-bindings: bus: simple-pm-bus: Add more matches for node name Date: Thu, 7 Oct 2021 15:48:57 +0300 Message-Id: <20211007124858.44011-3-tony@atomide.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211007124858.44011-1-tony@atomide.com> References: <20211007124858.44011-1-tony@atomide.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At least omaps use simple-pm-bus for interconnects and interconnect segments. While the interconnects do have configurable registers, there is currently no need for a dedicated interconnect driver. Let's update the list of allowed node names to remove the related dt_binding_check warnings for omaps. Cc: Geert Uytterhoeven Cc: Rob Herring Cc: Simon Horman Cc: Suman Anna Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/bus/simple-pm-bus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml --- a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml @@ -23,7 +23,7 @@ description: | properties: $nodename: - pattern: "^bus(@[0-9a-f]+)?$" + pattern: "^(bus|interconnect|segment)(@[0-9a-f]+)?$" compatible: contains: From patchwork Thu Oct 7 12:48:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 1537683 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HQB3b3NMKz9sPB for ; Thu, 7 Oct 2021 23:49:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241501AbhJGMvV (ORCPT ); Thu, 7 Oct 2021 08:51:21 -0400 Received: from muru.com ([72.249.23.125]:41878 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241505AbhJGMvN (ORCPT ); Thu, 7 Oct 2021 08:51:13 -0400 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id A819182CA; Thu, 7 Oct 2021 12:49:48 +0000 (UTC) From: Tony Lindgren To: linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Rob Herring , Suman Anna , Geert Uytterhoeven , Simon Horman Subject: [PATCH 3/3] dt-bindings: bus: ti-sysc: Update to use yaml binding Date: Thu, 7 Oct 2021 15:48:58 +0300 Message-Id: <20211007124858.44011-4-tony@atomide.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211007124858.44011-1-tony@atomide.com> References: <20211007124858.44011-1-tony@atomide.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the binding for ti-sysc interconnect target module driver to yaml format. Cc: Rob Herring Cc: Suman Anna Signed-off-by: Tony Lindgren --- .../devicetree/bindings/bus/ti-sysc.txt | 139 ---------------- .../devicetree/bindings/bus/ti-sysc.yaml | 150 ++++++++++++++++++ 2 files changed, 150 insertions(+), 139 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.yaml diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt deleted file mode 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,139 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-dra7-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - "ti,sysc-pruss" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -- ti,no-idle interconnect target module should not be idled - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = , - ; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multiple child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnect target module. diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml new file mode 100644 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interconnect target module binding + +maintainers: + - Tony Lindgren + +description: | + Texas Instruments SoCs can have a generic interconnect target module + for devices connected to various interconnects such as L3 interconnect + using Arteris NoC, and L4 interconnect using Sonics s3220. This module + is mostly used for interaction between module and Power, Reset and Clock + Manager PRCM. It participates in the OCP Disconnect Protocol, but other + than that it is mostly independent of the interconnect. + + Each interconnect target module can have one or more devices connected to + it. There is a set of control registers for managing the interconnect target + module clocks, idle modes and interconnect level resets. + + The interconnect target module control registers are sprinkled into the + unused register address space of the first child device IP block managed by + the interconnect target module. Typically the register names are REVISION, + SYSCONFIG and SYSSTATUS. + +properties: + $nodename: + pattern: "^target-module(@[0-9a-f]+)?$" + + compatible: + oneOf: + - items: + - enum: + - ti,sysc-omap2 + - ti,sysc-omap2 + - ti,sysc-omap4 + - ti,sysc-omap4-simple + - ti,sysc-omap2-timer + - ti,sysc-omap4-timer + - ti,sysc-omap3430-sr + - ti,sysc-omap3630-sr + - ti,sysc-omap4-sr + - ti,sysc-omap3-sham + - ti,sysc-omap-aes + - ti,sysc-mcasp + - ti,sysc-dra7-mcasp + - ti,sysc-usb-host-fs + - ti,sysc-dra7-mcan + - ti,sysc-pruss + - const: ti,sysc + - items: + - const: ti,sysc + + reg: true + + reg-names: true + + clocks: true + + clock-names: true + + power-domains: true + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + ti,sysc-mask: + description: Mask of supported register bits for the SYSCONFIG register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-midle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,sysc-sidle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,syss-mask: + description: Mask of supported register bits for the SYSSTATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-delay-us: + description: Delay needed after OCP softreset before accessing SYCONFIG + default: 0 + minimum: 0 + maximum: 2 + + ti,no-reset-on-init: + description: Interconnect target module shall not be reset at init + type: boolean + + ti,no-idle-on-init: + description: Interconnect target module shall not be idled at init + type: boolean + + ti,no-idle: + description: Interconnect target module shall not be idled + type: boolean + + ti,hwmods: + description: Interconnect module name to use with legacy hwmod data + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: true + +examples: + - | + #include + #include + + target-module@2b000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + };