From patchwork Wed Sep 29 00:41:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1534163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FrP+ioCc; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HJyHC22J5z9tk8 for ; Wed, 29 Sep 2021 10:41:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242626AbhI2AnF (ORCPT ); Tue, 28 Sep 2021 20:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243446AbhI2AnE (ORCPT ); Tue, 28 Sep 2021 20:43:04 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37682C06161C; Tue, 28 Sep 2021 17:41:24 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id v10so1857874edj.10; Tue, 28 Sep 2021 17:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u8/OQHyTfBKc9k6MqctWLYPYytJ0Iv55vUhhrisQJfM=; b=FrP+ioCcZEEzsbMeYmqzBcjfJME8t6Sy58v9aLRWQ8XOhHcKVxVqaIl7CiSStFGfPy hK7reVMDpkRbBFAXIDxOuN7qaVg0AzuY7rZn+sugw2la/WXkrUsxf1y/AsZtB69bkAf1 4eYJs5yffe70MC0TWj6t1cGeHz1SDteIUu1j/aLIkuW9Y4CYyAGHGNYGBY2sB5VI2HHN c1ofSdWtkFtnn+7ZSxk8DdF1TA0BFRYCE+FGwkUFgX9waIXT6wnP8GkiFZFq81CQ7bFY DK2Qqo3k3il5jC8KnOa684Gub6eWwFee1IFVKoLs+tTAagv98W1V6K8W3ICSEsBWBWiR HAGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u8/OQHyTfBKc9k6MqctWLYPYytJ0Iv55vUhhrisQJfM=; b=WrS7JwcqIHfCrd4yIL/bsNzBxProcD1oWIux11nkp+UIuEzony+goGgubxV9qVXpcc yf50B32f3ZsLXEg4O1Sbl8WzuzgGWpD+Q+zF5gLdh5+Ol72tiQpbdN8q0YzOIUjkpRC9 YlN7l7KLXdTePb54soNce80mR61+buMFx3TtqXaGFLCWjrZAHbs6uM4yQx0rNcGviReu 6rI0dZrEsGzVjaG08s0YFXmz0L03YHuzISCDY1gVF2OVTMnzamwNFvAgHpdDYsW74mrW 37yZPaRKbNs+tOV19BOdjfKOITvVlvlzw6YRS94znkl2pgGut+aecA8ue8RInAuRfj/p +djg== X-Gm-Message-State: AOAM5319KMW8p2+WKELf/i/VMXIzg6On4gJWJMJayOZ0AS31mKaDVMWT V7/+cvVR6lxuzIn3Xh2IRGo= X-Google-Smtp-Source: ABdhPJySrbPE7KqvfC1MwWLuySFf5L4BICAdL37D4dMjCDIEfEmBT7CNHdWzkIggDbitm01HuUBAUA== X-Received: by 2002:a17:907:7675:: with SMTP id kk21mr8844245ejc.114.1632876082829; Tue, 28 Sep 2021 17:41:22 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:10f:c9f0:35c7:3af0:a197:61d0]) by smtp.googlemail.com with ESMTPSA id y1sm372727edv.79.2021.09.28.17.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Sep 2021 17:41:22 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 1/3] PCI/ASPM: Do not cache link latencies Date: Wed, 29 Sep 2021 02:41:14 +0200 Message-Id: <20210929004116.20650-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210929004116.20650-1-refactormyself@gmail.com> References: <20210929004116.20650-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The latencies of the upstream and downstream are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.latency_* These values are only used in pcie_aspm_check_latency() where they are compared with the acceptable latencies on the link. This patch: - removes `latency_*` entries from struct pcie_link_state. - calculates the latencies directly where they are needed. - moves pci_function_0() upward, so that the downstream device can be obtained by calling it directly. - further removes dependencies on struct pcie_link_state. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 013a47f587ce..9e85dfc56657 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -66,9 +66,6 @@ struct pcie_link_state { u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - /* Exit latencies */ - struct aspm_latency latency_up; /* Upstream direction exit latency */ - struct aspm_latency latency_dw; /* Downstream direction exit latency */ /* * Endpoint acceptable latencies. A pcie downstream port only * has one slot under it, so at most there are 8 functions. @@ -376,9 +373,25 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } } +/* + * The L1 PM substate capability is only implemented in function 0 in a + * multi function device. + */ +static struct pci_dev *pci_function_0(struct pci_bus *linkbus) +{ + struct pci_dev *child; + + list_for_each_entry(child, &linkbus->devices, bus_list) + if (PCI_FUNC(child->devfn) == 0) + return child; + return NULL; +} + static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, l1_switch_latency = 0; + u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + struct pci_dev *downstream; + struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; struct pcie_link_state *link; @@ -388,17 +401,26 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) return; link = endpoint->bus->self->link_state; + downstream = pci_function_0(link->pdev->subordinate); acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; while (link) { + /* Read direction exit latencies */ + pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, &lnkcap_up); + pcie_capability_read_dword(downstream, PCI_EXP_LNKCAP, &lnkcap_dw); + latency_up.l0s = calc_l0s_latency(lnkcap_up); + latency_up.l1 = calc_l1_latency(lnkcap_up); + latency_dw.l0s = calc_l0s_latency(lnkcap_dw); + latency_dw.l1 = calc_l1_latency(lnkcap_dw); + /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (link->latency_up.l0s > acceptable->l0s)) + (latency_up.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (link->latency_dw.l0s > acceptable->l0s)) + (latency_dw.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -413,7 +435,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); + latency = max_t(u32, latency_up.l1, latency_dw.l1); if ((link->aspm_capable & ASPM_STATE_L1) && (latency + l1_switch_latency > acceptable->l1)) link->aspm_capable &= ~ASPM_STATE_L1; @@ -423,20 +445,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) } } -/* - * The L1 PM substate capability is only implemented in function 0 in a - * multi function device. - */ -static struct pci_dev *pci_function_0(struct pci_bus *linkbus) -{ - struct pci_dev *child; - - list_for_each_entry(child, &linkbus->devices, bus_list) - if (PCI_FUNC(child->devfn) == 0) - return child; - return NULL; -} - static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, u32 clear, u32 set) { @@ -593,8 +601,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(parent_lnkcap); - link->latency_dw.l0s = calc_l0s_latency(child_lnkcap); /* Setup L1 state */ if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) @@ -602,8 +608,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(parent_lnkcap); - link->latency_dw.l1 = calc_l1_latency(child_lnkcap); /* Setup L1 substate */ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, From patchwork Wed Sep 29 00:41:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1534164 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=kAi7RnTY; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HJyHC4tGPz9svs for ; Wed, 29 Sep 2021 10:41:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243475AbhI2AnG (ORCPT ); Tue, 28 Sep 2021 20:43:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243471AbhI2AnF (ORCPT ); Tue, 28 Sep 2021 20:43:05 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A1D6C06161C; Tue, 28 Sep 2021 17:41:25 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id g8so1901503edt.7; Tue, 28 Sep 2021 17:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zBaxdjR458Cms2rk+PE1YK0Xhx5uxYTQbasRo/1RH8s=; b=kAi7RnTYzsJw+xBNyo7tVSdA1R74ghjgx9CsY1SC3iVw5HcqooLIxFafkG4rW688zc DRme2z4pLza4ozX1s9g459KNL3eXe+HgxQiQf2i3wkR1JQH2x5MynMc+VVT7n24rom+I +p8KaGNR0PTjGGJKU7bCOEaYzGWbInIzoX9ERqDpTWwmXf6Jq2UCMCz/zF0KRB4iqPz/ NcP/n6FK9Yxh9KSVGJbQQCNsMFqGBiCTvD5I4Axo2znnB/plzsGCHTThUOp58sIB/30s q2eJZAiNV1PgqVmDbzu6ywDjb8ukvQf/PUKt2gXaHSKTlcsMZjXHf5BHdWzknpGYWlwW a97A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zBaxdjR458Cms2rk+PE1YK0Xhx5uxYTQbasRo/1RH8s=; b=ym/Au0uZ8Pqa1mDOKASHf26KplAIB/3lD04uaAkZBscfJRm61PAzbqYrUXsGkhI7Mv +w6l9K5ur55jGeFWyN2HHsOZmy7PsKOT3DZasJpJ4TW499NFwQmqvo3Cgye7QOp+pYxj m/Bb4SkVC0gU2Spyy3XTp+Qxx+8V7Gq6MdeEX5GAnZ9ek5in1YnF1BLtHWvcuNuTc16t qYdMMuIIM3ayrmX13SPYqLlfm6slKGVQoGtXtyq42DuvESUZqOrLb8MdvZ2WI01q/g1U eOA9AlX7MqBGvF9zECUo2iuCP3tTxmGrGvzptRjF+IiZlEXx0tK9fIb+qFqFDOkixCze /9mA== X-Gm-Message-State: AOAM532NCzdKliCORNIB8pwO9jxxLNtNBkufsMmTUXea7HYIcOb7j0TV aWjcj+m28IkC+lGMh905Ysc= X-Google-Smtp-Source: ABdhPJz72n7t7ggRbMU/mxGc0sdAdt5XmtpU/sLNfJp3ce8zz9o9+fn37H3qdiJfweDcRM29/74gOw== X-Received: by 2002:a50:d8c5:: with SMTP id y5mr11265142edj.370.1632876083805; Tue, 28 Sep 2021 17:41:23 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:10f:c9f0:35c7:3af0:a197:61d0]) by smtp.googlemail.com with ESMTPSA id y1sm372727edv.79.2021.09.28.17.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Sep 2021 17:41:23 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 2/3] PCI/ASPM: Remove struct pcie_link_state.acceptable Date: Wed, 29 Sep 2021 02:41:15 +0200 Message-Id: <20210929004116.20650-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210929004116.20650-1-refactormyself@gmail.com> References: <20210929004116.20650-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The acceptable latencies for each device on the bus are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.acceptable. They are only used within pcie_aspm_check_latency() to validate actual latencies. Thus, it is possible to avoid caching these values. This patch: - removes `acceptable` from struct pcie_link_state - calculates the acceptable latency for each device directly - removes the calculations done within pcie_aspm_cap_init() Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 9e85dfc56657..0c0c055823f1 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -65,12 +65,6 @@ struct pcie_link_state { u32 clkpm_enabled:1; /* Current Clock PM state */ u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - - /* - * Endpoint acceptable latencies. A pcie downstream port only - * has one slot under it, so at most there are 8 functions. - */ - struct aspm_latency acceptable[8]; }; static int aspm_disabled, aspm_force; @@ -389,7 +383,7 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; struct pci_dev *downstream; struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; @@ -402,7 +396,13 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) link = endpoint->bus->self->link_state; downstream = pci_function_0(link->pdev->subordinate); - acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; + pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); + /* Calculate endpoint L0s acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; + acceptable->l0s = calc_l0s_acceptable(encoding); + /* Calculate endpoint L1 acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; + acceptable->l1 = calc_l1_acceptable(encoding); while (link) { /* Read direction exit latencies */ @@ -664,22 +664,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - u32 reg32, encoding; - struct aspm_latency *acceptable = - &link->acceptable[PCI_FUNC(child->devfn)]; if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue; - pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); - /* Calculate endpoint L0s acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); - /* Calculate endpoint L1 acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); - pcie_aspm_check_latency(child); } } From patchwork Wed Sep 29 00:41:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v3 PATCH 3/3] PCI/ASPM: Remove struct aspm_latency Date: Wed, 29 Sep 2021 02:41:16 +0200 Message-Id: <20210929004116.20650-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210929004116.20650-1-refactormyself@gmail.com> References: <20210929004116.20650-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The struct aspm_latency is now used only inside pcie_aspm_check_latency(). Since this struct is trivial, this patch: - replaces struct aspm_latency variables with u32 variables - removes struct aspm_latency Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 0c0c055823f1..8093c9335e1f 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -41,11 +41,6 @@ #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ ASPM_STATE_L1SS) -struct aspm_latency { - u32 l0s; /* L0s latency (nsec) */ - u32 l1; /* L1 latency (nsec) */ -}; - struct pcie_link_state { struct pci_dev *pdev; /* Upstream component of the Link */ struct pci_dev *downstream; /* Downstream component, function 0 */ @@ -384,9 +379,9 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + u32 latency_up_l0s, latency_up_l1, latency_dw_l0s, latency_dw_l1; + u32 acceptable_l0s, acceptable_l1; struct pci_dev *downstream; - struct aspm_latency latency_up, latency_dw; - struct aspm_latency *acceptable; struct pcie_link_state *link; /* Device not in D0 doesn't need latency check */ @@ -399,28 +394,28 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); /* Calculate endpoint L0s acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); + acceptable_l0s = calc_l0s_acceptable(encoding); /* Calculate endpoint L1 acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); + acceptable_l1 = calc_l1_acceptable(encoding); while (link) { /* Read direction exit latencies */ pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, &lnkcap_up); pcie_capability_read_dword(downstream, PCI_EXP_LNKCAP, &lnkcap_dw); - latency_up.l0s = calc_l0s_latency(lnkcap_up); - latency_up.l1 = calc_l1_latency(lnkcap_up); - latency_dw.l0s = calc_l0s_latency(lnkcap_dw); - latency_dw.l1 = calc_l1_latency(lnkcap_dw); + latency_up_l0s = calc_l0s_latency(lnkcap_up); + latency_up_l1 = calc_l1_latency(lnkcap_up); + latency_dw_l0s = calc_l0s_latency(lnkcap_dw); + latency_dw_l1 = calc_l1_latency(lnkcap_dw); /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (latency_up.l0s > acceptable->l0s)) + (latency_up_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (latency_dw.l0s > acceptable->l0s)) + (latency_dw_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -435,9 +430,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, latency_up.l1, latency_dw.l1); + latency = max_t(u32, latency_up_l1, latency_dw_l1); if ((link->aspm_capable & ASPM_STATE_L1) && - (latency + l1_switch_latency > acceptable->l1)) + (latency + l1_switch_latency > acceptable_l1)) link->aspm_capable &= ~ASPM_STATE_L1; l1_switch_latency += 1000; @@ -664,7 +659,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue;