From patchwork Mon Sep 20 23:28:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Sneddon X-Patchwork-Id: 1530466 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=oZGxK+ey; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HD15G69Ksz9sR4 for ; Tue, 21 Sep 2021 09:30:42 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EF83983257; Tue, 21 Sep 2021 01:30:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="oZGxK+ey"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 83C0480224; Tue, 21 Sep 2021 01:29:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A595182E67 for ; Tue, 21 Sep 2021 01:28:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Dan.Sneddon@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632180536; x=1663716536; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+wyg7R+YHFFmduRFIuU32047/Cu0d41JdgqQPvXBM98=; b=oZGxK+eyjgEhkFP3A4axzM1SUdZuvmlJvmwz5he7Gopn/zCyM9bzFDrk 5hhCNX8AOlasv6nJtKi9IyiKav0O4C/VU7cH3vZC265kOw3j6G/v8J9GG h4OqgcIBXWwDXItCmqYOUK0KKSrxpvUX7sdyMlwNpnp87wAe2fDw9+Bs/ +ByDLdNV6fni3sJp/iAqES89c1PxGTfIZP35fSjBwYHp9MHvb/7bPdlft wq0w0gbYJnSra8567de68O+fpsYGz7Lqnjpx/QgzRQs1G4jyDlkM8uMhp xOGfjtH6/f1CpYIl4WWf9usaGYG0wF2n8Sf4CJTRRUlnnrZ/NiBanJKkl g==; IronPort-SDR: qlbPsI3xtKOY2ncPHrwRihT4Dhb1e3+JVBrY60reZqpPCyjfbZL2qT4LtnYuULto4LDI9dA9Ml LBk0q/o3+HNF7ZdmdRDFS7XPsgZBbVnIynzY9PLVHrjARp4tom4FOQl4tURXv17+02WUKjSC3A vG5keAqJsUFg1A+OmhUr80lxJVjOQt9giq73UUUCfu2Fcm+RKimQODcVzd95yK4dNBHNkm62fs I0IOnmv0cvxxdi6vcsR2g26fxnR7ZVSjTT+s6nYn3aT1fCu6ZzwNYxD7L7q9bRbkKGLxDnbp5Q w6JSyWqzEnhEC+P3bQaCruW3 X-IronPort-AV: E=Sophos;i="5.85,309,1624345200"; d="scan'208";a="137283211" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Sep 2021 16:28:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 20 Sep 2021 16:28:51 -0700 Received: from dan-linux.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 20 Sep 2021 16:28:51 -0700 From: Dan Sneddon To: CC: Dan Sneddon Subject: [PATCH 1/3] pwm: Add PWM driver for SAMA5D2 Date: Mon, 20 Sep 2021 16:28:44 -0700 Message-ID: <20210920232846.25954-2-dan.sneddon@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920232846.25954-1-dan.sneddon@microchip.com> References: <20210920232846.25954-1-dan.sneddon@microchip.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 21 Sep 2021 01:30:14 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add support for the PWM found on the SAMA5D2 family of devices. Signed-off-by: Dan Sneddon --- drivers/pwm/Kconfig | 6 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-at91.c | 207 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 drivers/pwm/pwm-at91.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840..691bbcd469 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -91,3 +91,9 @@ config PWM_TI_EHRPWM default y help PWM driver support for the EHRPWM controller found on TI SOCs. + +config PWM_AT91 + bool "Enable support for PWM found on AT91 SoC's" + depends on DM_PWM && ARCH_AT91 + help + Support for PWM hardware on AT91 based SoC. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb7..6cdcbdb996 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o obj-$(CONFIG_PWM_TI_EHRPWM) += pwm-ti-ehrpwm.o +obj-$(CONFIG_PWM_AT91) += pwm-at91.o diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c new file mode 100644 index 0000000000..95597aee55 --- /dev/null +++ b/drivers/pwm/pwm-at91.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PWM support for Microchip AT91 architectures. + * + * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries + * + * Author: Dan Sneddon + * + * Based on drivers/pwm/pwm-atmel.c from Linux. + */ +#include +#include +#include +#include +#include +#include +#include + +#define PERIOD_BITS 16 +#define PWM_MAX_PRES 10 +#define NSEC_PER_SEC 1000000000L + +#define PWM_ENA 0x04 +#define PWM_CHANNEL_OFFSET 0x20 +#define PWM_CMR 0x200 +#define PWM_CMR_CPRE_MSK GENMASK(3, 0) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CDTY 0x204 +#define PWM_CPRD 0x20C + +struct at91_pwm_priv { + void __iomem *base; + struct clk pclk; + u32 clkrate; +}; + +static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev, + unsigned long clkrate, + uint period_ns, uint duty_ns, + unsigned long *cprd, u32 *pres) +{ + u64 cycles = period_ns; + int shift; + + /* Calculate the period cycles and prescale value */ + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + + /* + * The register for the period length is period_bits bits wide. + * So for each bit the number of clock cycles is wider divide the input + * clock frequency by two using pres and shift cprd accordingly. + */ + shift = fls(cycles) - PERIOD_BITS; + + if (shift > PWM_MAX_PRES) { + return -EINVAL; + } else if (shift > 0) { + *pres = shift; + cycles >>= *pres; + } else { + *pres = 0; + } + + *cprd = cycles; + + return 0; +} + +static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns, + unsigned long clkrate, unsigned long cprd, + u32 pres, unsigned long *cdty) +{ + u64 cycles = duty_ns; + + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + cycles >>= pres; + *cdty = cprd - cycles; +} + +/** + * Returns: channel status after set operation + */ +static bool at91_pwm_set(void __iomem *base, uint channel, bool enable) +{ + u32 val, cur_status; + + val = ioread32(base + PWM_ENA); + cur_status = !!(val & BIT(channel)); + + /* if channel is already in that state, do nothing */ + if (!(enable ^ cur_status)) + return cur_status; + + if (enable) + val |= BIT(channel); + else + val &= ~(BIT(channel)); + + iowrite32(val, base + PWM_ENA); + + return cur_status; +} + +static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + + at91_pwm_set(priv->base, channel, enable); + + return 0; +} + +static int at91_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + unsigned long cprd, cdty; + u32 pres, val; + int channel_enabled; + int ret; + + ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns, + duty_ns, &cprd, &pres); + if (ret) + return ret; + + at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty); + + /* disable the channel */ + channel_enabled = at91_pwm_set(priv->base, channel, false); + + /* It is necessary to preserve CPOL, inside CMR */ + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD); + + iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY); + + /* renable the channel if needed */ + if (channel_enabled) + at91_pwm_set(priv->base, channel, true); + + return 0; +} + +static int at91_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + u32 val; + + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + if (polarity) + val |= PWM_CMR_CPOL; + else + val &= ~PWM_CMR_CPOL; + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + return 0; +} + +static int at91_pwm_probe(struct udevice *dev) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret) + return ret; + + /* clocks aren't ref-counted so just enabled them once here */ + ret = clk_enable(&priv->pclk); + if (ret) + return ret; + + priv->clkrate = clk_get_rate(&priv->pclk); + + return ret; +} + +static const struct pwm_ops at91_pwm_ops = { + .set_config = at91_pwm_set_config, + .set_enable = at91_pwm_set_enable, + .set_invert = at91_pwm_set_invert, +}; + +static const struct udevice_id at91_pwm_of_match[] = { + { .compatible = "atmel,sama5d2-pwm" }, + { } +}; + +U_BOOT_DRIVER(at91_pwm) = { + .name = "at91_pwm", + .id = UCLASS_PWM, + .of_match = at91_pwm_of_match, + .probe = at91_pwm_probe, + .priv_auto = sizeof(struct at91_pwm_priv), + .ops = &at91_pwm_ops, +}; From patchwork Mon Sep 20 23:28:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Sneddon X-Patchwork-Id: 1530467 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=hytXWAx+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HD15T5XDcz9sR4 for ; Tue, 21 Sep 2021 09:30:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EB23883259; Tue, 21 Sep 2021 01:30:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="hytXWAx+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B7BC382D74; Tue, 21 Sep 2021 01:29:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9A1BF831CA for ; Tue, 21 Sep 2021 01:28:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Dan.Sneddon@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632180537; x=1663716537; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Ls0PFgQTJEjnYCIkiJwlNHrW5qo8XJzXhM0WhDKAMN8=; b=hytXWAx+mETIBL/IRMiqzWqSk+Sblb2FgkUZPEv7RLYQotDPeMWyr0C6 ebdukR93hV9aCS9K+5UAVvTHYL27LjIzmJzfrSgxu9hg8ZsmOaWUkZTWl Vwkt0NNoS3Lo9HM+t40s9LAahx7RctqEPagSrzqp4n8D6YP9oUtdf4lxP imDE2qZr9ot3wRPA3xzKxD4NQkh0ct5lMAeupgo0L8b+hhJrNRQQ6uSaC +rboS5qP/MInC52cqoOBcCMlRWbhAmWQPoQdVz3YzyWrfh2rJ6epqpkCI iUUBfqBvo8tlLJZ118gdUuRSXYpf7JqEyjHhy66qXHdtJoKGRG/qAHp+H g==; IronPort-SDR: Hy597CXeAgHYYiNvcLkSkNPU27ovuj5SWrYD8DPfysz4vDzCG+3GeWucNRAlp3eUBV2PMt9nJK 4EzyQn0Oz+NdTp0oLlcxVmNCq1ygGOeCcm18oZKY67riGQpUh83gvo4PHv8Ynbd8OksyMCiahd WIaEndJCxLlT6q/RNJF0pVsaPAzfiInArSd0Cx3psYLn43t51gPg9zVjrLuHa5bLuJku9RxFXy UE7t5DjsvudmfQfoI2EfopTrIH8md1w/x9M2fLJIdvoHEJrnj8PS6TngSrgmwGLVR5cRhuPipz gh3PjzQyeNDtx8s5Hk9gk5U9 X-IronPort-AV: E=Sophos;i="5.85,309,1624345200"; d="scan'208";a="137283212" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Sep 2021 16:28:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 20 Sep 2021 16:28:52 -0700 Received: from dan-linux.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 20 Sep 2021 16:28:52 -0700 From: Dan Sneddon To: CC: Dan Sneddon Subject: [PATCH 2/3] dt-bindings: pwm: pwm-at91: Add PWM bindings for A5D2 Date: Mon, 20 Sep 2021 16:28:45 -0700 Message-ID: <20210920232846.25954-3-dan.sneddon@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920232846.25954-1-dan.sneddon@microchip.com> References: <20210920232846.25954-1-dan.sneddon@microchip.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 21 Sep 2021 01:30:14 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Document the bindings needed for the PWM device on the SAMA5D2. Signed-off-by: Dan Sneddon --- doc/device-tree-bindings/pwm/pwm-at91.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 doc/device-tree-bindings/pwm/pwm-at91.txt diff --git a/doc/device-tree-bindings/pwm/pwm-at91.txt b/doc/device-tree-bindings/pwm/pwm-at91.txt new file mode 100644 index 0000000000..a03da404f5 --- /dev/null +++ b/doc/device-tree-bindings/pwm/pwm-at91.txt @@ -0,0 +1,16 @@ +Microchip AT91 PWM controller for SAMA5D2 + +Required properties: + - compatible: Should be "atmel,sama5d2-pwm" + - reg: Physical base address and length of the controller's registers. + - clocks: Should contain a clock identifier for the PWM's parent clock. + - #pwm-cells: Should be 3. + +Example: + +pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; +}; From patchwork Mon Sep 20 23:28:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Sneddon X-Patchwork-Id: 1530468 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=QQvCZoXR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HD15k0ZH1z9sR4 for ; Tue, 21 Sep 2021 09:31:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 59CFF8326B; Tue, 21 Sep 2021 01:30:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="QQvCZoXR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E114982E67; Tue, 21 Sep 2021 01:29:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0046583230 for ; Tue, 21 Sep 2021 01:28:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Dan.Sneddon@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632180538; x=1663716538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=HI6wSxKXcB4Kmsw8W1i6sf3yCP5Kl1AUV8BH/OWjj+M=; b=QQvCZoXRG7pnksYArT8deVKggqRpAxbObNu76ge86l44ImRmLCRLhvRo 7+H2OQM9qMScVCZjuR//NzlF6xucDfNUw51CpKiNTgMl0YA1U0JeiEU3z wAu/gv+ky37ClZQvToCXFp5QQ2i26QrVw5sTFMFzgoYJw3ZLqohM6qwE3 UVYrNuMtxRC4JsKbJBpU7xDx3Ko0+OUm3+XKzJccJ5uBhh0NaeIPGcaTL N6pm4iFZxVs+ZSVNsZc49eze7n+JzdZ96qoMfK7KP2Ph2xxBTi/gHzqKB EjDvn9FdTrzDxRdJJbhR8A67w1JIimcTCJdTFsN4gQTaDh14fSKcx0R3P w==; IronPort-SDR: 4YqDSsaw1+tp8lLdwr1iMTe5fBLG0bbvxPxW4y6Fy06O3uYNFw5sth+qGBibwmQgZZo1SvN6ib ANqyzBcVaxaRlTp10YQXM0BlDjA4Qb7AeWQ3f2pKloz6UDWkIsvk2HTuSBtQD5jMP4B1jyEBvf BiCcDY0ttRQIOUtr3gmrAhvIxppHB579VRMxJ43xzY40owGVU6RW726ZjCOeacQpHD7oFkqa1W Eca66LBkQpfKqEefMgG1CStDkKTFMjSLdlyH6l4nbJp/LJ+iNpFitPEaHoEowHbtpx8gdmtKV/ f4BW8zYDA2iuHFQPFrcP7QzA X-IronPort-AV: E=Sophos;i="5.85,309,1624345200"; d="scan'208";a="137283213" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Sep 2021 16:28:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 20 Sep 2021 16:28:52 -0700 Received: from dan-linux.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 20 Sep 2021 16:28:52 -0700 From: Dan Sneddon To: CC: Dan Sneddon Subject: [PATCH 3/3] ARM:dts: sama5d2: Add pwm definition Date: Mon, 20 Sep 2021 16:28:46 -0700 Message-ID: <20210920232846.25954-4-dan.sneddon@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920232846.25954-1-dan.sneddon@microchip.com> References: <20210920232846.25954-1-dan.sneddon@microchip.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 21 Sep 2021 01:30:14 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add the PWM on the SAMA5D2. Signed-off-by: Dan Sneddon --- arch/arm/dts/sama5d2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 6fb2cb25f9..ba1b69e629 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -671,6 +671,14 @@ status = "disabled"; }; + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>;