From patchwork Fri Sep 17 10:54:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1529339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=LHc5TX4g; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H9rRv1Cnyz9svs for ; Fri, 17 Sep 2021 20:54:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343900AbhIQKzj (ORCPT ); Fri, 17 Sep 2021 06:55:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242359AbhIQKzh (ORCPT ); Fri, 17 Sep 2021 06:55:37 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8306C061767; Fri, 17 Sep 2021 03:54:15 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id c190-20020a1c9ac7000000b0030b459ea869so1092791wme.4; Fri, 17 Sep 2021 03:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Xbi2CxEi+IpEXJ5ypGdOvWg9Sd7CJbQdgWYZaFnG9uA=; b=LHc5TX4gPkLeB72kkkX1qmJ+n0DFlYYFGnfwrXePNYlxXegcanaBjNOPX6EM7iZb11 SK6Fzp4OLuYIQ/oi/TscLON8XXA4bBeZMBm/Dp3g4LQfnpVCvtcA0wxYlAM6DVDTrx4r fX7Y/rgfu+NhkbppjuBBzDCK0BgUEaGnun0NnlD+ZZyiTH9w1nGwFEZcnLdSuV2gZxCa aBlUEUzO+aocFpi2Wtlvoo4Chl5rTH3dDPivQlk7PLCi9t+sbeH5Evi+9infST5XjXxt gN2LX4AfWAGyCt4+OMMHR2nSH4N9m4DPX77fBhDTtCDTmAWYHriHIu2AlPq6Q7LGdvHM X0ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Xbi2CxEi+IpEXJ5ypGdOvWg9Sd7CJbQdgWYZaFnG9uA=; b=FgZIRWQUzG/00lh1PCRxJgWng7zLXxxKkAEuNNCGNAQ6IUrvw01aRAqdSiz76Mzm1H uWp9y0U5hdtifnr5havIYe+bo+lZ0gXpcb2D8XMl1Bc58oLkWUanGNMMiwlzqjRQEiTQ zPAGj16dXQW1jLtkr7DTzofKupmF5CL8fL5yLAk9uU3yk4KD5LDyjyRt0qwsKU2qoQDH 6wfEM0Sx+eL5KAvNe4CZFxU5WEo5Nq1l9yRao8SA2MX1urWJUtYA3CJ/EioDjeBZtzWm xTLbhqcAG5mOXb6x7Ou5shjxU0iyo5TfPifGTUfGw4d2C/4Nx46Zvm60Bm48cLn9tx7f 2qag== X-Gm-Message-State: AOAM533n+lPyO8ENyEpDP1NH0HPhZuPWmyUG32f6tZg2kgqswuys+ZQ1 QusPKmzUHQj0xp2ACD8qkLwA/ZWGOb8= X-Google-Smtp-Source: ABdhPJzTKzUQt4lNaGNVQPwITNzpxde4AGRnL7HjiBMjnBEF4nNiUsjGMXxAuTtKY3vm44lI3hPWtQ== X-Received: by 2002:a1c:7ed3:: with SMTP id z202mr4372365wmc.152.1631876054322; Fri, 17 Sep 2021 03:54:14 -0700 (PDT) Received: from localhost ([217.111.27.204]) by smtp.gmail.com with ESMTPSA id z13sm7582249wrs.90.2021.09.17.03.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Sep 2021 03:54:13 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Bartosz Golaszewski Cc: Jon Hunter , Prathamesh Shete , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] gpio: tegra186: Force one interrupt per bank Date: Fri, 17 Sep 2021 12:54:11 +0200 Message-Id: <20210917105412.595539-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Newer chips support up to 8 interrupts per bank, which can be useful to balance the load and decrease latency. However, it also required a very complicated interrupt routing to be set up. To keep things simple for now, ensure that a single interrupt per bank is enforced, even if all possible interrupts are described in device tree. Signed-off-by: Thierry Reding Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tegra186.c | 68 ++++++++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index c99858f40a27..1bc4152e0275 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -81,6 +81,8 @@ struct tegra_gpio { unsigned int *irq; const struct tegra_gpio_soc *soc; + unsigned int num_irqs_per_bank; + unsigned int num_banks; void __iomem *secure; void __iomem *base; @@ -594,6 +596,28 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) } } +static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) +{ + struct device *dev = gpio->gpio.parent; + + if (gpio->num_irq > gpio->num_banks) { + if (gpio->num_irq % gpio->num_banks != 0) + goto error; + } + + if (gpio->num_irq < gpio->num_banks) + goto error; + + gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; + + return 0; + +error: + dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", + gpio->num_irq, gpio->num_banks); + return -EINVAL; +} + static int tegra186_gpio_probe(struct platform_device *pdev) { unsigned int i, j, offset; @@ -608,7 +632,17 @@ static int tegra186_gpio_probe(struct platform_device *pdev) return -ENOMEM; gpio->soc = device_get_match_data(&pdev->dev); + gpio->gpio.label = gpio->soc->name; + gpio->gpio.parent = &pdev->dev; + + /* count the number of banks in the controller */ + for (i = 0; i < gpio->soc->num_ports; i++) + if (gpio->soc->ports[i].bank > gpio->num_banks) + gpio->num_banks = gpio->soc->ports[i].bank; + + gpio->num_banks++; + /* get register apertures */ gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); if (IS_ERR(gpio->secure)) { gpio->secure = devm_platform_ioremap_resource(pdev, 0); @@ -629,6 +663,10 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->num_irq = err; + err = tegra186_gpio_irqs_per_bank(gpio); + if (err < 0) + return err; + gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), GFP_KERNEL); if (!gpio->irq) @@ -642,9 +680,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->irq[i] = err; } - gpio->gpio.label = gpio->soc->name; - gpio->gpio.parent = &pdev->dev; - gpio->gpio.request = gpiochip_generic_request; gpio->gpio.free = gpiochip_generic_free; gpio->gpio.get_direction = tegra186_gpio_get_direction; @@ -708,7 +743,30 @@ static int tegra186_gpio_probe(struct platform_device *pdev) irq->parent_handler = tegra186_gpio_irq; irq->parent_handler_data = gpio; irq->num_parents = gpio->num_irq; - irq->parents = gpio->irq; + + /* + * To simplify things, use a single interrupt per bank for now. Some + * chips support up to 8 interrupts per bank, which can be useful to + * distribute the load and decrease the processing latency for GPIOs + * but it also requires a more complicated interrupt routing than we + * currently program. + */ + if (gpio->num_irqs_per_bank > 1) { + irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, + sizeof(*irq->parents), GFP_KERNEL); + if (!irq->parents) + return -ENOMEM; + + for (i = 0; i < gpio->num_banks; i++) + irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; + + irq->num_parents = gpio->num_banks; + } else { + irq->num_parents = gpio->num_irq; + irq->parents = gpio->irq; + } + + tegra186_gpio_init_route_mapping(gpio); np = of_find_matching_node(NULL, tegra186_pmc_of_match); if (np) { @@ -719,8 +777,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - tegra186_gpio_init_route_mapping(gpio); - irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, sizeof(*irq->map), GFP_KERNEL); if (!irq->map) From patchwork Fri Sep 17 10:54:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1529341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Wxb4CF/l; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H9rRx6k20z9t0T for ; Fri, 17 Sep 2021 20:54:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343926AbhIQKzl (ORCPT ); Fri, 17 Sep 2021 06:55:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343904AbhIQKzk (ORCPT ); Fri, 17 Sep 2021 06:55:40 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F37D4C061574; Fri, 17 Sep 2021 03:54:17 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id i23so14502047wrb.2; Fri, 17 Sep 2021 03:54:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=si4x9NoZruUfMwjjOkCcKTyRfQDxhp+QOI7/QUzui6w=; b=Wxb4CF/lG5HmSN+yBf/znISKPZSM5M73lUA6eroKyQH9OaqrcZ46HgmzXAVYhW9ltv k+WFR3VI31rvlGvKJkRQYaMH3eV+/6tiOlC3SR59VIzY+CLIWHnTncKUtjQVGZuOMxN5 l0w+BoUVQDkKyl2TkpbA+BdA8dK0rDttMdeDfhyngNdO3zpWGm0pidi7/bMum/f35E59 H0G/CVAARPDMpUVKq6BfvMwSuVswqRhA+wn3Nwxt0b3k8tgultdO5BGZKt55BhnayBQ1 1q9idodfs9dOConk127JiC/12ja9jdolfFhrm9RuegyL+lK0Pa1Au26EFflkPMEIY1W9 Mm5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=si4x9NoZruUfMwjjOkCcKTyRfQDxhp+QOI7/QUzui6w=; b=xnV3/ylT4NMMsZFB4K/Fn4HqQBIL9ijgaTW1aTqVzwSrEgjdBaihUT6GEr/19bFGcv tM1mUALCwuyU5ZPw5hPEz6GozdKaWQeXbaTfUDdhNJd9+eyLRENs3+THTTvl4Ehndha/ 37hQf9dhFNHxWOUtOfr7CmLo+lUMY5qdr1dFc6Hto8xuMk0GTxOIDlx1+OZ2XUUJI9BT 7mF9mBPQKm2cNlDz3TIjGZ4XX3HJ1DEUVZkmrIDWUgcNArDdRb4fWfLrB/r6o+v0mAg4 MvY5VGHcIDldGflFA95C9JOly3cZDA50Pnkmzt2ckjOwXL4bQF46xfvHVrDKqqI1ytFk E7Ng== X-Gm-Message-State: AOAM531ZvzaATdt5OC23lrnYyl+WvUz7z+WGTdzxK4qeuu58Nrc35gyi HQita2765vUCxLA6AuWF/tk= X-Google-Smtp-Source: ABdhPJxmy7wVtNuzXGqMKfBmv2eVJNd77Vye4zFaPEvNep8dSDHKlAidj7poLfCcL7AUGmbKcVRQng== X-Received: by 2002:adf:e603:: with SMTP id p3mr11408824wrm.357.1631876056587; Fri, 17 Sep 2021 03:54:16 -0700 (PDT) Received: from localhost ([217.111.27.204]) by smtp.gmail.com with ESMTPSA id i67sm1415531wmi.41.2021.09.17.03.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Sep 2021 03:54:15 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Bartosz Golaszewski Cc: Jon Hunter , Prathamesh Shete , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] gpio: tegra186: Support multiple interrupts per bank Date: Fri, 17 Sep 2021 12:54:12 +0200 Message-Id: <20210917105412.595539-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210917105412.595539-1-thierry.reding@gmail.com> References: <20210917105412.595539-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra194 and later support more than a single interrupt per bank. This is primarily useful for virtualization but can also be helpful for more fine-grained CPU affinity control. To keep things simple for now, route all pins to the first interrupt. For backwards-compatibility, support old device trees that specify only one interrupt per bank by counting the interrupts at probe time. Signed-off-by: Thierry Reding Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tegra186.c | 48 ++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 1bc4152e0275..c026e7141e4e 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -69,6 +69,8 @@ struct tegra_gpio_soc { const char *name; unsigned int instance; + unsigned int num_irqs_per_bank; + const struct tegra186_pin_range *pin_ranges; unsigned int num_pin_ranges; const char *pinmux; @@ -452,7 +454,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc) struct irq_domain *domain = gpio->gpio.irq.domain; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int parent = irq_desc_get_irq(desc); - unsigned int i, offset = 0; + unsigned int i, j, offset = 0; chained_irq_enter(chip, desc); @@ -465,7 +467,12 @@ static void tegra186_gpio_irq(struct irq_desc *desc) base = gpio->base + port->bank * 0x1000 + port->port * 0x200; /* skip ports that are not associated with this bank */ - if (parent != gpio->irq[port->bank]) + for (j = 0; j < gpio->num_irqs_per_bank; j++) { + if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) + break; + } + + if (j == gpio->num_irqs_per_bank) goto skip; value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); @@ -567,6 +574,7 @@ static const struct of_device_id tegra186_pmc_of_match[] = { static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) { + struct device *dev = gpio->gpio.parent; unsigned int i, j; u32 value; @@ -585,12 +593,30 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) */ if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { - for (j = 0; j < 8; j++) { + /* + * On Tegra194 and later, each pin can be routed to one or more + * interrupts. + */ + for (j = 0; j < gpio->num_irqs_per_bank; j++) { + dev_dbg(dev, "programming default interrupt routing for port %s\n", + port->name); + offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); - value = readl(base + offset); - value = BIT(port->pins) - 1; - writel(value, base + offset); + /* + * By default we only want to route GPIO pins to IRQ 0. This works + * only under the assumption that we're running as the host kernel + * and hence all GPIO pins are owned by Linux. + * + * For cases where Linux is the guest OS, the hypervisor will have + * to configure the interrupt routing and pass only the valid + * interrupts via device tree. + */ + if (j == 0) { + value = readl(base + offset); + value = BIT(port->pins) - 1; + writel(value, base + offset); + } } } } @@ -610,6 +636,9 @@ static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; + if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) + goto error; + return 0; error: @@ -766,7 +795,8 @@ static int tegra186_gpio_probe(struct platform_device *pdev) irq->parents = gpio->irq; } - tegra186_gpio_init_route_mapping(gpio); + if (gpio->soc->num_irqs_per_bank > 1) + tegra186_gpio_init_route_mapping(gpio); np = of_find_matching_node(NULL, tegra186_pmc_of_match); if (np) { @@ -833,6 +863,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { .ports = tegra186_main_ports, .name = "tegra186-gpio", .instance = 0, + .num_irqs_per_bank = 1, }; #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -859,6 +890,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { .ports = tegra186_aon_ports, .name = "tegra186-gpio-aon", .instance = 1, + .num_irqs_per_bank = 1, }; #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -910,6 +942,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .ports = tegra194_main_ports, .name = "tegra194-gpio", .instance = 0, + .num_irqs_per_bank = 8, .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), .pin_ranges = tegra194_main_pin_ranges, .pinmux = "nvidia,tegra194-pinmux", @@ -936,6 +969,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .ports = tegra194_aon_ports, .name = "tegra194-gpio-aon", .instance = 1, + .num_irqs_per_bank = 8, }; static const struct of_device_id tegra186_gpio_of_match[] = {