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Content preview: Signed-off-by: Atish Patra --- include/sbi/riscv_encoding.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index e1d0b463c668..f01c6cf0264d 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -516,6 +516,40 [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Signed-off-by: Atish Patra --- include/sbi/riscv_encoding.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index e1d0b463c668..f01c6cf0264d 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -516,6 +516,40 @@ #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +/* For RV32 */ +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + +/* Counter Overflow CSR */ +#define CSR_SCOUNTOVF 0xd33 + /* Debug/Trace Registers */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 From patchwork Thu Sep 9 20:40:24 2021 Content-Type: text/plain; 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X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The sscof extension introduces mhpmeventh csrs to handle filtering /overflow bits in RV32. Add the support to read/write them. Signed-off-by: Atish Patra --- lib/sbi/riscv_asm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The sscof extension introduces mhpmeventh csrs to handle filtering /overflow bits in RV32. Add the support to read/write them. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- lib/sbi/riscv_asm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 4c24a5132195..ea6dd0837774 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -124,6 +124,11 @@ unsigned long csr_read_num(int csr_num) switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret) switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret) switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret) + switchcase_csr_read(CSR_MCOUNTINHIBIT, ret) + switchcase_csr_read(CSR_MHPMEVENT3, ret) + switchcase_csr_read_4(CSR_MHPMEVENT4, ret) + switchcase_csr_read_8(CSR_MHPMEVENT8, ret) + switchcase_csr_read_16(CSR_MHPMEVENT16, ret) #if __riscv_xlen == 32 switchcase_csr_read(CSR_MCYCLEH, ret) switchcase_csr_read(CSR_MINSTRETH, ret) @@ -131,6 +136,10 @@ unsigned long csr_read_num(int csr_num) switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) + switchcase_csr_read(CSR_MHPMEVENT3H, ret) + switchcase_csr_read_4(CSR_MHPMEVENT4H, ret) + switchcase_csr_read_8(CSR_MHPMEVENT8H, ret) + switchcase_csr_read_16(CSR_MHPMEVENT16H, ret) #endif default: @@ -189,6 +198,10 @@ void csr_write_num(int csr_num, unsigned long val) switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val) switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val) switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val) + switchcase_csr_write(CSR_MHPMEVENT3H, val) + switchcase_csr_write_4(CSR_MHPMEVENT4H, val) + switchcase_csr_write_8(CSR_MHPMEVENT8H, val) + switchcase_csr_write_16(CSR_MHPMEVENT16H, val) #endif switchcase_csr_write(CSR_MCOUNTINHIBIT, val) switchcase_csr_write(CSR_MHPMEVENT3, val) From patchwork Thu Sep 9 20:40:25 2021 Content-Type: text/plain; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: SSCOF ISA extension introduces PMU counter overflow and filtering support. It introduces a read only `scountovf` csr that can be used to detect if a hart supports this extension at runtime. However, t [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org SSCOF ISA extension introduces PMU counter overflow and filtering support. It introduces a read only `scountovf` csr that can be used to detect if a hart supports this extension at runtime. However, this feature is only useful if the hart already supports mcounteren and mcountinhibit. Add a dynamic detection mechanism and boot time print message if sscof is present. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_hart.h | 4 +++- lib/sbi/sbi_hart.c | 12 ++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 0c18ef9325b2..580a7989a4de 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -20,8 +20,10 @@ enum sbi_hart_features { SBI_HART_HAS_MCOUNTEREN = (1 << 1), /** Hart has counter inhibit CSR */ SBI_HART_HAS_MCOUNTINHIBIT = (1 << 2), + /** Hart has sscofpmf extension */ + SBI_HART_HAS_SSCOF = (1 << 3), /** HART has timer csr implementation in hardware */ - SBI_HART_HAS_TIME = (1 << 3), + SBI_HART_HAS_TIME = (1 << 4), /** Last index of Hart features*/ SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME, diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 6254452e11bb..44b8dfd1b551 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -288,6 +288,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature) case SBI_HART_HAS_MCOUNTINHIBIT: fstr = "mcountinhibit"; break; + case SBI_HART_HAS_SSCOF: + fstr = "sscof"; + break; case SBI_HART_HAS_TIME: fstr = "time"; break; @@ -497,6 +500,15 @@ __mhpm_skip: hfeatures->features |= SBI_HART_HAS_MCOUNTINHIBIT; } + /* Counter overflow/filtering is not useful without mcounter/inhibit */ + if (hfeatures->features & SBI_HART_HAS_MCOUNTINHIBIT && + hfeatures->features & SBI_HART_HAS_MCOUNTEREN) { + /* Detect if hart supports sscofpmf */ + csr_read_allowed(CSR_SCOUNTOVF, (unsigned long)&trap); + if (!trap.cause) + hfeatures->features |= SBI_HART_HAS_SSCOF; + } + /* Detect if hart supports time CSR */ csr_read_allowed(CSR_TIME, (unsigned long)&trap); if (!trap.cause) From patchwork Thu Sep 9 20:40:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1526308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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09 Sep 2021 13:15:37 -0700 IronPort-SDR: eV8N4gtTCJIPLPuIqkFV9eF/BVQPE6wFD9IkKSNzzIvu+c/nI8R/R3+QRWO2Yw66Ns38R/zc1t b+m0kb9CsRTBpm5iSP61WKZcN4Gos1I1Or7T/8TRWRaI/e3Mm9H9dIrb7VrEFjryjZD2Cr6CDG SCogN9wMcUf0UmVw/SGHYOuoBvZApebn5QXOBqSUGF38NU1RLq1pT6lP9ryRL2diXKQ4FJNjHT tXI5Ja3my6cryOFwwAtPxBduDi7t9GzEBkKEO0JjAuiQcXCLQ37UckQ1jzDeYlFpkX4dIFrnO1 2Ws= WDCIronportException: Internal Received: from unknown (HELO hulk.wdc.com) ([10.225.167.73]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Sep 2021 13:40:42 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [RFC PATCH 4/9] lib: sbi: Delegate PMU counter overflow interrupt to S mode Date: Thu, 9 Sep 2021 13:40:26 -0700 Message-Id: <20210909204031.1239254-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909204031.1239254-1-atish.patra@wdc.com> References: <20210909204031.1239254-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210909_134044_892795_9E36FAED X-CRM114-Status: UNSURE ( 9.53 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: We don't handle PMU counters for now. Delete the overflow counter to S-mode always. Signed-off-by: Atish Patra --- include/sbi/riscv_encoding.h | 2 ++ lib/sbi/sbi_hart.c | 3 +++ 2 files changed, 5 insertions(+) Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org We don't handle PMU counters for now. Delete the overflow counter to S-mode always. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/riscv_encoding.h | 2 ++ lib/sbi/sbi_hart.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index f01c6cf0264d..c2cf0f4d69f4 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -86,6 +86,7 @@ #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 #define MIP_SSIP (_UL(1) << IRQ_S_SOFT) #define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) @@ -97,6 +98,7 @@ #define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) #define MIP_MEIP (_UL(1) << IRQ_M_EXT) #define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 44b8dfd1b551..6076bea2470d 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -115,6 +115,9 @@ static int delegate_traps(struct sbi_scratch *scratch) /* Send M-mode interrupts and most exceptions to S-mode */ interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOF)) + interrupts |= MIP_LCOFIP; + exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) | (1U << CAUSE_USER_ECALL); if (sbi_platform_has_mfaults_delegation(plat)) From patchwork Thu Sep 9 20:40:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1526312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=J2qZhlNn; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=WJnJv/tP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; 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09 Sep 2021 13:40:42 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [RFC PATCH 5/9] lib:sbi: Support sscof extension in OpenSBI Date: Thu, 9 Sep 2021 13:40:27 -0700 Message-Id: <20210909204031.1239254-6-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909204031.1239254-1-atish.patra@wdc.com> References: <20210909204031.1239254-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210909_134046_285749_0F44264D X-CRM114-Status: GOOD ( 22.09 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This patch adds sscof extension in pmu module which includes following things. 1. Enable overflow irq when starting a counter. 2. Setting the correct event filters passed from supervisor. 3. Delegating the overflow interrupt to the supervisor. 4. Add RV32 support for sscof. Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds sscof extension in pmu module which includes following things. 1. Enable overflow irq when starting a counter. 2. Setting the correct event filters passed from supervisor. 3. Delegating the overflow interrupt to the supervisor. 4. Add RV32 support for sscof. Signed-off-by: Atish Patra --- include/sbi/riscv_encoding.h | 19 ++++++++ lib/sbi/sbi_pmu.c | 85 ++++++++++++++++++++++++++++++------ 2 files changed, 90 insertions(+), 14 deletions(-) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index c2cf0f4d69f4..f71412eae563 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -173,6 +173,25 @@ #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT #endif +#if __riscv_xlen == 64 +#define MHPMEVENT_OF (_UL(1) << 63) +#define MHPMEVENT_MINH (_UL(1) << 62) +#define MHPMEVENT_SINH (_UL(1) << 61) +#define MHPMEVENT_UINH (_UL(1) << 60) +#define MHPMEVENT_VSINH (_UL(1) << 59) +#define MHPMEVENT_VUINH (_UL(1) << 58) +#else +#define MHPMEVENT_OF (_ULL(1) << 63) +#define MHPMEVENT_MINH (_ULL(1) << 62) +#define MHPMEVENT_SINH (_ULL(1) << 61) +#define MHPMEVENT_UINH (_ULL(1) << 60) +#define MHPMEVENT_VSINH (_ULL(1) << 59) +#define MHPMEVENT_VUINH (_ULL(1) << 58) + +#define MHPMEVENTH_OF (_UL(1) << 31) +#endif + +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) /* ===== User-level CSRs ===== */ /* User Trap Setup (N-extension) */ diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index c276a46e2876..bbbd033b4cfe 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -226,11 +226,47 @@ int sbi_pmu_add_raw_event_counter_map(uint64_t select, u32 cmap) SBI_PMU_EVENT_RAW_IDX, cmap, select); } +static int pmu_ctr_enable_irq_hw(int ctr_idx) +{ + unsigned long mhpmevent_csr; + unsigned long mhpmevent_curr; + unsigned long mip_val; + unsigned long of_mask; + + if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) + return SBI_EFAIL; + +#if __riscv_xlen == 32 + mhpmevent_csr = CSR_MHPMEVENT3H + ctr_idx - 3; + of_mask = ~MHPMEVENTH_OF; +#else + mhpmevent_csr = CSR_MCOUNTINHIBIT + ctr_idx; + of_mask = ~MHPMEVENT_OF; +#endif + + mhpmevent_curr = csr_read_num(mhpmevent_csr); + mip_val = csr_read(CSR_MIP); + /** + * Clear out the OF bit so that next interrupt can be enabled. + * This should be done only when the corresponding overflow interrupt + * bit is cleared. That indicates that software has already handled the + * previous interrupts or the hardware yet to set an overflow interrupt. + * Otherwise, there will be race conditions where we may clear the bit + * the software is yet to handle the interrupt. + */ + if (!(mip_val & MIP_LCOFIP)) { + mhpmevent_curr &= of_mask; + csr_write_num(mhpmevent_csr, mhpmevent_curr); + } + + return 0; +} + static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival) { #if __riscv_xlen == 32 csr_write_num(CSR_MCYCLE + cidx, 0); - csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFF); + csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFFFFFF); csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG); #else csr_write_num(CSR_MCYCLE + cidx, ival); @@ -252,12 +288,14 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update) __set_bit(cidx, &mctr_en); __clear_bit(cidx, &mctr_inhbt); - if (ival_update) - pmu_ctr_write_hw(cidx, ival); - + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOF)) + pmu_ctr_enable_irq_hw(cidx); csr_write(CSR_MCOUNTEREN, mctr_en); csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); + if (ival_update) + pmu_ctr_write_hw(cidx, ival); + return 0; } @@ -326,7 +364,6 @@ static int pmu_ctr_stop_hw(uint32_t cidx) static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) { u32 hartid = current_hartid(); - fw_event_map[hartid][fw_evt_code].bStarted = FALSE; return 0; @@ -362,8 +399,21 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, return ret; } +static void pmu_update_inhibit_flags(unsigned long flags, uint64_t *mhpmevent_val) +{ + if (flags & SBI_PMU_CFG_FLAG_SET_VUINH) + *mhpmevent_val |= MHPMEVENT_VUINH; + if (flags & SBI_PMU_CFG_FLAG_SET_VSINH) + *mhpmevent_val |= MHPMEVENT_VSINH; + if (flags & SBI_PMU_CFG_FLAG_SET_UINH) + *mhpmevent_val |= MHPMEVENT_UINH; + if (flags & SBI_PMU_CFG_FLAG_SET_SINH) + *mhpmevent_val |= MHPMEVENT_SINH; +} + static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, - unsigned long eindex, uint64_t data) + unsigned long flags, unsigned long eindex, + uint64_t data) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); const struct sbi_platform *plat = sbi_platform_ptr(scratch); @@ -375,17 +425,23 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) return SBI_EFAIL; - /* TODO: The upper 16 bits of mhpmevent is reserved by sscofpmf extension. - * Update those bits based on the flags received from supervisor. - * The OVF bit also should be cleared here in case it was not cleared - * during event stop. - */ + /* Always clear the OVF bit and inhibit countin of events in M-mode */ + mhpmevent_val = (mhpmevent_val & ~MHPMEVENT_SSCOF_MASK) | MHPMEVENT_MINH; + + /* Update the inhibit flags based on inhibit flags received from supervisor */ + pmu_update_inhibit_flags(flags, &mhpmevent_val); + +#if __riscv_xlen == 32 + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, mhpmevent_val & 0xFFFFFFFF); + csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, mhpmevent_val >> BITS_PER_LONG); +#else csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, mhpmevent_val); +#endif return 0; } -static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, +static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags, unsigned long event_idx, uint64_t data) { unsigned long ctr_mask; @@ -427,7 +483,7 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, if (ctr_idx == SBI_ENOTSUPP) return SBI_EFAIL; - ret = pmu_update_hw_mhpmevent(temp, ctr_idx, event_idx, data); + ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data); if (!ret) ret = ctr_idx; @@ -490,7 +546,8 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, /* Any firmware counter can be used track any firmware event */ ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, hartid); } else { - ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, event_idx, event_data); + ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx, + event_data); } if (ctr_idx < 0) From patchwork Thu Sep 9 20:40:28 2021 Content-Type: text/plain; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: OpenSBI doesn't use any counters for its own usage. Thus, all the counters can be made accessible for lower privilege mode always. However, the mcountinhibit must be set so that the counter don't incr [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org OpenSBI doesn't use any counters for its own usage. Thus, all the counters can be made accessible for lower privilege mode always. However, the mcountinhibit must be set so that the counter don't increment. As a result, we don't have enable/disable mcounteren at every start/stop. Signed-off-by: Atish Patra --- lib/sbi/sbi_hart.c | 17 +++++------------ lib/sbi/sbi_pmu.c | 17 +++++------------ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 6076bea2470d..7ea089bc158e 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -57,18 +57,11 @@ static void mstatus_init(struct sbi_scratch *scratch) csr_write(CSR_SCOUNTEREN, 7); if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN)) { - if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) - /** - * Just enable the default counters (CY, TM, IR) because - * some OS (e.g FreeBSD) expect them to be enabled. - * - * All other counters will be enabled at runtime after - * S-mode request. - */ - csr_write(CSR_MCOUNTEREN, 7); - else - /* Supervisor mode usage are enabled by default */ - csr_write(CSR_MCOUNTEREN, -1); + /* OpenSBI doesn't use any PMU counters in M-mode. + * Supervisor mode usage for all counters are enabled by default + * But counters will not run until mcountinhibit is set. + */ + csr_write(CSR_MCOUNTEREN, -1); } /* All programmable counters will start running at runtime after S-mode request */ diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index bbbd033b4cfe..dbad4478e7e7 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -275,22 +275,20 @@ static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival) static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update) { - unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); /* Make sure the counter index lies within the range and is not TM bit */ if (cidx > num_hw_ctrs || cidx == 1) return SBI_EINVAL; - if (__test_bit(cidx, &mctr_en) && !__test_bit(cidx, &mctr_inhbt)) + if (!__test_bit(cidx, &mctr_inhbt)) return SBI_EALREADY_STARTED; - __set_bit(cidx, &mctr_en); __clear_bit(cidx, &mctr_inhbt); if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOF)) pmu_ctr_enable_irq_hw(cidx); - csr_write(CSR_MCOUNTEREN, mctr_en); csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); if (ival_update) @@ -344,17 +342,14 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, static int pmu_ctr_stop_hw(uint32_t cidx) { - unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); /* Make sure the counter index lies within the range and is not TM bit */ if (cidx > num_hw_ctrs || cidx == 1) return SBI_EINVAL; - if (__test_bit(cidx, &mctr_en) && !__test_bit(cidx, &mctr_inhbt)) { + if (!__test_bit(cidx, &mctr_inhbt)) { __set_bit(cidx, &mctr_inhbt); - __clear_bit(cidx, &mctr_en); - csr_write(CSR_MCOUNTEREN, mctr_en); csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); return 0; } else @@ -447,7 +442,6 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo unsigned long ctr_mask; int i, ret = 0, ctr_idx = SBI_ENOTSUPP; struct sbi_pmu_hw_event *temp; - unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); int evt_idx_code = get_cidx_code(event_idx); @@ -472,8 +466,7 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo ctr_mask = temp->counters & (cmask << cbase); for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) { - if (!__test_bit(cbase, &mctr_en) && - __test_bit(cbase, &mctr_inhbt)) { + if (__test_bit(cbase, &mctr_inhbt)) { ctr_idx = cbase; break; } @@ -645,7 +638,7 @@ void sbi_pmu_exit(struct sbi_scratch *scratch) return; csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8); - csr_write(CSR_MCOUNTEREN, 7); + csr_write(CSR_MCOUNTEREN, -1); pmu_reset_event_map(hartid); } From patchwork Thu Sep 9 20:40:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1526315 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=LGHQVAtz; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: A platform may use programmable counters for cycle/instret events. The priv spec allows that provided that cycle/instret also report those events in addition to the programmable counters. We should al [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org A platform may use programmable counters for cycle/instret events. The priv spec allows that provided that cycle/instret also report those events in addition to the programmable counters. We should allow that functionality in OpenSBI. Signed-off-by: Atish Patra --- lib/sbi/sbi_pmu.c | 57 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index dbad4478e7e7..20f78c75200e 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -175,9 +175,7 @@ static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap, struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events]; /* The first two counters are reserved by priv spec */ - if ((eidx_start == SBI_PMU_HW_CPU_CYCLES && cmap != 0x1) || - (eidx_start == SBI_PMU_HW_INSTRUCTIONS && cmap != 0x4) || - (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & 0x07))) + if (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & 0x07)) return SBI_EDENIED; if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) { @@ -188,8 +186,6 @@ static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap, event->start_idx = eidx_start; event->end_idx = eidx_end; - event->counters = cmap; - event->select = select; /* Sanity check */ for (i = 0; i < num_hw_events; i++) { @@ -199,11 +195,19 @@ static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap, else is_overlap = pmu_event_range_overlap(&hw_event_map[i], event); if (is_overlap) - return SBI_EINVALID_ADDR; + goto reset_event; } + + event->counters = cmap; + event->select = select; num_hw_events++; return 0; + +reset_event: + event->start_idx = 0; + event->end_idx = 0; + return SBI_EINVAL; } /** @@ -436,23 +440,36 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, return 0; } +static int pmu_ctr_find_fixed_fw(unsigned long evt_idx_code) +{ + /* Non-programmables counters are enabled always. No need to do lookup */ + if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES) + return 0; + else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return SBI_EINVAL; +} + static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned long flags, unsigned long event_idx, uint64_t data) { unsigned long ctr_mask; - int i, ret = 0, ctr_idx = SBI_ENOTSUPP; + int i, ret = 0, fixed_ctr, ctr_idx = SBI_ENOTSUPP; struct sbi_pmu_hw_event *temp; unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); - int evt_idx_code = get_cidx_code(event_idx); + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + bool sscof_present = sbi_hart_has_feature(scratch, SBI_HART_HAS_SSCOF); if (cbase > num_hw_ctrs) return SBI_EINVAL; - /* Non-programmables counters are enabled always. No need to do lookup */ - if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES) - return 0; - else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS) - return 2; + /* If Sscof is present try to find the programmable counter for + * cycle/instret as well. + */ + fixed_ctr = pmu_ctr_find_fixed_fw(event_idx); + if (fixed_ctr >= 0 && !sscof_present) + return fixed_ctr; for (i = 0; i < num_hw_events; i++) { temp = &hw_event_map[i]; @@ -464,7 +481,8 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo if ((event_idx == SBI_PMU_EVENT_RAW_IDX) && temp->select != data) continue; - ctr_mask = temp->counters & (cmask << cbase); + /* Fixed counters should not be part of the search */ + ctr_mask = temp->counters & (cmask << cbase) & (~0x07); for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) { if (__test_bit(cbase, &mctr_inhbt)) { ctr_idx = cbase; @@ -473,8 +491,15 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo } } - if (ctr_idx == SBI_ENOTSUPP) - return SBI_EFAIL; + if (ctr_idx == SBI_ENOTSUPP) { + /* We can't find any programmable counters for cycle/instret. + * Return the fixed counter as they are mandatory anyways. + */ + if (fixed_ctr >= 0) + return fixed_ctr; + else + return SBI_EFAIL; + } ret = pmu_update_hw_mhpmevent(temp, ctr_idx, flags, event_idx, data); From patchwork Thu Sep 9 20:40:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1526313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=mcE82Hj2; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=LNOR4eRd; dkim-atps=neutral Authentication-Results: ozlabs.org; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The hardware solely relies on the event selector value in mhpmevent to figure out what event to monitor using that counter. It should be reset when counter reset happens. Signed-off-by: Atish Patra --- lib/sbi/sbi_pmu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The hardware solely relies on the event selector value in mhpmevent to figure out what event to monitor using that counter. It should be reset when counter reset happens. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- lib/sbi/sbi_pmu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 20f78c75200e..f33842052a46 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -368,6 +368,20 @@ static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) return 0; } +static int pmu_reset_hw_mhpmevent(int ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) + return SBI_EFAIL; +#if __riscv_xlen == 32 + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, 0); + csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0); +#else + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, 0); +#endif + + return 0; +} + int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, unsigned long flag) { @@ -391,8 +405,10 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, else ret = pmu_ctr_stop_hw(cbase); - if (!ret && (flag & SBI_PMU_STOP_FLAG_RESET)) + if (flag & SBI_PMU_STOP_FLAG_RESET) { active_events[hartid][cbase] = SBI_PMU_EVENT_IDX_INVALID; + pmu_reset_hw_mhpmevent(cbase); + } } return ret; From patchwork Thu Sep 9 20:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1526314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=TaUv0mbl; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=YmZ9iNE7; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H59rV1Yw0z9t0T for ; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The mhpm bits represent the number of bits available in mhpmcounter while counter width describes a zero indexed value. Fix the counter width calculation. Signed-off-by: Atish Patra --- lib/sbi/sbi_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The mhpm bits represent the number of bits available in mhpmcounter while counter width describes a zero indexed value. Fix the counter width calculation. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- lib/sbi/sbi_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index f33842052a46..0e61417db14b 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -645,7 +645,7 @@ int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) if (cidx == 0 || cidx == 2) cinfo.width = 63; else - cinfo.width = sbi_hart_mhpm_bits(scratch); + cinfo.width = sbi_hart_mhpm_bits(scratch) - 1; } else { /* it's a firmware counter */ cinfo.type = SBI_PMU_CTR_TYPE_FW;