From patchwork Wed Sep 8 05:36:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1525631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=JBPdp9v5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H49qW4L6gz9sXV for ; Wed, 8 Sep 2021 15:36:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 89CF5385041D for ; Wed, 8 Sep 2021 05:36:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 89CF5385041D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1631079392; bh=T6YgWZdqR5zf6K3VY8l2wJO5daXTN7kqiKM3IWNL7BM=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=JBPdp9v5guqEo8VDwVsiSfOKYRP6a76nwTB3+sW8mTDwUQcLuVMyZTFnNh/hbjPHf 64YNIHtujnc64cxhhOgjZt5bjSWbuWDjNekm6xIXKmjLEr72Yfi7MVjKkHtoooBOXs S/XCQK9RC1mn+Cb0J/HsOIEJ5/m0ap+MWlpjfnxQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id ACC073858D29 for ; Wed, 8 Sep 2021 05:36:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ACC073858D29 X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="281405293" X-IronPort-AV: E=Sophos;i="5.85,276,1624345200"; d="scan'208";a="281405293" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2021 22:36:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,276,1624345200"; d="scan'208";a="479030063" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 07 Sep 2021 22:36:08 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 1885a6JE001639; Tue, 7 Sep 2021 22:36:07 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Optimize v4sf reduction. Date: Wed, 8 Sep 2021 13:36:06 +0800 Message-Id: <20210908053606.190077-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi: The optimization is decribled in PR. The two instruction sequences are almost as fast, but the optimized instruction sequences could be one mov instruction less on sse2 and 2 mov instruction less on sse3. Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. gcc/ChangeLog: PR target/101059 * config/i386/sse.md (reduc_plus_scal_): Split to .. (reduc_plus_scal_v4sf): .. this, New define_expand. (reduc_plus_scal_v2df): .. and this, New define_expand. gcc/testsuite/ChangeLog: PR target/101059 * gcc.target/i386/sse2-pr101059.c: New test. * gcc.target/i386/sse3-pr101059.c: New test. --- gcc/config/i386/sse.md | 39 +++++++++++++------ gcc/testsuite/gcc.target/i386/sse2-pr101059.c | 32 +++++++++++++++ gcc/testsuite/gcc.target/i386/sse3-pr101059.c | 13 +++++++ 3 files changed, 73 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/sse2-pr101059.c create mode 100644 gcc/testsuite/gcc.target/i386/sse3-pr101059.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5785e73241c..b8057344a1c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2874,19 +2874,36 @@ (define_insn "sse3_hv4sf3" (set_attr "prefix_rep" "1,*") (set_attr "mode" "V4SF")]) -(define_mode_iterator REDUC_SSE_PLUS_MODE - [(V2DF "TARGET_SSE") (V4SF "TARGET_SSE")]) +(define_expand "reduc_plus_scal_v4sf" + [(plus:V4SF + (match_operand:SF 0 "register_operand") + (match_operand:V4SF 1 "register_operand"))] + "TARGET_SSE" +{ + rtx vtmp = gen_reg_rtx (V4SFmode); + rtx stmp = gen_reg_rtx (SFmode); + if (TARGET_SSE3) + emit_insn (gen_sse3_movshdup (vtmp, operands[1])); + else + emit_insn (gen_sse_shufps (vtmp, operands[1], operands[1], GEN_INT(177))); -(define_expand "reduc_plus_scal_" - [(plus:REDUC_SSE_PLUS_MODE - (match_operand: 0 "register_operand") - (match_operand:REDUC_SSE_PLUS_MODE 1 "register_operand"))] - "" + emit_insn (gen_addv4sf3 (operands[1], operands[1], vtmp)); + emit_insn (gen_sse_movhlps (vtmp, vtmp, operands[1])); + emit_insn (gen_vec_extractv4sfsf (stmp, vtmp, const0_rtx)); + emit_insn (gen_vec_extractv4sfsf (operands[0], operands[1], const0_rtx)); + emit_insn (gen_addsf3 (operands[0], operands[0], stmp)); + DONE; +}) + +(define_expand "reduc_plus_scal_v2df" + [(plus:V2DF + (match_operand:DF 0 "register_operand") + (match_operand:V2DF 1 "register_operand"))] + "TARGET_SSE" { - rtx tmp = gen_reg_rtx (mode); - ix86_expand_reduc (gen_add3, tmp, operands[1]); - emit_insn (gen_vec_extract (operands[0], tmp, - const0_rtx)); + rtx tmp = gen_reg_rtx (V2DFmode); + ix86_expand_reduc (gen_addv2df3, tmp, operands[1]); + emit_insn (gen_vec_extractv2dfdf (operands[0], tmp, const0_rtx)); DONE; }) diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr101059.c b/gcc/testsuite/gcc.target/i386/sse2-pr101059.c new file mode 100644 index 00000000000..d155bf5b43c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-pr101059.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +float +__attribute__((noipa, optimize("tree-vectorize"))) +foo (float* p) +{ + float sum = 0.f; + for (int i = 0; i != 4; i++) + sum += p[i]; + return sum; +} + +static void +TEST (void) +{ + float p[4] = {1.0f, 2.0f, 3.0f, 4.0f}; + float res = foo (p); + if (res != 10.0f) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse3-pr101059.c b/gcc/testsuite/gcc.target/i386/sse3-pr101059.c new file mode 100644 index 00000000000..4795e892883 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse3-pr101059.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -msse3" } */ +/* { dg-require-effective-target sse3 } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include "sse2-pr101059.c"