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Tue, 7 Sep 2021 07:32:48 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 7 Sep 2021 00:32:47 -0700 Received: from pshete-ubuntu.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 7 Sep 2021 07:32:45 +0000 From: Prathamesh Shete To: , , , , , , CC: , Subject: [PATCH v3 1/2] gpio: tegra: add multiple interrupt support Date: Tue, 7 Sep 2021 13:02:23 +0530 Message-ID: <20210907073224.3070-2-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210907073224.3070-1-pshete@nvidia.com> References: <20210907073224.3070-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a6a69b2f-abc4-42af-fc31-08d971d1b160 X-MS-TrafficTypeDiagnostic: BN8PR12MB2866: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2021 07:32:48.6083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6a69b2f-abc4-42af-fc31-08d971d1b160 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2866 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: pshete T19x GPIO controller's support multiple interrupts. The GPIO controller is capable to route 8 interrupts per controller in case of NON-AON GPIO's and 4 interrupts per controller in AON GPIO. This is new feature starting Tegra194 The interrupt route map determines which interrupt line is to be used. Signed-off-by: Prathamesh Shete --- drivers/gpio/gpio-tegra186.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d38980b9923a..c1172da9aebf 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2017 NVIDIA Corporation + * Copyright (c) 2016-2021 NVIDIA Corporation * * Author: Thierry Reding */ @@ -68,6 +68,7 @@ struct tegra_gpio_soc { unsigned int num_ports; const char *name; unsigned int instance; + bool multi_ints; const struct tegra186_pin_range *pin_ranges; unsigned int num_pin_ranges; @@ -450,7 +451,8 @@ static void tegra186_gpio_irq(struct irq_desc *desc) struct irq_domain *domain = gpio->gpio.irq.domain; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int parent = irq_desc_get_irq(desc); - unsigned int i, offset = 0; + unsigned int i, j, offset = 0; + int intr_cntr; chained_irq_enter(chip, desc); @@ -462,9 +464,20 @@ static void tegra186_gpio_irq(struct irq_desc *desc) base = gpio->base + port->bank * 0x1000 + port->port * 0x200; - /* skip ports that are not associated with this bank */ - if (parent != gpio->irq[port->bank]) - goto skip; + if (!gpio->soc->multi_ints) { + /* skip ports that are not associated with this bank */ + if (parent != gpio->irq[port->bank]) + goto skip; + + } else { + intr_cntr = 0; + for (j = 0; j < 8; j++) { + if (parent != gpio->irq[(port->bank * 8) + j]) + intr_cntr++; + } + if (!(intr_cntr & 0xF)) + goto skip; + } value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); @@ -772,6 +785,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { .ports = tegra186_main_ports, .name = "tegra186-gpio", .instance = 0, + .multi_ints = false, }; #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -798,6 +812,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { .ports = tegra186_aon_ports, .name = "tegra186-gpio-aon", .instance = 1, + .multi_ints = false, }; #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -852,6 +867,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), .pin_ranges = tegra194_main_pin_ranges, .pinmux = "nvidia,tegra194-pinmux", + .multi_ints = true, }; #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -875,6 +891,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .ports = tegra194_aon_ports, .name = "tegra194-gpio-aon", .instance = 1, + .multi_ints = true, }; static const struct of_device_id tegra186_gpio_of_match[] = { From patchwork Tue Sep 7 07:32:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 1525138 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=ICEVd3XL; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2021 07:32:52.3093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efa3bb30-3da3-4c87-7574-08d971d1b38d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5438 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: pshete Tegra19x supports 8 entries for GPIO controller. This change adds the required interrupt entires for all GPIO controllers. Signed-off-by: Prathamesh Shete --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index b7d532841390..c681a79c44ec 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -34,11 +34,53 @@ reg = <0x2200000 0x10000>, <0x2210000 0x10000>; interrupts = , + , + , + , + , + , + , + , , + , + , + , + , + , + , + , , + , + , + , + , + , + , + , , + , + , + , + , + , + , + , , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #interrupt-cells = <2>; interrupt-controller; #gpio-cells = <2>; @@ -1273,7 +1315,10 @@ reg-names = "security", "gpio"; reg = <0xc2f0000 0x1000>, <0xc2f1000 0x1000>; - interrupts = ; + interrupts = , + , + , + ; gpio-controller; #gpio-cells = <2>; interrupt-controller;