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X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2021 18:51:42.1475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e672e7d-9f77-4555-ace4-08d968c28b75 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9;Ip=[158.140.1.148];Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM12FT032.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR07MB3547 X-Proofpoint-GUID: nfzEKx7cYZeC5aBbhNFdBx9lBy5hQkGb X-Proofpoint-ORIG-GUID: nfzEKx7cYZeC5aBbhNFdBx9lBy5hQkGb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-08-26_05,2021-08-26_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108260104 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Converted bindings into yaml format for Cadence UFS host controller Signed-off-by: Dhananjay Kangude --- .../devicetree/bindings/ufs/cdns,ufshc.txt | 32 -------- .../devicetree/bindings/ufs/cdns,ufshc.yaml | 80 ++++++++++++++++++++ 2 files changed, 80 insertions(+), 32 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt deleted file mode 100644 index 02347b0..0000000 --- a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Cadence Universal Flash Storage (UFS) Controller - -UFS nodes are defined to describe on-chip UFS host controllers. -Each UFS controller instance should have its own node. -Please see the ufshcd-pltfrm.txt for a list of all available properties. - -Required properties: -- compatible : Compatible list, contains one of the following controllers: - "cdns,ufshc" - Generic CDNS HCI, - "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY - complemented with the JEDEC version: - "jedec,ufs-2.0" - -- reg : Address and length of the UFS register set. -- interrupts : One interrupt mapping. -- freq-table-hz : Clock frequency table. - See the ufshcd-pltfrm.txt for details. -- clocks : List of phandle and clock specifier pairs. -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. "core_clk" is mandatory. - Depending on a type of a PHY, - the "phy_clk" clock can also be added, if needed. - -Example: - ufs@fd030000 { - compatible = "cdns,ufshc", "jedec,ufs-2.0"; - reg = <0xfd030000 0x10000>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; - freq-table-hz = <0 0>, <0 0>; - clocks = <&ufs_core_clk>, <&ufs_phy_clk>; - clock-names = "core_clk", "phy_clk"; - }; diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml new file mode 100644 index 0000000..4509ae0 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Universal Flash Storage (UFS) Controller + +maintainers: + - Dhananjay Kangude + +description: + UFS nodes are defined to describe on-chip Cadence UFS host controllers. + Each UFS controller instance should have its own node. + +properties: + compatible: + oneOf: + - items: + - enum: + - cdns,ufshc + - cdns,ufshc-m31-16nm + - const: jedec,ufs-2.0 + - items: + - const: jedec,ufs-2.0 + + reg: + items: + - description: UFS controller register set + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: Description of core_clk + - description: Description of phy_clk + - description: Description of ref_clk + + clock-names: + minItems: 1 + items: + - const: core_clk + - const: phy_clk + - const: ref_clk + + freq-table-hz: + $ref: /schemas/types.yaml#/definitions/uint64-matrix + description: + Clock frequency table. + See the ufshcd-pltfrm.txt for details. + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - freq-table-hz + - clocks + - clock-names + +additionalProperties: false +unevaluatedProperties: false + +examples: + - | + #include + #include + + ufs: ufs@fd030000 { + compatible = "cdns,ufshc", "jedec,ufs-2.0"; + reg = <0xfd030000 0x10000>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; + freq-table-hz = <0 0>; + clocks = <&ufs_core_clk>; + clock-names = "core_clk"; + }; +