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ppma04ams.nl.ibm.com with ESMTP id 3a4x590qgt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:22:05 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747M25t53739988 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:02 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 01E1AAE05D; Wed, 4 Aug 2021 07:22:02 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11EDCAE061; Wed, 4 Aug 2021 07:22:00 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:21:59 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:39 +0530 Message-Id: <20210804072137.1147875-2-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Y4hfEmRh8RyiHFMGBn_udQnzlsbg2Ih3 X-Proofpoint-GUID: RbIMh2dSrPOMAUp-TZ_dAkxQOfenF6uL X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 01/59] external/mambo: skiboot.tcl add POWER10 config X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ravi Bangoria , Madhavan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin Co-authored-by: Nicholas Piggin Signed-off-by: Nicholas Piggin Co-authored-by: Madhavan Srinivasan Signed-off-by: Madhavan Srinivasan Co-authored-by: Ravi Bangoria Signed-off-by: Ravi Bangoria [Folded Maddy's IMC changes and Ravi's DAWR changes - Vasant] Signed-off-by: Vasant Hegde --- external/mambo/skiboot.tcl | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl index 3a8e19406..0ecb55a77 100644 --- a/external/mambo/skiboot.tcl +++ b/external/mambo/skiboot.tcl @@ -143,6 +143,17 @@ if { $default_config == "P9" } { } } +if { $default_config == "P10" } { + # PVR configured for POWER10 DD1.0 + myconf config processor/initial/PVR 0x800100 + myconf config processor/initial/SIM_CTRL1 0xc228100400000000 + + if { $mconf(numa) } { + myconf config memory_region_id_shift 44 + } +} + + if { $mconf(numa) } { myconf config memory_regions $mconf(cpus) } @@ -390,8 +401,8 @@ mysim of addprop $fake_nvram_node empty "name" "ibm,fake-nvram" set opal_node [mysim of addchild $root_node "ibm,opal" ""] -# Allow P9 to use all idle states -if { $default_config == "P9" } { +# Allow P9/P10 to use all idle states +if { $default_config == "P9" || $default_config == "P10" } { set power_mgt_node [mysim of addchild $opal_node "power-mgt" ""] mysim of addprop $power_mgt_node int "ibm,enabled-stop-levels" 0xffffffff } @@ -461,7 +472,7 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { lappend reg 0x22 0x120 1 0x22 0x0003 ;# 16G seg 16G pages mysim of addprop $cpu_node array "ibm,segment-page-sizes" reg - if { $default_config == "P9" } { + if { $default_config == "P9" || $default_config == "P10" } { # Set actual page size encodings set reg {} # 4K pages @@ -476,8 +487,13 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { set reg {} # POWER9 PAPR defines upto bytes 62-63 + # POWER10 PAPR defines upto byte 64-65 # header + bytes 0-5 - lappend reg 0x4000f63fc70080c0 + if { $default_config == "P9" } { + lappend reg 0x4000f63fc70080c0 + } else { + lappend reg 0x4200f63fc70080c0 + } # bytes 6-13 lappend reg 0x8000000000000000 # bytes 14-21 @@ -492,8 +508,12 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { lappend reg 0x8000800080008000 # bytes 54-61 58/59=seg tbl lappend reg 0x8000800080008000 - # bytes 62-69 - lappend reg 0x8000000000000000 + # bytes 62-69 64/65=DAWR1(P10 only) + if { $default_config == "P9" } { + lappend reg 0x8000000000000000 + } else { + lappend reg 0x8000800000000000 + } mysim of addprop $cpu_node array64 "ibm,pa-features" reg } else { set reg {} @@ -514,7 +534,7 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { } #Add In-Memory Collection Counter nodes -if { $default_config == "P9" } { +if { $default_config == "P9" || $default_config == "P10" } { #Add the base node "imc-counters" set imc_c [mysim of addchild $root_node "imc-counters" ""] mysim of addprop $imc_c string "compatible" "ibm,opal-in-memory-counters" From patchwork Wed Aug 4 07:20:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com 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clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 02/59] Initial POWER10 enablement X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling , Mahesh Salgaonkar , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin Co-authored-by: Nicholas Piggin Signed-off-by: Nicholas Piggin Co-authored-by: Vaidyanathan Srinivasan Signed-off-by: Vaidyanathan Srinivasan Co-authored-by: Michael Neuling Signed-off-by: Michael Neuling Co-authored-by: Vasant Hegde Signed-off-by: Vasant Hegde Co-authored-by: Mahesh Salgaonkar Signed-off-by: Mahesh Salgaonkar Co-authored-by: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- asm/head.S | 55 +++++- asm/misc.S | 4 +- core/affinity.c | 2 + core/chip.c | 40 +++- core/cpu.c | 32 +++- core/direct-controls.c | 363 ++++++++++++++++++++++++++++++++++--- core/hmi.c | 221 ++++++++++++++++++++-- core/init.c | 2 +- core/mce.c | 129 ++++++++++++- core/test/run-timer.c | 2 +- doc/platforms-and-cpus.rst | 1 + hw/chiptod.c | 30 ++- hw/dts.c | 7 +- hw/lpc.c | 7 +- hw/xscom.c | 25 ++- include/chip.h | 49 +++++ include/opal-api.h | 1 + include/processor.h | 52 ++++-- include/skiboot.h | 1 + include/xscom-p10-regs.h | 54 ++++++ include/xscom.h | 85 +++++++++ 21 files changed, 1067 insertions(+), 95 deletions(-) create mode 100644 include/xscom-p10-regs.h diff --git a/asm/head.S b/asm/head.S index d773bde04..f85b0fe29 100644 --- a/asm/head.S +++ b/asm/head.S @@ -324,7 +324,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask - * r25 : P9 fused core flag + * r25 : P9/10 fused core flag */ .global boot_entry boot_entry: @@ -342,6 +342,8 @@ boot_entry: beq 3f cmpwi cr0,%r3,PVR_TYPE_P9P beq 3f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 4f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ @@ -352,8 +354,17 @@ boot_entry: mfspr %r3, SPR_SPRD andi. %r25, %r3, 1 beq 1f + b 2f - /* P8 or P9 fused -> 8 threads */ +4: /* + * P10 fused core check (SPRC/SPRD method does not work). + * PVR bit 12 set = normal code + */ + andi. %r3, %r28, 0x1000 + bne 1f + li %r25, 1 + + /* P8 or P9 fused or P10 fused -> 8 threads */ 2: li %r26,7 @@ -730,6 +741,8 @@ init_shared_sprs: beq 4f cmpwi cr0,%r3,PVR_TYPE_P9P beq 4f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 5f /* Unsupported CPU type... what do we do ? */ b 9f @@ -806,6 +819,32 @@ init_shared_sprs: LOAD_IMM64(%r3,0x00000103070F1F3F) mtspr SPR_RPR,%r3 + b 9f + +5: /* P10 */ + /* TSCR: UM recommended value */ + LOAD_IMM32(%r3,0x80287880) + mtspr SPR_TSCR, %r3 + + /* HID0: + * Boot with PPC_BIT(5) set (dis_recovery). + * Clear bit 5 to enable recovery. + */ + LOAD_IMM64(%r3, 0) + sync + mtspr SPR_HID0,%r3 + isync + + LOAD_IMM64(%r4,SPR_HMEER_P10_HMI_ENABLE_MASK) + mfspr %r3,SPR_HMEER + or %r3,%r3,%r4 + sync + mtspr SPR_HMEER,%r3 + isync + + LOAD_IMM64(%r3,0x00000103070F1F3F) + mtspr SPR_RPR,%r3 + 9: blr .global init_replicated_sprs @@ -822,6 +861,8 @@ init_replicated_sprs: beq 4f cmpwi cr0,%r3,PVR_TYPE_P9P beq 4f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 5f /* Unsupported CPU type... what do we do ? */ b 9f @@ -845,6 +886,16 @@ init_replicated_sprs: LOAD_IMM64(%r3,0x0000000000000010) mtspr SPR_DSCR,%r3 +5: /* P10 */ + /* LPCR: sane value */ + LOAD_IMM64(%r3,0x0040000000000000) + mtspr SPR_LPCR, %r3 + sync + isync + /* DSCR: Stride-N Stream Enable */ + LOAD_IMM64(%r3,0x0000000000000010) + mtspr SPR_DSCR,%r3 + 9: blr .global enter_nap diff --git a/asm/misc.S b/asm/misc.S index 033448975..ea4376322 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -99,13 +99,15 @@ cleanup_local_tlb: .global cleanup_global_tlb cleanup_global_tlb: - /* Only supported on P9 for now */ + /* Only supported on P9, P10 for now */ mfspr %r3,SPR_PVR srdi %r3,%r3,16 cmpwi cr0,%r3,PVR_TYPE_P9 beq cr0,1f cmpwi cr0,%r3,PVR_TYPE_P9P beq cr0,1f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq cr0,1f blr /* Sync out previous updates */ diff --git a/core/affinity.c b/core/affinity.c index 47ba33cf2..0209d3cd9 100644 --- a/core/affinity.c +++ b/core/affinity.c @@ -111,6 +111,8 @@ void add_core_associativity(struct cpu_thread *cpu) core_id = (cpu->pir >> 3) & 0xf; else if (proc_gen == proc_gen_p9) core_id = (cpu->pir >> 2) & 0x1f; + else if (proc_gen == proc_gen_p10) + core_id = (cpu->pir >> 2) & 0x1f; else return; diff --git a/core/chip.c b/core/chip.c index f1269d3f9..f79e8cd04 100644 --- a/core/chip.c +++ b/core/chip.c @@ -13,7 +13,9 @@ enum proc_chip_quirks proc_chip_quirks; uint32_t pir_to_chip_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + return P10_PIR2GCID(pir); + else if (proc_gen == proc_gen_p9) return P9_PIR2GCID(pir); else if (proc_gen == proc_gen_p8) return P8_PIR2GCID(pir); @@ -23,41 +25,59 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + if (this_cpu()->is_fused_core) + return P10_PIRFUSED2NORMALCOREID(pir); + else + return P10_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIRFUSED2NORMALCOREID(pir); else return P9_PIR2COREID(pir); - } else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) { return P8_PIR2COREID(pir); - else + } else { assert(false); + } } uint32_t pir_to_fused_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + if (this_cpu()->is_fused_core) + return P10_PIR2FUSEDCOREID(pir); + else + return P10_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIR2FUSEDCOREID(pir); else return P9_PIR2COREID(pir); - } else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) { return P8_PIR2COREID(pir); - else + } else { assert(false); + } } uint32_t pir_to_thread_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + if (this_cpu()->is_fused_core) + return P10_PIRFUSED2NORMALTHREADID(pir); + else + return P10_PIR2THREADID(pir); + } else if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIRFUSED2NORMALTHREADID(pir); else return P9_PIR2THREADID(pir); - } else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) { return P8_PIR2THREADID(pir); - else + } else { assert(false); + } } struct proc_chip *next_chip(struct proc_chip *chip) diff --git a/core/cpu.c b/core/cpu.c index dbc1ff445..f58aeb27a 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -100,7 +100,7 @@ static void cpu_wake(struct cpu_thread *cpu) if (proc_gen == proc_gen_p8) { /* Poke IPI */ icp_kick_cpu(cpu); - } else if (proc_gen == proc_gen_p9) { + } else if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) { p9_dbell_send(cpu->pir); } } @@ -507,6 +507,9 @@ static void cpu_idle_pm(enum cpu_wake_cause wake_on) case proc_gen_p9: vec = cpu_idle_p9(wake_on); break; + case proc_gen_p10: + vec = cpu_idle_p9(wake_on); + break; default: vec = 0; prlog_once(PR_DEBUG, "cpu_idle_pm called with bad processor type\n"); @@ -605,7 +608,7 @@ static void cpu_pm_disable(void) cpu_relax(); } } - } else if (proc_gen == proc_gen_p9) { + } else if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) { for_each_available_cpu(cpu) { if (cpu->in_sleep || cpu->in_idle) p9_dbell_send(cpu->pir); @@ -648,7 +651,7 @@ void cpu_set_sreset_enable(bool enabled) pm_enabled = true; } - } else if (proc_gen == proc_gen_p9) { + } else if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) { sreset_enabled = enabled; sync(); /* @@ -676,7 +679,7 @@ void cpu_set_ipi_enable(bool enabled) pm_enabled = true; } - } else if (proc_gen == proc_gen_p9) { + } else if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) { ipi_enabled = enabled; sync(); if (!enabled) @@ -1014,6 +1017,13 @@ void init_boot_cpu(void) hid0_hile = SPR_HID0_POWER9_HILE; hid0_attn = SPR_HID0_POWER9_ENABLE_ATTN; break; + case PVR_TYPE_P10: + proc_gen = proc_gen_p10; + hile_supported = true; + radix_supported = true; + hid0_hile = SPR_HID0_POWER10_HILE; + hid0_attn = SPR_HID0_POWER10_ENABLE_ATTN; + break; default: proc_gen = proc_gen_unknown; } @@ -1033,6 +1043,14 @@ void init_boot_cpu(void) prlog(PR_INFO, "CPU: P9 generation processor" " (max %d threads/core)\n", cpu_thread_count); break; + case proc_gen_p10: + if (is_fused_core(pvr)) + cpu_thread_count = 8; + else + cpu_thread_count = 4; + prlog(PR_INFO, "CPU: P10 generation processor" + " (max %d threads/core)\n", cpu_thread_count); + break; default: prerror("CPU: Unknown PVR, assuming 1 thread\n"); cpu_thread_count = 1; @@ -1535,7 +1553,8 @@ void cpu_fast_reboot_complete(void) current_hile_mode = HAVE_LITTLE_ENDIAN; /* and set HID0:RADIX */ - current_radix_mode = true; + if (proc_gen == proc_gen_p9) + current_radix_mode = true; } static int64_t opal_reinit_cpus(uint64_t flags) @@ -1616,7 +1635,8 @@ static int64_t opal_reinit_cpus(uint64_t flags) flags &= ~(OPAL_REINIT_CPUS_MMU_HASH | OPAL_REINIT_CPUS_MMU_RADIX); - if (radix != current_radix_mode) { + + if (proc_gen == proc_gen_p9 && radix != current_radix_mode) { if (radix) req.set_bits |= SPR_HID0_POWER9_RADIX; else diff --git a/core/direct-controls.c b/core/direct-controls.c index 0274367da..f7509dde0 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -268,6 +269,25 @@ static int p8_sreset_thread(struct cpu_thread *cpu) * using scom registers. */ +static int p9_core_is_gated(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t sshhyp_addr; + uint64_t val; + + sshhyp_addr = XSCOM_ADDR_P9_EC_SLAVE(core_id, P9_EC_PPM_SSHHYP); + + if (xscom_read(chip_id, sshhyp_addr, &val)) { + prlog(PR_ERR, "Could not query core gated on %u:%u:" + " Unable to read PPM_SSHHYP.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + + return !!(val & P9_CORE_GATED); +} + static int p9_core_set_special_wakeup(struct cpu_thread *cpu) { uint32_t chip_id = pir_to_chip_id(cpu->pir); @@ -301,7 +321,7 @@ static int p9_core_set_special_wakeup(struct cpu_thread *cpu) * out of stop state. If CORE_GATED is still set then * raise error. */ - if (dctl_core_is_gated(cpu)) { + if (p9_core_is_gated(cpu)) { /* Deassert spwu for this strange error */ xscom_write(chip_id, swake_addr, 0); prlog(PR_ERR, "Failed special wakeup on %u:%u" @@ -517,6 +537,295 @@ static int p9_sreset_thread(struct cpu_thread *cpu) return 0; } +/**************** POWER10 direct controls ****************/ + +/* Long running instructions may take time to complete. Timeout 100ms */ +#define P10_QUIESCE_POLL_INTERVAL 100 +#define P10_QUIESCE_TIMEOUT 100000 + +/* Waking may take up to 5ms for deepest sleep states. Set timeout to 100ms */ +#define P10_SPWU_POLL_INTERVAL 100 +#define P10_SPWU_TIMEOUT 100000 + +/* + * This implements direct control facilities of processor cores and threads + * using scom registers. + */ +static int p10_core_is_gated(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t ssh_addr; + uint64_t val; + + ssh_addr = XSCOM_ADDR_P10_QME_CORE(core_id, P10_QME_SSH_HYP); + + if (xscom_read(chip_id, ssh_addr, &val)) { + prlog(PR_ERR, "Could not query core gated on %u:%u:" + " Unable to read QME_SSH_HYP.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + + return !!(val & P10_SSH_CORE_GATED); +} + + +static int p10_core_set_special_wakeup(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t spwu_addr, ssh_addr; + uint64_t val; + int i; + + /* P10 could use SPWU_HYP done bit instead of SSH? */ + spwu_addr = XSCOM_ADDR_P10_QME_CORE(core_id, P10_QME_SPWU_HYP); + ssh_addr = XSCOM_ADDR_P10_QME_CORE(core_id, P10_QME_SSH_HYP); + + if (xscom_write(chip_id, spwu_addr, P10_SPWU_REQ)) { + prlog(PR_ERR, "Could not set special wakeup on %u:%u:" + " Unable to write QME_SPWU_HYP.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + + for (i = 0; i < P10_SPWU_TIMEOUT / P10_SPWU_POLL_INTERVAL; i++) { + if (xscom_read(chip_id, ssh_addr, &val)) { + prlog(PR_ERR, "Could not set special wakeup on %u:%u:" + " Unable to read QME_SSH_HYP.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + if (val & P10_SSH_SPWU_DONE) { + /* + * CORE_GATED will be unset on a successful special + * wakeup of the core which indicates that the core is + * out of stop state. If CORE_GATED is still set then + * raise error. + */ + if (p10_core_is_gated(cpu)) { + /* Deassert spwu for this strange error */ + xscom_write(chip_id, spwu_addr, 0); + prlog(PR_ERR, "Failed special wakeup on %u:%u" + " core remains gated.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } else { + return 0; + } + } + time_wait_us(P10_SPWU_POLL_INTERVAL); + } + + prlog(PR_ERR, "Could not set special wakeup on %u:%u:" + " operation timeout.\n", + chip_id, core_id); + /* + * As per the special wakeup protocol we should not de-assert + * the special wakeup on the core until WAKEUP_DONE is set. + * So even on error do not de-assert. + */ + + return OPAL_HARDWARE; +} + +static int p10_core_clear_special_wakeup(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t spwu_addr; + + spwu_addr = XSCOM_ADDR_P10_QME_CORE(core_id, P10_QME_SPWU_HYP); + + /* Add a small delay here if spwu problems time_wait_us(1); */ + if (xscom_write(chip_id, spwu_addr, 0)) { + prlog(PR_ERR, "Could not clear special wakeup on %u:%u:" + " Unable to write QME_SPWU_HYP.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + + return 0; +} + +static int p10_thread_quiesced(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t ras_addr; + uint64_t ras_status; + + ras_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_RAS_STATUS); + if (xscom_read(chip_id, ras_addr, &ras_status)) { + prlog(PR_ERR, "Could not check thread state on %u:%u:" + " Unable to read EC_RAS_STATUS.\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + + /* + * p10_thread_stop for the purpose of sreset wants QUIESCED + * and MAINT bits set. Step, RAM, etc. need more, but we don't + * use those in skiboot. + * + * P10 could try wait for more here in case of errors. + */ + if (!(ras_status & P10_THREAD_QUIESCED(thread_id))) + return 0; + + if (!(ras_status & P10_THREAD_MAINT(thread_id))) + return 0; + + return 1; +} + +static int p10_cont_thread(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t cts_addr; + uint32_t ti_addr; + uint32_t dctl_addr; + uint64_t core_thread_state; + uint64_t thread_info; + bool active, stop; + int rc; + int i; + + rc = p10_thread_quiesced(cpu); + if (rc < 0) + return rc; + if (!rc) { + prlog(PR_ERR, "Could not cont thread %u:%u:%u:" + " Thread is not quiesced.\n", + chip_id, core_id, thread_id); + return OPAL_BUSY; + } + + cts_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_CORE_THREAD_STATE); + ti_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_THREAD_INFO); + dctl_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_DIRECT_CONTROLS); + + if (xscom_read(chip_id, cts_addr, &core_thread_state)) { + prlog(PR_ERR, "Could not resume thread %u:%u:%u:" + " Unable to read EC_CORE_THREAD_STATE.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } + if (core_thread_state & P10_THREAD_STOPPED(thread_id)) + stop = true; + else + stop = false; + + if (xscom_read(chip_id, ti_addr, &thread_info)) { + prlog(PR_ERR, "Could not resume thread %u:%u:%u:" + " Unable to read EC_THREAD_INFO.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } + if (thread_info & P10_THREAD_ACTIVE(thread_id)) + active = true; + else + active = false; + + if (!active || stop) { + if (xscom_write(chip_id, dctl_addr, P10_THREAD_CLEAR_MAINT(thread_id))) { + prlog(PR_ERR, "Could not resume thread %u:%u:%u:" + " Unable to write EC_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + } + } else { + if (xscom_write(chip_id, dctl_addr, P10_THREAD_START(thread_id))) { + prlog(PR_ERR, "Could not resume thread %u:%u:%u:" + " Unable to write EC_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + } + } + + for (i = 0; i < P10_QUIESCE_TIMEOUT / P10_QUIESCE_POLL_INTERVAL; i++) { + int rc = p10_thread_quiesced(cpu); + if (rc < 0) + break; + if (!rc) + return 0; + + time_wait_us(P10_QUIESCE_POLL_INTERVAL); + } + + prlog(PR_ERR, "Could not start thread %u:%u:%u:" + " Unable to start thread.\n", + chip_id, core_id, thread_id); + + return OPAL_HARDWARE; +} + +static int p10_stop_thread(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t dctl_addr; + int rc; + int i; + + dctl_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_DIRECT_CONTROLS); + + rc = p10_thread_quiesced(cpu); + if (rc < 0) + return rc; + if (rc) { + prlog(PR_ERR, "Could not stop thread %u:%u:%u:" + " Thread is quiesced already.\n", + chip_id, core_id, thread_id); + return OPAL_BUSY; + } + + if (xscom_write(chip_id, dctl_addr, P10_THREAD_STOP(thread_id))) { + prlog(PR_ERR, "Could not stop thread %u:%u:%u:" + " Unable to write EC_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } + + for (i = 0; i < P10_QUIESCE_TIMEOUT / P10_QUIESCE_POLL_INTERVAL; i++) { + int rc = p10_thread_quiesced(cpu); + if (rc < 0) + break; + if (rc) + return 0; + + time_wait_us(P10_QUIESCE_POLL_INTERVAL); + } + + prlog(PR_ERR, "Could not stop thread %u:%u:%u:" + " Unable to quiesce thread.\n", + chip_id, core_id, thread_id); + + return OPAL_HARDWARE; +} + +static int p10_sreset_thread(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t dctl_addr; + + dctl_addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_DIRECT_CONTROLS); + + if (xscom_write(chip_id, dctl_addr, P10_THREAD_SRESET(thread_id))) { + prlog(PR_ERR, "Could not sreset thread %u:%u:%u:" + " Unable to write EC_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } + + return 0; +} + /**************** generic direct controls ****************/ int dctl_set_special_wakeup(struct cpu_thread *t) @@ -529,7 +838,9 @@ int dctl_set_special_wakeup(struct cpu_thread *t) lock(&c->dctl_lock); if (c->special_wakeup_count == 0) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + rc = p10_core_set_special_wakeup(c); + else if (proc_gen == proc_gen_p9) rc = p9_core_set_special_wakeup(c); else /* (proc_gen == proc_gen_p8) */ rc = p8_core_set_special_wakeup(c); @@ -553,7 +864,9 @@ int dctl_clear_special_wakeup(struct cpu_thread *t) if (!c->special_wakeup_count) goto out; if (c->special_wakeup_count == 1) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + rc = p10_core_clear_special_wakeup(c); + else if (proc_gen == proc_gen_p9) rc = p9_core_clear_special_wakeup(c); else /* (proc_gen == proc_gen_p8) */ rc = p8_core_clear_special_wakeup(c); @@ -569,24 +882,13 @@ out: int dctl_core_is_gated(struct cpu_thread *t) { struct cpu_thread *c = t->primary; - uint32_t chip_id = pir_to_chip_id(c->pir); - uint32_t core_id = pir_to_core_id(c->pir); - uint32_t sshhyp_addr; - uint64_t val; - if (proc_gen != proc_gen_p9) + if (proc_gen == proc_gen_p10) + return p10_core_is_gated(c); + else if (proc_gen == proc_gen_p9) + return p9_core_is_gated(c); + else return OPAL_UNSUPPORTED; - - sshhyp_addr = XSCOM_ADDR_P9_EC_SLAVE(core_id, P9_EC_PPM_SSHHYP); - - if (xscom_read(chip_id, sshhyp_addr, &val)) { - prlog(PR_ERR, "Could not query core gated on %u:%u:" - " Unable to read PPM_SSHHYP.\n", - chip_id, core_id); - return OPAL_HARDWARE; - } - - return !!(val & P9_CORE_GATED); } static int dctl_stop(struct cpu_thread *t) @@ -599,7 +901,9 @@ static int dctl_stop(struct cpu_thread *t) unlock(&c->dctl_lock); return OPAL_BUSY; } - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + rc = p10_stop_thread(t); + else if (proc_gen == proc_gen_p9) rc = p9_stop_thread(t); else /* (proc_gen == proc_gen_p8) */ rc = p8_stop_thread(t); @@ -615,7 +919,7 @@ static int dctl_cont(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p10 && proc_gen != proc_gen_p9) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); @@ -623,7 +927,10 @@ static int dctl_cont(struct cpu_thread *t) unlock(&c->dctl_lock); return OPAL_BUSY; } - rc = p9_cont_thread(t); + if (proc_gen == proc_gen_p10) + rc = p10_cont_thread(t); + else /* (proc_gen == proc_gen_p9) */ + rc = p9_cont_thread(t); if (!rc) t->dctl_stopped = false; unlock(&c->dctl_lock); @@ -647,7 +954,9 @@ static int dctl_sreset(struct cpu_thread *t) unlock(&c->dctl_lock); return OPAL_BUSY; } - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + rc = p10_sreset_thread(t); + else if (proc_gen == proc_gen_p9) rc = p9_sreset_thread(t); else /* (proc_gen == proc_gen_p8) */ rc = p8_sreset_thread(t); @@ -752,7 +1061,7 @@ int sreset_all_others(void) * Then sreset the target thread, which resumes execution on that thread. * Then de-assert special wakeup on the core. */ -static int64_t p9_sreset_cpu(struct cpu_thread *cpu) +static int64_t do_sreset_cpu(struct cpu_thread *cpu) { int rc; @@ -792,7 +1101,7 @@ int64_t opal_signal_system_reset(int cpu_nr) struct cpu_thread *cpu; int64_t ret; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p10) return OPAL_UNSUPPORTED; /* @@ -811,7 +1120,7 @@ int64_t opal_signal_system_reset(int cpu_nr) } lock(&sreset_lock); - ret = p9_sreset_cpu(cpu); + ret = do_sreset_cpu(cpu); unlock(&sreset_lock); return ret; @@ -822,7 +1131,7 @@ void direct_controls_init(void) if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) return; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p10) return; opal_register(OPAL_SIGNAL_SYSTEM_RESET, opal_signal_system_reset, 1); diff --git a/core/hmi.c b/core/hmi.c index 120fe4b57..35b609047 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ #include /* - * HMER register layout: + * P9 HMER register layout: * +===+==========+============================+========+===================+ * |Bit|Name |Description |PowerKVM|Action | * | | | |HMI | | @@ -147,6 +148,78 @@ * NOTE: Per Dave Larson, never enable 8,9,21-23 */ +/* + * P10 HMER register layout: + * Bit Name Description + * 0 malfunction_alert A processor core in the system has checkstopped + * (failed recovery). This is broadcasted to every + * processor in the system + * + * 1 reserved reserved + * + * 2 proc_rcvy_done Processor recovery occurred error-bit in fir not + * masked (see bit 11) + * + * 3 reserved reserved + * + * 4 tfac_error Timer facility experienced an error. TB, DEC, + * HDEC, PURR or SPURR may be corrupted (details in + * TFMR) + * + * 5 tfx_error Error occurred on transfer from tfac shadow to + * core + * + * 6 spurr_scale_limit Nominal frequency exceeded 399 percent + * + * 7 reserved reserved + * + * 8 xscom_fail An XSCOM operation caused by a cache inhibited + * load/store from this thread failed. A trap + * register is available. + * + * 9 xscom_done An XSCOM operation caused by a cache inhibited + * load/store from this thread completed. If + * hypervisor intends to use this bit, it is + * responsible for clearing it before performing the + * xscom operation. NOTE: this bit should always be + * masked in HMEER + * + * 10 reserved reserved + * + * 11 proc_rcvy_again Processor recovery occurred again before bit 2 + * was cleared + * + * 12-15 reserved reserved + * + * 16 scom_fir_hmi An error inject to PC FIR has occurred to set HMI. + * This error inject can also set FIR(61) to cause + * recovery. + * + * 17 reserved reserved + * + * 18 trig_fir_hmi Debug trigger has occurred to set HMI. This + * trigger can also set FIR(60) to cause recovery + * + * 19-20 reserved reserved + * + * 21-23 xscom_status If bit 8 is active, the reason will be detailed in + * these bits. These bits are information only and + * always masked (mask = ‘0’) If hypervisor intends + * to use this field, it is responsible for clearing + * it before performing the xscom operation. + * + * 24:63 Not implemented Not implemented. + * + * P10 HMEER enabled bits: + * Name Action + * malfunction_alert Decode and log FIR bits. + * proc_rcvy_done Log and continue. + * tfac_error Log and attempt to recover time facilities. + * tfx_error Log and attempt to recover time facilities. + * spurr_scale_limit Log and continue. XXX? + * proc_rcvy_again Log and continue. + */ + /* Used for tracking cpu threads inside hmi handling. */ #define HMI_STATE_CLEANUP_DONE 0x100 #define CORE_THREAD_MASK 0x0ff @@ -174,13 +247,17 @@ (SPR_TFMR_TBST_CORRUPT | SPR_TFMR_TB_MISSING_SYNC | \ SPR_TFMR_TB_MISSING_STEP | SPR_TFMR_FW_CONTROL_ERR | \ SPR_TFMR_TFMR_CORRUPT | SPR_TFMR_TB_RESIDUE_ERR | \ - SPR_TFMR_HDEC_PARITY_ERROR) + SPR_TFMR_HDEC_PARITY_ERROR | SPR_TFMR_TFAC_XFER_ERROR) /* TFMR "thread" errors */ #define SPR_TFMR_THREAD_ERRORS \ (SPR_TFMR_PURR_PARITY_ERR | SPR_TFMR_SPURR_PARITY_ERR | \ SPR_TFMR_DEC_PARITY_ERR) +/* + * Starting from p9, core inits are setup to escalate all core + * local checkstop to system checkstop. Review this list when that changes. + */ static const struct core_xstop_bit_info { uint8_t bit; /* CORE FIR bit number */ enum OpalHMI_CoreXstopReason reason; @@ -203,10 +280,12 @@ static const struct core_xstop_bit_info { { 63, CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ }, }; -static const struct core_recoverable_bit_info { +struct core_fir_bit_info { uint8_t bit; /* CORE FIR bit number */ const char *reason; -} recoverable_bits[] = { +}; + +static const struct core_fir_bit_info p9_recoverable_bits[] = { { 0, "IFU - SRAM (ICACHE parity, etc)" }, { 2, "IFU - RegFile" }, { 4, "IFU - Logic" }, @@ -226,6 +305,58 @@ static const struct core_recoverable_bit_info { { 43, "PC - Thread hang recovery" }, }; +static const struct core_fir_bit_info p10_core_fir_bits[] = { + { 0, "IFU - SRAM recoverable error (ICACHE parity error, etc.)" }, + { 1, "PC - TC checkstop" }, + { 2, "IFU - RegFile recoverable error" }, + { 3, "IFU - RegFile core checkstop" }, + { 4, "IFU - Logic recoverable error" }, + { 5, "IFU - Logic core checkstop" }, + { 7, "VSU - Inference accumulator recoverable error" }, + { 8, "PC - Recovery core checkstop" }, + { 9, "VSU - Slice Target File (STF) recoverable error" }, + { 11, "ISU - Logic recoverable error" }, + { 12, "ISU - Logic core checkstop" }, + { 14, "ISU - Machine check received while ME=0 checkstop" }, + { 15, "ISU - UE from L2" }, + { 16, "ISU - Number of UEs from L2 above threshold" }, + { 17, "ISU - UE on CI load" }, + { 18, "MMU - TLB recoverable error" }, + { 19, "MMU - SLB error" }, + { 21, "MMU - CXT recoverable error" }, + { 22, "MMU - Logic core checkstop" }, + { 23, "MMU - MMU system checkstop" }, + { 24, "VSU - Logic recoverable error" }, + { 25, "VSU - Logic core checkstop" }, + { 26, "PC - In maint mode and recovery in progress" }, + { 28, "PC - PC system checkstop" }, + { 29, "LSU - SRAM recoverable error (DCACHE parity error, etc.)" }, + { 30, "LSU - Set deleted" }, + { 31, "LSU - RegFile recoverable error" }, + { 32, "LSU - RegFile core checkstop" }, + { 33, "MMU - TLB multi hit error occurred" }, + { 34, "MMU - SLB multi hit error occurred" }, + { 35, "LSU - ERAT multi hit error occurred" }, + { 36, "PC - Forward progress error" }, + { 37, "LSU - Logic recoverable error" }, + { 38, "LSU - Logic core checkstop" }, + { 41, "LSU - System checkstop" }, + { 43, "PC - Thread hang recoverable error" }, + { 45, "PC - Logic core checkstop" }, + { 47, "PC - TimeBase facility checkstop" }, + { 52, "PC - Hang recovery failed core checkstop" }, + { 53, "PC - Core internal hang detected" }, + { 55, "PC - Nest hang detected" }, + { 56, "PC - Other core chiplet recoverable error" }, + { 57, "PC - Other core chiplet core checkstop" }, + { 58, "PC - Other core chiplet system checkstop" }, + { 59, "PC - SCOM satellite error detected" }, + { 60, "PC - Debug trigger error inject" }, + { 61, "PC - SCOM or firmware recoverable error inject" }, + { 62, "PC - Firmware checkstop error inject" }, + { 63, "PC - Firmware SPRC / SPRD checkstop" }, +}; + static const struct nx_xstop_bit_info { uint8_t bit; /* NX FIR bit number */ enum OpalHMI_NestAccelXstopReason reason; @@ -270,6 +401,12 @@ static int setup_scom_addresses(void) nx_dma_engine_fir = P9_NX_DMA_ENGINE_FIR; nx_pbi_fir = P9_NX_PBI_FIR; return 1; + case proc_gen_p10: + malf_alert_scom = P10_MALFUNC_ALERT; + nx_status_reg = P10_NX_STATUS_REG; + nx_dma_engine_fir = P10_NX_DMA_ENGINE_FIR; + nx_pbi_fir = P10_NX_PBI_FIR; + return 1; default: prerror("%s: Unknown CPU type\n", __func__); break; @@ -320,6 +457,10 @@ static int read_core_fir(uint32_t chip_id, uint32_t core_id, uint64_t *core_fir) rc = xscom_read(chip_id, XSCOM_ADDR_P9_EC(core_id, P9_CORE_FIR), core_fir); break; + case proc_gen_p10: + rc = xscom_read(chip_id, + XSCOM_ADDR_P10_EC(core_id, P10_CORE_FIR), core_fir); + break; default: rc = OPAL_HARDWARE; } @@ -335,6 +476,10 @@ static int read_core_wof(uint32_t chip_id, uint32_t core_id, uint64_t *core_wof) rc = xscom_read(chip_id, XSCOM_ADDR_P9_EC(core_id, P9_CORE_WOF), core_wof); break; + case proc_gen_p10: + rc = xscom_read(chip_id, + XSCOM_ADDR_P10_EC(core_id, P10_CORE_WOF), core_wof); + break; default: rc = OPAL_HARDWARE; } @@ -394,6 +539,13 @@ static bool decode_core_fir(struct cpu_thread *cpu, loc ? loc : "Not Available", cpu->chip_id, core_id, core_fir); + if (proc_gen == proc_gen_p10) { + for (i = 0; i < ARRAY_SIZE(p10_core_fir_bits); i++) { + if (core_fir & PPC_BIT(p10_core_fir_bits[i].bit)) + prlog(PR_INFO, " %s\n", p10_core_fir_bits[i].reason); + } + } + /* Check CORE FIR bits and populate HMI event with error info. */ for (i = 0; i < ARRAY_SIZE(xstop_bits); i++) { if (core_fir & PPC_BIT(xstop_bits[i].bit)) { @@ -910,6 +1062,7 @@ static void hmi_print_debug(const uint8_t *msg, uint64_t hmer) if (!loc) loc = "Not Available"; + /* Also covers P10 SPR_HMER_TFAC_SHADOW_XFER_ERROR */ if (hmer & (SPR_HMER_TFAC_ERROR | SPR_HMER_TFMR_PARITY_ERROR)) { prlog(PR_DEBUG, "[Loc: %s]: P:%d C:%d T:%d: TFMR(%016lx) %s\n", loc, this_cpu()->chip_id, core_id, thread_index, @@ -1231,10 +1384,16 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, int i; prlog(PR_DEBUG, "Core WOF = 0x%016llx recovered error:\n", core_wof); - for (i = 0; i < ARRAY_SIZE(recoverable_bits); i++) { - if (core_wof & PPC_BIT(recoverable_bits[i].bit)) - prlog(PR_DEBUG, "%s\n", - recoverable_bits[i].reason); + if (proc_gen <= proc_gen_p9) { + for (i = 0; i < ARRAY_SIZE(p9_recoverable_bits); i++) { + if (core_wof & PPC_BIT(p9_recoverable_bits[i].bit)) + prlog(PR_DEBUG, " %s\n", p9_recoverable_bits[i].reason); + } + } else if (proc_gen == proc_gen_p10) { + for (i = 0; i < ARRAY_SIZE(p10_core_fir_bits); i++) { + if (core_wof & PPC_BIT(p10_core_fir_bits[i].bit)) + prlog(PR_DEBUG, " %s\n", p10_core_fir_bits[i].reason); + } } } @@ -1245,7 +1404,8 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, queue_hmi_event(hmi_evt, recover, out_flags); } } - if (hmer & SPR_HMER_PROC_RECV_ERROR_MASKED) { + + if ((proc_gen <= proc_gen_p9) && (hmer & SPR_HMER_PROC_RECV_ERROR_MASKED)) { handled |= SPR_HMER_PROC_RECV_ERROR_MASKED; if (cpu_is_thread0(cpu) && hmi_evt) { hmi_evt->severity = OpalHMI_SEV_NO_ERROR; @@ -1254,6 +1414,7 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, } hmi_print_debug("Processor recovery Done (masked).", hmer); } + if (hmer & SPR_HMER_PROC_RECV_AGAIN) { handled |= SPR_HMER_PROC_RECV_AGAIN; if (cpu_is_thread0(cpu) && hmi_evt) { @@ -1264,17 +1425,30 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, hmi_print_debug("Processor recovery occurred again before" "bit2 was cleared\n", hmer); } + + /* XXX: what to do with this? */ + if (hmer & SPR_HMER_SPURR_SCALE_LIMIT) { + handled |= SPR_HMER_SPURR_SCALE_LIMIT; + if (cpu_is_thread0(cpu) && hmi_evt) { + hmi_evt->severity = OpalHMI_SEV_NO_ERROR; + hmi_evt->type = OpalHMI_ERROR_PROC_RECOV_DONE; + queue_hmi_event(hmi_evt, recover, out_flags); + } + hmi_print_debug("Turbo versus nominal frequency exceeded limit.", hmer); + } + /* Assert if we see malfunction alert, we can not continue. */ if (hmer & SPR_HMER_MALFUNCTION_ALERT) { handled |= SPR_HMER_MALFUNCTION_ALERT; hmi_print_debug("Malfunction Alert", hmer); + recover = 0; if (hmi_evt) decode_malfunction(hmi_evt, out_flags); } /* Assert if we see Hypervisor resource error, we can not continue. */ - if (hmer & SPR_HMER_HYP_RESOURCE_ERR) { + if ((proc_gen <= proc_gen_p9) && (hmer & SPR_HMER_HYP_RESOURCE_ERR)) { handled |= SPR_HMER_HYP_RESOURCE_ERR; hmi_print_debug("Hypervisor resource error", hmer); @@ -1285,7 +1459,21 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, queue_hmi_event(hmi_evt, recover, out_flags); } } - if (hmer & SPR_HMER_TRIG_FIR_HMI) { + + /* XXX: what to do with this? */ + if ((proc_gen <= proc_gen_p9) && (hmer & SPR_HMER_THD_WAKE_BLOCKED_TM_SUSPEND)) { + handled |= SPR_HMER_THD_WAKE_BLOCKED_TM_SUSPEND; + hmer &= ~SPR_HMER_THD_WAKE_BLOCKED_TM_SUSPEND; + + hmi_print_debug("Attempted to wake thread when threads in TM suspend mode.", hmer); + if (hmi_evt) { + hmi_evt->severity = OpalHMI_SEV_NO_ERROR; + hmi_evt->type = OpalHMI_ERROR_PROC_RECOV_DONE, + queue_hmi_event(hmi_evt, recover, out_flags); + } + } + + if ((proc_gen <= proc_gen_p9) && (hmer & SPR_HMER_TRIG_FIR_HMI)) { handled |= SPR_HMER_TRIG_FIR_HMI; hmer &= ~SPR_HMER_TRIG_FIR_HMI; @@ -1296,6 +1484,17 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, queue_hmi_event(hmi_evt, recover, out_flags); } } + if ((proc_gen == proc_gen_p10) && (hmer & SPR_HMER_P10_TRIG_FIR_HMI)) { + handled |= SPR_HMER_P10_TRIG_FIR_HMI; + hmer &= ~SPR_HMER_P10_TRIG_FIR_HMI; + + hmi_print_debug("Clearing unknown debug trigger", hmer); + if (hmi_evt) { + hmi_evt->severity = OpalHMI_SEV_NO_ERROR; + hmi_evt->type = OpalHMI_ERROR_DEBUG_TRIG_FIR, + queue_hmi_event(hmi_evt, recover, out_flags); + } + } if (recover == 0) disable_fast_reboot("Unrecoverable HMI"); diff --git a/core/init.c b/core/init.c index 09749f475..65f136daa 100644 --- a/core/init.c +++ b/core/init.c @@ -1167,7 +1167,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Initialize the rest of the cpu thread structs */ init_all_cpus(); - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) cpu_set_ipi_enable(true); /* Add the /opal node to the device-tree */ diff --git a/core/mce.c b/core/mce.c index 3f5091628..47674abcb 100644 --- a/core/mce.c +++ b/core/mce.c @@ -65,6 +65,42 @@ static const struct mce_ierror_table mce_p9_ierror_table[] = { "instruction fetch page table access to foreign address", }, { 0 } }; +static const struct mce_ierror_table mce_p10_ierror_table[] = { +{ 0x00000000081c0000, 0x0000000000040000, + MCE_INSNFETCH | MCE_MEMORY_ERROR | MCE_INVOLVED_EA, + "instruction fetch memory uncorrectable error", }, +{ 0x00000000081c0000, 0x0000000000080000, + MCE_INSNFETCH | MCE_SLB_ERROR | MCE_INVOLVED_EA, + "instruction fetch SLB parity error", }, +{ 0x00000000081c0000, 0x00000000000c0000, + MCE_INSNFETCH | MCE_SLB_ERROR | MCE_INVOLVED_EA, + "instruction fetch SLB multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000100000, + MCE_INSNFETCH | MCE_INVOLVED_EA | MCE_ERAT_ERROR, + "instruction fetch ERAT multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000140000, + MCE_INSNFETCH | MCE_INVOLVED_EA | MCE_TLB_ERROR, + "instruction fetch TLB multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000180000, + MCE_INSNFETCH | MCE_MEMORY_ERROR | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access memory uncorrectable error", }, +{ 0x00000000081c0000, 0x00000000001c0000, + MCE_INSNFETCH | MCE_INVOLVED_EA, + "instruction fetch to control real address", }, +{ 0x00000000081c0000, 0x00000000080c0000, + MCE_INSNFETCH | MCE_INVOLVED_EA, + "instruction fetch real address error", }, +{ 0x00000000081c0000, 0x0000000008100000, + MCE_INSNFETCH | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access real address error", }, +{ 0x00000000081c0000, 0x0000000008140000, + MCE_LOADSTORE | MCE_IMPRECISE, + "store real address asynchronous error", }, +{ 0x00000000081c0000, 0x00000000081c0000, + MCE_INSNFETCH | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access to control real address", }, +{ 0 } }; + struct mce_derror_table { unsigned long dsisr_value; uint64_t type; @@ -113,6 +149,42 @@ static const struct mce_derror_table mce_p9_derror_table[] = { "load/store to foreign address", }, { 0 } }; +static const struct mce_derror_table mce_p10_derror_table[] = { +{ 0x00008000, + MCE_LOADSTORE | MCE_MEMORY_ERROR, + "load/store memory uncorrectable error", }, +{ 0x00004000, + MCE_LOADSTORE | MCE_MEMORY_ERROR | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "load/store page table access memory uncorrectable error", }, +{ 0x00000800, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_ERAT_ERROR, + "load/store ERAT multi-hit error", }, +{ 0x00000400, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_TLB_ERROR, + "load/store TLB multi-hit error", }, +{ 0x00000200, + MCE_TLBIE_ERROR, + "TLBIE or TLBIEL instruction programming error", }, +{ 0x00000100, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_SLB_ERROR, + "load/store SLB parity error", }, +{ 0x00000080, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_SLB_ERROR, + "load/store SLB multi-hit error", }, +{ 0x00000040, + MCE_LOADSTORE | MCE_INVOLVED_EA, + "load real address error", }, +{ 0x00000020, + MCE_LOADSTORE | MCE_TABLE_WALK, + "load/store page table access real address error", }, +{ 0x00000010, + MCE_LOADSTORE | MCE_TABLE_WALK, + "load/store page table access to control real address", }, +{ 0x00000008, + MCE_LOADSTORE, + "load/store to control real address", }, +{ 0 } }; + static void decode_ierror(const struct mce_ierror_table table[], uint64_t srr1, uint64_t *type, @@ -145,20 +217,11 @@ static void decode_derror(const struct mce_derror_table table[], } } -void decode_mce(uint64_t srr0, uint64_t srr1, +static void decode_mce_p9(uint64_t srr0, uint64_t srr1, uint32_t dsisr, uint64_t dar, uint64_t *type, const char **error_str, uint64_t *address) { - *type = MCE_UNKNOWN; - *error_str = "unknown error"; - *address = 0; - - if (proc_gen != proc_gen_p9) { - *error_str = "unknown error (processor not supported)"; - return; - } - /* * On POWER9 DD2.1 and below, it's possible to get a machine check * caused by a paste instruction where only DSISR bit 25 is set. This @@ -198,3 +261,49 @@ void decode_mce(uint64_t srr0, uint64_t srr1, *address = srr0; } } + +static void decode_mce_p10(uint64_t srr0, uint64_t srr1, + uint32_t dsisr, uint64_t dar, + uint64_t *type, const char **error_str, + uint64_t *address) +{ + /* + * Async machine check due to bad real address from store or foreign + * link time out comes with the load/store bit (PPC bit 42) set in + * SRR1, but the cause comes in SRR1 not DSISR. Clear bit 42 so we're + * directed to the ierror table so it will find the cause (which + * describes it correctly as a store error). + */ + if (SRR1_MC_LOADSTORE(srr1) && + (srr1 & 0x081c0000) == 0x08140000) { + srr1 &= ~PPC_BIT(42); + } + + if (SRR1_MC_LOADSTORE(srr1)) { + decode_derror(mce_p10_derror_table, dsisr, type, error_str); + if (*type & MCE_INVOLVED_EA) + *address = dar; + } else { + decode_ierror(mce_p10_ierror_table, srr1, type, error_str); + if (*type & MCE_INVOLVED_EA) + *address = srr0; + } +} + +void decode_mce(uint64_t srr0, uint64_t srr1, + uint32_t dsisr, uint64_t dar, + uint64_t *type, const char **error_str, + uint64_t *address) +{ + *type = MCE_UNKNOWN; + *error_str = "unknown error"; + *address = 0; + + if (proc_gen == proc_gen_p9) { + decode_mce_p9(srr0, srr1, dsisr, dar, type, error_str, address); + } else if (proc_gen == proc_gen_p10) { + decode_mce_p10(srr0, srr1, dsisr, dar, type, error_str, address); + } else { + *error_str = "unknown error (processor not supported)"; + } +} diff --git a/core/test/run-timer.c b/core/test/run-timer.c index fef5648d7..8f8b20ed3 100644 --- a/core/test/run-timer.c +++ b/core/test/run-timer.c @@ -16,7 +16,7 @@ #define smt_lowest() #define smt_medium() -enum proc_gen proc_gen = proc_gen_p9; +enum proc_gen proc_gen = proc_gen_unknown; static uint64_t stamp, last; struct lock; diff --git a/doc/platforms-and-cpus.rst b/doc/platforms-and-cpus.rst index 658e00ed0..2f5e9436f 100644 --- a/doc/platforms-and-cpus.rst +++ b/doc/platforms-and-cpus.rst @@ -17,6 +17,7 @@ Power9N 0x004e1xxx Nimbus 24 small core Power9C 0x004e2xxx Cumulus 12 small core Power9C 0x004e3xxx Cumulus 24 small core Power9P 0x004fxxxx Axone +Power10 0x0080xxxx =============== =============== ===================== Platforms diff --git a/hw/chiptod.c b/hw/chiptod.c index f445fd49a..4e62fd714 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -959,6 +959,30 @@ bool chiptod_wakeup_resync(void) return false; } +/* + * Fixup for p10 TOD bug workaround. + * + * The TOD may fail to start if all clocks in the system are derived from + * the same reference oscillator. + * + * Avoiding this is pretty easy: Whenever we clear/reset the TOD registers, + * make sure to init bits 26:31 of TOD_SLAVE_PATH_CTRL (0x40005) to 0b111111 + * instead of 0b000000. The value 0 in TOD_S_PATH_CTRL_REG(26:31) must be + * avoided, and if it does get written it must be followed up by writing a + * value of all ones to clean up the resulting bad state before the (nonzero) + * final value can be written. + */ +static void fixup_tod_reg_value(struct chiptod_tod_regs *treg_entry) +{ + int32_t chip_id = this_cpu()->chip_id; + + if (proc_gen != proc_gen_p10) + return; + + if (treg_entry->xscom_addr == TOD_SLAVE_PATH_CTRL) + treg_entry->val[chip_id].data |= PPC_BITMASK(26,31); +} + static int __chiptod_recover_tod_errors(void) { uint64_t terr; @@ -997,8 +1021,12 @@ static int __chiptod_recover_tod_errors(void) return 0; } + fixup_tod_reg_value(&chiptod_tod_regs[i]); + prlog(PR_DEBUG, "Parity error, Restoring TOD register: " - "%08llx\n", chiptod_tod_regs[i].xscom_addr); + "%08llx = %016llx\n", + chiptod_tod_regs[i].xscom_addr, + chiptod_tod_regs[i].val[chip_id].data); if (xscom_writeme(chiptod_tod_regs[i].xscom_addr, chiptod_tod_regs[i].val[chip_id].data)) { prerror("XSCOM error writing 0x%08llx reg.\n", diff --git a/hw/dts.c b/hw/dts.c index b72516ab2..d8831e4d3 100644 --- a/hw/dts.c +++ b/hw/dts.c @@ -171,7 +171,11 @@ static void dts_async_read_temp(struct timer *t __unused, void *data, swkup_rc = dctl_set_special_wakeup(cpu); - rc = dts_read_core_temp_p9(cpu->pir, &dts); + if (proc_gen == proc_gen_p9) + rc = dts_read_core_temp_p9(cpu->pir, &dts); + else /* (proc_gen == proc_gen_p10) */ + rc = OPAL_UNSUPPORTED; /* XXX P10 */ + if (!rc) { if (cpu->sensor_attr == SENSOR_DTS_ATTR_TEMP_MAX) *cpu->sensor_data = cpu_to_be64(dts.temp); @@ -219,6 +223,7 @@ static int dts_read_core_temp(u32 pir, struct dts *dts, u8 attr, rc = OPAL_ASYNC_COMPLETION; unlock(&cpu->dts_lock); break; + case proc_gen_p10: /* XXX P10 */ default: rc = OPAL_UNSUPPORTED; } diff --git a/hw/lpc.c b/hw/lpc.c index c2a07a0db..bf3ab1fae 100644 --- a/hw/lpc.c +++ b/hw/lpc.c @@ -915,7 +915,8 @@ void lpc_finalize_interrupts(void) if (chip->lpc && chip->psi && (chip->type == PROC_CHIP_P9_NIMBUS || chip->type == PROC_CHIP_P9_CUMULUS || - chip->type == PROC_CHIP_P9P)) + chip->type == PROC_CHIP_P9P || + chip->type == PROC_CHIP_P10)) lpc_create_int_map(chip->lpc, chip->psi->node); } } @@ -959,6 +960,7 @@ static void lpc_init_interrupts_one(struct proc_chip *chip) case PROC_CHIP_P9_NIMBUS: case PROC_CHIP_P9_CUMULUS: case PROC_CHIP_P9P: + case PROC_CHIP_P10: /* On P9, we additionally setup the routing. */ lpc->has_serirq = true; for (i = 0; i < LPC_NUM_SERIRQ; i++) { @@ -1377,7 +1379,8 @@ void lpc_register_client(uint32_t chip_id, has_routes = chip->type == PROC_CHIP_P9_NIMBUS || chip->type == PROC_CHIP_P9_CUMULUS || - chip->type == PROC_CHIP_P9P; + chip->type == PROC_CHIP_P9P || + chip->type == PROC_CHIP_P10; if (policy != IRQ_ATTR_TARGET_OPAL && !has_routes) { prerror("Chip doesn't support OS interrupt policy\n"); diff --git a/hw/xscom.c b/hw/xscom.c index c97740a62..347457242 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -94,7 +94,11 @@ static void xscom_reset(uint32_t gcid, bool need_delay) mtspr(SPR_HMER, HMER_CLR_MASK); /* Setup local and target scom addresses */ - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + recv_status_reg = 0x00090018; + log_reg = 0x0090012; + err_reg = 0x0090013; + } else if (proc_gen == proc_gen_p9) { recv_status_reg = 0x00090018; log_reg = 0x0090012; err_reg = 0x0090013; @@ -497,7 +501,7 @@ static int xscom_indirect_read(uint32_t gcid, uint64_t pcb_addr, uint64_t *val) { uint64_t form = xscom_indirect_form(pcb_addr); - if ((proc_gen == proc_gen_p9) && (form == 1)) + if ((proc_gen >= proc_gen_p9) && (form == 1)) return OPAL_UNSUPPORTED; return xscom_indirect_read_form0(gcid, pcb_addr, val); @@ -565,7 +569,7 @@ static int xscom_indirect_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val) { uint64_t form = xscom_indirect_form(pcb_addr); - if ((proc_gen == proc_gen_p9) && (form == 1)) + if ((proc_gen >= proc_gen_p9) && (form == 1)) return xscom_indirect_write_form1(gcid, pcb_addr, val); return xscom_indirect_write_form0(gcid, pcb_addr, val); @@ -576,7 +580,7 @@ static uint32_t xscom_decode_chiplet(uint32_t partid, uint64_t *pcb_addr) uint32_t gcid = (partid & 0x0fffffff) >> 4; uint32_t core = partid & 0xf; - if (proc_gen == proc_gen_p9) { + if (proc_gen >= proc_gen_p9) { /* XXX Not supported */ *pcb_addr = 0; } else { @@ -821,7 +825,9 @@ int64_t xscom_read_cfam_chipid(uint32_t partid, uint32_t *chip_id) * something up */ if (chip_quirk(QUIRK_NO_F000F)) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p10) + val = 0x120DA04980000000UL; /* P10 DD1.0 */ + else if (proc_gen == proc_gen_p9) val = 0x203D104980000000UL; /* P9 Nimbus DD2.3 */ else val = 0x221EF04980000000UL; /* P8 Murano DD2.1 */ @@ -873,6 +879,10 @@ static void xscom_init_chip_info(struct proc_chip *chip) chip->type = PROC_CHIP_P9P; assert(proc_gen == proc_gen_p9); break; + case 0xda: + chip->type = PROC_CHIP_P10; + assert(proc_gen == proc_gen_p10); + break; default: printf("CHIP: Unknown chip type 0x%02x !!!\n", (unsigned char)(val & 0xff)); @@ -911,7 +921,7 @@ static void xscom_init_chip_info(struct proc_chip *chip) prlog(PR_INFO,"P9 DD%i.%i%d detected\n", 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf, rev); chip->ec_rev = rev; - } + } /* XXX P10 */ } /* @@ -949,7 +959,8 @@ void xscom_init(void) struct proc_chip *chip; const char *chip_name; static const char *chip_names[] = { - "UNKNOWN", "P8E", "P8", "P8NVL", "P9N", "P9C", "P9P" + "UNKNOWN", "P8E", "P8", "P8NVL", "P9N", "P9C", "P9P", + "P10", }; chip = get_chip(gcid); diff --git a/include/chip.h b/include/chip.h index 4deb96182..8bc48ba29 100644 --- a/include/chip.h +++ b/include/chip.h @@ -100,10 +100,58 @@ #define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) +#define P10_PIR2FUSEDCOREID(pir) P9_PIR2FUSEDCOREID(pir) +#define P10_PIRFUSED2NORMALCOREID(pir) P9_PIRFUSED2NORMALCOREID(pir) +#define P10_PIRFUSED2NORMALTHREADID(pir) P9_PIRFUSED2NORMALTHREADID(pir) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) +/* + * P10 PIR + * ------- + * + * PIR layout: + * + * | 49| 50| 51| 52| 53| 54| 55| 56| 57| 58| 59| 60| 61| 62| 63| + * |Spare ID |Topology ID |Sp. |Quad ID |Core ID |Thread ID| + * + * Bit 56 is a spare quad ID. In big-core mode, thread ID extends to bit 61. + * + * P10 GCID + * -------- + * + * - Global chip ID is also called Topology ID. + * - Node ID is called Group ID (? XXX P10). + * + * Global chip ID is a 4 bit number. + * + * There is a topology mode bit that can be 0 or 1, which changes GCID mapping. + * + * Topology mode 0: + * NodeID ChipID + * | | | + * |____|____|____|____| + * + * Topology mode 1: + * NodeID ChipID + * | | | + * |____|____|____|____| + */ +#define P10_PIR2GCID(pir) (((pir) >> 8) & 0xf) + +#define P10_PIR2COREID(pir) (((pir) >> 2) & 0x3f) + +#define P10_PIR2THREADID(pir) ((pir) & 0x3) + +// XXX P10 These depend on the topology mode, how to get that (system type?) +#define P10_GCID2NODEID(gcid, mode) ((mode) == 0 ? ((gcid) >> 1) & 0x7 : ((gcid) >> 2) & 0x3) +#define P10_GCID2CHIPID(gcid, mode) ((mode) == 0 ? (gcid) & 0x1 : (gcid) & 0x3) + +/* P10 specific ones mostly used by XIVE */ +#define P10_PIR2LOCALCPU(pir) ((pir) & 0xff) +#define P10_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) struct dt_node; struct centaur_chip; @@ -123,6 +171,7 @@ enum proc_chip_type { PROC_CHIP_P9_NIMBUS, PROC_CHIP_P9_CUMULUS, PROC_CHIP_P9P, + PROC_CHIP_P10, }; /* Simulator quirks */ diff --git a/include/opal-api.h b/include/opal-api.h index e90cab1e9..9cba35c7d 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -731,6 +731,7 @@ enum OpalHMI_CoreXstopReason { CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000, CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000, CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000, + CORE_CHECKSTOP_MMU_SYSTEM = 0x00020000, }; enum OpalHMI_NestAccelXstopReason { diff --git a/include/processor.h b/include/processor.h index 70e749f1a..973d7e77b 100644 --- a/include/processor.h +++ b/include/processor.h @@ -27,6 +27,7 @@ #define MSR_LE PPC_BIT(63) /* Little Endian */ /* PIR */ +#define SPR_PIR_P10_MASK 0x7fff /* Mask of implemented bits */ #define SPR_PIR_P9_MASK 0x7fff /* Mask of implemented bits */ #define SPR_PIR_P8_MASK 0x1fff /* Mask of implemented bits */ @@ -114,6 +115,7 @@ #define SPR_TFMR_MOVE_CHIP_TOD_TO_TB PPC_BIT(18) #define SPR_TFMR_CLEAR_TB_ERRORS PPC_BIT(24) /* Bits in TFMR - thread indep. status bits */ +#define SPR_TFMR_TFAC_XFER_ERROR PPC_BIT(25) #define SPR_TFMR_HDEC_PARITY_ERROR PPC_BIT(26) #define SPR_TFMR_TBST_CORRUPT PPC_BIT(27) #define SPR_TFMR_TBST_ENCODED PPC_BITMASK(28,31) @@ -140,17 +142,21 @@ /* Bits in HMER/HMEER */ #define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) #define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) -#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) +#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) /* Not P10 */ #define SPR_HMER_TFAC_ERROR PPC_BIT(4) -#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) +#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) /* P9 */ +#define SPR_HMER_TFAC_SHADOW_XFER_ERROR PPC_BIT(5) /* P10 */ +#define SPR_HMER_SPURR_SCALE_LIMIT PPC_BIT(6) /* P10 */ #define SPR_HMER_XSCOM_FAIL PPC_BIT(8) #define SPR_HMER_XSCOM_DONE PPC_BIT(9) #define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) -#define SPR_HMER_WARN_RISE PPC_BIT(14) -#define SPR_HMER_WARN_FALL PPC_BIT(15) +#define SPR_HMER_WARN_RISE PPC_BIT(14) /* Not P10 */ +#define SPR_HMER_WARN_FALL PPC_BIT(15) /* Not P10 */ #define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) -#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) -#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) +#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) /* Not P10 */ +#define SPR_HMER_THD_WAKE_BLOCKED_TM_SUSPEND PPC_BIT(17) /* Not P10 */ +#define SPR_HMER_P10_TRIG_FIR_HMI PPC_BIT(18) +#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) /* Not P10 */ #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) /* @@ -165,14 +171,23 @@ SPR_HMER_TFMR_PARITY_ERROR |\ SPR_HMER_PROC_RECV_AGAIN) +#define SPR_HMEER_P10_HMI_ENABLE_MASK (SPR_HMER_MALFUNCTION_ALERT |\ + SPR_HMER_PROC_RECV_DONE |\ + SPR_HMER_TFAC_ERROR |\ + SPR_HMER_TFAC_SHADOW_XFER_ERROR |\ + SPR_HMER_SPURR_SCALE_LIMIT |\ + SPR_HMER_PROC_RECV_AGAIN) + /* Bits in HID0 */ #define SPR_HID0_POWER8_4LPARMODE PPC_BIT(2) #define SPR_HID0_POWER8_2LPARMODE PPC_BIT(6) #define SPR_HID0_POWER8_DYNLPARDIS PPC_BIT(15) #define SPR_HID0_POWER8_HILE PPC_BIT(19) #define SPR_HID0_POWER9_HILE PPC_BIT(4) +#define SPR_HID0_POWER10_HILE PPC_BIT(4) #define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31) #define SPR_HID0_POWER9_ENABLE_ATTN (PPC_BIT(2) | PPC_BIT(3)) +#define SPR_HID0_POWER10_ENABLE_ATTN (PPC_BIT(2) | PPC_BIT(3)) #define SPR_HID0_POWER9_RADIX PPC_BIT(8) /* PVR bits */ @@ -192,6 +207,7 @@ #define PVR_TYPE_P8NVL 0x004c /* Naples */ #define PVR_TYPE_P9 0x004e #define PVR_TYPE_P9P 0x004f /* Axone */ +#define PVR_TYPE_P10 0x0080 #ifdef __ASSEMBLY__ @@ -236,16 +252,22 @@ static inline bool is_power9n(uint32_t version) static inline bool is_fused_core(uint32_t version) { - if (PVR_TYPE(version) != PVR_TYPE_P9) - return false; - - switch(PVR_CHIP_TYPE(version)) { - case 0: - case 2: - return true; - default: + if (PVR_TYPE(version) == PVR_TYPE_P9) { + switch(PVR_CHIP_TYPE(version)) { + case 0: + case 2: + return true; + default: + return false; + } + + } else if(PVR_TYPE(version) == PVR_TYPE_P10) { + if(PVR_CHIP_TYPE(version) & 0x01) return false; - } + else + return true; + } else + return false; } static inline bool is_power9c(uint32_t version) diff --git a/include/skiboot.h b/include/skiboot.h index d33c02506..f3378ec28 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -97,6 +97,7 @@ enum proc_gen { proc_gen_unknown, proc_gen_p8, proc_gen_p9, + proc_gen_p10, }; extern enum proc_gen proc_gen; diff --git a/include/xscom-p10-regs.h b/include/xscom-p10-regs.h new file mode 100644 index 000000000..8096b2f91 --- /dev/null +++ b/include/xscom-p10-regs.h @@ -0,0 +1,54 @@ +#ifndef __XSCOM_P10_REGS_H__ +#define __XSCOM_P10_REGS_H__ + +/* Core FIR (Fault Isolation Register) */ +#define P10_CORE_FIR 0x440 + +/* Core WOF (Whose On First) */ +#define P10_CORE_WOF 0x448 + +#define P10_MALFUNC_ALERT 0x00090022 + +#define P10_NX_STATUS_REG 0x02011040 /* NX status register */ +#define P10_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */ +#define P10_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */ + +#define P10_EC_CORE_THREAD_STATE 0x412 /* XXX P10 is this right? */ +#define P10_THREAD_STOPPED(t) PPC_BIT(56 + (t)) + +#define P10_EC_THREAD_INFO 0x413 +#define P10_THREAD_ACTIVE(t) PPC_BIT(t) + +#define P10_EC_RAS_STATUS 0x454 +#define P10_THREAD_MAINT(t) PPC_BIT(0 + 8*(t)) +#define P10_THREAD_QUIESCED(t) PPC_BIT(1 + 8*(t)) +#define P10_THREAD_ICT_EMPTY(t) PPC_BIT(2 + 8*(t)) + +#define P10_EC_DIRECT_CONTROLS 0x449 +#define P10_THREAD_STOP(t) PPC_BIT(7 + 8*(t)) +#define P10_THREAD_START(t) PPC_BIT(6 + 8*(t)) +#define P10_THREAD_SRESET(t) PPC_BIT(4 + 8*(t)) +#define P10_THREAD_CLEAR_MAINT(t) PPC_BIT(3 + 8*(t)) +#define P10_THREAD_PWR(t) PPC_BIT(32 + 8*(t)) + +#define P10_QME_FIR 0x000 + +#define P10_QME_SPWU_HYP 0x83c +#define P10_SPWU_REQ PPC_BIT(0) +#define P10_SPWU_DONE PPC_BIT(4) + +#define P10_QME_SSH_HYP 0x82c +#define P10_SSH_CORE_GATED PPC_BIT(0) +#define P10_SSH_SPWU_DONE PPC_BIT(1) + +#define P10_NCU_STATUS_REG 0x64f +#define P10_NCU_SPEC_BAR 0x650 +#define P10_NCU_SPEC_BAR_ENABLE PPC_BIT(0) +#define P10_NCU_SPEC_BAR_256K PPC_BIT(1) +#define P10_NCU_SPEC_BAR_ADDRMSK 0x000fffffffffc000ull /* 16k aligned */ + +#define P10_NCU_DARN_BAR 0x651 +#define P10_NCU_DARN_BAR_EN PPC_BIT(0) +#define P10_NCU_DARN_BAR_ADDRMSK 0x000ffffffffff000ull /* 4k aligned */ + +#endif /* __XSCOM_P10_REGS_H__ */ diff --git a/include/xscom.h b/include/xscom.h index db6d3fcd6..a6bb7e400 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -137,6 +137,91 @@ #define XSCOM_ADDR_P9_EC_SLAVE(core, addr) \ XSCOM_ADDR_P9_EC(core, (addr) | 0xf0000) +/* + * Additional useful definitions for P10 + */ + +/* + * POWER10 pervasive structure + * Chip has 8 EQ chiplets (aka super-chiplets), and other nest chiplets. + * Each EQ contains 4 EX regions. + * Each EX contains an ECL2, L3, MMA. + * Each ECL2 contains an EC (core), L2, and NCU. + * + * Each EQ has a Quad Management Engine (QME), responsible for power management + * for the cores, among other things. + * + * POWER10 XSCOM address format: + * + * | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|16-31| + * MC=0 |WR|MC|SLAVE ADDR |PIB MASTER |PORT NUMBER|LOCAL| + * MC=1 |WR|MC|MC TYPE |MC GROUP|PIB MASTER |PORT NUMBER|LOCAL| + * + * * Port is also known as PSCOM endpoint. + * + * WR is set by the xscom access functions (XSCOM_DATA_IND_READ bit) + * MC is always 0 (skiboot does not use multicast scoms). + * + * For unicast: + * EQ0-7 is addressed from 0x20 to 0x27 in the top 8 bits. + * L3 is on port 1 + * NCU is on port 1 + * ECL2 (core+L2) is on port 2 (XXX P10 scoms html doc suggests port 1?) + * QME is on port E. + * + * EQ chiplets (aka super chiplet) local address format: + * + * | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15| + * |C0|C1|C2|C3|RING ID |SAT ID |REGISTER ID | + * + * EX0-4 are selected with one-hot encoding (C0-3) + * + * QME per-core register access address format: + * | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15| + * |C0|C1|C2|C3| 1| 0| 0| 0|PER-CORE REGISTER ID | + * + * NCU - ring 6 (port 1) + * L3 - ring 3 (port 1) (XXX P10 scoms html doc suggests ring 6) + * L2 - ring 0 (port 2) (XXX P10 scoms html doc suggests ring 4) + * EC (PC unit) - rings 2-5 (port 2) + * + * Other chiplets: + * + * | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15| + * | 1|RING ID |SAT ID |REGISTER ID | + */ + +#define P10_CORE_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) +#define P10_CORE_PROC(core) ((core) & 0x3) + +#define XSCOM_P10_EQ(chiplet) ((chiplet) << 24) + +#define XSCOM_P10_QME(chiplet) \ + (XSCOM_P10_EQ(chiplet) | (0xE << 16)) + +#define XSCOM_P10_QME_CORE(chiplet, proc) \ + (XSCOM_P10_QME(chiplet) | ((1 << (3 - proc)) << 12)) + +#define XSCOM_P10_EC(chiplet, proc) \ + (XSCOM_P10_EQ(chiplet) | (0x2 << 16) | ((1 << (3 - proc)) << 12)) + +#define XSCOM_P10_NCU(chiplet, proc) \ + (XSCOM_P10_EQ(chiplet) | (0x1 << 16) | ((1 << (3 - proc)) << 12)) + +#define XSCOM_ADDR_P10_EQ(core, addr) \ + (XSCOM_P10_EQ(P10_CORE_EQ_CHIPLET(core)) | (addr)) + +#define XSCOM_ADDR_P10_QME(core, addr) \ + (XSCOM_P10_QME(P10_CORE_EQ_CHIPLET(core)) | (addr)) + +#define XSCOM_ADDR_P10_QME_CORE(core, addr) \ + (XSCOM_P10_QME_CORE(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr)) + +#define XSCOM_ADDR_P10_EC(core, addr) \ + (XSCOM_P10_EC(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr)) + +#define XSCOM_ADDR_P10_NCU(core, addr) \ + (XSCOM_P10_NCU(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr)) /* Definitions relating to indirect XSCOMs shared with centaur */ #define XSCOM_ADDR_IND_FLAG PPC_BIT(0) From patchwork Wed Aug 4 07:20:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513201 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=g8IR4yZf; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gfjqm192mz9sT6 for ; Wed, 4 Aug 2021 17:22:28 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org 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(d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747J9ls48497128 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:19:09 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 17F29AE059; Wed, 4 Aug 2021 07:22:07 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C4B54AE045; Wed, 4 Aug 2021 07:22:05 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:05 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:41 +0530 Message-Id: <20210804072137.1147875-4-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 0ukycPwLXdfeq7JLDMnuVGGStuM2MFkm X-Proofpoint-GUID: mziiOzQDmY1gai_FvS1mUmtURjwzzhGk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=705 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 03/59] hw/p8-i2c: Add POWER10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Early P8s didn't have the I2C interrupt, but all the subsequent chips have one. Flip the interrupt support checking so the old chips are the special case rather than having to add a new entry for every new chip. P10 added several additional flag registers and moved the existing flag register. The actual data bits have not changed so the existing handshake protocol between the OCC and OPAL works just fine. Signed-off-by: Oliver O'Halloran Signed-off-by: Vasant Hegde --- hw/p8-i2c.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 6e24c3e82..45815858e 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -315,21 +315,15 @@ static bool p8_i2c_has_irqs(struct p8_i2c_master *master) * DD2.0. When operating without interrupts, we need to bump the * timeouts as we rely solely on the polls from Linux which can * be up to 2s apart ! - * - * Also we don't have interrupts for the Centaur i2c. */ - switch (chip->type) { - case PROC_CHIP_P8_MURANO: + if (proc_gen >= proc_gen_p9) + return true; + else if (chip->type == PROC_CHIP_P8_MURANO) return chip->ec_level >= 0x21; - case PROC_CHIP_P8_VENICE: + else if (chip->type == PROC_CHIP_P8_VENICE) return chip->ec_level >= 0x20; - case PROC_CHIP_P8_NAPLES: - case PROC_CHIP_P9_NIMBUS: - case PROC_CHIP_P9_CUMULUS: - return true; - default: - return false; - } + + return true; } static int p8_i2c_enable_irqs(struct p8_i2c_master *master) @@ -928,8 +922,8 @@ static int p8_i2c_check_initial_status(struct p8_i2c_master_port *port) */ static bool occ_uses_master(struct p8_i2c_master *master) { - /* OCC uses I2CM Engines 1,2 and 3, only on POWER9 */ - if (master->type == I2C_POWER8 && proc_gen == proc_gen_p9) + /* OCC uses I2CM Engines 1,2 and 3, only on POWER9/10 */ + if (master->type == I2C_POWER8 && proc_gen >= proc_gen_p9) return master->engine_id >= 1; return false; @@ -1591,7 +1585,12 @@ void p8_i2c_init(void) int i; /* setup the handshake reg */ - occflg = 0x6C08A; + if (proc_gen <= proc_gen_p9) + occflg = 0x6C08A; + else if (proc_gen == proc_gen_p10) + occflg = 0x6C0AC; + else + return; prlog(PR_INFO, "I2C: OCC flag reg: %x\n", occflg); From patchwork Wed Aug 4 07:20:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=fIQr8yKt; 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Wed, 4 Aug 2021 07:22:07 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:07 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:42 +0530 Message-Id: <20210804072137.1147875-5-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2Ut-edU8GgD-ZTdLECVNO6gMAkWKKl1p X-Proofpoint-ORIG-GUID: 2Ut-edU8GgD-ZTdLECVNO6gMAkWKKl1p X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 04/59] p10: Workaround core recovery issue X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Michael Neuling This works around a core recovery issue in P10. The workaround involves the CME polling for a core recovery and performing the recovery procedure itself. For this to happen, the host leaves core recovery off (HID[5]) and then masks the PC system checkstop. This patch does this. Firmware starts skiboot with recovery already off, so we just leave it off for longer and then mask the PC system checkstop. This makes the window longer where a core recovery can cause an xstop but this window is still small and can still only happens on boot. Signed-off-by: Michael Neuling [Added mambo check - Vasant] Signed-off-by: Vasant Hegde --- asm/head.S | 4 ++-- core/init.c | 36 ++++++++++++++++++++++++++++++++++++ include/xscom-p10-regs.h | 2 ++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/asm/head.S b/asm/head.S index f85b0fe29..fa8933b14 100644 --- a/asm/head.S +++ b/asm/head.S @@ -828,9 +828,9 @@ init_shared_sprs: /* HID0: * Boot with PPC_BIT(5) set (dis_recovery). - * Clear bit 5 to enable recovery. + * Leave bit 5 set to disable recovery (due to HW570622) */ - LOAD_IMM64(%r3, 0) + LOAD_IMM64(%r3, PPC_BIT(5)) sync mtspr SPR_HID0,%r3 isync diff --git a/core/init.c b/core/init.c index 65f136daa..0bf4ab269 100644 --- a/core/init.c +++ b/core/init.c @@ -47,6 +47,7 @@ #include #include #include +#include enum proc_gen proc_gen; unsigned int pcie_max_link_speed; @@ -989,6 +990,38 @@ bool verify_romem(void) return true; } +static void mask_pc_system_xstop(void) +{ + struct cpu_thread *cpu; + uint32_t chip_id, core_id; + int rc; + + if (proc_gen != proc_gen_p10) + return; + + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return; + + /* + * On P10 Mask PC system checkstop (bit 28). This is needed + * for HW570622. We keep processor recovery disabled via + * HID[5] and mask the checkstop that it can cause. CME does + * the recovery handling for us. + */ + for_each_cpu(cpu) { + chip_id = cpu->chip_id; + core_id = pir_to_core_id(cpu->pir); + + rc = xscom_write(chip_id, + XSCOM_ADDR_P10_EC(core_id, P10_CORE_FIRMASK_OR), + PPC_BIT(28)); + if (rc) + prerror("Error setting FIR MASK rc:%d on PIR:%x\n", + rc, cpu->pir); + } +} + + /* Called from head.S, thus no prototype. */ void __noreturn __nomcount main_cpu_entry(const void *fdt); @@ -1170,6 +1203,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) cpu_set_ipi_enable(true); + /* Once all CPU are up apply this workaround */ + mask_pc_system_xstop(); + /* Add the /opal node to the device-tree */ add_opal_node(); diff --git a/include/xscom-p10-regs.h b/include/xscom-p10-regs.h index 8096b2f91..6045152d2 100644 --- a/include/xscom-p10-regs.h +++ b/include/xscom-p10-regs.h @@ -4,6 +4,8 @@ /* Core FIR (Fault Isolation Register) */ #define P10_CORE_FIR 0x440 +#define P10_CORE_FIRMASK_OR 0x445 + /* Core WOF (Whose On First) */ #define P10_CORE_WOF 0x448 From patchwork Wed Aug 4 07:20:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=fL+Cxz3d; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 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Date: Wed, 4 Aug 2021 12:50:43 +0530 Message-Id: <20210804072137.1147875-6-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: JlINLuiKu41jnu3ZuIQI2vh9Y0GqIR_E X-Proofpoint-ORIG-GUID: b5Eggssyt4Gdwq0I5J8lI9PLQ38Wl5wJ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 05/59] cpufeatures: Add POWER10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ravi Bangoria Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin Signed-off-by: Nicholas Piggin Signed-off-by: Ravi Bangoria [Folded Ravi's DAWR patch - Vasant] Signed-off-by: Vasant Hegde --- core/cpufeatures.c | 104 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 82 insertions(+), 22 deletions(-) diff --git a/core/cpufeatures.c b/core/cpufeatures.c index 2e33d8ad3..5620b741d 100644 --- a/core/cpufeatures.c +++ b/core/cpufeatures.c @@ -20,6 +20,7 @@ /* Device-tree visible constants follow */ #define ISA_V2_07B 2070 #define ISA_V3_0B 3000 +#define ISA_V3_1 3100 #define USABLE_PR (1U << 0) #define USABLE_OS (1U << 1) @@ -47,12 +48,13 @@ #define CPU_P9P (1U << 4) #define CPU_P9_DD2_2 (1U << 5) #define CPU_P9_DD2_3 (1U << 6) +#define CPU_P10 (1U << 7) #define CPU_P9_DD2 (CPU_P9_DD2_0_1|CPU_P9_DD2_2|CPU_P9_DD2_3|CPU_P9P) #define CPU_P8 (CPU_P8_DD1|CPU_P8_DD2) #define CPU_P9 (CPU_P9_DD1|CPU_P9_DD2|CPU_P9P) -#define CPU_ALL (CPU_P8|CPU_P9) +#define CPU_ALL (CPU_P8|CPU_P9|CPU_P10) struct cpu_feature { const char *name; @@ -202,6 +204,16 @@ static const struct cpu_feature cpu_features_table[] = { -1, -1, -1, NULL, }, + /* + * DAWR1, DAWRX1 etc. + */ + { "debug-facilities-v31", + CPU_P10, + ISA_V3_1, USABLE_HV|USABLE_OS, + HV_CUSTOM, OS_CUSTOM, + -1, -1, -1, + NULL, }, + /* * ISAv2.07B CFAR */ @@ -473,7 +485,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B radix based MMU */ { "mmu-radix", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS, HV_CUSTOM, OS_CUSTOM, -1, -1, -1, @@ -483,7 +495,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B hash based MMU, new hash pte format, PCTR, etc */ { "mmu-hash-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS, HV_CUSTOM, OS_CUSTOM, -1, -1, -1, @@ -493,7 +505,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B wait instruction */ { "wait-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -504,7 +516,7 @@ static const struct cpu_feature cpu_features_table[] = { * XXX: Same question as for idle-nap */ { "idle-stop", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS, HV_CUSTOM, OS_CUSTOM, -1, -1, -1, @@ -516,7 +528,7 @@ static const struct cpu_feature cpu_features_table[] = { * system reset SRR1 reason, etc. */ { "hypervisor-virtualization-interrupt", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV, HV_CUSTOM, OS_NONE, -1, -1, -1, @@ -532,6 +544,16 @@ static const struct cpu_feature cpu_features_table[] = { -1, -1, -1, NULL, }, + /* + * POWER10 MCE / machine check exception. + */ + { "machine-check-power10", + CPU_P10, + ISA_V3_0B, USABLE_HV|USABLE_OS, + HV_CUSTOM, OS_CUSTOM, + -1, -1, -1, + NULL, }, + /* * POWER9 PMU / performance monitor unit. */ @@ -542,12 +564,22 @@ static const struct cpu_feature cpu_features_table[] = { -1, -1, -1, NULL, }, + /* + * POWER10 PMU / performance monitor unit. + */ + { "performance-monitor-power10", + CPU_P10, + ISA_V3_1, USABLE_HV|USABLE_OS, + HV_CUSTOM, OS_CUSTOM, + -1, -1, -1, + NULL, }, + /* * ISAv3.0B scv/rfscv system call instructions and exceptions, fscr bit * etc. */ { "system-call-vectored", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_OS|USABLE_PR, HV_NONE, OS_CUSTOM, -1, PPC_BITLSHIFT(51), 52, @@ -558,7 +590,7 @@ static const struct cpu_feature cpu_features_table[] = { * global msgsnd, msgsndp, msgsync, doorbell, etc. */ { "processor-control-facility-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS, HV_CUSTOM, OS_NONE, PPC_BITLSHIFT(53), -1, -1, @@ -568,7 +600,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B addpcis instruction */ { "pc-relative-addressing", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -591,7 +623,7 @@ static const struct cpu_feature cpu_features_table[] = { * Large decrementer and hypervisor decrementer */ { "timer-facilities-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS, HV_NONE, OS_NONE, -1, -1, -1, @@ -601,7 +633,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B deliver a random number instruction (darn) */ { "random-number-generator", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, 53, @@ -614,14 +646,14 @@ static const struct cpu_feature cpu_features_table[] = { * mcrxrx, setb */ { "fixed-point-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, NULL, }, { "decimal-integer-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -631,42 +663,42 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B lightweight mffs */ { "floating-point-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, "floating-point", }, { "decimal-floating-point-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, "floating-point-v3 decimal-floating-point", }, { "vector-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, "vector", }, { "vector-scalar-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, "vector-v3 vector-scalar" }, { "vector-binary128", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, 54, "vector-scalar-v3", }, { "vector-binary16", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -676,7 +708,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B external exception for EBB */ { "event-based-branch-v3", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -686,7 +718,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B Atomic Memory Operations (AMO) */ { "atomic-memory-operations", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -696,7 +728,7 @@ static const struct cpu_feature cpu_features_table[] = { * ISAv3.0B Copy-Paste Facility */ { "copy-paste", - CPU_P9, + CPU_P9|CPU_P10, ISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR, HV_NONE, OS_NONE, -1, -1, -1, @@ -713,6 +745,27 @@ static const struct cpu_feature cpu_features_table[] = { -1, -1, -1, NULL, }, + /* + * Enable matrix multiply accumulate. + */ + { "matrix-multiply-accumulate", + CPU_P10, + ISA_V3_1, USABLE_PR, + HV_CUSTOM, OS_CUSTOM, + -1, -1, 49, + NULL, }, + + /* + * Enable prefix instructions. Toolchains assume this is + * enabled for when compiling for ISA 3.1. + */ + { "prefix-instructions", + CPU_P10, + ISA_V3_1, USABLE_HV|USABLE_OS|USABLE_PR, + HV_HFSCR, OS_FSCR, + 13, 13, -1, + NULL, }, + /* * Due to hardware bugs in POWER9, the hypervisor needs to assist * guests. @@ -973,6 +1026,13 @@ void dt_add_cpufeatures(struct dt_node *root) cpu_feature_isa = ISA_V3_0B; cpu_feature_cpu = CPU_P9P; break; + case PVR_TYPE_P10: + if (!cpu_name) + cpu_name = "POWER10"; + + cpu_feature_isa = ISA_V3_1; + cpu_feature_cpu = CPU_P10; + break; default: return; } From patchwork Wed Aug 4 07:20:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; 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Wed, 4 Aug 2021 07:22:10 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:10 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:44 +0530 Message-Id: <20210804072137.1147875-7-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: nFjwmT-ZgcHesApLPp7QwbMDBh1aWQkE X-Proofpoint-GUID: dSGsTT-6TDFmsZ5gPJKFWkXQYebd4cED X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 06/59] hw/chiptod: Add POWER10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin POWER10 changes to use the SCOM addressing mode, as it was found to be more robust than the core ID addressing mode. Signed-off-by: Nicholas Piggin Signed-off-by: Vasant Hegde --- hw/chiptod.c | 74 +++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 15 deletions(-) diff --git a/hw/chiptod.c b/hw/chiptod.c index 4e62fd714..3b57f5f16 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -105,6 +105,9 @@ /* -- TOD Error interrupt register -- */ #define TOD_ERROR_INJECT 0x00040031 +/* PC unit PIB address which recieves the timebase transfer from TOD */ +#define PC_TOD 0x4A3 + /* Local FIR EH.TPCHIP.TPC.LOCAL_FIR */ #define LOCAL_CORE_FIR 0x0104000C #define LFIR_SWITCH_COMPLETE PPC_BIT(18) @@ -122,7 +125,8 @@ static enum chiptod_type { chiptod_unknown, chiptod_p8, - chiptod_p9 + chiptod_p9, + chiptod_p10, } chiptod_type; enum chiptod_chip_role { @@ -595,7 +599,8 @@ static bool chiptod_poll_running(void) static bool chiptod_to_tb(void) { - uint64_t tval, tfmr, tvbits; + uint32_t pir = this_cpu()->pir; + uint64_t tval, tfmr; uint64_t timeout = 0; /* Tell the ChipTOD about our fabric address @@ -605,25 +610,51 @@ static bool chiptod_to_tb(void) * PIR between p7 and p8, we need to do the calculation differently. * * p7: 0b00001 || 3-bit core id - * p8: 0b0001 || 4-bit core id + * p8: 0b0001 || 4-bit core id + * p9: 0b001 || 5-bit core id + * p10: 0b001 || 5-bit core id + * + * However in P10 we don't use the core ID addressing, but rather core + * scom addressing mode, which appears to work better. */ if (xscom_readme(TOD_PIB_MASTER, &tval)) { prerror("XSCOM error reading PIB_MASTER\n"); return false; } - if (chiptod_type == chiptod_p9) { - tvbits = (this_cpu()->pir >> 2) & 0x1f; - tvbits |= 0x20; - } else if (chiptod_type == chiptod_p8) { - tvbits = (this_cpu()->pir >> 3) & 0xf; - tvbits |= 0x10; + + if (chiptod_type == chiptod_p10) { + uint32_t core_id = pir_to_core_id(pir); + + if (this_cpu()->is_fused_core && + PVR_VERS_MAJ(mfspr(SPR_PVR)) == 2) { + /* Workaround: must address the even small core. */ + core_id &= ~1; + } + + tval = XSCOM_ADDR_P10_EC(core_id, PC_TOD); + + tval <<= 32; /* PIB slave address goes in PPC bits [0:31] */ + + tval |= PPC_BIT(35); /* Enable SCOM addressing. */ + } else { - tvbits = (this_cpu()->pir >> 2) & 0x7; - tvbits |= 0x08; + uint64_t tvbits; + + if (chiptod_type == chiptod_p9) { + tvbits = (pir >> 2) & 0x1f; + tvbits |= 0x20; + } else if (chiptod_type == chiptod_p8) { + tvbits = (pir >> 3) & 0xf; + tvbits |= 0x10; + } else { + tvbits = (pir >> 2) & 0x7; + tvbits |= 0x08; + } + tval &= ~TOD_PIBM_ADDR_CFG_MCAST; + tval = SETFIELD(TOD_PIBM_ADDR_CFG_SLADDR, tval, tvbits); } - tval &= ~TOD_PIBM_ADDR_CFG_MCAST; - tval = SETFIELD(TOD_PIBM_ADDR_CFG_SLADDR, tval, tvbits); + if (xscom_writeme(TOD_PIB_MASTER, tval)) { prerror("XSCOM error writing PIB_MASTER\n"); return false; @@ -868,10 +899,21 @@ static void chiptod_sync_master(void *data) static void chiptod_sync_slave(void *data) { bool *result = data; + bool do_sync = false; /* Only get primaries, not threads */ - if (this_cpu()->is_secondary) { - /* On secondaries we just cleanup the TFMR */ + if (!this_cpu()->is_secondary) + do_sync = true; + + if (chiptod_type == chiptod_p10 && this_cpu()->is_fused_core && + PVR_VERS_MAJ(mfspr(SPR_PVR)) == 2) { + /* P10 DD2 fused core workaround, must sync on small cores */ + if (this_cpu() == this_cpu()->ec_primary) + do_sync = true; + } + + if (!do_sync) { + /* Just cleanup the TFMR */ chiptod_cleanup_thread_tfmr(); *result = true; return; @@ -1667,6 +1709,8 @@ static bool chiptod_probe(void) chiptod_type = chiptod_p8; if (dt_node_is_compatible(np, "ibm,power9-chiptod")) chiptod_type = chiptod_p9; + if (dt_node_is_compatible(np, "ibm,power10-chiptod")) + chiptod_type = chiptod_p10; } if (dt_has_node_property(np, "secondary", NULL)) From patchwork Wed Aug 4 07:20:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513204 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=gDO/JjKY; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gfjr16lw6z9sW5 for ; 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Wed, 4 Aug 2021 07:22:12 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:12 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:45 +0530 Message-Id: <20210804072137.1147875-8-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ALF9c9X04yHrzHPNTMEVHb55XxlcF7Za X-Proofpoint-GUID: ALF9c9X04yHrzHPNTMEVHb55XxlcF7Za X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 07/59] Basic P10 stop state support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pratik R . Sampat" Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan Adds support for STOP0 lite, STOP2 and STOP3 for Power10 with the following latencies, residency requirements: latency residency stop0lite 1us 10us stop0 10us 100us stop2 20us 200us stop3 45us 450us Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Pratik R. Sampat Signed-off-by: Vasant Hegde --- hw/homer.c | 16 +++++++ hw/slw.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 126 insertions(+), 16 deletions(-) diff --git a/hw/homer.c b/hw/homer.c index c5dbd58e3..3ff6ed1ae 100644 --- a/hw/homer.c +++ b/hw/homer.c @@ -15,6 +15,9 @@ #define P9_PBA_BAR0 0x5012B00 #define P9_PBA_BARMASK0 0x5012B04 +#define P10_PBA_BAR0 0x01010CDA +#define P10_PBA_BARMASK0 0x01010CDE + #define PBA_MASK_ALL_BITS 0x000001FFFFF00000ULL /* Bits 23:43 */ enum P8_BAR { @@ -31,6 +34,13 @@ enum P9_BAR { P9_BAR_SBE = 3, }; +enum P10_BAR { + P10_BAR_HOMER = 0, + P10_BAR_OCMB_THERMAL = 1, + P10_BAR_OCC_COMMON = 2, + P10_BAR_SBE = 3, +}; + static u64 pba_bar0, pba_barmask0; static u8 bar_homer, bar_slw, bar_occ_common; @@ -190,6 +200,12 @@ void homer_init(void) bar_homer = P9_BAR_HOMER; bar_occ_common = P9_BAR_OCC_COMMON; break; + case proc_gen_p10: + pba_bar0 = P10_PBA_BAR0; + pba_barmask0 = P10_PBA_BARMASK0; + bar_homer = P10_BAR_HOMER; + bar_occ_common = P10_BAR_OCC_COMMON; + break; default: return; }; diff --git a/hw/slw.c b/hw/slw.c index a0145deb6..8969096ac 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -761,6 +761,92 @@ static struct cpu_idle_states power9_fusedcore_cpu_idle_states[] = { .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, }; +/* + * Note latency_ns and residency_ns are estimated values for now. + */ +static struct cpu_idle_states power10_cpu_idle_states[] = { + { + .name = "stop0_lite", /* Enter stop0 with no state loss */ + .latency_ns = 1000, + .residency_ns = 10000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 0*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(0) \ + | OPAL_PM_PSSCR_TR(3), + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop0", + .latency_ns = 10000, + .residency_ns = 100000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(0) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop2", + .latency_ns = 20000, + .residency_ns = 200000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(2) \ + | OPAL_PM_PSSCR_MTL(2) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop3", + .latency_ns = 45000, + .residency_ns = 450000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(3) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, +#if 0 + { + .name = "stop11", + .latency_ns = 10000000, + .residency_ns = 100000000, + .flags = 1*OPAL_PM_DEC_STOP \ + | 1*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 1*OPAL_PM_LOSE_HYP_CONTEXT \ + | 1*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_DEEP, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(11) \ + | OPAL_PM_PSSCR_MTL(11) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, +#endif +}; + static void slw_late_init_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -801,7 +887,7 @@ void add_cpu_idle_state_properties(void) fdt64_t *pm_ctrl_reg_val_buf; fdt64_t *pm_ctrl_reg_mask_buf; u32 supported_states_mask; - u32 opal_disabled_states_mask = ~0xEC000000; /* all but stop11 */ + u32 opal_disabled_states_mask = ~0xFC000000; /* all but stop11 */ const char* nvram_disable_str; u32 nvram_disabled_states_mask = 0x00; u32 stop_levels; @@ -839,18 +925,26 @@ void add_cpu_idle_state_properties(void) */ chip = next_chip(NULL); assert(chip); - if (chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS || - chip->type == PROC_CHIP_P9P) { - if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { - states = power9_mambo_cpu_idle_states; - nr_states = ARRAY_SIZE(power9_mambo_cpu_idle_states); - } else if (this_cpu()->is_fused_core) { - states = power9_fusedcore_cpu_idle_states; - nr_states = ARRAY_SIZE(power9_fusedcore_cpu_idle_states); - } else { - states = power9_cpu_idle_states; - nr_states = ARRAY_SIZE(power9_cpu_idle_states); + if (proc_gen >= proc_gen_p9) { + if (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS || + chip->type == PROC_CHIP_P9P) { + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { + states = power9_mambo_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_mambo_cpu_idle_states); + } else if (this_cpu()->is_fused_core) { + states = power9_fusedcore_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_fusedcore_cpu_idle_states); + } else { + states = power9_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_cpu_idle_states); + } + } else if (chip->type == PROC_CHIP_P10) { + states = power10_cpu_idle_states; + nr_states = ARRAY_SIZE(power10_cpu_idle_states); + } else { + prlog(PR_ERR, "determining chip type\n"); + return; } has_stop_inst = true; @@ -934,7 +1028,7 @@ void add_cpu_idle_state_properties(void) * device-tree */ if (has_stop_inst) { - /* Power 9 / POWER ISA 3.0 */ + /* Power 9/10 / POWER ISA 3.0 and above */ supported_states_mask = OPAL_PM_STOP_INST_FAST; if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; @@ -1463,7 +1557,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) return OPAL_PARAMETER; } - if (proc_gen == proc_gen_p9) { + if (proc_gen >= proc_gen_p9) { if (!has_deep_states) { prlog(PR_INFO, "SLW: Deep states not enabled\n"); return OPAL_SUCCESS; @@ -1540,7 +1634,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); - } else if (proc_gen == proc_gen_p9) { + } else if (proc_gen >= proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); if(slw_image_check_p9(chip)) From patchwork Wed Aug 4 07:20:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Wed, 04 Aug 2021 07:22:17 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747JKcL31588656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:19:20 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 67BD9AE063; Wed, 4 Aug 2021 07:22:15 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4A7E2AE057; Wed, 4 Aug 2021 07:22:14 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:13 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:46 +0530 Message-Id: <20210804072137.1147875-9-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: OUvSTFwC_lpHt5xjd9kpbSCf4XV69lSt X-Proofpoint-GUID: OUvSTFwC_lpHt5xjd9kpbSCf4XV69lSt X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 08/59] plat/qemu/p10: add a POWER10 platform X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater BMC is still defined as ast2500 but it should change to ast2600 when available. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- core/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/core/chip.c b/core/chip.c index f79e8cd04..a4ba3249e 100644 --- a/core/chip.c +++ b/core/chip.c @@ -173,6 +173,7 @@ void init_chips(void) if (dt_node_is_compatible(dt_root, "qemu,powernv") || dt_node_is_compatible(dt_root, "qemu,powernv8") || dt_node_is_compatible(dt_root, "qemu,powernv9") || + dt_node_is_compatible(dt_root, "qemu,powernv10") || dt_find_by_path(dt_root, "/qemu")) { proc_chip_quirks |= QUIRK_QEMU | QUIRK_NO_CHIPTOD | QUIRK_NO_DIRECT_CTL | QUIRK_NO_RNG; From patchwork Wed Aug 4 07:20:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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Wed, 04 Aug 2021 07:22:19 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747MHKw15991228 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:17 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E2F08AE051; Wed, 4 Aug 2021 07:22:16 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D1F1CAE053; Wed, 4 Aug 2021 07:22:15 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:15 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:47 +0530 Message-Id: <20210804072137.1147875-10-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VYIi7-Elu6B_51jFFuf5mREVft7RQOCV X-Proofpoint-GUID: VYIi7-Elu6B_51jFFuf5mREVft7RQOCV X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 09/59] psi/p10: Activate P10 interrupts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Behave as P9 for now until we know more on P10. Interface should be the same, apart from the size of the ESB pages. Signed-off-by: Cédric Le Goater [Fixed suprious interrupt issue - Vasant] Signed-off-by: Vasant Hegde --- hw/psi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++- include/psi.h | 7 ++++++ 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 545a81643..f95a066d3 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -266,7 +266,10 @@ static void psi_spurious_fsp_irq(struct psi *psi) prlog(PR_NOTICE, "PSI: Spurious interrupt, attempting clear\n"); - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + reg = PSIHB_XSCOM_P10_HBCSR_CLR; + bit = PSIHB_XSCOM_P10_HBSCR_FSP_IRQ; + } else if (proc_gen == proc_gen_p9) { reg = PSIHB_XSCOM_P9_HBCSR_CLR; bit = PSIHB_XSCOM_P9_HBSCR_FSP_IRQ; } else if (proc_gen == proc_gen_p8) { @@ -737,6 +740,61 @@ static void psi_init_p9_interrupts(struct psi *psi) out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); } +/* + * P9 and P10 have the same PSIHB interface + */ +static const struct irq_source_ops psi_p10_irq_ops = { + .interrupt = psihb_p9_interrupt, + .attributes = psi_p9_irq_attributes, + .name = psi_p9_irq_name, +}; + +static void psi_init_p10_interrupts(struct psi *psi) +{ + struct proc_chip *chip; + u64 val; + /* TODO (clg) : fix ESB page size to 64k when ready */ + uint32_t esb_shift = 12; + + /* Grab chip */ + chip = get_chip(psi->chip_id); + if (!chip) + return; + + /* Configure the CI BAR */ + phys_map_get(chip->id, PSIHB_ESB, 0, &val, NULL); + val |= PSIHB_ESB_CI_VALID; + out_be64(psi->regs + PSIHB_ESB_CI_BASE, val); + + val = in_be64(psi->regs + PSIHB_ESB_CI_BASE); + psi->esb_mmio = (void *)(val & ~PSIHB_ESB_CI_VALID); + prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", + psi->chip_id, psi->esb_mmio); + + /* Grab and configure the notification port */ + val = xive_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); + val |= PSIHB_ESB_NOTIF_VALID; + out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); + + /* Setup interrupt offset */ + val = xive_get_notify_base(psi->interrupt); + val <<= 32; + out_be64(psi->regs + PSIHB_IVT_OFFSET, val); + + /* Register sources */ + prlog(PR_DEBUG, + "PSI[0x%03x]: Interrupts sources registered for P10 DD%i.%i\n", + psi->chip_id, 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf); + + xive_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, + esb_shift, psi->esb_mmio, XIVE_SRC_LSI, + psi, &psi_p10_irq_ops); + + /* Reset irq handling and switch to ESB mode */ + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); +} + static void psi_init_interrupts(struct psi *psi) { /* Configure the interrupt BUID and mask it */ @@ -747,6 +805,9 @@ static void psi_init_interrupts(struct psi *psi) case proc_gen_p9: psi_init_p9_interrupts(psi); break; + case proc_gen_p10: + psi_init_p10_interrupts(psi); + break; default: /* Unknown: just no interrupts */ prerror("PSI: Unknown interrupt type\n"); @@ -826,6 +887,7 @@ static void psi_create_mm_dtnode(struct psi *psi) "ibm,power8-psi"); break; case proc_gen_p9: + case proc_gen_p10: dt_add_property_strings(np, "compatible", "ibm,psi", "ibm,power9-psi"); psi_create_p9_int_map(psi, np); diff --git a/include/psi.h b/include/psi.h index f7b5927ca..a7104ef0b 100644 --- a/include/psi.h +++ b/include/psi.h @@ -116,6 +116,13 @@ #define PSIHB_XSCOM_P9_HBCSR_CLR 0x13 #define PSIHB_XSCOM_P9_HBSCR_FSP_IRQ PPC_BIT(17) +#define PSIHB_XSCOM_P10_BASE 0xa +#define PSIHB_XSCOM_P10_HBBAR_EN PPC_BIT(63) +#define PSIHB_XSCOM_P10_HBCSR 0xe +#define PSIHB_XSCOM_P10_HBCSR_SET 0x12 +#define PSIHB_XSCOM_P10_HBCSR_CLR 0x13 +#define PSIHB_XSCOM_P10_HBSCR_FSP_IRQ PPC_BIT(17) + /* P9 PSI Interrupts */ #define P9_PSI_IRQ_PSI 0 #define P9_PSI_IRQ_OCC 1 From patchwork Wed Aug 4 07:20:48 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:22:17 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:17 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:48 +0530 Message-Id: <20210804072137.1147875-11-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: TkyuiayTq6N-HmqO14BiusFPRmiynQwa X-Proofpoint-GUID: TkyuiayTq6N-HmqO14BiusFPRmiynQwa X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 10/59] external/gard: Enable Power10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Klaus Heinrich Kiwi Add Power10 support for opal-gard utility. Signed-off-by: Klaus Heinrich Kiwi [Folded test case fix and updated commit message - Vasant] Signed-off-by: Vasant Hegde --- external/gard/gard.c | 15 ++++- external/gard/gard.h | 1 + external/gard/test/results/02-usage.err | 1 + external/gard/units.c | 89 +++++++++++++++++++++++++ 4 files changed, 103 insertions(+), 3 deletions(-) diff --git a/external/gard/gard.c b/external/gard/gard.c index b012cf9b7..53a26d0e9 100644 --- a/external/gard/gard.c +++ b/external/gard/gard.c @@ -157,8 +157,12 @@ static void guess_chip_gen(void) set_chip_gen(p9_chip_units); return; + case 0x0080: /* power10 */ + set_chip_gen(p10_chip_units); + return; + default: - fprintf(stderr, "Unsupported processor (pvr %#x)! Set the processor generation manually with -8 or -9\n", pvr); + fprintf(stderr, "Unsupported processor (pvr %#x)! Set the processor generation manually with -8, -9 or -0\n", pvr); exit(1); } } @@ -773,7 +777,8 @@ static void usage(const char *progname) fprintf(stderr, "Usage: %s [-a -e -f -p] []\n\n", progname); fprintf(stderr, "-8 --p8\n"); - fprintf(stderr, "-9 --p9\n\tSet the processor generation\n\n"); + fprintf(stderr, "-9 --p9\n"); + fprintf(stderr, "-0 --p10\n\tSet the processor generation\n\n"); fprintf(stderr, "-e --ecc\n\tForce reading/writing with ECC bytes.\n\n"); fprintf(stderr, "-f --file \n\tDon't search for MTD device," " read from .\n\n"); @@ -802,9 +807,10 @@ static struct option global_options[] = { { "ecc", no_argument, 0, 'e' }, { "p8", no_argument, 0, '8' }, { "p9", no_argument, 0, '9' }, + { "p10", no_argument, 0, '0' }, { 0 }, }; -static const char *global_optstring = "+ef:p89"; +static const char *global_optstring = "+ef:p890"; int main(int argc, char **argv) { @@ -853,6 +859,9 @@ int main(int argc, char **argv) case '9': set_chip_gen(p9_chip_units); break; + case '0': + set_chip_gen(p10_chip_units); + break; case '?': usage(progname); rc = EXIT_FAILURE; diff --git a/external/gard/gard.h b/external/gard/gard.h index 329772a74..d59c2a0de 100644 --- a/external/gard/gard.h +++ b/external/gard/gard.h @@ -71,3 +71,4 @@ struct chip_unit_desc { extern const struct chip_unit_desc *chip_units; extern const struct chip_unit_desc p8_chip_units[]; extern const struct chip_unit_desc p9_chip_units[]; +extern const struct chip_unit_desc p10_chip_units[]; diff --git a/external/gard/test/results/02-usage.err b/external/gard/test/results/02-usage.err index 0e0782628..453fcf52f 100644 --- a/external/gard/test/results/02-usage.err +++ b/external/gard/test/results/02-usage.err @@ -2,6 +2,7 @@ Usage: ./opal-gard [-a -e -f -p] [] -8 --p8 -9 --p9 +-0 --p10 Set the processor generation -e --ecc diff --git a/external/gard/units.c b/external/gard/units.c index 35d46e443..f3b435a3a 100644 --- a/external/gard/units.c +++ b/external/gard/units.c @@ -151,3 +151,92 @@ const struct chip_unit_desc p9_chip_units[] = { {0x4F, "LAST_IN_RANGE"}, }; +const struct chip_unit_desc p10_chip_units[] = { + {0x00, "NA"}, + {0x01, "Sys"}, + {0x02, "Node"}, + {0x03, "DIMM"}, + {0x04, "Membuf"}, + {0x05, "Proc"}, + {0x06, "EX"}, + {0x07, "Core"}, + {0x08, "L2"}, + {0x09, "L3"}, + {0x0A, "L4"}, + {0x0B, "MCS"}, + /* a hole! */ + {0x0D, "MBA"}, + {0x0E, "XBUS"}, + {0x0F, "ABUS"}, + {0x10, "PCI"}, + {0x11, "DPSS"}, + {0x12, "APSS"}, + {0x13, "OCC"}, + {0x14, "PSI"}, + {0x15, "FSP"}, + {0x16, "PNOR"}, + {0x17, "OSC"}, + {0x18, "TODCLK"}, + {0x19, "CONTROL_NODE"}, + {0x1A, "OSCREFCLK"}, + {0x1B, "OSCPCICLK"}, + {0x1C, "REFCLKENDPT"}, + {0x1D, "PCICLKENDPT"}, + {0x1E, "NX"}, + {0x1F, "PORE"}, + {0x20, "PCIESWITCH"}, + {0x21, "CAPP"}, + {0x22, "FSI"}, + {0x23, "EQ"}, + {0x24, "MCA"}, + {0x25, "MCBIST"}, + {0x26, "MI"}, + {0x27, "DMI"}, + {0x28, "OBUS"}, + {0x2A, "SBE"}, + {0x2B, "PPE"}, + {0x2C, "PERV"}, + {0x2D, "PEC"}, + {0x2E, "PHB"}, + {0x2F, "SYSREFCLKENDPT"}, + {0x30, "MFREFCLKENDPT"}, + {0x31, "TPM"}, + {0x32, "SP"}, + {0x33, "UART"}, + {0x34, "PS"}, + {0x35, "FAN"}, + {0x36, "VRM"}, + {0x37, "USB"}, + {0x38, "ETH"}, + {0x39, "PANEL"}, + {0x3A, "BMC"}, + {0x3B, "FLASH"}, + {0x3C, "SEEPROM"}, + {0x3D, "TMP"}, + {0x3E, "GPIO_EXPANDER"}, + {0x3F, "POWER_SEQUENCER"}, + {0x40, "RTC"}, + {0x41, "FANCTLR"}, + {0x42, "OBUS_BRICK"}, + {0x43, "NPU"}, + {0x44, "MC"}, + {0x45, "TEST_FAIL"}, + {0x46, "MFREFCLK"}, + {0x47, "SMPGROUP"}, + {0x48, "OMI"}, + {0x49, "MCC"}, + {0x4A, "OMIC"}, + {0x4B, "OCMB_CHIP"}, + {0x4C, "MEM_PORT"}, + {0x4D, "I2C_MUX"}, + {0x4E, "PMIC"}, + {0x4F, "NMMU"}, + {0x50, "PAU"}, + {0x51, "IOHS"}, + {0x52, "PAUC"}, + {0x53, "FC"}, + {0x54, "LPCREFCLKENDPT"}, + {0x55, "GENERIC_I2C_DEVICE"}, + {0x56, "LAST_IN_RANGE"}, +}; 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Wed, 4 Aug 2021 07:22:19 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:19 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:49 +0530 Message-Id: <20210804072137.1147875-12-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: bfllp6U_MANFSP83Ey8p-j4I9qZtVXYK X-Proofpoint-ORIG-GUID: bfllp6U_MANFSP83Ey8p-j4I9qZtVXYK X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 11/59] external/xscom-utils: Add P10 chip info X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Vasant Hegde --- external/xscom-utils/adu_scoms.py | 2 ++ external/xscom-utils/getscom.c | 3 +++ external/xscom-utils/sram.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/external/xscom-utils/adu_scoms.py b/external/xscom-utils/adu_scoms.py index d651b7e9f..e90634190 100755 --- a/external/xscom-utils/adu_scoms.py +++ b/external/xscom-utils/adu_scoms.py @@ -176,6 +176,8 @@ class GetSCom(object): name = "P9 (Cumulus) processor" elif id == 0xd9: name = "P9P (Axone) processor" + elif id == 0xda: + name = "P10 processor" elif id == 0xe9: name = "Centaur memory buffer" else: diff --git a/external/xscom-utils/getscom.c b/external/xscom-utils/getscom.c index c18a04972..67596e618 100644 --- a/external/xscom-utils/getscom.c +++ b/external/xscom-utils/getscom.c @@ -56,6 +56,9 @@ static void print_chip_info(uint32_t chip_id) case 0xd9: name = "P9P (Axone) processor"; break; + case 0xda: + name = "P10 processor"; + break; case 0xe9: name = "Centaur memory buffer"; break; diff --git a/external/xscom-utils/sram.c b/external/xscom-utils/sram.c index 87df70e10..efe08d8e7 100644 --- a/external/xscom-utils/sram.c +++ b/external/xscom-utils/sram.c @@ -28,6 +28,7 @@ #define PVR_TYPE_P8NVL 0x004c /* Naples */ #define PVR_TYPE_P9 0x004e #define PVR_TYPE_P9P 0x004f /* Axone */ +#define PVR_TYPE_P10 0x0080 #ifdef __powerpc__ static uint64_t get_xscom_base(void) @@ -39,6 +40,7 @@ static uint64_t get_xscom_base(void) switch (pvr >> 16) { case PVR_TYPE_P9: case PVR_TYPE_P9P: + case PVR_TYPE_P10: /* P10 OCB_PIB OCC Control Register is same for P9 and P10 */ return OCB_PIB_BASE_P9; case PVR_TYPE_P8E: From patchwork Wed Aug 4 07:20:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:22:20 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:50 +0530 Message-Id: <20210804072137.1147875-13-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: pyzxpHtrtf8TO5fW3DNOQzuDY7LkrXDm X-Proofpoint-ORIG-GUID: pyzxpHtrtf8TO5fW3DNOQzuDY7LkrXDm X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 12/59] external/opal-prd: Fix occ, homer node label search X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Starting P10, hostboot/HDAT will provide consistent reserved node name. It will just provide node name without starting string "ibm,". That will cause `pm-complex <*>` operation to fails. This patch fixes above issue. For backward compatability purpose I have kept support for old variant of node name as well. Signed-off-by: Vasant Hegde --- external/opal-prd/opal-prd.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/external/opal-prd/opal-prd.c b/external/opal-prd/opal-prd.c index 12269e8eb..1c610da4c 100644 --- a/external/opal-prd/opal-prd.c +++ b/external/opal-prd/opal-prd.c @@ -1508,17 +1508,23 @@ static int pm_complex_load_start(void) range = find_range("ibm,occ-common-area", 0); if (!range) { - pr_log(LOG_ERR, "PM: ibm,occ-common-area not found"); - return rc; + range = find_range("occ-common-area", 0); + if (!range) { + pr_log(LOG_ERR, "PM: occ-common-area not found"); + return rc; + } } occ_common = range->physaddr; for (i = 0; i < nr_chips; i++) { range = find_range("ibm,homer-image", chips[i]); if (!range) { - pr_log(LOG_ERR, "PM: ibm,homer-image not found 0x%lx", - chips[i]); - return -1; + range = find_range("homer-image", chips[i]); + if (!range) { + pr_log(LOG_ERR, "PM: homer-image not found 0x%lx", + chips[i]); + return -1; + } } homer = range->physaddr; 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Wed, 4 Aug 2021 07:22:22 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:22 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:51 +0530 Message-Id: <20210804072137.1147875-14-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: q0GkkIYtLOKhfoENiZfDaSwBDP69R_wB X-Proofpoint-GUID: q0GkkIYtLOKhfoENiZfDaSwBDP69R_wB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 13/59] occ: Add POWER10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pratik R . Sampat" Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan Add support for parsing OCC on Power10 to populate the pstate information. Also enables OCC on P10 Denali system. Co-authored-by: Pratik R. Sampat Co-authored-by: Vaidyanathan Srinivasan Signed-off-by: Pratik R. Sampat Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Vasant Hegde --- hw/fsp/fsp-occ.c | 3 +- hw/occ-sensor.c | 4 +- hw/occ.c | 172 ++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 165 insertions(+), 14 deletions(-) diff --git a/hw/fsp/fsp-occ.c b/hw/fsp/fsp-occ.c index 3081f89a9..58926f408 100644 --- a/hw/fsp/fsp-occ.c +++ b/hw/fsp/fsp-occ.c @@ -167,7 +167,7 @@ static void occ_do_load(u8 scope, u32 dbob_id __unused, u32 seq_id) if (err) return; - if (proc_gen == proc_gen_p9) { + if (proc_gen >= proc_gen_p9) { if (in_ipl) { /* OCC is pre-loaded in P9, so send SUCCESS to FSP */ rsp = fsp_mkmsg(FSP_CMD_LOAD_OCC_STAT, 2, 0, seq_id); @@ -316,6 +316,7 @@ static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id) rc = host_services_occ_stop(); break; case proc_gen_p9: + case proc_gen_p10: last_seq_id = seq_id; chip = next_chip(NULL); prd_fsp_occ_reset(chip->id); diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c index 8605c405e..6efaf908b 100644 --- a/hw/occ-sensor.c +++ b/hw/occ-sensor.c @@ -500,8 +500,8 @@ bool occ_sensors_init(void) int occ_num = 0, i; bool has_gpu = false; - /* OCC inband sensors is only supported in P9 */ - if (proc_gen != proc_gen_p9) + /* OCC inband sensors is only supported in P9/10 */ + if (proc_gen < proc_gen_p9) return false; /* Sensors are copied to BAR2 OCC Common Area */ diff --git a/hw/occ.c b/hw/occ.c index b09b76dc4..8d7bcbec9 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -36,12 +36,14 @@ #define MAX_PSTATES 256 #define MAX_P8_CORES 12 #define MAX_P9_CORES 24 +#define MAX_P10_CORES 32 #define MAX_OPAL_CMD_DATA_LENGTH 4090 #define MAX_OCC_RSP_DATA_LENGTH 8698 #define P8_PIR_CORE_MASK 0xFFF8 #define P9_PIR_QUAD_MASK 0xFFF0 +#define P10_PIR_CHIP_MASK 0x0000 #define FREQ_MAX_IN_DOMAIN 0 #define FREQ_MOST_RECENTLY_SET 1 @@ -120,6 +122,28 @@ struct occ_pstate_table { u8 core_max[MAX_P9_CORES]; u8 pad[56]; } v9; + struct __packed { /* Version 0xA0 */ + u8 occ_role; + u8 pstate_min; + u8 pstate_fixed_freq; + u8 pstate_base; + u8 pstate_ultra_turbo; + u8 pstate_fmax; + u8 minor; + u8 pstate_bottom_throttle; + u8 spare; + u8 spare1; + u32 reserved_32; + u64 reserved_64; + struct __packed { + u8 id; + u8 valid; + u16 reserved; + __be32 freq_khz; + } pstates[MAX_PSTATES]; + u8 core_max[MAX_P10_CORES]; + u8 pad[48]; + } v10; }; } __packed; @@ -237,7 +261,12 @@ struct occ_dynamic_data { u8 major_version; u8 minor_version; u8 gpus_present; - u8 spare1; + struct __packed { /* Version 0x90 */ + u8 spare1; + } v9; + struct __packed { /* Version 0xA0 */ + u8 wof_enabled; + } v10; u8 cpu_throttle; u8 mem_throttle; u8 quick_pwr_drop; @@ -370,7 +399,7 @@ static bool wait_for_all_occ_init(void) * Tuletta), OCC is not loaded before OPAL boot. Hence * initialization can take a while. * - * Note: Checking for occ_data->version == (0x01/0x02/0x90) + * Note: Checking for occ_data->version == (0x01/0x02/0x90/0xA0) * is ok because we clear all of * homer_base+size before passing memory to host * services. This ensures occ_data->version == 0x0 @@ -381,7 +410,7 @@ static bool wait_for_all_occ_init(void) version = occ_data->version; if (version == 0x01 || version == 0x02 || - version == 0x90) + version == 0x90 || version == 0xA0) break; time_wait_ms(100); @@ -465,6 +494,57 @@ static bool wait_for_all_occ_init(void) } break; + case 0xA0: + /* + * OCC-OPAL interface version 0x90 has a + * dynamic data section. This has an + * occ_state field whose values inform about + * the state of the OCC. + * + * 0x00 = OCC not running. No communication + * allowed. + * + * 0x01 = Standby. No communication allowed. + * + * 0x02 = Observation State. Communication + * allowed and is command dependent. + * + * 0x03 = Active State. Communication allowed + * and is command dependent. + * + * 0x04 = Safe State. No communication + * allowed. Just like CPU throttle + * status, some failures will not allow + * for OCC to update state to safe. + * + * 0x05 = Characterization State. + * Communication allowed and is command + * dependent. + * + * We will error out if OCC is not in the + * Active State. + * + * XXX : Should we error out only if no + * communication is allowed with the + * OCC ? + */ + occ_dyn_data = get_occ_dynamic_data(chip); + if (occ_dyn_data->occ_state != 0x3) { + /** + * @fwts-label OCCInactive + * @fwts-advice The OCC for a chip was not active. + * This means that CPU frequency scaling will + * not be functional. CPU may be set to a low, + * safe frequency. This means that CPU idle + * states and CPU frequency scaling may not be + * functional. + */ + prlog(PR_ERR, "OCC: Chip: %x: OCC not active\n", + chip->id); + return false; + } + break; + default: prlog(PR_ERR, "OCC: Unknown OCC-OPAL interface version.\n"); return false; @@ -476,7 +556,7 @@ static bool wait_for_all_occ_init(void) prlog(PR_DEBUG, "OCC: Chip %02x Data (%016llx) = %016llx\n", chip->id, (uint64_t)occ_data, be64_to_cpu(*(__be64 *)occ_data)); - if (version == 0x90) { + if (version == 0x90 || version == 0xA0) { occ_dyn_data = get_occ_dynamic_data(chip); prlog(PR_DEBUG, "OCC: Chip %02x Dynamic Data (%016llx) = %016llx\n", chip->id, (uint64_t)occ_dyn_data, @@ -549,6 +629,36 @@ static void parse_pstates_v9(struct occ_pstate_table *data, __be32 *dt_id, nr_pstates, j); } +static void parse_pstates_v10(struct occ_pstate_table *data, __be32 *dt_id, + __be32 *dt_freq, int nr_pstates, int pmax, int pmin) +{ + int i, j; + int invalid = 0; + + for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) { + if (cmp_pstates(data->v10.pstates[i].id, pmax) > 0) + continue; + + if (!data->v10.pstates[i].valid) { + prlog(PR_WARNING, "OCC: Found Invalid pstate with index %d. Skipping it.\n", i); + invalid++; + continue; + } + + dt_id[j] = cpu_to_be32(data->v10.pstates[i].id); + dt_freq[j] = cpu_to_be32(be32_to_cpu(data->v10.pstates[i].freq_khz) / 1000); + j++; + + if (data->v10.pstates[i].id == pmin) + break; + } + + if ((j + invalid) != nr_pstates) { + prerror("OCC: Expected pstates(%d) not equal to (Parsed pstates(%d) + Invalid Pstates (%d))\n", + nr_pstates, j, invalid); + } +} + static void parse_vid(struct occ_pstate_table *occ_data, struct dt_node *node, u8 nr_pstates, int pmax, int pmin) @@ -588,6 +698,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, struct proc_chip *chip; uint64_t occ_data_area; struct occ_pstate_table *occ_data = NULL; + struct occ_dynamic_data *occ_dyn_data; /* Arrays for device tree */ __be32 *dt_id, *dt_freq; int pmax, pmin, pnom; @@ -647,7 +758,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, /* Parse Pmax, Pmin and Pnominal */ switch (major) { case 0: - if (proc_gen == proc_gen_p9) { + if (proc_gen >= proc_gen_p9) { /** * @fwts-label OCCInvalidVersion02 * @fwts-advice The PState table layout version is not @@ -685,6 +796,15 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, pnom = occ_data->v9.pstate_nom; pmax = occ_data->v9.pstate_ultra_turbo; break; + case 0xA: + pmin = occ_data->v10.pstate_min; + pnom = occ_data->v10.pstate_fixed_freq; + occ_dyn_data = get_occ_dynamic_data(chip); + if (occ_dyn_data->v10.wof_enabled) + pmax = occ_data->v10.pstate_ultra_turbo; + else + pmax = occ_data->v10.pstate_fmax; + break; default: /** * @fwts-label OCCUnsupportedVersion @@ -730,7 +850,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, nr_pstates = labs(pmax - pmin) + 1; prlog(PR_DEBUG, "OCC: Version %x Min %d Nom %d Max %d Nr States %d\n", occ_data->version, pmin, pnom, pmax, nr_pstates); - if ((major == 0x9 && nr_pstates <= 1) || + if (((major == 0x9 || major == 0xA) && nr_pstates <= 1) || (major == 0 && (nr_pstates <= 1 || nr_pstates > 128))) { /** * @fwts-label OCCInvalidPStateRange @@ -760,6 +880,10 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, parse_pstates_v9(occ_data, dt_id, dt_freq, nr_pstates, pmax, pmin); break; + case 0xA: + parse_pstates_v10(occ_data, dt_id, dt_freq, nr_pstates, + pmax, pmin); + break; default: return false; } @@ -801,6 +925,12 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, for (i = 0; i < nr_cores; i++) dt_cmax[i] = cpu_to_be32(occ_data->v9.core_max[i]); break; + case 0xA: + pturbo = occ_data->v10.pstate_base; + pultra_turbo = occ_data->v10.pstate_ultra_turbo; + for (i = 0; i < nr_cores; i++) + dt_cmax[i] = cpu_to_be32(occ_data->v10.core_max[i]); + break; default: return false; } @@ -824,7 +954,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, free(dt_cmax); } - if (major == 0x9) + if (major == 0x9 || major == 0xA) goto out; dt_add_property_cells(power_mgt, "#address-cells", 2); @@ -888,7 +1018,7 @@ static bool cpu_pstates_prepare_core(struct proc_chip *chip, * * Use the OR SCOM to set the required bits in PM_GP1 register * since the OCC might be mainpulating the PM_GP1 register as well. - */ + */ rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SET_GP1), EX_PM_SETUP_GP1_PM_SPR_OVERRIDE_EN); if (rc) { @@ -970,6 +1100,7 @@ static inline u8 get_cpu_throttle(struct proc_chip *chip) case 0: return pdata->v2.throttle; case 0x9: + case 0xA: data = get_occ_dynamic_data(chip); return data->cpu_throttle; default: @@ -1379,7 +1510,7 @@ static void occ_cmd_interface_init(void) struct occ_pstate_table *pdata; struct dt_node *power_mgt; struct proc_chip *chip; - int i = 0; + int i = 0, major; /* Check if the OCC data is valid */ for_each_chip(chip) { @@ -1390,7 +1521,8 @@ static void occ_cmd_interface_init(void) chip = next_chip(NULL); pdata = get_occ_pstate_table(chip); - if ((pdata->version >> 4) != 0x9) + major = pdata->version >> 4; + if (major != 0x9 || major != 0xA) return; for_each_chip(chip) @@ -1403,11 +1535,18 @@ static void occ_cmd_interface_init(void) pdata = get_occ_pstate_table(chip); data = get_occ_dynamic_data(chip); chips[i].chip_id = chip->id; - chips[i].occ_role = pdata->v9.occ_role; chips[i].occ_state = &data->occ_state; chips[i].valid = &pdata->valid; chips[i].cmd = &data->cmd; chips[i].rsp = &data->rsp; + switch (major) { + case 0x9: + chips[i].occ_role = pdata->v9.occ_role; + break; + case 0xA: + chips[i].occ_role = pdata->v10.occ_role; + break; + } init_lock(&chips[i].queue_lock); chips[i].cmd_in_progress = false; chips[i].request_id = 0; @@ -1881,6 +2020,7 @@ void occ_pstates_init(void) homer_opal_data_offset = P8_HOMER_OPAL_DATA_OFFSET; break; case proc_gen_p9: + case proc_gen_p10: homer_opal_data_offset = P9_HOMER_OPAL_DATA_OFFSET; break; default: @@ -1943,6 +2083,11 @@ void occ_pstates_init(void) } else if (proc_gen == proc_gen_p9) { freq_domain_mask = P9_PIR_QUAD_MASK; domain_runs_at = FREQ_MAX_IN_DOMAIN; + } else if (proc_gen == proc_gen_p10) { + freq_domain_mask = P10_PIR_CHIP_MASK; + domain_runs_at = FREQ_MAX_IN_DOMAIN; + } else { + assert(0); } dt_add_property_cells(power_mgt, "freq-domain-mask", freq_domain_mask); @@ -2112,6 +2257,11 @@ void occ_send_dummy_interrupt(void) OCB_OCI_OCIMISC_IRQ | OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY); break; + case proc_gen_p10: + xscom_write(psi->chip_id, P9_OCB_OCI_OCCMISC_OR, + OCB_OCI_OCIMISC_IRQ | + OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY); + break; default: break; } From patchwork Wed Aug 4 07:20:52 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:22:25 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 20C7DAE053; Wed, 4 Aug 2021 07:22:24 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:23 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:52 +0530 Message-Id: <20210804072137.1147875-15-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DYNNYAx_aWQwfHLBwMFR1YaOplFIUS_0 X-Proofpoint-GUID: rAQ_2QtN0bhK0n5cjm5l70X_Mlt4OhUb X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 14/59] hdata: Add POWER10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ravi Bangoria , Reza Arbab Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ravi Bangoria Initial P10 support - LPC : This contains two useful information: LPC MCTP Memory Window Base Address Second vUART console details - Enable memory-buffer mmio - Fix ipmi sensors IPMI sensors are deprecated in P10. Hence do not parse ipmi sensors. - I2C support - Detect PHB5 - Create p10 xscom, xive, chiptod nodes - Set pa-features bit for 2nd DAWR Availability of 2nd DAWR depends on 0th bit of 64th byte of ibm,pa-features property. Set it for p10. Co-authored-by: Vasant Hegde Signed-off-by: Vasant Hegde Co-authored-by: Nicholas Piggin Signed-off-by: Nicholas Piggin Co-authored-by: Reza Arbab Signed-off-by: Reza Arbab Co-authored-by: Ravi Bangoria Signed-off-by: Ravi Bangoria Signed-off-by: Vasant Hegde --- hdata/cpu-common.c | 19 ++++++++++++++- hdata/fsp.c | 10 ++++++-- hdata/i2c.c | 5 ++-- hdata/iohub.c | 50 +++++++++++++++++++++++++++++--------- hdata/memory.c | 8 ++++--- hdata/spira.c | 52 ++++++++++++++++++++++++++++++++++------ hdata/spira.h | 20 ++++++++++++++-- hdata/test/hdata_to_dt.c | 14 +++++++++-- 8 files changed, 148 insertions(+), 30 deletions(-) diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c index e46f919b7..bf821c154 100644 --- a/hdata/cpu-common.c +++ b/hdata/cpu-common.c @@ -46,6 +46,18 @@ struct dt_node * add_core_common(struct dt_node *cpus, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */ }; + const uint8_t pa_features_p10[] = { + 66, 0, + 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */ + 0x80, 0x00, /* 64 .. 65 */ + }; const uint8_t *pa_features; size_t pa_features_size; @@ -83,6 +95,11 @@ struct dt_node * add_core_common(struct dt_node *cpus, pa_features_size = sizeof(pa_features_p9); } break; + case PVR_TYPE_P10: + name = "PowerPC,POWER10"; + pa_features = pa_features_p10; + pa_features_size = sizeof(pa_features_p10); + break; default: name = "PowerPC,Unknown"; pa_features = NULL; @@ -103,7 +120,7 @@ struct dt_node * add_core_common(struct dt_node *cpus, dt_add_property_cells(cpu, "ibm,processor-page-sizes", 0xc, 0x10, 0x18, 0x22); - if (proc_gen == proc_gen_p9) + if (proc_gen >= proc_gen_p9) dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings", 0x0000000c, 0xa0000010, 0x20000015, 0x4000001e); diff --git a/hdata/fsp.c b/hdata/fsp.c index 18380e7d4..458b7e636 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -355,7 +355,7 @@ static void add_ipmi_sensors(struct dt_node *bmc_node) static void bmc_create_node(const struct HDIF_common_hdr *sp) { struct dt_node *bmc_node; - u32 fw_bar, io_bar, mem_bar, internal_bar; + u32 fw_bar, io_bar, mem_bar, internal_bar, mctp_base; const struct spss_iopath *iopath; const struct spss_sp_impl *sp_impl; struct dt_node *lpcm, *lpc, *n; @@ -370,7 +370,8 @@ static void bmc_create_node(const struct HDIF_common_hdr *sp) dt_add_property_cells(bmc_node, "#size-cells", 0); /* Add sensor info under /bmc */ - add_ipmi_sensors(bmc_node); + if (proc_gen < proc_gen_p10) + add_ipmi_sensors(bmc_node); sp_impl = HDIF_get_idata(sp, SPSS_IDATA_SP_IMPL, &size); if (CHECK_SPPTR(sp_impl) && (size > 8)) { @@ -425,12 +426,17 @@ static void bmc_create_node(const struct HDIF_common_hdr *sp) mem_bar = be32_to_cpu(iopath->lpc.memory_bar); io_bar = be32_to_cpu(iopath->lpc.io_bar); internal_bar = be32_to_cpu(iopath->lpc.internal_bar); + mctp_base = be32_to_cpu(iopath->lpc.mctp_base); prlog(PR_DEBUG, "LPC: IOPATH chip id = %x\n", chip_id); prlog(PR_DEBUG, "LPC: FW BAR = %#x\n", fw_bar); prlog(PR_DEBUG, "LPC: MEM BAR = %#x\n", mem_bar); prlog(PR_DEBUG, "LPC: IO BAR = %#x\n", io_bar); prlog(PR_DEBUG, "LPC: Internal BAR = %#x\n", internal_bar); + if (proc_gen >= proc_gen_p10) { + /* MCTP is part of FW BAR */ + prlog(PR_DEBUG, "LPC: MCTP base = %#x\n", mctp_base); + } /* * The internal address space BAR actually points to the LPC master diff --git a/hdata/i2c.c b/hdata/i2c.c index 8aa93d8f5..7d5d655a5 100644 --- a/hdata/i2c.c +++ b/hdata/i2c.c @@ -250,7 +250,7 @@ int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, * This code makes a few assumptions about XSCOM addrs, etc * and will need updating for new processors */ - assert(proc_gen == proc_gen_p9); + assert(proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10); /* * Emit an error if we get a newer version. This is an interim measure @@ -301,7 +301,8 @@ int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, * engines outside this range so we don't create bogus * i2cm@ nodes. */ - if (dev->i2cm_engine >= 4 && proc_gen == proc_gen_p9) + if (dev->i2cm_engine >= 4 && + (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10)) continue; bus = p8_i2c_add_port_node(xscom, dev->i2cm_engine, dev->i2cm_port, diff --git a/hdata/iohub.c b/hdata/iohub.c index fa3afbf7a..fb215e1fb 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -151,6 +151,7 @@ static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, int phb_index, u8 active_phbs) { struct dt_node *stack; + const char *compat; u64 eq[8]; u8 *gen4; int i; @@ -158,9 +159,14 @@ static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, stack = dt_new_addr(pbcq, "stack", stack_index); assert(stack); + if (proc_gen == proc_gen_p9) + compat = "ibm,power9-phb-stack"; + else + compat = "ibm,power10-phb-stack"; + dt_add_property_cells(stack, "reg", stack_index); dt_add_property_cells(stack, "ibm,phb-index", phb_index); - dt_add_property_string(stack, "compatible", "ibm,power9-phb-stack"); + dt_add_property_string(stack, "compatible", compat); /* XXX: This should probably just return if the PHB is disabled * rather than adding the extra properties. @@ -190,6 +196,7 @@ static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, return stack; } +/* Add PHB4 on p9, PHB5 on p10 */ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, const struct HDIF_common_hdr *sp_iohubs, struct dt_node *xcom, @@ -199,10 +206,21 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, { struct dt_node *pbcq; uint8_t active_phb_mask = hub->fab_br0_pdt; - uint32_t pe_xscom = 0x4010c00 + (pec_index * 0x0000400); - uint32_t pci_xscom = 0xd010800 + (pec_index * 0x1000000); + uint32_t pe_xscom; + uint32_t pci_xscom; + const char *compat; int i; + if (proc_gen == proc_gen_p9) { + pe_xscom = 0x4010c00 + (pec_index * 0x0000400); + pci_xscom = 0xd010800 + (pec_index * 0x1000000); + compat = "ibm,power9-pbcq"; + } else { + pe_xscom = 0x3011800 - (pec_index * 0x1000000); + pci_xscom = 0x8010800 + (pec_index * 0x1000000); + compat = "ibm,power10-pbcq"; + } + /* Create PBCQ node under xscom */ pbcq = dt_new_addr(xcom, "pbcq", pe_xscom); if (!pbcq) @@ -214,7 +232,7 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, pci_xscom, 0x200); /* The hubs themselves go under the stacks */ - dt_add_property_strings(pbcq, "compatible", "ibm,power9-pbcq"); + dt_add_property_strings(pbcq, "compatible", compat); dt_add_property_cells(pbcq, "ibm,pec-index", pec_index); dt_add_property_cells(pbcq, "#address-cells", 1); dt_add_property_cells(pbcq, "#size-cells", 0); @@ -229,7 +247,7 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, */ io_get_loc_code(sp_iohubs, pbcq, "ibm,loc-code"); - prlog(PR_INFO, "CEC: Added PHB4 PBCQ %d with %d stacks\n", + prlog(PR_INFO, "CEC: Added PBCQ %d with %d stacks\n", pec_index, stacks); /* the actual PHB nodes created later on by skiboot */ @@ -267,6 +285,7 @@ static struct dt_node *io_add_p8(const struct cechub_io_hub *hub, return xscom; } +/* Add PBCQs for p9/p10 */ static struct dt_node *io_add_p9(const struct cechub_io_hub *hub, const struct HDIF_common_hdr *sp_iohubs) { @@ -280,17 +299,22 @@ static struct dt_node *io_add_p9(const struct cechub_io_hub *hub, xscom = find_xscom_for_chip(chip_id); if (!xscom) { - prerror("P9: Can't find XSCOM for chip %d\n", chip_id); + prerror("IOHUB: Can't find XSCOM for chip %d\n", chip_id); return NULL; } - prlog(PR_DEBUG, "IOHUB: PHB4 active bridge mask %x\n", + prlog(PR_DEBUG, "IOHUB: PHB active bridge mask %x\n", (u32) hub->fab_br0_pdt); /* Create PBCQs */ - io_add_phb4(hub, sp_iohubs, xscom, 0, 1, 0); - io_add_phb4(hub, sp_iohubs, xscom, 1, 2, 1); - io_add_phb4(hub, sp_iohubs, xscom, 2, 3, 3); + if (proc_gen == proc_gen_p9) { + io_add_phb4(hub, sp_iohubs, xscom, 0, 1, 0); + io_add_phb4(hub, sp_iohubs, xscom, 1, 2, 1); + io_add_phb4(hub, sp_iohubs, xscom, 2, 3, 3); + } else { /* p10 */ + io_add_phb4(hub, sp_iohubs, xscom, 0, 3, 0); + io_add_phb4(hub, sp_iohubs, xscom, 1, 3, 3); + } return xscom; } @@ -806,6 +830,10 @@ static void io_parse_fru(const void *sp_iohubs) prlog(PR_INFO, "CEC: Axone !\n"); io_add_p9(hub, sp_iohubs); break; + case CECHUB_HUB_RAINIER: + prlog(PR_INFO, "CEC: Rainier !\n"); + io_add_p9(hub, sp_iohubs); + break; default: prlog(PR_ERR, "CEC: Hub ID 0x%04x unsupported !\n", hub_id); @@ -817,7 +845,7 @@ static void io_parse_fru(const void *sp_iohubs) io_parse_slots(sp_iohubs, chip_id); } - if (proc_gen == proc_gen_p8 || proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p8 || proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) io_add_p8_cec_vpd(sp_iohubs); } diff --git a/hdata/memory.c b/hdata/memory.c index 6602addd9..efdb502b1 100755 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -53,6 +53,8 @@ struct HDIF_ms_area_address_range { #define PHYS_ATTR_STATUS_SAVE_FAILED 0x02 #define PHYS_ATTR_STATUS_SAVED 0x04 #define PHYS_ATTR_STATUS_NOT_SAVED 0x08 +#define PHYS_ATTR_STATUS_ENCRYPTED 0x10 +#define PHYS_ATTR_STATUS_ERR_DETECTED 0x40 #define PHYS_ATTR_STATUS_MEM_INVALID 0xff /* Memory Controller ID for Nimbus P9 systems */ @@ -514,7 +516,7 @@ static void add_memory_buffer_mmio(const struct HDIF_common_hdr *msarea) struct dt_node *membuf; beint64_t *reg, *flags; - if (PVR_TYPE(mfspr(SPR_PVR)) != PVR_TYPE_P9P) + if (proc_gen <= proc_gen_p9 && PVR_TYPE(mfspr(SPR_PVR)) != PVR_TYPE_P9P) return; if (be16_to_cpu(msarea->version) < 0x50) { @@ -911,7 +913,8 @@ static bool __memory_parse(struct dt_node *root) prlog(PR_DEBUG, "MS VPD: is at %p\n", ms_vpd); msac = HDIF_get_idata(ms_vpd, MSVPD_IDATA_MS_ADDR_CONFIG, &size); - if (!CHECK_SPPTR(msac) || size < sizeof(*msac)) { + if (!CHECK_SPPTR(msac) || + size < offsetof(struct msvpd_ms_addr_config, max_possible_ms_address)) { prerror("MS VPD: bad msac size %u @ %p\n", size, msac); op_display(OP_FATAL, OP_MOD_MEM, 0x0002); return false; @@ -953,4 +956,3 @@ void memory_parse(void) abort(); } } - diff --git a/hdata/spira.c b/hdata/spira.c index 2e3b3a463..85c2fe71c 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -301,6 +301,7 @@ static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28)); break; case proc_gen_p9: + case proc_gen_p10: /* XXX P10 */ default: /* On P9 we need to put the chip ID in the natural powerbus * position. @@ -332,6 +333,10 @@ static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, dt_add_property_strings(node, "compatible", "ibm,xscom", "ibm,power9-xscom"); break; + case proc_gen_p10: + dt_add_property_strings(node, "compatible", + "ibm,xscom", "ibm,power10-xscom"); + break; default: dt_add_property_strings(node, "compatible", "ibm,xscom"); } @@ -420,6 +425,11 @@ static void add_psihb_node(struct dt_node *np) psi_slen = 0x100; psi_comp = "ibm,power9-psihb-x"; break; + case proc_gen_p10: + psi_scom = 0x3011d00; + psi_slen = 0x100; + psi_comp = "ibm,power10-psihb-x"; + break; default: psi_comp = NULL; } @@ -438,10 +448,28 @@ static void add_psihb_node(struct dt_node *np) static void add_xive_node(struct dt_node *np) { - struct dt_node *xive = dt_new_addr(np, "xive", 0x5013000); + struct dt_node *xive; + const char *comp; + u32 scom, slen; + + switch (proc_gen) { + case proc_gen_p9: + scom = 0x5013000; + slen = 0x300; + comp = "ibm,power9-xive-x"; + break; + case proc_gen_p10: + scom = 0x2010800; + slen = 0x400; + comp = "ibm,power10-xive-x"; + break; + default: + return; + } - dt_add_property_cells(xive, "reg", 0x5013000, 0x300); - dt_add_property_string(xive, "compatible", "ibm,power9-xive-x"); + xive = dt_new_addr(np, "xive", scom); + dt_add_property_cells(xive, "reg", scom, slen); + dt_add_property_string(xive, "compatible", comp); /* HACK: required for simics */ dt_add_property(xive, "force-assign-bars", NULL, 0); @@ -725,6 +753,9 @@ static void add_chiptod_node(unsigned int chip_id, int flags) case proc_gen_p9: compat_str = "ibm,power9-chiptod"; break; + case proc_gen_p10: + compat_str = "ibm,power10-chiptod"; + break; default: return; } @@ -866,6 +897,7 @@ static void add_nx_node(u32 gcid) /* POWER9 NX is not software compatible with P8 NX */ dt_add_property_strings(nx, "compatible", "ibm,power9-nx"); break; + case proc_gen_p10: /* XXX P10 */ default: return; } @@ -903,15 +935,21 @@ static void add_nx(void) static void add_nmmu(void) { struct dt_node *xscom, *nmmu; + u32 scom; - /* Nest MMU only exists on POWER9 */ - if (proc_gen != proc_gen_p9) + /* Nest MMU only exists on POWER9 or later */ + if (proc_gen < proc_gen_p9) return; + if (proc_gen == proc_gen_p9) + scom = 0x5012c40; + else + scom = 0x2010c40; + dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { - nmmu = dt_new_addr(xscom, "nmmu", 0x5012c40); + nmmu = dt_new_addr(xscom, "nmmu", scom); dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu"); - dt_add_property_cells(nmmu, "reg", 0x5012c40, 0x20); + dt_add_property_cells(nmmu, "reg", scom, 0x20); } } diff --git a/hdata/spira.h b/hdata/spira.h index 18d73bdfa..7c5341f94 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -304,7 +304,7 @@ struct spss_iopath { __be32 firmware_bar; __be32 internal_bar; - __be32 reserved2; + __be32 mctp_base; __be64 uart_base; __be32 uart_size; @@ -316,13 +316,27 @@ struct spss_iopath { #define UART_INT_LVL_LOW 0x1 #define UART_INT_RISING 0x2 #define UART_INT_LVL_HIGH 0x3 - uint8_t reserved3[2]; + uint8_t uart_valid; + uint8_t reserved3; __be64 bt_base; __be32 bt_size; uint8_t bt_sms_int_num; uint8_t bt_bmc_response_int_num; uint8_t reserved4[2]; + + __be16 kcs_data_reg_addr; + __be16 kcs_status_reg_addr; + uint8_t kcs_int_number; + + __be64 uart2_base; + __be32 uart2_size; + __be32 uart2_clk; /* UART baud clock in Hz */ + __be32 uart2_baud; /* UART baud rate */ + uint8_t uart2_int_number; + uint8_t uart2_int_type; + uint8_t uart2_valid; + uint8_t reserved5; } __packed lpc; }; } __packed; @@ -493,6 +507,7 @@ struct msvpd_ms_addr_config { __be64 max_possible_ms_address; __be32 deprecated; __be64 mirrorable_memory_starting_address; + __be64 hrmor_stash_loc_address; } __packed; /* Idata index 1: Total configured mainstore */ @@ -651,6 +666,7 @@ struct cechub_io_hub { #define CECHUB_HUB_NIMBUS_LAGRANGE 0x0022 /* Nimbus+lagrange from spec */ #define CECHUB_HUB_CUMULUS_DUOMO 0x0030 /* cumulus+duomo from spec */ #define CECHUB_HUB_AXONE_HOPPER 0x0040 /* axone+hopper */ +#define CECHUB_HUB_RAINIER 0x0050 __be32 ec_level; __be32 aff_dom2; /* HDAT < v9.x only */ __be32 aff_dom3; /* HDAT < v9.x only */ diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c index 90d83f937..1729f1ca9 100644 --- a/hdata/test/hdata_to_dt.c +++ b/hdata/test/hdata_to_dt.c @@ -2,7 +2,7 @@ /* * Given a hdata dump, output the device tree. * - * Copyright 2013-2019 IBM Corp. + * Copyright 2013-2020 IBM Corp. */ #include @@ -63,11 +63,13 @@ unsigned long tb_hz = 512000000; #define PVR_TYPE_P8NVL 0x004c #define PVR_TYPE_P9 0x004e #define PVR_TYPE_P9P 0x004f +#define PVR_TYPE_P10 0x0080 #define PVR_P8E 0x004b0201 #define PVR_P8 0x004d0200 #define PVR_P8NVL 0x004c0100 #define PVR_P9 0x004e0200 #define PVR_P9P 0x004f0100 +#define PVR_P10 0x00800100 #define SPR_PVR 0x11f /* RO: Processor version register */ @@ -328,6 +330,10 @@ int main(int argc, char *argv[]) fake_pvr = PVR_P9P; proc_gen = proc_gen_p9; opt_count++; + } else if (strcmp(argv[i], "-10") == 0) { + fake_pvr = PVR_P10; + proc_gen = proc_gen_p10; + opt_count++; } } @@ -347,13 +353,17 @@ int main(int argc, char *argv[]) " -8 Force PVR to POWER8\n" " -8E Force PVR to POWER8E\n" " -9 Force PVR to POWER9 (nimbus)\n" + " -9P Force PVR to POWER9P (Axone)\n" + " -10 Force PVR to POWER10\n" "\n" "When no PVR is specified -8 is assumed" "\n" "Pipe to 'dtc -I dtb -O dts' for human readable output\n"); } - phys_map_init(fake_pvr); + /* We don't have phys mapping for P8 */ + if (proc_gen != proc_gen_p8) + phys_map_init(fake_pvr); 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Wed, 4 Aug 2021 07:22:26 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:25 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:53 +0530 Message-Id: <20210804072137.1147875-16-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Nsme2na-fklj1xB0upmyJIdhvm_DySG3 X-Proofpoint-ORIG-GUID: Nsme2na-fklj1xB0upmyJIdhvm_DySG3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 15/59] hdat/spira: Define ibm, primary-topology-index property per chip X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni HDAT provides Topology ID table and the primary topology location on P10. This primary location points to primary topology entry in ID table which contains the primary topology index and this index is used to define the paste base address per chip. This patch reads Topology ID table and the primary topology location from hdata and retrieves the primary topology index in the ID table. Make this primaty topology index value available with ibm,primary-topology-index property per chip. VAS reads this property to setup paste base address for each chip. Signed-off-by: Haren Myneni Signed-off-by: Vasant Hegde --- core/chip.c | 3 +++ hdata/spira.c | 12 ++++++++++++ hdata/spira.h | 5 ++++- include/chip.h | 3 +++ 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/core/chip.c b/core/chip.c index a4ba3249e..2d95b2e05 100644 --- a/core/chip.c +++ b/core/chip.c @@ -133,6 +133,9 @@ static void init_chip(struct dt_node *dn) if (lc) chip->loc_code = strdup(lc); + chip->primary_topology = dt_prop_get_u32_def(dn, + "ibm,primary-topology-index", 0xffffffff); + prlog(PR_INFO, "CHIP: Initialised chip %d from %s\n", id, dn->name); chips[id] = chip; } diff --git a/hdata/spira.c b/hdata/spira.c index 85c2fe71c..2fd3da108 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -688,6 +688,18 @@ static bool add_xscom_sppcrd(uint64_t xscom_base) be32_to_cpu(cinfo->sw_xstop_fir_scom), fir_bit); } + + if (proc_gen >= proc_gen_p10) { + uint8_t primary_loc = cinfo->primary_topology_loc; + + if (primary_loc >= CHIP_MAX_TOPOLOGY_ENTRIES) { + prerror("XSCOM: Invalid primary topology index %d\n", + primary_loc); + continue; + } + dt_add_property_cells(np, "ibm,primary-topology-index", + cinfo->topology_id_table[primary_loc]); + } } return i > 0; diff --git a/hdata/spira.h b/hdata/spira.h index 7c5341f94..7da1154d7 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -1092,7 +1092,10 @@ struct sppcrd_chip_info { /* From latest version (possibly 0x21 and later) */ __be32 sw_xstop_fir_scom; uint8_t sw_xstop_fir_bitpos; - uint8_t reserved_1[3]; + /* Latest version for P10 */ +#define CHIP_MAX_TOPOLOGY_ENTRIES 32 + uint8_t topology_id_table[CHIP_MAX_TOPOLOGY_ENTRIES]; + uint8_t primary_topology_loc; /* Index in topology_id_table */ } __packed; /* Idata index 1 : Chip TOD */ diff --git a/include/chip.h b/include/chip.h index 8bc48ba29..bbfc65e3a 100644 --- a/include/chip.h +++ b/include/chip.h @@ -277,6 +277,9 @@ struct proc_chip { /* Used during OCC init */ bool ex_present; + + /* Used by hw/vas.c on p10 */ + uint32_t primary_topology; }; extern uint32_t pir_to_chip_id(uint32_t pir); From patchwork Wed Aug 4 07:20:54 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:22:27 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:27 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:54 +0530 Message-Id: <20210804072137.1147875-17-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VPw3Nbrz4rUcUGe6dNwZGYkQhrtrrRIN X-Proofpoint-GUID: VPw3Nbrz4rUcUGe6dNwZGYkQhrtrrRIN X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 16/59] hdat/spira: Add ibm, power10-vas-x string to VAS compatible property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni VAS SCOM base address and paste address format are changed on P10. This patch adds ibm,power10-vas-x string to compatible property per each VAS node. This compatible string is used to define the paste base address later during VAS initialization. Also enables NX on P10 without adding any compatible string since the NX SCOM base address is not changed. Signed-off-by: Haren Myneni Signed-off-by: Vasant Hegde --- hdata/spira.c | 25 ++++++++++++++++--------- include/vas.h | 5 +++-- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/hdata/spira.c b/hdata/spira.c index 2fd3da108..b7101d72e 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "hdata.h" #include "hostservices.h" @@ -475,17 +476,23 @@ static void add_xive_node(struct dt_node *np) dt_add_property(xive, "force-assign-bars", NULL, 0); } -/* - * SCOM Base Address from P9 SCOM Assignment spreadsheet - */ -#define VAS_SCOM_BASE_ADDR 0x03011800 - static void add_vas_node(struct dt_node *np, int idx) { - struct dt_node *vas = dt_new_addr(np, "vas", VAS_SCOM_BASE_ADDR); + struct dt_node *vas; + const char *comp; + uint64_t base_addr; - dt_add_property_cells(vas, "reg", VAS_SCOM_BASE_ADDR, 0x300); - dt_add_property_string(vas, "compatible", "ibm,power9-vas-x"); + if (proc_gen == proc_gen_p9) { + base_addr = P9_VAS_SCOM_BASE_ADDR; + comp = "ibm,power9-vas-x"; + } else { + base_addr = VAS_SCOM_BASE_ADDR; + comp = "ibm,power10-vas-x"; + } + + vas = dt_new_addr(np, "vas", base_addr); + dt_add_property_cells(vas, "reg", base_addr, 0x300); + dt_add_property_string(vas, "compatible", comp); dt_add_property_cells(vas, "ibm,vas-id", idx); } @@ -906,10 +913,10 @@ static void add_nx_node(u32 gcid) "ibm,power8-nx"); break; case proc_gen_p9: + case proc_gen_p10: /* POWER9 NX is not software compatible with P8 NX */ dt_add_property_strings(nx, "compatible", "ibm,power9-nx"); break; - case proc_gen_p10: /* XXX P10 */ default: return; } diff --git a/include/vas.h b/include/vas.h index 1c06e5606..369c3807a 100644 --- a/include/vas.h +++ b/include/vas.h @@ -67,9 +67,10 @@ extern __attrconst uint64_t vas_get_wcbs_bar(int chipid); #define VAS_WINDOWS_PER_CHIP 65536 /* 64K */ /* - * SCOM Base Address from P9 SCOM Assignment spreadsheet + * SCOM Base Address from P9/P10 SCOM Assignment spreadsheet */ -#define VAS_SCOM_BASE_ADDR 0x03011800 +#define P9_VAS_SCOM_BASE_ADDR 0x03011800 +#define VAS_SCOM_BASE_ADDR 0x02011400 /* * NOTE: VAS_SCOM_BASE_ADDR (0x3011800) includes the SCOM ring of 6. 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Wed, 4 Aug 2021 07:22:29 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:29 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:55 +0530 Message-Id: <20210804072137.1147875-18-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: SqCCYfC-Vz2T4x4j1RGQ1Iwpu_Ibv2JO X-Proofpoint-GUID: SqCCYfC-Vz2T4x4j1RGQ1Iwpu_Ibv2JO X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 17/59] hdata/P10: Fix xscom address and ibm, chip-id property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" `xscom_id` is deprecated in P10. Instead we should use topology ID's ("Primary topology table index") to calculate xscom address. Also use ("Processor fabric topology id") for "ibm,chip-id" property. Signed-off-by: Vasant Hegde --- hdata/fsp.c | 2 +- hdata/hdata.h | 1 + hdata/spira.c | 34 +++++++++++++++++++++++----------- hdata/spira.h | 3 +++ 4 files changed, 28 insertions(+), 12 deletions(-) diff --git a/hdata/fsp.c b/hdata/fsp.c index 458b7e636..42f1121ab 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -297,7 +297,7 @@ static void add_chip_id_to_sensors(struct dt_node *sensor_node, uint32_t slca_in } dt_add_property_cells(sensor_node, - "ibm,chip-id", be32_to_cpu(cinfo->xscom_id)); + "ibm,chip-id", get_xscom_id(cinfo)); return; } } diff --git a/hdata/hdata.h b/hdata/hdata.h index cbc61c31d..bae4eaa58 100644 --- a/hdata/hdata.h +++ b/hdata/hdata.h @@ -24,6 +24,7 @@ extern void vpd_data_parse(struct dt_node *node, extern struct dt_node *find_xscom_for_chip(uint32_t chip_id); extern uint32_t pcid_to_chip_id(uint32_t proc_chip_id); +extern uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo); extern struct dt_node *add_core_common(struct dt_node *cpus, const struct sppcia_cpu_cache *cache, diff --git a/hdata/spira.c b/hdata/spira.c index b7101d72e..7d56f3f29 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -289,12 +289,23 @@ struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, const char id[], return h; } -static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, - uint32_t proc_chip_id) +uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo) +{ + if (proc_gen <= proc_gen_p9) + return be32_to_cpu(cinfo->xscom_id); + + /* On P10 use Processor fabric topology id for chip id */ + return (uint32_t)(cinfo->fab_topology_id); +} + +static struct dt_node *add_xscom_node(uint64_t base, + const struct sppcrd_chip_info *cinfo) { struct dt_node *node; uint64_t addr, size; uint64_t freq; + uint32_t hw_id = get_xscom_id(cinfo); + uint32_t proc_chip_id = be32_to_cpu(cinfo->proc_chip_id); switch (proc_gen) { case proc_gen_p8: @@ -302,13 +313,16 @@ static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28)); break; case proc_gen_p9: - case proc_gen_p10: /* XXX P10 */ - default: /* On P9 we need to put the chip ID in the natural powerbus * position. */ addr = base | (((uint64_t)hw_id) << 42); break; + case proc_gen_p10: + default: + /* Use Primary topology table index for xscom address */ + addr = base | (((uint64_t)cinfo->topology_id_table[cinfo->primary_topology_loc]) << 44); + break; }; size = (u64)1 << PPC_BITLSHIFT(28); @@ -611,9 +625,7 @@ static bool add_xscom_sppcrd(uint64_t xscom_base) continue; /* Create the XSCOM node */ - np = add_xscom_node(xscom_base, - be32_to_cpu(cinfo->xscom_id), - be32_to_cpu(cinfo->proc_chip_id)); + np = add_xscom_node(xscom_base, cinfo); if (!np) continue; @@ -636,7 +648,7 @@ static bool add_xscom_sppcrd(uint64_t xscom_base) SPPCRD_IDATA_KW_VPD); if (vpd_node) dt_add_property_cells(vpd_node, "ibm,chip-id", - be32_to_cpu(cinfo->xscom_id)); + get_xscom_id(cinfo)); fru_id = HDIF_get_idata(hdif, SPPCRD_IDATA_FRU_ID, NULL); if (fru_id) @@ -875,7 +887,7 @@ static bool add_chiptod_new(void) flags |= CHIPTOD_ID_FLAGS_PRIMARY; } - add_chiptod_node(be32_to_cpu(cinfo->xscom_id), flags); + add_chiptod_node(get_xscom_id(cinfo), flags); found = true; } return found; @@ -947,7 +959,7 @@ static void add_nx(void) continue; if (cinfo->nx_state) - add_nx_node(be32_to_cpu(cinfo->xscom_id)); + add_nx_node(get_xscom_id(cinfo)); } } @@ -1397,7 +1409,7 @@ uint32_t pcid_to_chip_id(uint32_t proc_chip_id) continue; } if (proc_chip_id == be32_to_cpu(cinfo->proc_chip_id)) - return be32_to_cpu(cinfo->xscom_id); + return get_xscom_id(cinfo); } /* Not found, what to do ? Assert ? For now return a number diff --git a/hdata/spira.h b/hdata/spira.h index 7da1154d7..3a8a31e1a 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -1096,6 +1096,9 @@ struct sppcrd_chip_info { #define CHIP_MAX_TOPOLOGY_ENTRIES 32 uint8_t topology_id_table[CHIP_MAX_TOPOLOGY_ENTRIES]; uint8_t primary_topology_loc; /* Index in topology_id_table */ + __be32 abc_bus_speed; /* SMP A */ + __be32 wxyz_bus_speed; /* SMP X */ + uint8_t fab_topology_id;/* topology id associated with the chip. */ } __packed; /* Idata index 1 : Chip TOD */ From patchwork Wed Aug 4 07:20:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513217 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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Wed, 04 Aug 2021 07:22:35 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747MWbD50200956 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:32 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F0218AE058; Wed, 4 Aug 2021 07:22:31 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA102AE051; Wed, 4 Aug 2021 07:22:30 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:30 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:56 +0530 Message-Id: <20210804072137.1147875-19-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: bcticQk5CSsEdE4atYg4Xg7EHefeYNcV X-Proofpoint-GUID: bcticQk5CSsEdE4atYg4Xg7EHefeYNcV X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 18/59] phys/P10: Use topology index to get phys mapping X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This fixes multipchip rainier boot issue. for Rainer: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x4>; chip2: ibm,primary-topology-index = < 0x8>; chip3: ibm,primary-topology-index = < 0xc>; for Denali: node0: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x1>; chip2: ibm,primary-topology-index = < 0x2>; chip3: ibm,primary-topology-index = < 0x3>; node1: chip0: ibm,primary-topology-index = < 0x4>; chip1: ibm,primary-topology-index = < 0x5>; chip2: ibm,primary-topology-index = < 0x6>; chip3: ibm,primary-topology-index = < 0x7>; Note that bmc_create_node() gets called very early in the boot process. Hence we have to traverse through HDAT ntuple to get right topology index. May be we can optimize pcid_to_topology_idx() function as its pretty much duplicate of pcid_to_chip_id(). But for now lets keep it as separate function. Signed-off-by: Vasant Hegde Signed-off-by: Ryan Grimm Signed-off-by: Vasant Hegde --- hdata/fsp.c | 4 +++- hdata/hdata.h | 1 + hdata/spira.c | 28 ++++++++++++++++++++++++++++ hw/phys-map.c | 18 ++++++++++++++++-- hw/test/phys-map-test.c | 7 ++++++- include/phys-map.h | 3 +++ 6 files changed, 57 insertions(+), 4 deletions(-) diff --git a/hdata/fsp.c b/hdata/fsp.c index 42f1121ab..30cda53f6 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -361,6 +361,7 @@ static void bmc_create_node(const struct HDIF_common_hdr *sp) struct dt_node *lpcm, *lpc, *n; u64 lpcm_base, lpcm_end; uint32_t chip_id; + uint32_t topology_idx; int size; bmc_node = dt_new(dt_root, "bmc"); @@ -399,8 +400,9 @@ static void bmc_create_node(const struct HDIF_common_hdr *sp) * phys map offset */ chip_id = pcid_to_chip_id(be32_to_cpu(iopath->lpc.chip_id)); + topology_idx = pcid_to_topology_idx(be32_to_cpu(iopath->lpc.chip_id)); - phys_map_get(chip_id, LPC_BUS, 0, &lpcm_base, NULL); + __phys_map_get(topology_idx, chip_id, LPC_BUS, 0, &lpcm_base, NULL); lpcm = dt_new_addr(dt_root, "lpcm-opb", lpcm_base); assert(lpcm); diff --git a/hdata/hdata.h b/hdata/hdata.h index bae4eaa58..6aad82932 100644 --- a/hdata/hdata.h +++ b/hdata/hdata.h @@ -24,6 +24,7 @@ extern void vpd_data_parse(struct dt_node *node, extern struct dt_node *find_xscom_for_chip(uint32_t chip_id); extern uint32_t pcid_to_chip_id(uint32_t proc_chip_id); +extern uint32_t pcid_to_topology_idx(uint32_t proc_chip_id); extern uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo); extern struct dt_node *add_core_common(struct dt_node *cpus, diff --git a/hdata/spira.c b/hdata/spira.c index 7d56f3f29..baa23751d 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1418,6 +1418,34 @@ uint32_t pcid_to_chip_id(uint32_t proc_chip_id) return (uint32_t)-1; } +uint32_t pcid_to_topology_idx(uint32_t proc_chip_id) +{ + unsigned int i; + const void *hdif; + + /* First, try the proc_chip ntuples for chip data */ + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL); + if (!CHECK_SPPTR(cinfo)) { + prerror("XSCOM: Bad ChipID data %d\n", i); + continue; + } + if (proc_chip_id == be32_to_cpu(cinfo->proc_chip_id)) { + if (proc_gen <= proc_gen_p9) + return get_xscom_id(cinfo); + else + return ((u32)cinfo->topology_id_table[cinfo->primary_topology_loc]); + } + } + + /* Not found, what to do ? Assert ? For now return a number + * guaranteed to not exist + */ + return (uint32_t)-1; +} /* Create '/ibm,opal/led' node */ static void dt_init_led_node(void) { diff --git a/hw/phys-map.c b/hw/phys-map.c index 2c4d8e45f..194e4953d 100644 --- a/hw/phys-map.c +++ b/hw/phys-map.c @@ -277,7 +277,7 @@ static inline bool phys_map_entry_null(const struct phys_map_entry *e) /* This crashes skiboot on error as any bad calls here are almost * certainly a developer error */ -void phys_map_get(uint64_t gcid, enum phys_map_type type, +void __phys_map_get(uint64_t topology_idx, uint64_t gcid, enum phys_map_type type, int index, uint64_t *addr, uint64_t *size) { const struct phys_map_entry *e; uint64_t a; @@ -302,7 +302,7 @@ void phys_map_get(uint64_t gcid, enum phys_map_type type, break; } a = e->addr; - a += gcid << phys_map->chip_select_shift; + a += topology_idx << (phys_map->chip_select_shift); if (addr) *addr = a; @@ -322,6 +322,20 @@ error: assert(0); } +void phys_map_get(uint64_t gcid, enum phys_map_type type, + int index, uint64_t *addr, uint64_t *size) +{ + struct proc_chip *chip; + uint64_t topology_idx = gcid; + + if (proc_gen >= proc_gen_p10) { + chip = get_chip(gcid); + topology_idx = chip->primary_topology; + } + + return __phys_map_get(topology_idx, gcid, type, index, addr, size); +} + void phys_map_init(unsigned long pvr) { const char *name = "unused"; diff --git a/hw/test/phys-map-test.c b/hw/test/phys-map-test.c index 2aabdb826..aa5b7339a 100644 --- a/hw/test/phys-map-test.c +++ b/hw/test/phys-map-test.c @@ -79,6 +79,11 @@ static inline bool map_call_entry_null(const struct map_call_entry *t) /* Pick a chip ID, any ID. */ #define FAKE_CHIP_ID 8 +struct proc_chip *get_chip(uint32_t chip_id __unused) +{ + return NULL; +} + static void check_map_call(void) { uint64_t start, size, end; @@ -98,7 +103,7 @@ static void check_map_call(void) /* Loop over table entries ... */ for (e = phys_map->table; !phys_map_entry_null(e); e++) { - phys_map_get(FAKE_CHIP_ID, e->type, e->index, &start, &size); + __phys_map_get(FAKE_CHIP_ID, FAKE_CHIP_ID, e->type, e->index, &start, &size); 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Wed, 04 Aug 2021 07:22:37 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747MYZn48890156 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:34 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EC653AE045; Wed, 4 Aug 2021 07:22:33 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8267DAE051; Wed, 4 Aug 2021 07:22:32 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:32 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:57 +0530 Message-Id: <20210804072137.1147875-20-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: LM7xGGECv3HJ51DDWivz772pEo3-NmP6 X-Proofpoint-ORIG-GUID: LM7xGGECv3HJ51DDWivz772pEo3-NmP6 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 19/59] hdata/iohub: Read PCI Gen5 equalization settings for P10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat HDAT spec added fields to define the equalization settings for PCI Gen5 link. Format is the same as PCI Gen4, so we just need to add extra fields in the "ibm,lane-eq" in the device tree. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hdata/iohub.c | 27 ++++++++++++++++++--------- hdata/spira.h | 8 +++++++- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/hdata/iohub.c b/hdata/iohub.c index fb215e1fb..92df48b8f 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -152,8 +152,8 @@ static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, { struct dt_node *stack; const char *compat; - u64 eq[8]; - u8 *gen4; + u64 eq[12]; + u8 *ptr; int i; stack = dt_new_addr(pbcq, "stack", stack_index); @@ -181,18 +181,27 @@ static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, eq[i] = be64_to_cpu(hub->phb_lane_eq[phb_index][i]); for (i = 0; i < 4; i++) /* gen 4 eq settings */ eq[i+4] = be64_to_cpu(hub->phb4_lane_eq[phb_index][i]); + for (i = 0; i < 4; i++) /* gen 5 eq settings */ + eq[i+8] = be64_to_cpu(hub->phb5_lane_eq[phb_index][i]); /* Lane-eq settings are packed 2 bytes per lane for 16 lanes - * On P9 DD2, 1 byte per lane is used in the hardware + * On P9 DD2 and P10, 1 byte per lane is used in the hardware */ - /* Repack 2 byte lane settings into 1 byte */ - gen4 = (u8 *)&eq[4]; - for (i = 0; i < 16; i++) - gen4[i] = gen4[2*i]; + /* Repack 2 byte lane settings into 1 byte for gen 4 & 5 */ + ptr = (u8 *)&eq[4]; + for (i = 0; i < 32; i++) + ptr[i] = ptr[2*i]; - dt_add_property_u64s(stack, "ibm,lane-eq", eq[0], eq[1], - eq[2], eq[3], eq[4], eq[5]); + if (proc_gen == proc_gen_p9) + dt_add_property_u64s(stack, "ibm,lane-eq", + eq[0], eq[1], eq[2], eq[3], + eq[4], eq[5]); + else + dt_add_property_u64s(stack, "ibm,lane-eq", + eq[0], eq[1], eq[2], eq[3], + eq[4], eq[5], + eq[6], eq[7]); return stack; } diff --git a/hdata/spira.h b/hdata/spira.h index 3a8a31e1a..7fcf5c302 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -706,8 +706,11 @@ struct cechub_io_hub { /* HDAT >= v9.x, HDIF version 0x6A adds phb_lane_eq with four * words per PHB (4 PHBs). * - * HDAT >= 10.x, HDIF version 0x7A adds space for another two + * HDAT >= 10.x, HDIF version 0x7A adds space for another * two PHBs (6 total) and the gen4 EQ values. + * + * HDAT >= 10.5x, HDIF version 0x8B adds space for the + * gen5 EQ values. */ struct { /* Gen 3 PHB eq values, 6 PHBs */ @@ -715,6 +718,9 @@ struct cechub_io_hub { /* Gen 4 PHB eq values */ __be64 phb4_lane_eq[6][4]; + + /* Gen 5 PHB eq values */ + __be64 phb5_lane_eq[6][4]; }; }; } __packed; From patchwork Wed Aug 4 07:20:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=ma0Jbpww; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GfjsN2Brdz9sX1 for ; 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Wed, 4 Aug 2021 07:22:35 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B9CFAE064; Wed, 4 Aug 2021 07:22:34 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:34 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:58 +0530 Message-Id: <20210804072137.1147875-21-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NaZIfLRvrTkwUg1SEJXhryGaEmf5CCHt X-Proofpoint-GUID: 68_sHosQ_NPJVm5Btjn87yN4u7TILB5w X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 20/59] prd: Add base P10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Signed-off-by: Oliver O'Halloran Signed-off-by: Vasant Hegde --- hw/prd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/prd.c b/hw/prd.c index 761d0a42b..45d765457 100644 --- a/hw/prd.c +++ b/hw/prd.c @@ -740,6 +740,11 @@ void prd_init(void) prd_ipoll_status_reg = PRD_P9_IPOLL_REG_STATUS; prd_ipoll_mask = PRD_P9_IPOLL_MASK; break; + case proc_gen_p10: /* IPOLL regs are the same for p9 and p10 */ + prd_ipoll_mask_reg = PRD_P9_IPOLL_REG_MASK; + prd_ipoll_status_reg = PRD_P9_IPOLL_REG_STATUS; + prd_ipoll_mask = PRD_P9_IPOLL_MASK; + break; default: assert(0); } From patchwork Wed Aug 4 07:20:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513220 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=GmtGtoJW; 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Wed, 4 Aug 2021 07:22:36 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:35 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:50:59 +0530 Message-Id: <20210804072137.1147875-22-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: QHC-TQWyByBpWTGuE64_PergKJMAnMyZ X-Proofpoint-ORIG-GUID: QHC-TQWyByBpWTGuE64_PergKJMAnMyZ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 21/59] hw/phys-map/p10: Add P10 MMIO map X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple , =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Alistair Popple Adds a phys map for P10 based on the MMIO spreadsheet. Also updates the phys map test to take a parameter which selects which map to test. - Introduce new BAR for the PC subengine of XIVE2 On P10, the NVP (Process) and NVG (Group) pages share the MMIO range. The even page gives access to the NVP structure and the odd page to the NVG structure. OPAL only uses the NVP. - Introduce new BARs for the VC subengine of XIVE2 On P10, the source ESB pages and END ESB pages have now their own MMIO range. - Increase the MMIO range for the END ESB pages The range was increased to 2TB to be able to address more END entries. We now have a maximum of 16M entries per chip. The END and ESB ranges are reordered for alignment. Signed-off-by: Alistair Popple Signed-off-by: Cédric Le Goater [Folded Cedric's patches - Vasant] Signed-off-by: Vasant Hegde --- hw/phys-map.c | 87 ++++++++++++++++++++++++++++++++++++++++- hw/test/phys-map-test.c | 18 +++++++-- include/phys-map.h | 6 ++- 3 files changed, 106 insertions(+), 5 deletions(-) diff --git a/hw/phys-map.c b/hw/phys-map.c index 194e4953d..b8fff0a4f 100644 --- a/hw/phys-map.c +++ b/hw/phys-map.c @@ -26,6 +26,84 @@ struct phys_map_info { static const struct phys_map_info *phys_map; +static const struct phys_map_entry phys_map_table_p10[] = { + /* System memory upto 4TB minus GPU memory */ + { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull }, + + /* TODO: Figure out GPU memory */ + + /* 0 TB offset @ MMIO 0x0006000000000000ull */ + { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull }, + { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull }, + { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull }, + { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull }, + { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull }, + { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull }, + { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull }, + { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull }, + { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull }, + { PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull }, + { PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull }, + { PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull }, + { PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull }, + { PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull }, + { PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull }, + { PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull }, + { PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull }, + { PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull }, + { PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull }, + { PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull }, + { PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull }, + { RESV , 0, 0x000600c3c0600000ull, 0x0000003c3fa00000ull }, + + /* 1 TB offset */ + { RESV , 1, 0x0006010000000000ull, 0x0000010000000000ull }, + + /* 2 TB offset */ + { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull }, + { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull }, + { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull }, + { RESV , 2, 0x000602c000000000ull, 0x0000004000000000ull }, + + /* 3 TB offset */ + { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull }, + { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull }, + { XIVE_IC , 0, 0x0006030200000000ull, 0x0000000002000000ull }, + { PSIHB_ESB , 0, 0x0006030202000000ull, 0x0000000000100000ull }, + { RESV , 3, 0x0006030202100000ull, 0x0000000000f00000ull }, + { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull }, + { RESV , 4, 0x0006030203100000ull, 0x0000000000080000ull }, + { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull }, + { RESV , 5, 0x00060302031c0000ull, 0x0000000000010000ull }, + { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull }, + { RESV , 6, 0x00060302031e0000ull, 0x0000000004e20000ull }, + { XIVE_NVC , 0, 0x0006030208000000ull, 0x0000000008000000ull }, + { RESV , 7, 0x0006030210000000ull, 0x00000000ee000000ull }, + { VAS_HYP_WIN , 0, 0x00060302fe000000ull, 0x0000000002000000ull }, + { VAS_USER_WIN , 0, 0x0006030300000000ull, 0x0000000100000000ull }, + + /* TODO: MC, OCMB, PAU */ + { RESV , 8, 0x0006030400000000ull, 0x000000f800000000ull }, + { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull }, + + /* 4 TB offset */ + { XIVE_NVPG , 0, 0x0006040000000000ull, 0x0000010000000000ull }, + + /* 5 - 7 TB offset */ + /* for P10 the END and ESB regions are separate in the MMIO + * table */ + { XIVE_ESB , 0, 0x0006050000000000ull, 0x0000010000000000ull }, + { XIVE_END , 0, 0x0006060000000000ull, 0x0000020000000000ull }, + + /* 8 - 13 TB offset */ + { RESV , 9, 0x0006080000000000ull, 0x0000060000000000ull }, + + /* 14 TB offset */ + { RESV ,10, 0x00060e0000000000ull, 0x0000008000000000ull }, + + { NULL_MAP, 0, 0, 0 }, +}; + static const struct phys_map_entry phys_map_table_nimbus[] = { /* System memory upto 4TB minus GPU memory */ @@ -266,6 +344,11 @@ static const struct phys_map_info phys_map_axone = { .table = phys_map_table_axone, }; +static const struct phys_map_info phys_map_p10 = { + .chip_select_shift = 44, + .table = phys_map_table_p10, +}; + static inline bool phys_map_entry_null(const struct phys_map_entry *e) { if (e->type == NULL_MAP) @@ -352,9 +435,11 @@ void phys_map_init(unsigned long pvr) name = "nimbus"; phys_map = &phys_map_nimbus; } + } else if (proc_gen == proc_gen_p10) { + name = "p10"; + phys_map = &phys_map_p10; } prlog(PR_DEBUG, "Assigning physical memory map table for %s\n", name); } - diff --git a/hw/test/phys-map-test.c b/hw/test/phys-map-test.c index aa5b7339a..d507175fe 100644 --- a/hw/test/phys-map-test.c +++ b/hw/test/phys-map-test.c @@ -172,14 +172,26 @@ static void check_map_call(void) unsigned long fake_pvr[] = { 0x004e0200, /* PVR_P9 */ 0x004f0100, /* PVR_P9P */ + 0x00800100, /* PVR_P10 */ }; int main(void) { - /* Fake we are POWER9 */ - proc_gen = proc_gen_p9; - for (int i = 0; i < ARRAY_SIZE(fake_pvr); i++) { + switch(PVR_TYPE(fake_pvr[i])) { + case PVR_TYPE_P9: + case PVR_TYPE_P9P: + proc_gen = proc_gen_p9; + break; + case PVR_TYPE_P10: + proc_gen = proc_gen_p10; + break; + default: + printf("Unknown PVR 0x%lx\n", fake_pvr[i]); + return 1; + break; + } + phys_map_init(fake_pvr[i]); /* Run tests */ diff --git a/include/phys-map.h b/include/phys-map.h index 97351a720..a3394c0d0 100644 --- a/include/phys-map.h +++ b/include/phys-map.h @@ -42,7 +42,11 @@ enum phys_map_type { MC_OCMB_CFG, MC_OCMB_MMIO, XSCOM, - RESV + RESV, + XIVE_NVC, + XIVE_NVPG, + XIVE_ESB, + XIVE_END, }; extern void phys_map_get(uint64_t gcid, enum phys_map_type type, From patchwork Wed Aug 4 07:21:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:22:42 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma02fra.de.ibm.com with ESMTP id 3a4x58qutj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Aug 2021 07:22:42 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747MdgP59310432 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:39 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 44F8DAE053; Wed, 4 Aug 2021 07:22:39 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 27E68AE059; Wed, 4 Aug 2021 07:22:38 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:37 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:00 +0530 Message-Id: <20210804072137.1147875-23-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: qd87v2DIXEi9N9ttYWGMn9OTB2KYan17 X-Proofpoint-GUID: qd87v2DIXEi9N9ttYWGMn9OTB2KYan17 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=859 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 22/59] VAS: Define Remote Memory Access paste address on P10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni Paste base address format is changed on p10. Instead of node/chip IDs, Primary topology index is used to define paste base address. Also RA(11) bit is used to define the foreign address. Changes to define the paste base address for each VAS engine with the new format on P10. Signed-off-by: Haren Myneni Signed-off-by: Vasant Hegde --- hw/vas.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/vas.c b/hw/vas.c index 393ad801e..c9639831f 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -160,6 +160,11 @@ static void reset_fir(struct proc_chip *chip) #define P9_RMA_LSMP_64K_SYS_ID PPC_BITMASK(8, 12) #define P9_RMA_LSMP_64K_NODE_ID PPC_BITMASK(15, 18) #define P9_RMA_LSMP_64K_CHIP_ID PPC_BITMASK(19, 21) + +/* Paste base address format (on P10 or later) */ +#define RMA_FOREIGN_ADDR_ENABLE PPC_BITMASK(8, 11) +#define RMA_TOPOLOGY_INDEX PPC_BITMASK(15, 19) + #define RMA_LSMP_WINID_START_BIT 32 #define RMA_LSMP_WINID_NUM_BITS 16 @@ -221,6 +226,59 @@ static void p9_get_rma_bar(int chipid, uint64_t *val) *val = v; } +/* + * The start/base of the paste BAR is computed using the tables 1.1 through + * 1.3 in Section 1.3.3.1 (Send Message w/Paste Commands (cl_rma_w)) of VAS + * P10 Workbook. + * + * With 64K mode and Large SMP Mode the bits are used as follows: + * + * Bits Values Comments + * -------------------------------------- + * 0:7 0b 0000_0000 Reserved + * 8:11 0b 0001 Foreign Address Enable + * 12 0b 0 SMF + * 13:14 0b 00 Memory Select + * + * 15:19 0 throuh 16 Topology Index + * 20:23 0b 0000 Chip Internal Address + * + * 24:31 0b 0000_0000 RPN 0:7, Reserved + * 32:47 0 through 64K Send Window Id + * 48:51 0b 0000 Spare + * + * 52 0b 0 Reserved + * 53 0b 1 Report Enable (Set to 1 for NX). + * 54 0b 0 Reserved + * + * 55:56 0b 00 Snoop Bus + * 57:63 0b 0000_000 Reserved + * + * Example: For Node 0, Chip 0, Window id 4, Report Enable 1: + * + * Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 + * 00000000 00010000 00000000 00000000 00000000 00000100 00000100 00000000 + * | | | | | + * +---+ +-------+-------+ v + * | | Report Enable + * v v + * Topology Index Window id 4 + * + * Thus the paste address for window id 4 is 0x00100000_00040400 and + * the _base_ paste address for Node 0 Chip 0 is 0x00100000_00000000. + */ + +static void get_rma_bar(struct proc_chip *chip, uint64_t *val) +{ + uint64_t v; + + v = 0ULL; + v = SETFIELD(RMA_FOREIGN_ADDR_ENABLE, v, 1); + v = SETFIELD(RMA_TOPOLOGY_INDEX, v, chip->primary_topology); + + *val = v; +} + /* * Initialize RMA BAR on this chip to correspond to its node/chip id. * This will cause VAS to accept paste commands to targeted for this chip. @@ -231,7 +289,10 @@ static int init_rma(struct proc_chip *chip) int rc; uint64_t val; - p9_get_rma_bar(chip->id, &val); + if (proc_gen == proc_gen_p9) + p9_get_rma_bar(chip->id, &val); + else + get_rma_bar(chip, &val); rc = vas_scom_write(chip, VAS_RMA_BAR, val); if (rc) @@ -271,9 +332,18 @@ static int init_rma(struct proc_chip *chip) static inline void get_paste_bar(int chipid, uint64_t *start, uint64_t *len) { + struct proc_chip *chip; uint64_t val; - p9_get_rma_bar(chipid, &val); + if (proc_gen == proc_gen_p9) + p9_get_rma_bar(chipid, &val); + else { + chip = get_chip(chipid); + if (!chip) + return; + + get_rma_bar(chip, &val); + } *start = val; *len = VAS_PASTE_BAR_LEN; @@ -394,8 +464,8 @@ static void create_mm_dt_node(struct proc_chip *chip) struct vas *vas; uint64_t hvwc_start, hvwc_len; uint64_t uwc_start, uwc_len; - uint64_t pbar_start, pbar_len; uint64_t pbf_start, pbf_nbits; + uint64_t pbar_start = 0, pbar_len = 0; vas = chip->vas; get_hvwc_mmio_bar(chip->id, &hvwc_start, &hvwc_len); From patchwork Wed Aug 4 07:21:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=r6RGTTxk; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gfjsg0NK4z9sWq for ; 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Wed, 4 Aug 2021 07:22:39 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:39 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:01 +0530 Message-Id: <20210804072137.1147875-24-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: HK013VHOpfuzVGomS1NxaV0wEB8Vv1QY X-Proofpoint-GUID: HK013VHOpfuzVGomS1NxaV0wEB8Vv1QY X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 23/59] VAS: Enable VAS on P10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni Enable VAS on P10 based on "ibm,power10-vas-x" compatible string and export the new compatible property to kernel. Also do not set foreign address enable for VAS/NX RMA BAR From section 1.3.3.1 in VAS workbook, RA(0:12) = 0's for VAS/NX RMA BAR. It means foreign address enable bit (RA(11) should be 0 for RMA VAR. But this bit has to be set for paste base address which is used for COPY/PASTE. Signed-off-by: Haren Myneni Signed-off-by: Vasant Hegde --- hw/vas.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/vas.c b/hw/vas.c index c9639831f..274008665 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -266,6 +266,9 @@ static void p9_get_rma_bar(int chipid, uint64_t *val) * * Thus the paste address for window id 4 is 0x00100000_00040400 and * the _base_ paste address for Node 0 Chip 0 is 0x00100000_00000000. + * + * Note: Bit 11 (Foreign Address Enable) is set only for paste base address. + * Not for VAS/NX RMA BAR. RA(0:12) = 0 for VAS/NX RMA BAR. */ static void get_rma_bar(struct proc_chip *chip, uint64_t *val) @@ -273,7 +276,6 @@ static void get_rma_bar(struct proc_chip *chip, uint64_t *val) uint64_t v; v = 0ULL; - v = SETFIELD(RMA_FOREIGN_ADDR_ENABLE, v, 1); v = SETFIELD(RMA_TOPOLOGY_INDEX, v, chip->primary_topology); *val = v; @@ -343,6 +345,12 @@ static inline void get_paste_bar(int chipid, uint64_t *start, uint64_t *len) return; get_rma_bar(chip, &val); + + /* + * RA(11) (Foreign Address Enable) is set only for paste + * base address. + */ + val = SETFIELD(RMA_FOREIGN_ADDR_ENABLE, val, 1); } *start = val; @@ -462,6 +470,7 @@ static void create_mm_dt_node(struct proc_chip *chip) { struct dt_node *dn; struct vas *vas; + const char *compat; uint64_t hvwc_start, hvwc_len; uint64_t uwc_start, uwc_len; uint64_t pbf_start, pbf_nbits; @@ -473,9 +482,14 @@ static void create_mm_dt_node(struct proc_chip *chip) get_paste_bar(chip->id, &pbar_start, &pbar_len); get_paste_bitfield(&pbf_start, &pbf_nbits); + if (proc_gen == proc_gen_p9) + compat = "ibm,power9-vas"; + else + compat = "ibm,power10-vas"; + dn = dt_new_addr(dt_root, "vas", hvwc_start); - dt_add_property_strings(dn, "compatible", "ibm,power9-vas", + dt_add_property_strings(dn, "compatible", compat, "ibm,vas"); dt_add_property_u64s(dn, "reg", hvwc_start, hvwc_len, @@ -579,13 +593,18 @@ void vas_init(void) { bool enabled; struct dt_node *np; + const char *compat; - if (proc_gen != proc_gen_p9) + if (proc_gen == proc_gen_p9) + compat = "ibm,power9-vas-x"; + else if (proc_gen == proc_gen_p10) + compat = "ibm,power10-vas-x"; + else return; enabled = vas_nx_enabled(); - dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { + dt_for_each_compatible(dt_root, np, compat) { if (init_vas_inst(np, enabled)) goto out; } @@ -594,7 +613,7 @@ void vas_init(void) return; out: - dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") + dt_for_each_compatible(dt_root, np, compat) disable_vas_inst(np); vas_err("Disabled (failed initialization)\n"); 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Wed, 4 Aug 2021 07:22:41 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:41 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:02 +0530 Message-Id: <20210804072137.1147875-25-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ArlqNem89KUWDh5zEwA6Qw4LZ6QCCDhY X-Proofpoint-GUID: ArlqNem89KUWDh5zEwA6Qw4LZ6QCCDhY X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 24/59] NX: Set VAS RMA write BAR register on P10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni For each NX instance, VAS RMA write BAR register should be set with the corresponding VAS RMA BAR value. Refer section: 5.30 VAS RMA write BAR (P10 NX work Book V1.01) Signed-off-by: Haren Myneni Signed-off-by: Vasant Hegde --- hw/nx-compress.c | 36 ++++++++++++++++++++++++++++++++++++ hw/vas.c | 18 ++++++++++++++++++ include/nx.h | 3 +++ include/vas.h | 1 + 4 files changed, 58 insertions(+) diff --git a/hw/nx-compress.c b/hw/nx-compress.c index b2302866b..9b3c6717d 100644 --- a/hw/nx-compress.c +++ b/hw/nx-compress.c @@ -115,6 +115,30 @@ static int nx_cfg_umac_status_ctrl(u32 gcid, u64 xcfg) return rc; } +static int nx_cfg_vas_rma_bar(u32 gcid, u64 xcfg) +{ + int rc = 0; + u64 cfg; + + cfg = vas_get_rma_bar(gcid); + /* + * NOTE: Write the entire bar address to SCOM. VAS/NX will extract + * the relevant (NX_P10_VAS_RMA_WRITE_BAR) bits. IOW, _don't_ + * just write the bit field like: + * cfg = SETFIELD(NX_P10_VAS_RMA_WRITE_BAR, 0ULL, cfg); + */ + rc = xscom_write(gcid, xcfg, cfg); + + if (rc) + prerror("NX%d: ERROR: VAS RMA WRITE BAR, %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: VAS RMA WRITE BAR, 0x%016lx, " + "xcfg 0x%llx\n", gcid, (unsigned long)cfg, + xcfg); + + return rc; +} + int nx_cfg_rx_fifo(struct dt_node *node, const char *compat, const char *priority, u32 gcid, u32 pid, u32 tid, u64 umac_bar, u64 umac_notify) @@ -272,6 +296,10 @@ void nx_create_compress_node(struct dt_node *node) prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base); + /* + * ibm,power9-nx is compatible on P10. So using same + * compatible string. + */ if (dt_node_is_compatible(node, "ibm,power9-nx")) { u64 cfg_mmio, cfg_txwc, cfg_uctrl, cfg_dma; @@ -297,6 +325,14 @@ void nx_create_compress_node(struct dt_node *node) if (rc) return; + if (proc_gen > proc_gen_p9) { + u64 cfg_rma = pb_base + NX_P10_VAS_RMA_WRITE_BAR; + + rc = nx_cfg_vas_rma_bar(gcid, cfg_rma); + if (rc) + return; + } + p9_nx_enable_842(node, gcid, pb_base); p9_nx_enable_gzip(node, gcid, pb_base); } else diff --git a/hw/vas.c b/hw/vas.c index 274008665..0dbe0bcda 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -281,6 +281,24 @@ static void get_rma_bar(struct proc_chip *chip, uint64_t *val) *val = v; } +/* Interface for NX - make sure VAS is fully initialized first */ +__attrconst uint64_t vas_get_rma_bar(int chipid) +{ + struct proc_chip *chip; + uint64_t addr; + + if (!vas_initialized) + return 0ULL; + + chip = get_chip(chipid); + if (!chip) + return 0ULL; + + get_rma_bar(chip, &addr); + + return addr; +} + /* * Initialize RMA BAR on this chip to correspond to its node/chip id. * This will cause VAS to accept paste commands to targeted for this chip. diff --git a/include/nx.h b/include/nx.h index 5734e24a3..c42d165e9 100644 --- a/include/nx.h +++ b/include/nx.h @@ -141,6 +141,9 @@ #define NX_P9_ERAT_STATUS_CTRL NX_P9_SAT(0x3, 0x16) +/* Introduced in P10, but P10 NX SCOM address is same as P9 */ +#define NX_P10_VAS_RMA_WRITE_BAR NX_P9_SAT(0x3, 0x19) + /* NX Status Register */ #define NX_P8_STATUS NX_P8_SAT(0x1, 0x00) #define NX_P9_STATUS NX_P9_SAT(0x1, 0x00) /* DMA Status register */ diff --git a/include/vas.h b/include/vas.h index 369c3807a..1f59b1d9c 100644 --- a/include/vas.h +++ b/include/vas.h @@ -27,6 +27,7 @@ extern void vas_init(void); extern __attrconst bool vas_nx_enabled(void); extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); extern __attrconst uint64_t vas_get_wcbs_bar(int chipid); +extern __attrconst uint64_t vas_get_rma_bar(int chipid); /* * HVWC and UWC BAR. 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Wed, 4 Aug 2021 07:22:43 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:42 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:03 +0530 Message-Id: <20210804072137.1147875-26-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: i6oz5XdgcSsTcen--dJqnWN_SYsfA-81 X-Proofpoint-GUID: i6oz5XdgcSsTcen--dJqnWN_SYsfA-81 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 25/59] hw/nx: Enable p10 DARN X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ryan Grimm Init and enable NCU DARN BAR on sibling cores as well for fused core mode. Signed-off-by: Ryan Grimm Signed-off-by: Vaidyanathan Srinivasan [Folded Vaidy's fused core support fix - Vasant] Signed-off-by: Vasant Hegde --- hw/nx.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/hw/nx.c b/hw/nx.c index 122048087..fdadf53c7 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -12,11 +12,12 @@ #include #include #include +#include #include #include #include -static void p9_darn_init(void) +static void darn_init(void) { struct dt_node *nx; struct proc_chip *chip; @@ -45,11 +46,25 @@ static void p9_darn_init(void) for_each_available_core_in_chip(c, chip->id) { uint64_t addr; - addr = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir), + + if (proc_gen == proc_gen_p9) { + addr = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir), P9X_EX_NCU_DARN_BAR); - xscom_write(chip->id, addr, + xscom_write(chip->id, addr, bar | P9X_EX_NCU_DARN_BAR_EN); - + } else if (proc_gen >= proc_gen_p10) { + addr = XSCOM_ADDR_P10_NCU(pir_to_core_id(c->pir), + P10_NCU_DARN_BAR); + xscom_write(chip->id, addr, + bar | P10_NCU_DARN_BAR_EN); + /* Init for sibling core also */ + if (c->is_fused_core) { + addr = XSCOM_ADDR_P10_NCU(pir_to_core_id(c->pir + 1), + P10_NCU_DARN_BAR); + xscom_write(chip->id, addr, + bar | P10_NCU_DARN_BAR_EN); + } + } } } } @@ -59,7 +74,7 @@ void nx_p9_rng_late_init(void) struct cpu_thread *c; uint64_t rc; - if (proc_gen != proc_gen_p9) + if (proc_gen < proc_gen_p9) return; if (chip_quirk(QUIRK_NO_RNG)) return; @@ -118,6 +133,6 @@ void nx_init(void) nx_init_one(node); } - if (proc_gen == proc_gen_p9) - p9_darn_init(); + if (proc_gen >= proc_gen_p9) + darn_init(); } From patchwork Wed Aug 4 07:21:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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Wed, 04 Aug 2021 07:22:48 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747Mk3M32637296 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:46 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E62CAE04D; Wed, 4 Aug 2021 07:22:46 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E0F11AE05D; Wed, 4 Aug 2021 07:22:44 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:44 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:04 +0530 Message-Id: <20210804072137.1147875-27-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MsV9aZlKKODYD9pCwS0S5-_snA3nl1ox X-Proofpoint-ORIG-GUID: MsV9aZlKKODYD9pCwS0S5-_snA3nl1ox X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 26/59] hw/imc: Power10 support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Anju T Sudhakar POWER10 IMC support: Add POWER10 scom addresses for IMC Add support for IMC trace-mode Fix the catalog subit for POWER10 Signed-off-by: Anju T Sudhakar Signed-off-by: Madhavan Srinivasan Signed-off-by: Vasant Hegde --- hw/fsp/fsp.c | 5 +++++ hw/imc.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------- include/imc.h | 2 ++ 3 files changed, 58 insertions(+), 10 deletions(-) diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 70452cf98..2c5f9d71b 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -2373,6 +2373,9 @@ int fsp_fetch_data_queue(uint8_t flags, uint16_t id, uint32_t sub_id, #define CAPP_IDX_NIMBUS_DD23 0x203d1 #define IMA_CATALOG_NIMBUS 0x4e0200 +#define IMA_CATALOG_P10_DD1 0x800100 +#define IMA_CATALOG_P10_DD2 0x800200 + static struct { enum resource_id id; @@ -2392,6 +2395,8 @@ static struct { { RESOURCE_ID_CAPP, CAPP_IDX_NIMBUS_DD21, 0x80a02007 }, { RESOURCE_ID_CAPP, CAPP_IDX_NIMBUS_DD22, 0x80a02007 }, { RESOURCE_ID_CAPP, CAPP_IDX_NIMBUS_DD23, 0x80a02007 }, + { RESOURCE_ID_IMA_CATALOG,IMA_CATALOG_P10_DD1, 0x80f00103 }, + { RESOURCE_ID_IMA_CATALOG,IMA_CATALOG_P10_DD2, 0x80f00103 }, }; static void fsp_start_fetching_next_lid(void); diff --git a/hw/imc.c b/hw/imc.c index 7d29ce6f7..cbd68edc4 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -170,6 +170,20 @@ static unsigned int htm_scom_index_p9[] = { 0x10012700 }; +static unsigned int pdbar_scom_index_p10[] = { + 0x2001868B, + 0x2001468B, + 0x2001268B, + 0x2001168B +}; + +static unsigned int htm_scom_index_p10[] = { + 0x20018680, + 0x20014680, + 0x20012680, + 0x20011680 +}; + static struct imc_chip_cb *get_imc_cb(uint32_t chip_id) { struct proc_chip *chip = get_chip(chip_id); @@ -263,13 +277,23 @@ static bool is_imc_device_type_supported(struct dt_node *node) if (val == IMC_COUNTER_TRACE) { pvr = mfspr(SPR_PVR); - /* - * Trace mode is supported in Nimbus DD2.2 - * and later versions. - */ - if ((chip->type == PROC_CHIP_P9_NIMBUS) && - (PVR_VERS_MAJ(pvr) == 2) && (PVR_VERS_MIN(pvr) >= 2)) + + switch (chip->type) { + case PROC_CHIP_P9_NIMBUS: + /* + * Trace mode is supported in Nimbus DD2.2 + * and later versions. + */ + if ((PVR_VERS_MAJ(pvr) == 2) && + (PVR_VERS_MIN(pvr) >= 2)) + return true; + break; + case PROC_CHIP_P10: return true; + default: + return false; + } + } return false; } @@ -453,8 +477,8 @@ void imc_catalog_preload(void) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return; - /* Enable only for power 9 */ - if (proc_gen != proc_gen_p9) + /* Enable only for power 9/10 */ + if (proc_gen < proc_gen_p9) return; compress_buf = malloc(MAX_COMPRESSED_IMC_DTB_SIZE); @@ -559,6 +583,17 @@ static int setup_imc_scoms(void) IMC_TRACE_CPMC2SEL_VAL, IMC_TRACE_BUFF_SIZE); return 0; + case proc_gen_p10: + CORE_IMC_EVENT_MASK_ADDR = CORE_IMC_EVENT_MASK_ADDR_P10; + TRACE_IMC_ADDR = TRACE_IMC_ADDR_P10; + pdbar_scom_index = pdbar_scom_index_p10; + htm_scom_index = htm_scom_index_p10; + trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_CPMC1, + IMC_TRACE_CPMCLOAD_VAL, + IMC_TRACE_CPMC1SEL_VAL, + IMC_TRACE_CPMC2SEL_VAL, + IMC_TRACE_BUFF_SIZE); + return 0; default: prerror("%s: Unknown cpu type\n", __func__); break; @@ -586,8 +621,8 @@ void imc_init(void) goto imc_mambo; } - /* Enable only for power 9 */ - if (proc_gen != proc_gen_p9) + /* Enable only for power 9/10 */ + if (proc_gen < proc_gen_p9) return; if (!imc_xz) @@ -720,6 +755,9 @@ static uint32_t get_imc_scom_addr_for_core(int core, uint64_t addr) case proc_gen_p9: scom_addr = XSCOM_ADDR_P9_EC(core, addr); return scom_addr; + case proc_gen_p10: + scom_addr = XSCOM_ADDR_P10_EC(core, addr); + return scom_addr; default: return 0; } @@ -734,6 +772,9 @@ static uint32_t get_imc_scom_addr_for_quad(int core, uint64_t addr) case proc_gen_p9: scom_addr = XSCOM_ADDR_P9_EQ(core, addr); return scom_addr; + case proc_gen_p10: + scom_addr = XSCOM_ADDR_P10_EQ(core, addr); + return scom_addr; default: return 0; } diff --git a/include/imc.h b/include/imc.h index a446dc581..96f9ec4b6 100644 --- a/include/imc.h +++ b/include/imc.h @@ -110,6 +110,7 @@ struct imc_chip_cb * Core IMC SCOMs */ #define CORE_IMC_EVENT_MASK_ADDR_P9 0x20010AA8ull +#define CORE_IMC_EVENT_MASK_ADDR_P10 0x20020400ull #define CORE_IMC_EVENT_MASK 0x0402010000000000ull #define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull #define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull @@ -133,6 +134,7 @@ struct imc_chip_cb * *CPMC1SEL *CPMC2SEL *BUFFERSIZE */ #define TRACE_IMC_ADDR_P9 0x20010AA9ull +#define TRACE_IMC_ADDR_P10 0x20020401ull #define TRACE_IMC_SAMPLESEL(x) ((uint64_t)x << 62) #define TRACE_IMC_CPMC_LOAD(x) ((0xffffffff - (uint64_t)x) << 30) #define TRACE_IMC_CPMC1SEL(x) ((uint64_t)x << 23) From patchwork Wed Aug 4 07:21:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513226 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:22:51 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma03ams.nl.ibm.com with ESMTP id 3a4x590r5d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Aug 2021 07:22:51 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747MlAC7012686 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:47 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B73DCAE063; Wed, 4 Aug 2021 07:22:47 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FB7CAE05D; Wed, 4 Aug 2021 07:22:46 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:46 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:05 +0530 Message-Id: <20210804072137.1147875-28-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 2De3Z1GZNEmJLaUPL9V2L3_i_0URypqM X-Proofpoint-GUID: 2De3Z1GZNEmJLaUPL9V2L3_i_0URypqM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 27/59] platforms/astbmc: Add ast2600 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Reza Arbab Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Reza Arbab Signed-off-by: Reza Arbab Signed-off-by: Vasant Hegde --- platforms/astbmc/astbmc.h | 2 ++ platforms/astbmc/common.c | 19 +++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/platforms/astbmc/astbmc.h b/platforms/astbmc/astbmc.h index 86631bc4e..00f221230 100644 --- a/platforms/astbmc/astbmc.h +++ b/platforms/astbmc/astbmc.h @@ -87,9 +87,11 @@ static struct slot_table_entry st_name[] = \ extern const struct bmc_hw_config bmc_hw_ast2400; extern const struct bmc_hw_config bmc_hw_ast2500; +extern const struct bmc_hw_config bmc_hw_ast2600; extern const struct bmc_platform bmc_plat_ast2400_ami; extern const struct bmc_platform bmc_plat_ast2500_ami; extern const struct bmc_platform bmc_plat_ast2500_openbmc; +extern const struct bmc_platform bmc_plat_ast2600_openbmc; extern void astbmc_early_init(void); extern int64_t astbmc_ipmi_reboot(void); diff --git a/platforms/astbmc/common.c b/platforms/astbmc/common.c index d96e070e5..83ef70ad3 100644 --- a/platforms/astbmc/common.c +++ b/platforms/astbmc/common.c @@ -266,8 +266,9 @@ static void astbmc_fixup_dt_mbox(struct dt_node *lpc) * can indicate they support mbox using the scratch register, or ipmi * by configuring the hiomap ipmi command. If neither are configured * for P8 then skiboot will drive the flash controller directly. + * XXX P10 */ - if (proc_gen != proc_gen_p9 && !ast_scratch_reg_is_mbox()) + if (proc_gen == proc_gen_p8 && !ast_scratch_reg_is_mbox()) return; /* First check if the mbox interface is already there */ @@ -478,7 +479,7 @@ void astbmc_early_init(void) * never MBOX. Thus only populate the MBOX node on P9 to allow * fallback. */ - if (proc_gen == proc_gen_p9) { + if (proc_gen >= proc_gen_p9) { astbmc_fixup_dt_mbox(dt_find_primary_lpc()); ast_setup_sio_mbox(MBOX_IO_BASE, MBOX_LPC_IRQ); } @@ -530,6 +531,14 @@ const struct bmc_hw_config bmc_hw_ast2500 = { .mcr_scu_strap = 0x00000000, }; +/* XXX P10: Update with Rainier values */ +const struct bmc_hw_config bmc_hw_ast2600 = { + .scu_revision_id = 0x05000303, + .mcr_configuration = 0x11200756, + .mcr_scu_mpll = 0x1008405F, + .mcr_scu_strap = 0x000030E0, +}; + const struct bmc_platform bmc_plat_ast2400_ami = { .name = "ast2400:ami", .hw = &bmc_hw_ast2400, @@ -547,3 +556,9 @@ const struct bmc_platform bmc_plat_ast2500_openbmc = { .hw = &bmc_hw_ast2500, .sw = &bmc_sw_openbmc, }; + +const struct bmc_platform bmc_plat_ast2600_openbmc = { + .name = "ast2600:openbmc", + .hw = &bmc_hw_ast2600, + .sw = &bmc_sw_openbmc, +}; From patchwork Wed Aug 4 07:21:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:22:48 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:47 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:06 +0530 Message-Id: <20210804072137.1147875-29-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: xWYSk6zLcHVegaZX7TtJspQBY5LtKnTw X-Proofpoint-ORIG-GUID: UrqRbY9N-ne9DpoIA0dF9C5ySBuCx_jv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 28/59] platforms: Add Rainier X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple , Reza Arbab Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Alistair Popple Rainier comes in two variants; 4U and 2U. PCIe slot power on from oohall with multi-socket support from fbarrat: On Rainier the PCIe slots have individual slot power controllers. These need to be enabled at boot so that we can scan the devices in the PHB root ports. This should really be integrated into the OPAL slot power control framework that was used for PCIe Hotplug support on Frienze (P8 FSP systems). Unfortunately, the way that is implemented is difficult to extend at best and needs to be refactored before we can add support for runtime power control on rainier. Signed-off-by: Alistair Popple Signed-off-by: Oliver O'Halloran Signed-off-by: Frederic Barrat [arbab@linux.ibm.com: Use bmc_plat_ast2600_openbmc] Signed-off-by: Reza Arbab Signed-off-by: Vasant Hegde --- platforms/astbmc/Makefile.inc | 3 +- platforms/astbmc/rainier.c | 136 ++++++++++++++++++++++++++++++++++ 2 files changed, 137 insertions(+), 2 deletions(-) create mode 100644 platforms/astbmc/rainier.c diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 24e94039f..070813231 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -7,8 +7,7 @@ ASTBMC_OBJS = pnor.o common.o slots.o \ witherspoon.o zaius.o romulus.o p9dsu.o \ vesnin.o nicole.o mihawk.o mowgli.o \ talos.o blackbird.o \ - swift.o + swift.o rainier.o ASTBMC = $(PLATDIR)/astbmc/built-in.a $(ASTBMC): $(ASTBMC_OBJS:%=$(PLATDIR)/astbmc/%) - diff --git a/platforms/astbmc/rainier.c b/platforms/astbmc/rainier.c new file mode 100644 index 000000000..17d9fe2bf --- /dev/null +++ b/platforms/astbmc/rainier.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (c) 2020 IBM + */ + +#include +#include +#include +#include +#include +#include + +#include "astbmc.h" + +/* + * puti2c pu 2 1 C6 00 6 1 -quiet + * puti2c pu 2 1 C6 54 7 1 -quiet + * puti2c pu 2 1 C6 05 8 1 -quiet + * puti2c pu 2 1 C6 00 9 1 -quiet + * + * sleep 4 + * + * puti2c pu 2 1 C6 55 6 1 -quiet + * puti2c pu 2 1 C6 55 7 1 -quiet + * 2 - engine + * 1 - port + * C6 - slave addr + * 55 - data + * 7 - register + * 1 - register length? + */ + +static int64_t smbus_write8(struct i2c_bus *bus, uint8_t reg, uint8_t data) +{ + struct i2c_request req; + + memset(&req, 0, sizeof(req)); + + req.bus = bus; + req.dev_addr = 0xC6 >> 1; /* Docs use 8bit addresses */ + + req.op = SMBUS_WRITE; + req.offset = reg; + req.offset_bytes = 1; + req.rw_buf = &data; + req.rw_len = 1; + req.timeout = 100; + + return i2c_request_sync(&req); +} + +static int64_t slot_power_enable(struct i2c_bus *bus) +{ + /* FIXME: we could do this in one transaction using auto-increment */ + if (smbus_write8(bus, 0x6, 0x00)) + return -1; + if (smbus_write8(bus, 0x7, 0x54)) + return -1; + if (smbus_write8(bus, 0x8, 0x05)) + return -1; + if (smbus_write8(bus, 0x9, 0x00)) + return -1; + + /* FIXME: Poll for PGOOD going high */ + + if (smbus_write8(bus, 0x6, 0x55)) + return -1; + if (smbus_write8(bus, 0x7, 0x55)) + return -1; + + return 0; +} + +static void rainier_init_slot_power(void) +{ + struct proc_chip *chip; + struct i2c_bus *bus; + + /* + * Controller on P0 is for slots C7 -> C11 + * on P2 is for slots C0 -> C4 + * Both chips use engine 2 port 1 + * + * Rainier with only one socket is officially supported, so + * we may not have slots C0 -> C4 + */ + for_each_chip(chip) { + if (chip->id % 4) + continue; + bus = p8_i2c_add_bus(chip->id, 2, 1, 400000); + if (!bus) { + prerror("Unable to find PCIe power controller I2C bus!\n"); + return; + } + if (slot_power_enable(bus)) { + prerror("Error enabling PCIe slot power on chip %d\n", + chip->id); + } + } +} + +static void rainier_init(void) +{ + astbmc_init(); + rainier_init_slot_power(); +} + +static bool rainier_probe(void) +{ + if (!dt_node_is_compatible(dt_root, "ibm,rainier") && + !dt_node_is_compatible(dt_root, "ibm,rainier-2s2u") && + !dt_node_is_compatible(dt_root, "ibm,rainier-2s4u")) + return false; + + /* Lot of common early inits here */ + astbmc_early_init(); + + /* Setup UART for use by OPAL (Linux hvc) */ + uart_set_console_policy(UART_CONSOLE_OPAL); + + return true; +} + +DECLARE_PLATFORM(rainier) = { + .name = "Rainier", + .probe = rainier_probe, + .init = rainier_init, + .start_preload_resource = flash_start_preload_resource, + .resource_loaded = flash_resource_loaded, + .bmc = &bmc_plat_ast2600_openbmc, + .cec_power_down = astbmc_ipmi_power_down, + .cec_reboot = astbmc_ipmi_reboot, + .elog_commit = ipmi_elog_commit, + .exit = astbmc_exit, + .terminate = ipmi_terminate, +}; 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Wed, 4 Aug 2021 07:22:50 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:50 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:07 +0530 Message-Id: <20210804072137.1147875-30-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: IBAj_0KOMKNRO3dwSZhSaWOBardKwzoJ X-Proofpoint-GUID: IBAj_0KOMKNRO3dwSZhSaWOBardKwzoJ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 29/59] platform: Add Denali platform support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Denali is P10 system. But FSP interaction (MBOX protocol) is same as ZZ. Hence add denali platform detection code inside zz.c for now. We can think of adding separate platform later. Also enable : - P10 TCE mapping support - Detect PHBs Signed-off-by: Vasant Hegde --- hdata/iohub.c | 4 ++++ hdata/spira.h | 1 + hw/fsp/fsp-psi.c | 1 + platforms/ibm-fsp/hostservices.c | 4 ++++ platforms/ibm-fsp/zz.c | 6 ++++++ 5 files changed, 16 insertions(+) diff --git a/hdata/iohub.c b/hdata/iohub.c index 92df48b8f..92655407e 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -843,6 +843,10 @@ static void io_parse_fru(const void *sp_iohubs) prlog(PR_INFO, "CEC: Rainier !\n"); io_add_p9(hub, sp_iohubs); break; + case CECHUB_HUB_DENALI: + prlog(PR_INFO, "CEC: Denali !\n"); + io_add_p9(hub, sp_iohubs); + break; default: prlog(PR_ERR, "CEC: Hub ID 0x%04x unsupported !\n", hub_id); diff --git a/hdata/spira.h b/hdata/spira.h index 7fcf5c302..afdc9228a 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -667,6 +667,7 @@ struct cechub_io_hub { #define CECHUB_HUB_CUMULUS_DUOMO 0x0030 /* cumulus+duomo from spec */ #define CECHUB_HUB_AXONE_HOPPER 0x0040 /* axone+hopper */ #define CECHUB_HUB_RAINIER 0x0050 +#define CECHUB_HUB_DENALI 0x0051 __be32 ec_level; __be32 aff_dom2; /* HDAT < v9.x only */ __be32 aff_dom3; /* HDAT < v9.x only */ diff --git a/hw/fsp/fsp-psi.c b/hw/fsp/fsp-psi.c index aeaf47e89..38f130dd7 100644 --- a/hw/fsp/fsp-psi.c +++ b/hw/fsp/fsp-psi.c @@ -37,6 +37,7 @@ void psi_init_for_fsp(struct psi *psi) switch (proc_gen) { case proc_gen_p8: case proc_gen_p9: + case proc_gen_p10: out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE | PSIHB_TAR_256K_ENTRIES); break; diff --git a/platforms/ibm-fsp/hostservices.c b/platforms/ibm-fsp/hostservices.c index 81fd6bdd3..accc0989a 100644 --- a/platforms/ibm-fsp/hostservices.c +++ b/platforms/ibm-fsp/hostservices.c @@ -551,6 +551,10 @@ int hservice_wakeup(uint32_t i_core, uint32_t i_mode) i_core &= SPR_PIR_P9_MASK; i_core <<= 2; break; + case proc_gen_p10: + i_core &= SPR_PIR_P10_MASK; + i_core <<= 2; + break; default: return OPAL_UNSUPPORTED; } diff --git a/platforms/ibm-fsp/zz.c b/platforms/ibm-fsp/zz.c index 7c6050ab7..493d6030a 100644 --- a/platforms/ibm-fsp/zz.c +++ b/platforms/ibm-fsp/zz.c @@ -160,6 +160,12 @@ static bool zz_probe(void) if (dt_node_is_compatible(dt_root, "ibm,fleetwood-m9s")) { return true; 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Wed, 4 Aug 2021 07:22:51 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:51 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:08 +0530 Message-Id: <20210804072137.1147875-31-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: yqGhCNM1AH6c12JGk1CFhavob09lAzVD X-Proofpoint-GUID: yqGhCNM1AH6c12JGk1CFhavob09lAzVD X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 30/59] xive/p10: Add a XIVE2 driver X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE structures, and a set of new features which are described below. The OPAL XIVE2 driver code activating this controller was duplicated from P9 for clarity as the registers and structures have changed considerably. The same OPAL interface is implemented for OS compatibility and it should not impact existing Linux kernels, KVM included. Guest OS is not impacted either. Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - cache injection mechanism - 4 cache watch engines - a configurable number of priorities : 1 -8 - StoreEOI with load-after-store ordering is activated by default - new sync/kill operations for cache operations Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - Automatic Context save & restore - increase to 24bit for VP number - New escalations schems : ESB, Adaptive, CPPR POWER10 adds support for User interrupts. When configured, the XIVE2 controller can notify directly user processes using the Event Based Branch exception line of the thread. If not running, the OS is notified through an escalation event. New OPAL and PAPR interfaces will be required and OS support needs to be studied. * XIVE2 P9-compat mode, or Gen1 The thread interrupt management area (TIMA) is a set of pages mapped in the Hypervisor and in the guest OS address space giving access to the interrupt thread context registers for interrupt management, ACK, EOI, CPPR, etc. XIVE2 changes slightly the TIMA layout with extra bits for the new features, larger CAM lines and the controller provides configuration switches for backward compatibility. This is called the XIVE2 P9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and the availability of the internal features associated with it, Automatic Save & Restore for instance. Using a P9 layout also means setting the controller in such a mode at init time. The XIVE2 driver in OPAL chooses to initialize the XIVE2 controller with a XIVE2/P10 TIMA directly because the layouts are compatible with the Linux PowerNV and the guest OSes expectations. For KVM support, the OPAL calls abstract the HW interface and no assumption is made on the OS CAM line width. * Activating new XIVE2 features Everything related to OPAL internals such as the use of the new cache sync mechanism can be implemented in time without impact on the OS. Other features will require new device tree properties exposed to the OS and extra support for the OS. Automatic Context save & restore is one of the first feature which should be looked at. * XICS-over-XICS driver (P8 compatibility) The P8 emulation mode is an OPAL compat interface used for Linux kernels which did not have XIVE native support. This was useful for POWER9 bringup but it is much less now. As it was adding a lot of complexity and reducing the interrupt controller resources, this mode is not available in the XIVE2 driver for POWER10. It will still be possible to add this compat mode in the future if required. The OS will have to reset the driver at boot time, like on POWER9. * Impact on other drivers (PSI, PHB, NPU) Interrupts are allocated in a very similar way. Each controller might have different ESB characteristics, StoreEOI support, 64K pages for PSI. All is in place to support these changes already. PHB5 will have support for "address-based trigger mode", probably in the DD2.0 time frame when verification is completed. When activated, the XIVE IC ESB pages will be used instead of the PHB ESB pages for a lower interrupt latency. LSI will still use old fashion triggers without StoreEOI. * Yet to be addressed : - OPAL P10 interface incomplete (stop states) - Clarify the PHB5 strategy regarding the use of the XIVE IC ESB pages instead of the PHB ones when address-based trigger mode is supported. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- core/fast-reboot.c | 4 + core/init.c | 12 +- hw/Makefile.inc | 2 +- hw/psi.c | 25 +- hw/slw.c | 12 +- hw/xive.c | 6 +- hw/xive2.c | 4444 ++++++++++++++++++++++++++++++++++++++++++ include/xive.h | 29 + include/xive2-regs.h | 549 ++++++ 9 files changed, 5071 insertions(+), 12 deletions(-) create mode 100644 hw/xive2.c create mode 100644 include/xive2-regs.h diff --git a/core/fast-reboot.c b/core/fast-reboot.c index ac9b3b284..9f92525a9 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -262,6 +262,8 @@ static void cleanup_cpu_state(void) if (proc_gen == proc_gen_p9) xive_cpu_reset(); + else if (proc_gen == proc_gen_p10) + xive2_cpu_reset(); /* Per core cleanup */ if (cpu_is_thread0(cpu) || cpu_is_core_chiplet_primary(cpu)) { @@ -381,6 +383,8 @@ void __noreturn fast_reboot_entry(void) if (proc_gen == proc_gen_p9) xive_reset(); + else if (proc_gen == proc_gen_p10) + xive2_reset(); /* Let the CPU layer do some last minute global cleanups */ cpu_fast_reboot_complete(); diff --git a/core/init.c b/core/init.c index 0bf4ab269..e38969554 100644 --- a/core/init.c +++ b/core/init.c @@ -1225,8 +1225,11 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) if (proc_gen == proc_gen_p8) cpu_set_ipi_enable(true); - /* On P9, initialize XIVE */ - init_xive(); + /* On P9 and P10, initialize XIVE */ + if (proc_gen == proc_gen_p9) + init_xive(); + else if (proc_gen == proc_gen_p10) + xive2_init(); /* Grab centaurs from device-tree if present (only on FSP-less) */ centaur_init(); @@ -1437,7 +1440,10 @@ void __noreturn __secondary_cpu_entry(void) mtmsrd(MSR_RI, 1); /* Some XIVE setup */ - xive_cpu_callin(cpu); + if (proc_gen == proc_gen_p9) + xive_cpu_callin(cpu); + else if (proc_gen == proc_gen_p10) + xive2_cpu_callin(cpu); /* Wait for work to do */ while(true) { diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a7f450cf7..37256d3cc 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -9,7 +9,7 @@ HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o -HW_OBJS += ocmb.o +HW_OBJS += ocmb.o xive2.o HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/psi.c b/hw/psi.c index f95a066d3..26677a3b2 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -772,12 +772,12 @@ static void psi_init_p10_interrupts(struct psi *psi) psi->chip_id, psi->esb_mmio); /* Grab and configure the notification port */ - val = xive_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); + val = xive2_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); val |= PSIHB_ESB_NOTIF_VALID; out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); /* Setup interrupt offset */ - val = xive_get_notify_base(psi->interrupt); + val = xive2_get_notify_base(psi->interrupt); val <<= 32; out_be64(psi->regs + PSIHB_IVT_OFFSET, val); @@ -786,7 +786,7 @@ static void psi_init_p10_interrupts(struct psi *psi) "PSI[0x%03x]: Interrupts sources registered for P10 DD%i.%i\n", psi->chip_id, 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf); - xive_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, + xive2_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, esb_shift, psi->esb_mmio, XIVE_SRC_LSI, psi, &psi_p10_irq_ops); @@ -956,6 +956,23 @@ static struct psi *psi_probe_p9(struct proc_chip *chip, u64 base) return psi; } +static struct psi *psi_probe_p10(struct proc_chip *chip, u64 base) +{ + struct psi *psi = NULL; + uint64_t addr; + + phys_map_get(chip->id, PSIHB_REG, 0, &addr, NULL); + xscom_write(chip->id, base + PSIHB_XSCOM_P9_BASE, + addr | PSIHB_XSCOM_P9_HBBAR_EN); + + psi = alloc_psi(chip, base); + if (!psi) + return NULL; + psi->regs = (void *)addr; + psi->interrupt = xive2_alloc_hw_irqs(chip->id, P9_PSI_NUM_IRQS, 16); + return psi; +} + static bool psi_init_psihb(struct dt_node *psihb) { uint32_t chip_id = dt_get_chip_id(psihb); @@ -974,6 +991,8 @@ static bool psi_init_psihb(struct dt_node *psihb) psi = psi_probe_p8(chip, base); else if (dt_node_is_compatible(psihb, "ibm,power9-psihb-x")) psi = psi_probe_p9(chip, base); + else if (dt_node_is_compatible(psihb, "ibm,power10-psihb-x")) + psi = psi_probe_p10(chip, base); else { prerror("PSI: Unknown processor type\n"); return false; diff --git a/hw/slw.c b/hw/slw.c index 8969096ac..9e676af74 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -965,9 +965,15 @@ void add_cpu_idle_state_properties(void) } } if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT) && has_deep_states) { - slw_late_init_p9(chip); - xive_late_init(); - nx_p9_rng_late_init(); + if (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS) { + slw_late_init_p9(chip); + xive_late_init(); + nx_p9_rng_late_init(); + } else if (chip->type == PROC_CHIP_P10) { + /* TODO (p10): need P10 stop state engine */ + xive2_late_init(); + } } if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) has_deep_states = false; diff --git a/hw/xive.c b/hw/xive.c index c442ea5e3..51b03549a 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1776,7 +1776,8 @@ static void xive_create_mmio_dt_node(struct xive *x) dt_add_property_cells(xive_dt_node, "ibm,xive-eq-sizes", 12, 16, 21, 24); - dt_add_property_cells(xive_dt_node, "ibm,xive-#priorities", 8); + dt_add_property_cells(xive_dt_node, "ibm,xive-#priorities", + NUM_INT_PRIORITIES); dt_add_property(xive_dt_node, "single-escalation-support", NULL, 0); xive_add_provisioning_properties(); @@ -4191,7 +4192,8 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) if (!memcmp(eq_orig, &eq, sizeof(eq))) rc = 0; else - rc = xive_eqc_cache_update(x, blk, idx + 7, &eq, false); + rc = xive_eqc_cache_update(x, blk, idx + XIVE_ESCALATION_PRIO, + &eq, false); if (rc) return rc; diff --git a/hw/xive2.c b/hw/xive2.c new file mode 100644 index 000000000..a7bfdcbde --- /dev/null +++ b/hw/xive2.c @@ -0,0 +1,4444 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * XIVE2: eXternal Interrupt Virtualization Engine. POWER10 interrupt + * controller + * + * Copyright (c) 2016-2019, IBM Corporation. + */ + +#define pr_fmt(fmt) "XIVE: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* TODO (p10): need P10 stop state engine */ + + +/* Verbose debug */ +#undef XIVE_VERBOSE_DEBUG +#undef DEBUG + +/* Extra debug options used in debug builds */ +#ifdef DEBUG +#define XIVE_CHECK_LOCKS +#define XIVE_DEBUG_INIT_CACHE_UPDATES +#define XIVE_EXTRA_CHECK_INIT_CACHE +#else +#undef XIVE_CHECK_LOCKS +#undef XIVE_DEBUG_INIT_CACHE_UPDATES +#undef XIVE_EXTRA_CHECK_INIT_CACHE +#endif + +/* + * VSDs, blocks, set translation etc... + * + * For the following data structures, the XIVE use a mechanism called + * Virtualization Structure Tables (VST) to manage the memory layout + * and access: ESBs (Event State Buffers), EAS (Event assignment + * structures), ENDs (Event Notification Descriptors) and NVT/NVP + * (Notification Virtual Targets/Processors). + * + * These structures divide those tables into 16 "blocks". Each XIVE + * instance has a definition for all 16 blocks that can either represent + * an actual table in memory or a remote XIVE MMIO port to access a + * block that is owned by that remote XIVE. + * + * Our SW design will consist of allocating one block per chip (and thus + * per XIVE instance) for now, thus giving us up to 16 supported chips in + * the system. We may have to revisit that if we ever support systems with + * more than 16 chips but that isn't on our radar at the moment or if we + * want to do like pHyp on some machines and dedicate 2 blocks per chip + * for some structures. + * + * Thus we need to be careful that we never expose to Linux the concept + * of block and block boundaries, but instead we provide full number ranges + * so that consecutive blocks can be supported. + * + * Similarily, for MMIO access, the BARs support what is called "set + * translation" which allows the BAR to be devided into a certain + * number of sets. Each "set" can be routed to a specific block and + * offset within a block. + */ + +#define XIVE_MAX_BLOCKS 16 +#define XIVE_VSD_SIZE 8 + +/* + * Max number of ESBs. (direct table) + * + * The max number of ESBs supported in the P10 MMIO space is 1TB/128K: 8M. + * + * 1M is our current top limit of ESB entries and EAS entries + * pre-allocated per chip. That allocates 256KB per chip for the state + * bits and 8M per chip for the EAS. + */ + +#define XIVE_INT_ORDER 20 /* 1M interrupts */ +#define XIVE_INT_COUNT (1ul << XIVE_INT_ORDER) + +/* + * First interrupt number, also the first logical interrupt number + * allocated by Linux (maximum ISA interrupt number + 1) + */ +#define XIVE_INT_FIRST 0x10 + +/* Corresponding direct table sizes */ +#define XIVE_ESB_SIZE (XIVE_INT_COUNT / 4) +#define XIVE_EAT_SIZE (XIVE_INT_COUNT * 8) + +/* Use 64K for everything by default */ +#define XIVE_ESB_SHIFT (16 + 1) /* trigger + mgmt pages */ +#define XIVE_ESB_PAGE_SIZE (1ul << XIVE_ESB_SHIFT) /* 2 pages */ + +/* + * Max number of ENDs. (indirect table) + * + * The max number of ENDs supported in the P10 MMIO space is 2TB/128K: 16M. + * Since one END is 32 bytes, a 64K indirect subpage can hold 2K ENDs. + * We need 8192 subpages, ie, 64K of memory for the indirect table. + */ +#define END_PER_PAGE (PAGE_SIZE / sizeof(struct xive_end)) + +#define XIVE_END_ORDER 23 /* 8M ENDs */ +#define XIVE_END_COUNT (1ul << XIVE_END_ORDER) +#define XIVE_END_TABLE_SIZE ((XIVE_END_COUNT / END_PER_PAGE) * XIVE_VSD_SIZE) + +#define XIVE_END_SHIFT (16 + 1) /* ESn + ESe pages */ + +/* One bit per number of priorities configured */ +#define xive_end_bitmap_size(x) (XIVE_END_COUNT >> xive_cfg_vp_prio_shift(x)) + +/* Number of priorities (and thus ENDs) we allocate for each VP */ +#define xive_cfg_vp_prio_shift(x) GETFIELD(CQ_XIVE_CFG_VP_INT_PRIO, (x)->config) +#define xive_cfg_vp_prio(x) (1 << xive_cfg_vp_prio_shift(x)) + +/* Max priority number */ +#define xive_max_prio(x) (xive_cfg_vp_prio(x) - 1) + +/* Priority used for gather/silent escalation (KVM) */ +#define xive_escalation_prio(x) xive_max_prio(x) + +/* + * Max number of VPs. (indirect table) + * + * The max number of NVPs we support in our MMIO space is 1TB/128K: 8M. + * Since one NVP is 32 bytes, a 64K indirect subpage can hold 2K NVPs. + * We need 4096 pointers, ie, 32K of memory for the indirect table. + * + * However, we use 8 priorities (by default) per NVP and the number of + * ENDs is configured to 8M. Therefore, our VP space is limited to 1M. + */ +#define VP_PER_PAGE (PAGE_SIZE / sizeof(struct xive_nvp)) + +#define XIVE_VP_ORDER(x) (XIVE_END_ORDER - xive_cfg_vp_prio_shift(x)) +#define XIVE_VP_COUNT(x) (1ul << XIVE_VP_ORDER(x)) +#define XIVE_VP_TABLE_SIZE(x) ((XIVE_VP_COUNT(x) / VP_PER_PAGE) * XIVE_VSD_SIZE) + +#define XIVE_NVP_SHIFT 17 /* NVPG BAR: two pages, even NVP, odd NVG */ + +/* VP Space maximums in Gen1 and Gen2 modes */ +#define VP_SHIFT_GEN1 19 /* in sync with END_W6_VP_OFFSET_GEN1 */ +#define VP_SHIFT_GEN2 24 /* in sync with END_W6_VP_OFFSET */ + +/* + * VP ids for HW threads. + * + * Depends on the thread id bits configuration of the IC. 8bit is the + * default for P10 and 7bit for p9. + * + * These values are global because they should be common to all chips + */ +static uint32_t xive_threadid_shift; +static uint32_t xive_hw_vp_base; +static uint32_t xive_hw_vp_count; + +/* + * The XIVE operation mode indicates the active "API" and corresponds + * to the "version/mode" parameter of the opal_xive_reset() call + */ +static enum { + /* No XICS emulation */ + XIVE_MODE_EXPL = OPAL_XIVE_MODE_EXPL, /* default */ + XIVE_MODE_NONE, +} xive_mode = XIVE_MODE_NONE; + +/* + * Each source controller has one of these. There's one embedded in + * the XIVE struct for IPIs + */ +struct xive_src { + struct irq_source is; + const struct irq_source_ops *orig_ops; + struct xive *xive; + void *esb_mmio; + uint32_t esb_base; + uint32_t esb_shift; + uint32_t flags; +}; + +struct xive_cpu_state { + struct xive *xive; + void *tm_ring1; + + /* Base HW VP and associated queues */ + uint32_t vp_blk; + uint32_t vp_idx; + uint32_t end_blk; + uint32_t end_idx; /* Base end index of a block of 8 */ + + struct lock lock; +}; + +enum xive_generation { + XIVE_GEN1 = 1, /* P9 compat mode */ + XIVE_GEN2 = 2, /* P10 default */ +}; + +enum xive_quirks { + /* HW527671 - 8bits Hardwired Thread Id range not implemented */ + XIVE_QUIRK_THREADID_7BITS = 0x00000001, + /* HW542974 - interrupt command priority checker not working properly */ + XIVE_QUIRK_BROKEN_PRIO_CHECK = 0x00000002, +}; + +struct xive { + uint32_t chip_id; + uint32_t block_id; + struct dt_node *x_node; + + enum xive_generation generation; + uint64_t config; + + uint64_t xscom_base; + + /* MMIO regions */ + void *ic_base; + uint64_t ic_size; + uint32_t ic_shift; + void *ic_tm_direct_base; + + void *tm_base; + uint64_t tm_size; + uint32_t tm_shift; + void *nvp_base; + uint64_t nvp_size; + void *esb_base; + uint64_t esb_size; + void *end_base; + uint64_t end_size; + + /* Set on XSCOM register access error */ + bool last_reg_error; + + /* Per-XIVE mutex */ + struct lock lock; + + /* Pre-allocated tables. + * + * We setup all the VDS for actual tables (ie, by opposition to + * forwarding ports) as either direct pre-allocated or indirect + * and partially populated. + * + * Currently, the ESB and the EAS tables are direct and fully + * pre-allocated based on XIVE_INT_COUNT. + * + * The other tables are indirect, we thus pre-allocate the indirect + * table (ie, pages of pointers) and populate enough of the pages + * for our basic setup using 64K subpages. + * + * The size of the indirect tables are driven by XIVE_VP_COUNT + * and XIVE_END_COUNT. The number of pre-allocated ones are + * driven by xive_hw_vp_count for the HW threads. The number + * of END depends on number of VP. + */ + + /* Direct SBE and EAT tables */ + void *sbe_base; + void *eat_base; + + /* Indirect END table. NULL entries are unallocated, count is + * the numbre of pointers (ie, sub page placeholders). + */ + beint64_t *end_ind_base; + uint32_t end_ind_count; + uint64_t end_ind_size; + + /* END allocation bitmap. Each bit represent #priority ENDs */ + bitmap_t *end_map; + + /* Indirect NVT/VP table. NULL entries are unallocated, count is + * the numbre of pointers (ie, sub page placeholders). + */ + beint64_t *vp_ind_base; + uint32_t vp_ind_count; + uint64_t vp_ind_size; + + /* VP space size. Depends on Gen1/2 mode */ + uint32_t vp_shift; + + /* Pool of donated pages for provisioning indirect END and VP pages */ + struct list_head donated_pages; + + /* To ease a possible change to supporting more than one block of + * interrupts per chip, we store here the "base" global number + * and max number of interrupts for this chip. The global number + * encompass the block number and index. + */ + uint32_t int_base; + uint32_t int_count; + + /* Due to the overlap between IPIs and HW sources in the EAS table, + * we keep some kind of top-down allocator. It is used for HW sources + * to "allocate" interrupt entries and will limit what can be handed + * out as IPIs. Of course this assumes we "allocate" all HW sources + * before we start handing out IPIs. + * + * Note: The numbers here are global interrupt numbers so that we can + * potentially handle more than one block per chip in the future. + */ + uint32_t int_hw_bot; /* Bottom of HW allocation */ + uint32_t int_ipi_top; /* Highest IPI handed out so far + 1 */ + + /* The IPI allocation bitmap */ + bitmap_t *ipi_alloc_map; + + /* We keep track of which interrupts were ever enabled to + * speed up xive_reset + */ + bitmap_t *int_enabled_map; + + /* Embedded source IPIs */ + struct xive_src ipis; + + /* Embedded escalation interrupts */ + struct xive_src esc_irqs; + + /* In memory queue overflow */ + void *q_ovf; + + /* Cache/sync injection */ + uint64_t sync_inject_size; + void *sync_inject; + + /* INT HW Errata */ + uint64_t quirks; +}; + +#define XIVE_CAN_STORE_EOI(x) XIVE2_STORE_EOI_ENABLED + +/* First XIVE unit configured on the system */ +static struct xive *one_xive; + +/* Global DT node */ +static struct dt_node *xive_dt_node; + +/* Block <-> Chip conversions. + * + * As chipIDs may not be within the range of 16 block IDs supported by XIVE, + * we have a 2 way conversion scheme. + * + * From block to chip, use the global table below. + * + * From chip to block, a field in struct proc_chip contains the first block + * of that chip. For now we only support one block per chip but that might + * change in the future + */ +#define XIVE_INVALID_CHIP 0xffffffff +#define XIVE_MAX_CHIPS 16 +static uint32_t xive_block_to_chip[XIVE_MAX_CHIPS]; +static uint32_t xive_block_count; + +static uint32_t xive_chip_to_block(uint32_t chip_id) +{ + struct proc_chip *c = get_chip(chip_id); + + assert(c); + assert(c->xive); + return c->xive->block_id; +} + +/* + * Conversion between GIRQ and block/index. + * + * ------------------------------------ + * |000E|BLOC| INDEX| + * ------------------------------------ + * 4 4 24 + * + * the E bit indicates that this is an escalation interrupt, in + * that case, the BLOC/INDEX represents the END containing the + * corresponding escalation descriptor. + * + * Global interrupt numbers for non-escalation interrupts are thus + * limited to 28 bits. + */ + +#define INT_SHIFT 24 +#define INT_ESC_SHIFT (INT_SHIFT + 4) /* 4bits block id */ + +#if XIVE_INT_ORDER > INT_SHIFT +#error "Too many ESBs for IRQ encoding" +#endif + +#if XIVE_END_ORDER > INT_SHIFT +#error "Too many ENDs for escalation IRQ number encoding" +#endif + +#define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) +#define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) +#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) + +#define GIRQ_IS_ESCALATION(__g) ((__g) & (1 << INT_ESC_SHIFT)) +#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | (1 << INT_ESC_SHIFT)) + + +/* Block/IRQ to chip# conversions */ +#define PC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b]) +#define VC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b]) +#define GIRQ_TO_CHIP(__isn) (VC_BLK_TO_CHIP(GIRQ_TO_BLK(__isn))) + +/* Routing of physical processors to VPs */ +#define PIR2VP_IDX( __pir) (xive_hw_vp_base | P10_PIR2LOCALCPU(__pir)) +#define PIR2VP_BLK(__pir) (xive_chip_to_block(P10_PIR2GCID(__pir))) +#define VP2PIR(__blk, __idx) (P10_PIRFROMLOCALCPU(VC_BLK_TO_CHIP(__blk), (__idx) & 0xff)) + +/* Decoding of OPAL API VP IDs. The VP IDs are encoded as follow + * + * Block group mode: + * + * ----------------------------------- + * |GVEOOOOO| INDEX| + * ----------------------------------- + * || | + * || Order + * |Virtual + * Group + * + * G (Group) : Set to 1 for a group VP (not currently supported) + * V (Virtual) : Set to 1 for an allocated VP (vs. a physical processor ID) + * E (Error) : Should never be 1, used internally for errors + * O (Order) : Allocation order of the VP block + * + * The conversion is thus done as follow (groups aren't implemented yet) + * + * If V=0, O must be 0 and 24-bit INDEX value is the PIR + * If V=1, the order O group is allocated such that if N is the number of + * chip bits considered for allocation (*) + * then the INDEX is constructed as follow (bit numbers such as 0=LSB) + * - bottom O-N bits is the index within the "VP block" + * - next N bits is the XIVE blockID of the VP + * - the remaining bits is the per-chip "base" + * so the conversion consists of "extracting" the block ID and moving + * down the upper bits by N bits. + * + * In non-block-group mode, the difference is that the blockID is + * on the left of the index (the entire VP block is in a single + * block ID) + */ + +#define VP_GROUP_SHIFT 31 +#define VP_VIRTUAL_SHIFT 30 +#define VP_ERROR_SHIFT 29 +#define VP_ORDER_SHIFT 24 + +#define vp_group(vp) (((vp) >> VP_GROUP_SHIFT) & 1) +#define vp_virtual(vp) (((vp) >> VP_VIRTUAL_SHIFT) & 1) +#define vp_order(vp) (((vp) >> VP_ORDER_SHIFT) & 0x1f) +#define vp_index(vp) ((vp) & ((1 << VP_ORDER_SHIFT) - 1)) + +/* VP allocation */ +static uint32_t xive_chips_alloc_bits = 0; +static struct buddy *xive_vp_buddy; +static struct lock xive_buddy_lock = LOCK_UNLOCKED; + +/* VP# decoding/encoding */ +static bool xive_decode_vp(uint32_t vp, uint32_t *blk, uint32_t *idx, + uint8_t *order, bool *group) +{ + uint32_t o = vp_order(vp); + uint32_t n = xive_chips_alloc_bits; + uint32_t index = vp_index(vp); + uint32_t imask = (1 << (o - n)) - 1; + + /* Groups not supported yet */ + if (vp_group(vp)) + return false; + if (group) + *group = false; + + /* PIR case */ + if (!vp_virtual(vp)) { + if (find_cpu_by_pir(index) == NULL) + return false; + if (blk) + *blk = PIR2VP_BLK(index); + if (idx) + *idx = PIR2VP_IDX(index); + return true; + } + + /* Ensure o > n, we have *at least* 2 VPs per block */ + if (o <= n) + return false; + + /* Combine the index base and index */ + if (idx) + *idx = ((index >> n) & ~imask) | (index & imask); + /* Extract block ID */ + if (blk) + *blk = (index >> (o - n)) & ((1 << n) - 1); + + /* Return order as well if asked for */ + if (order) + *order = o; + + return true; +} + +static uint32_t xive_encode_vp(uint32_t blk, uint32_t idx, uint32_t order) +{ + uint32_t vp = (1 << VP_VIRTUAL_SHIFT) | (order << VP_ORDER_SHIFT); + uint32_t n = xive_chips_alloc_bits; + uint32_t imask = (1 << (order - n)) - 1; + + vp |= (idx & ~imask) << n; + vp |= blk << (order - n); + vp |= idx & imask; + return vp; +} + +/* + * XSCOM/MMIO helpers + */ +#define XIVE_NO_MMIO -1 + +#define xive_regw(__x, __r, __v) \ + __xive_regw(__x, __r, X_##__r, __v, #__r) +#define xive_regr(__x, __r) \ + __xive_regr(__x, __r, X_##__r, #__r) +#define xive_regwx(__x, __r, __v) \ + __xive_regw(__x, XIVE_NO_MMIO, X_##__r, __v, #__r) +#define xive_regrx(__x, __r) \ + __xive_regr(__x, XIVE_NO_MMIO, X_##__r, #__r) + +#ifdef XIVE_VERBOSE_DEBUG +#define xive_vdbg(__x,__fmt,...) prlog(PR_DEBUG,"[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__) +#define xive_cpu_vdbg(__c,__fmt,...) prlog(PR_DEBUG,"[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__) +#else +#define xive_vdbg(x,fmt,...) do { } while(0) +#define xive_cpu_vdbg(x,fmt,...) do { } while(0) +#endif + +#define xive_dbg(__x,__fmt,...) prlog(PR_DEBUG,"[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__) +#define xive_cpu_dbg(__c,__fmt,...) prlog(PR_DEBUG,"[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__) +#define xive_notice(__x,__fmt,...) prlog(PR_NOTICE,"[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__) +#define xive_cpu_notice(__c,__fmt,...) prlog(PR_NOTICE,"[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__) +#define xive_warn(__x,__fmt,...) prlog(PR_WARNING,"[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__) +#define xive_cpu_warn(__c,__fmt,...) prlog(PR_WARNING,"[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__) +#define xive_err(__x,__fmt,...) prlog(PR_ERR,"[ IC %02x ] " __fmt, (__x)->chip_id, ##__VA_ARGS__) +#define xive_cpu_err(__c,__fmt,...) prlog(PR_ERR,"[CPU %04x] " __fmt, (__c)->pir, ##__VA_ARGS__) + +/* + * The XIVE subengine being accessed can be deduced from the XSCOM + * reg, and from there, the page offset in the IC BAR. + */ +static void* xive_ic_page(struct xive *x, uint32_t x_reg) +{ + uint64_t pgoff = (x_reg >> 8) & 0x3; + + return x->ic_base + (pgoff << x->ic_shift); +} + +static void __xive_regw(struct xive *x, uint32_t m_reg, uint32_t x_reg, uint64_t v, + const char *rname) +{ + bool use_xscom = (m_reg == XIVE_NO_MMIO) || !x->ic_base; + int64_t rc; + + x->last_reg_error = false; + + assert(x_reg != 0); + + if (use_xscom) { + rc = xscom_write(x->chip_id, x->xscom_base + x_reg, v); + if (rc) { + if (!rname) + rname = "???"; + xive_err(x, "Error writing register %s\n", rname); + /* Anything else we can do here ? */ + x->last_reg_error = true; + } + } else { + out_be64(xive_ic_page(x, x_reg) + m_reg, v); + } +} + +static uint64_t __xive_regr(struct xive *x, uint32_t m_reg, uint32_t x_reg, + const char *rname) +{ + bool use_xscom = (m_reg == XIVE_NO_MMIO) || !x->ic_base; + int64_t rc; + uint64_t val; + + x->last_reg_error = false; + + assert(x_reg != 0); + + if (use_xscom) { + rc = xscom_read(x->chip_id, x->xscom_base + x_reg, &val); + if (rc) { + if (!rname) + rname = "???"; + xive_err(x, "Error reading register %s\n", rname); + /* Anything else we can do here ? */ + x->last_reg_error = true; + return -1ull; + } + } else { + val = in_be64(xive_ic_page(x, x_reg) + m_reg); + } + return val; +} + +/* Locate a controller from an IRQ number */ +static struct xive *xive_from_isn(uint32_t isn) +{ + uint32_t chip_id = GIRQ_TO_CHIP(isn); + struct proc_chip *c = get_chip(chip_id); + + if (!c) + return NULL; + return c->xive; +} + +static struct xive *xive_from_pc_blk(uint32_t blk) +{ + uint32_t chip_id = PC_BLK_TO_CHIP(blk); + struct proc_chip *c = get_chip(chip_id); + + if (!c) + return NULL; + return c->xive; +} + +static struct xive *xive_from_vc_blk(uint32_t blk) +{ + uint32_t chip_id = VC_BLK_TO_CHIP(blk); + struct proc_chip *c = get_chip(chip_id); + + if (!c) + return NULL; + return c->xive; +} + +static struct xive_end *xive_get_end(struct xive *x, unsigned int idx) +{ + struct xive_end *p; + + if (idx >= (x->end_ind_count * END_PER_PAGE)) + return NULL; + p = (struct xive_end *)(be64_to_cpu(x->end_ind_base[idx / END_PER_PAGE]) & + VSD_ADDRESS_MASK); + if (!p) + return NULL; + + return &p[idx % END_PER_PAGE]; +} + +static struct xive_eas *xive_get_eas(struct xive *x, unsigned int isn) +{ + struct xive_eas *eat; + uint32_t idx = GIRQ_TO_IDX(isn); + + if (GIRQ_IS_ESCALATION(isn)) { + /* Allright, an escalation EAS is buried inside an END, let's + * try to find it + */ + struct xive_end *end; + + if (x->chip_id != VC_BLK_TO_CHIP(GIRQ_TO_BLK(isn))) { + xive_err(x, "%s, ESC ISN 0x%x not on right chip\n", + __func__, isn); + return NULL; + } + end = xive_get_end(x, idx); + if (!end) { + xive_err(x, "%s, ESC ISN 0x%x END not found\n", + __func__, isn); + return NULL; + } + + /* If using single-escalation, don't let anybody get + * to the individual escalation interrupts + */ + if (xive_get_field32(END_W0_UNCOND_ESCALATE, end->w0)) + return NULL; + + /* Grab the escalation END */ + return (struct xive_eas *)(char *)&end->w4; + } else { + /* Check the block matches */ + if (isn < x->int_base || isn >= x->int_count) { + xive_err(x, "%s, ISN 0x%x not on right chip\n", + __func__, isn); + return NULL; + } + assert (idx < XIVE_INT_COUNT); + + /* If we support >1 block per chip, this should still + * work as we are likely to make the table contiguous + * anyway + */ + eat = x->eat_base; + assert(eat); + + return eat + idx; + } +} + +static struct xive_nvp *xive_get_vp(struct xive *x, unsigned int idx) +{ + struct xive_nvp *p; + + assert(idx < (x->vp_ind_count * VP_PER_PAGE)); + p = (struct xive_nvp *)(be64_to_cpu(x->vp_ind_base[idx / VP_PER_PAGE]) & + VSD_ADDRESS_MASK); + if (!p) + return NULL; + + return &p[idx % VP_PER_PAGE]; +} + +/* + * Store the END base of the VP in W5, using the new architected field + * in P10. Used to be the pressure relief interrupt field on P9. + */ +static void xive_vp_set_end_base(struct xive_nvp *vp, + uint32_t end_blk, uint32_t end_idx) +{ + vp->w5 = xive_set_field32(NVP_W5_VP_END_BLOCK, 0, end_blk) | + xive_set_field32(NVP_W5_VP_END_INDEX, 0, end_idx); + + /* This is the criteria to know if a VP was allocated */ + assert(vp->w5 != 0); +} + +static void xive_init_default_vp(struct xive_nvp *vp, + uint32_t end_blk, uint32_t end_idx) +{ + memset(vp, 0, sizeof(struct xive_nvp)); + + xive_vp_set_end_base(vp, end_blk, end_idx); + + vp->w0 = xive_set_field32(NVP_W0_VALID, 0, 1); +} + +/* + * VPs of the HW threads have their own set of ENDs which is allocated + * when XIVE is initialized. These are tagged with a FIRMWARE bit so + * that they can be identified when the driver is reset (kexec). + */ +static void xive_init_hw_end(struct xive_end *end) +{ + memset(end, 0, sizeof(struct xive_end)); + end->w0 = xive_set_field32(END_W0_FIRMWARE1, 0, 1); +} + +static void *xive_get_donated_page(struct xive *x) +{ + return (void *)list_pop_(&x->donated_pages, 0); +} + +#define XIVE_ALLOC_IS_ERR(_idx) ((_idx) >= 0xfffffff0) + +#define XIVE_ALLOC_NO_SPACE 0xffffffff /* No possible space */ +#define XIVE_ALLOC_NO_IND 0xfffffffe /* Indirect need provisioning */ +#define XIVE_ALLOC_NO_MEM 0xfffffffd /* Local allocation failed */ + +static uint32_t xive_alloc_end_set(struct xive *x, bool alloc_indirect) +{ + uint32_t ind_idx; + int idx; + int end_base_idx; + + xive_vdbg(x, "Allocating END set...\n"); + + assert(x->end_map); + + /* Allocate from the END bitmap. Each bit is 8 ENDs */ + idx = bitmap_find_zero_bit(*x->end_map, 0, xive_end_bitmap_size(x)); + if (idx < 0) { + xive_dbg(x, "Allocation from END bitmap failed !\n"); + return XIVE_ALLOC_NO_SPACE; + } + + end_base_idx = idx << xive_cfg_vp_prio_shift(x); + + xive_vdbg(x, "Got ENDs 0x%x..0x%x\n", end_base_idx, + end_base_idx + xive_max_prio(x)); + + /* Calculate the indirect page where the ENDs reside */ + ind_idx = end_base_idx / END_PER_PAGE; + + /* Is there an indirect page ? If not, check if we can provision it */ + if (!x->end_ind_base[ind_idx]) { + /* Default flags */ + uint64_t vsd_flags = SETFIELD(VSD_TSIZE, 0ull, 4) | + SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); + void *page; + + /* If alloc_indirect is set, allocate the memory from OPAL own, + * otherwise try to provision from the donated pool + */ + if (alloc_indirect) { + /* Allocate/provision indirect page during boot only */ + xive_vdbg(x, "Indirect empty, provisioning from local pool\n"); + page = local_alloc(x->chip_id, PAGE_SIZE, PAGE_SIZE); + if (!page) { + xive_dbg(x, "provisioning failed !\n"); + return XIVE_ALLOC_NO_MEM; + } + vsd_flags |= VSD_FIRMWARE; + } else { + xive_vdbg(x, "Indirect empty, provisioning from donated pages\n"); + page = xive_get_donated_page(x); + if (!page) { + xive_vdbg(x, "no idirect pages available !\n"); + return XIVE_ALLOC_NO_IND; + } + } + memset(page, 0, PAGE_SIZE); + x->end_ind_base[ind_idx] = cpu_to_be64(vsd_flags | + (((uint64_t)page) & VSD_ADDRESS_MASK)); + /* Any cache scrub needed ? */ + } + + bitmap_set_bit(*x->end_map, idx); + return end_base_idx; +} + +static void xive_free_end_set(struct xive *x, uint32_t ends) +{ + uint32_t idx; + uint8_t prio_mask = xive_max_prio(x); + + xive_vdbg(x, "Freeing END 0x%x..0x%x\n", ends, ends + xive_max_prio(x)); + + assert((ends & prio_mask) == 0); + assert(x->end_map); + + idx = ends >> xive_cfg_vp_prio_shift(x); + bitmap_clr_bit(*x->end_map, idx); +} + +static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t order) +{ + uint32_t pbase, pend, i; + + pbase = vp_idx / VP_PER_PAGE; + pend = (vp_idx + (1 << order)) / VP_PER_PAGE; + + for (i = pbase; i <= pend; i++) { + void *page; + u64 vsd; + + /* Already provisioned ? */ + if (x->vp_ind_base[i]) + continue; + + /* Try to grab a donated page */ + page = xive_get_donated_page(x); + if (!page) + return false; + + /* Install the page */ + memset(page, 0, PAGE_SIZE); + vsd = ((uint64_t)page) & VSD_ADDRESS_MASK; + vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); + vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); + x->vp_ind_base[i] = cpu_to_be64(vsd); + } + return true; +} + +static void xive_init_vp_allocator(void) +{ + /* Initialize chip alloc bits */ + xive_chips_alloc_bits = ilog2(xive_block_count); + + prlog(PR_INFO, "%d chips considered for VP allocations\n", + 1 << xive_chips_alloc_bits); + + /* Allocate a buddy big enough for XIVE_VP_ORDER allocations. + * + * each bit in the buddy represents 1 << xive_chips_alloc_bits + * VPs. + */ + xive_vp_buddy = buddy_create(XIVE_VP_ORDER(one_xive)); + assert(xive_vp_buddy); + + /* + * We reserve the whole range of VP ids representing HW threads. + */ + assert(buddy_reserve(xive_vp_buddy, xive_hw_vp_base, + xive_threadid_shift)); +} + +static uint32_t xive_alloc_vps(uint32_t order) +{ + uint32_t local_order, i; + int vp; + + /* The minimum order is 2 VPs per chip */ + if (order < (xive_chips_alloc_bits + 1)) + order = xive_chips_alloc_bits + 1; + + /* We split the allocation */ + local_order = order - xive_chips_alloc_bits; + + /* We grab that in the global buddy */ + assert(xive_vp_buddy); + lock(&xive_buddy_lock); + vp = buddy_alloc(xive_vp_buddy, local_order); + unlock(&xive_buddy_lock); + if (vp < 0) + return XIVE_ALLOC_NO_SPACE; + + /* Provision on every chip considered for allocation */ + for (i = 0; i < (1 << xive_chips_alloc_bits); i++) { + struct xive *x = xive_from_pc_blk(i); + bool success; + + /* Return internal error & log rather than assert ? */ + assert(x); + lock(&x->lock); + success = xive_provision_vp_ind(x, vp, local_order); + unlock(&x->lock); + if (!success) { + lock(&xive_buddy_lock); + buddy_free(xive_vp_buddy, vp, local_order); + unlock(&xive_buddy_lock); + return XIVE_ALLOC_NO_IND; + } + } + + /* Encode the VP number. "blk" is 0 as this represents + * all blocks and the allocation always starts at 0 + */ + return xive_encode_vp(0, vp, order); +} + +static void xive_free_vps(uint32_t vp) +{ + uint32_t idx; + uint8_t order, local_order; + + assert(xive_decode_vp(vp, NULL, &idx, &order, NULL)); + + /* We split the allocation */ + local_order = order - xive_chips_alloc_bits; + + /* Free that in the buddy */ + lock(&xive_buddy_lock); + buddy_free(xive_vp_buddy, idx, local_order); + unlock(&xive_buddy_lock); +} + +enum xive_cache_type { + xive_cache_easc, + xive_cache_esbc, + xive_cache_endc, + xive_cache_nxc, +}; + +/* + * Cache update + */ + +#define FLUSH_CTRL_POLL_VALID PPC_BIT(0) /* POLL bit is the same for all */ + +static int64_t __xive_cache_scrub(struct xive *x, + enum xive_cache_type ctype, + uint64_t block, uint64_t idx, + bool want_inval __unused, bool want_disable __unused) +{ + uint64_t ctrl_reg, x_ctrl_reg; + uint64_t poll_val, ctrl_val; + +#ifdef XIVE_CHECK_LOCKS + assert(lock_held_by_me(&x->lock)); +#endif + switch (ctype) { + case xive_cache_easc: + poll_val = + SETFIELD(VC_EASC_FLUSH_POLL_BLOCK_ID, 0ll, block) | + SETFIELD(VC_EASC_FLUSH_POLL_OFFSET, 0ll, idx) | + VC_EASC_FLUSH_POLL_BLOCK_ID_MASK | + VC_EASC_FLUSH_POLL_OFFSET_MASK; + xive_regw(x, VC_EASC_FLUSH_POLL, poll_val); + ctrl_reg = VC_EASC_FLUSH_CTRL; + x_ctrl_reg = X_VC_EASC_FLUSH_CTRL; + break; + case xive_cache_esbc: + poll_val = + SETFIELD(VC_ESBC_FLUSH_POLL_BLOCK_ID, 0ll, block) | + SETFIELD(VC_ESBC_FLUSH_POLL_OFFSET, 0ll, idx) | + VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK | + VC_ESBC_FLUSH_POLL_OFFSET_MASK; + xive_regw(x, VC_ESBC_FLUSH_POLL, poll_val); + ctrl_reg = VC_ESBC_FLUSH_CTRL; + x_ctrl_reg = X_VC_ESBC_FLUSH_CTRL; + break; + case xive_cache_endc: + poll_val = + SETFIELD(VC_ENDC_FLUSH_POLL_BLOCK_ID, 0ll, block) | + SETFIELD(VC_ENDC_FLUSH_POLL_OFFSET, 0ll, idx) | + VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK | + VC_ENDC_FLUSH_POLL_OFFSET_MASK; + xive_regw(x, VC_ENDC_FLUSH_POLL, poll_val); + ctrl_reg = VC_ENDC_FLUSH_CTRL; + x_ctrl_reg = X_VC_ENDC_FLUSH_CTRL; + break; + case xive_cache_nxc: + poll_val = + SETFIELD(PC_NXC_FLUSH_POLL_BLOCK_ID, 0ll, block) | + SETFIELD(PC_NXC_FLUSH_POLL_OFFSET, 0ll, idx) | + PC_NXC_FLUSH_POLL_BLOCK_ID_MASK | + PC_NXC_FLUSH_POLL_OFFSET_MASK; + xive_regw(x, PC_NXC_FLUSH_POLL, poll_val); + ctrl_reg = PC_NXC_FLUSH_CTRL; + x_ctrl_reg = X_PC_NXC_FLUSH_CTRL; + break; + default: + return OPAL_INTERNAL_ERROR; + } + + /* XXX Add timeout !!! */ + for (;;) { + ctrl_val = __xive_regr(x, ctrl_reg, x_ctrl_reg, NULL); + if (!(ctrl_val & FLUSH_CTRL_POLL_VALID)) + break; + /* Small delay */ + time_wait(100); + } + sync(); + return 0; +} + +static int64_t xive_easc_scrub(struct xive *x, uint64_t block, uint64_t idx) +{ + return __xive_cache_scrub(x, xive_cache_easc, block, idx, false, false); +} + +static int64_t xive_nxc_scrub(struct xive *x, uint64_t block, uint64_t idx) +{ + return __xive_cache_scrub(x, xive_cache_nxc, block, idx, false, false); +} + +static int64_t xive_nxc_scrub_clean(struct xive *x, uint64_t block, uint64_t idx) +{ + return __xive_cache_scrub(x, xive_cache_nxc, block, idx, true, false); +} + +static int64_t xive_endc_scrub(struct xive *x, uint64_t block, uint64_t idx) +{ + return __xive_cache_scrub(x, xive_cache_endc, block, idx, false, false); +} + +#define XIVE_CACHE_WATCH_MAX_RETRIES 10 + +static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, + uint64_t block, uint64_t idx, + uint32_t start_dword, uint32_t dword_count, + beint64_t *new_data, bool light_watch, + bool synchronous) +{ + uint64_t sreg, sregx, dreg0, dreg0x; + uint64_t dval0, sval, status; + int64_t i; + int retries = 0; + +#ifdef XIVE_CHECK_LOCKS + assert(lock_held_by_me(&x->lock)); +#endif + switch (ctype) { + case xive_cache_endc: + sreg = VC_ENDC_WATCH0_SPEC; + sregx = X_VC_ENDC_WATCH0_SPEC; + dreg0 = VC_ENDC_WATCH0_DATA0; + dreg0x = X_VC_ENDC_WATCH0_DATA0; + sval = SETFIELD(VC_ENDC_WATCH_BLOCK_ID, idx, block); + break; + case xive_cache_nxc: + sreg = PC_NXC_WATCH0_SPEC; + sregx = X_PC_NXC_WATCH0_SPEC; + dreg0 = PC_NXC_WATCH0_DATA0; + dreg0x = X_PC_NXC_WATCH0_DATA0; + sval = SETFIELD(PC_NXC_WATCH_BLOCK_ID, idx, block); + break; + default: + return OPAL_INTERNAL_ERROR; + } + + /* The full bit is in the same position for ENDC and NXC */ + if (!light_watch) + sval |= VC_ENDC_WATCH_FULL; + + for (;;) { + /* Write the cache watch spec */ + __xive_regw(x, sreg, sregx, sval, NULL); + + /* Load data0 register to populate the watch */ + dval0 = __xive_regr(x, dreg0, dreg0x, NULL); + + /* If new_data is NULL, this is a dummy watch used as a + * workaround for a HW bug + */ + if (!new_data) { + __xive_regw(x, dreg0, dreg0x, dval0, NULL); + return 0; + } + + /* Write the words into the watch facility. We write in reverse + * order in case word 0 is part of it as it must be the last + * one written. + */ + for (i = start_dword + dword_count - 1; i >= start_dword ;i--) { + uint64_t dw = be64_to_cpu(new_data[i - start_dword]); + __xive_regw(x, dreg0 + i * 8, dreg0x + i, dw, NULL); + } + + /* Write data0 register to trigger the update if word 0 wasn't + * written above + */ + if (start_dword > 0) + __xive_regw(x, dreg0, dreg0x, dval0, NULL); + + /* This may not be necessary for light updates (it's possible + * that a sync in sufficient, TBD). Ensure the above is + * complete and check the status of the watch. + */ + status = __xive_regr(x, sreg, sregx, NULL); + + /* Bits FULL and CONFLICT are in the same position in + * ENDC and NXC + */ + if (!(status & VC_ENDC_WATCH_FULL) || + !(status & VC_ENDC_WATCH_CONFLICT)) + break; + if (!synchronous) + return OPAL_BUSY; + + if (++retries == XIVE_CACHE_WATCH_MAX_RETRIES) { + xive_err(x, "Reached maximum retries %d when doing " + "a %s cache update\n", retries, + ctype == xive_cache_endc ? "ENDC" : "NXC"); + return OPAL_BUSY; + } + } + + /* Perform a scrub with "want_invalidate" set to false to push the + * cache updates to memory as well + */ + return __xive_cache_scrub(x, ctype, block, idx, false, false); +} + +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES +static bool xive_check_endc_update(struct xive *x, uint32_t idx, struct xive_end *end) +{ + struct xive_end *end_p = xive_get_end(x, idx); + struct xive_end end2; + + assert(end_p); + end2 = *end_p; + if (memcmp(end, &end2, sizeof(struct xive_end)) != 0) { + xive_err(x, "END update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + end->w0, end->w1, end->w2, end->w3); + xive_err(x, " %08x %08x %08x %08x\n", + end->w4, end->w5, end->w6, end->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + end2.w0, end2.w1, end2.w2, end2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + end2.w4, end2.w5, end2.w6, end2.w7); + return false; + } + return true; +} + +static bool xive_check_nxc_update(struct xive *x, uint32_t idx, struct xive_nvp *vp) +{ + struct xive_nvp *vp_p = xive_get_vp(x, idx); + struct xive_nvp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(vp, &vp2, sizeof(struct xive_nvp)) != 0) { + xive_err(x, "VP update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + vp->w0, vp->w1, vp->w2, vp->w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp->w4, vp->w5, vp->w6, vp->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + return false; + } + return true; +} +#else +static inline bool xive_check_endc_update(struct xive *x __unused, + uint32_t idx __unused, + struct xive_end *end __unused) +{ + return true; +} + +static inline bool xive_check_nxc_update(struct xive *x __unused, + uint32_t idx __unused, + struct xive_nvp *vp __unused) +{ + return true; +} +#endif + +static int64_t xive_escalation_ive_cache_update(struct xive *x, uint64_t block, + uint64_t idx, struct xive_eas *eas, + bool synchronous) +{ + return __xive_cache_watch(x, xive_cache_endc, block, idx, + 2, 1, &eas->w, true, synchronous); +} + +static int64_t xive_endc_cache_update(struct xive *x, uint64_t block, + uint64_t idx, struct xive_end *end, + bool synchronous) +{ + int64_t ret; + + ret = __xive_cache_watch(x, xive_cache_endc, block, idx, + 0, 4, (beint64_t *)end, false, synchronous); + xive_check_endc_update(x, idx, end); + return ret; +} + +static int64_t xive_nxc_cache_update(struct xive *x, uint64_t block, + uint64_t idx, struct xive_nvp *vp, + bool synchronous) +{ + int64_t ret; + + ret = __xive_cache_watch(x, xive_cache_nxc, block, idx, + 0, 4, (beint64_t *)vp, false, synchronous); + xive_check_nxc_update(x, idx, vp); + return ret; +} + +/* + * VSD + */ +static bool xive_set_vsd(struct xive *x, uint32_t tbl, uint32_t idx, uint64_t v) +{ + /* Set VC subengine */ + xive_regw(x, VC_VSD_TABLE_ADDR, + SETFIELD(VC_VSD_TABLE_SELECT, 0ull, tbl) | + SETFIELD(VC_VSD_TABLE_ADDRESS, 0ull, idx)); + if (x->last_reg_error) + return false; + xive_regw(x, VC_VSD_TABLE_DATA, v); + if (x->last_reg_error) + return false; + + /* also set PC subengine if table is used */ + if (tbl == VST_EAS || tbl == VST_ERQ || tbl == VST_IC) + return true; + + xive_regw(x, PC_VSD_TABLE_ADDR, + SETFIELD(PC_VSD_TABLE_SELECT, 0ull, tbl) | + SETFIELD(PC_VSD_TABLE_ADDRESS, 0ull, idx)); + if (x->last_reg_error) + return false; + xive_regw(x, PC_VSD_TABLE_DATA, v); + if (x->last_reg_error) + return false; + return true; +} + +static bool xive_set_local_tables(struct xive *x) +{ + uint64_t base, i; + + /* These have to be power of 2 sized */ + assert(is_pow2(XIVE_ESB_SIZE)); + assert(is_pow2(XIVE_EAT_SIZE)); + + /* All tables set as exclusive */ + base = SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); + + /* ESB: direct mode */ + if (!xive_set_vsd(x, VST_ESB, x->block_id, base | + (((uint64_t)x->sbe_base) & VSD_ADDRESS_MASK) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(XIVE_ESB_SIZE) - 12))) + return false; + + /* EAS: direct mode */ + if (!xive_set_vsd(x, VST_EAS, x->block_id, base | + (((uint64_t)x->eat_base) & VSD_ADDRESS_MASK) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(XIVE_EAT_SIZE) - 12))) + return false; + + /* END: indirect mode with 64K subpages */ + if (!xive_set_vsd(x, VST_END, x->block_id, base | + (((uint64_t)x->end_ind_base) & VSD_ADDRESS_MASK) | + VSD_INDIRECT | SETFIELD(VSD_TSIZE, 0ull, + ilog2(x->end_ind_size) - 12))) + return false; + + /* NVP: indirect mode with 64K subpages */ + if (!xive_set_vsd(x, VST_NVP, x->block_id, base | + (((uint64_t)x->vp_ind_base) & VSD_ADDRESS_MASK) | + VSD_INDIRECT | SETFIELD(VSD_TSIZE, 0ull, + ilog2(x->vp_ind_size) - 12))) + return false; + + /* NVG: not used */ + /* NVC: not used */ + + /* INT and SYNC: indexed with the Topology# */ + if (!xive_set_vsd(x, VST_IC, x->chip_id, base | + (((uint64_t)x->ic_base) & VSD_ADDRESS_MASK) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->ic_size) - 12))) + return false; + + if (!xive_set_vsd(x, VST_SYNC, x->chip_id, base | + (((uint64_t)x->sync_inject) & VSD_ADDRESS_MASK) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->sync_inject_size) - 12))) + return false; + + /* + * ERQ: one 64K page for each queue overflow. Indexed with : + * + * 0:IPI, 1:HWD, 2:NxC, 3:INT, 4:OS-Queue, 5:Pool-Queue, 6:Hard-Queue + */ + for (i = 0; i < VC_QUEUE_COUNT; i++) { + u64 addr = ((uint64_t)x->q_ovf) + i * PAGE_SIZE; + u64 cfg, sreg, sregx; + + if (!xive_set_vsd(x, VST_ERQ, i, base | + (addr & VSD_ADDRESS_MASK) | + SETFIELD(VSD_TSIZE, 0ull, 4))) + return false; + + sreg = VC_QUEUES_CFG_REM0 + i * 8; + sregx = X_VC_QUEUES_CFG_REM0 + i; + cfg = __xive_regr(x, sreg, sregx, NULL); + cfg |= VC_QUEUES_CFG_MEMB_EN; + cfg = SETFIELD(VC_QUEUES_CFG_MEMB_SZ, cfg, 4); + __xive_regw(x, sreg, sregx, cfg, NULL); + } + + return true; +} + + +/* + * IC BAR layout + * + * Page 0: Internal CQ register accesses (reads & writes) + * Page 1: Internal PC register accesses (reads & writes) + * Page 2: Internal VC register accesses (reads & writes) + * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) + * Page 4: Notify Port page (writes only, w/data), + * Page 5: Reserved + * Page 6: Sync Poll page (writes only, dataless) + * Page 7: Sync Inject page (writes only, dataless) + * Page 8: LSI Trigger page (writes only, dataless) + * Page 9: LSI SB Management page (reads & writes dataless) + * Pages 10-255: Reserved + * Pages 256-383: Direct mapped Thread Context Area (reads & writes) + * covering the 128 threads in P10. + * Pages 384-511: Reserved + */ + +#define XIVE_IC_CQ_PGOFF 0 +#define XIVE_IC_PC_PGOFF 1 +#define XIVE_IC_VC_PGOFF 2 +#define XIVE_IC_TCTXT_PGOFF 3 +#define XIVE_NOTIFY_PGOFF 4 +#define XIVE_SYNC_POLL_PGOFF 6 +#define XIVE_SYNC_INJECT_PGOFF 7 +#define XIVE_LSI_TRIGGER_PGOFF 8 +#define XIVE_LSI_MGMT_PGOFF 9 +#define XIVE_IC_TM_DIRECT_PGOFF 256 + +static bool xive_configure_ic_bars(struct xive *x) +{ + uint64_t chip_id = x->chip_id; + uint64_t val; + + /* Reset all bars to zero */ + xive_regwx(x, CQ_RST_CTL, CQ_RST_PB_BAR_RESET); + + /* IC BAR */ + phys_map_get(chip_id, XIVE_IC, 0, (uint64_t *)&x->ic_base, &x->ic_size); + val = (uint64_t)x->ic_base | CQ_IC_BAR_VALID | CQ_IC_BAR_64K; + x->ic_shift = 16; + + xive_regwx(x, CQ_IC_BAR, val); + if (x->last_reg_error) + return false; + + /* + * TM BAR, same address for each chip. Hence we create a fake + * chip 0 and use that for all phys_map_get(XIVE_TM) calls. + */ + phys_map_get(0, XIVE_TM, 0, (uint64_t *)&x->tm_base, &x->tm_size); + val = (uint64_t)x->tm_base | CQ_TM_BAR_VALID | CQ_TM_BAR_64K; + x->tm_shift = 16; + + xive_regwx(x, CQ_TM_BAR, val); + if (x->last_reg_error) + return false; + + /* IC BAR sub-pages shortcuts */ + x->ic_tm_direct_base = x->ic_base + + (XIVE_IC_TM_DIRECT_PGOFF << x->ic_shift); + + return true; +} + +/* + * NVPG, NVC, ESB, END BARs have common attributes: 64k page and only + * one set covering the whole BAR. + */ +static bool xive_configure_bars(struct xive *x) +{ + uint64_t chip_id = x->chip_id; + uint64_t val; + uint64_t esb_size; + uint64_t end_size; + uint64_t nvp_size; + + x->nvp_size = XIVE_VP_COUNT(x) << XIVE_NVP_SHIFT; + x->esb_size = XIVE_INT_COUNT << XIVE_ESB_SHIFT; + x->end_size = XIVE_END_COUNT << XIVE_END_SHIFT; + + /* + * NVC BAR is not configured because we do not use the XIVE2 + * Crowd capability. + */ + + /* NVPG BAR: two pages, even NVP, odd NVG */ + phys_map_get(chip_id, XIVE_NVPG, 0, (uint64_t *)&x->nvp_base, &nvp_size); + if (x->nvp_size > nvp_size) { + xive_err(x, "NVP table is larger than default: " + "0x%012llx > 0x%012llx\n", x->nvp_size, nvp_size); + return false; + } + + val = (uint64_t)x->nvp_base | CQ_BAR_VALID | CQ_BAR_64K | + SETFIELD(CQ_BAR_RANGE, 0ull, ilog2(x->nvp_size) - 24); + xive_regwx(x, CQ_NVPG_BAR, val); + if (x->last_reg_error) + return false; + + /* ESB BAR */ + phys_map_get(chip_id, XIVE_ESB, 0, (uint64_t *)&x->esb_base, &esb_size); + if (x->esb_size > esb_size) { + xive_err(x, "ESB table is larger than default: " + "0x%012llx > 0x%012llx\n", x->esb_size, esb_size); + return false; + } + + val = (uint64_t)x->esb_base | CQ_BAR_VALID | CQ_BAR_64K | + SETFIELD(CQ_BAR_RANGE, 0ull, ilog2(x->esb_size) - 24); + xive_regwx(x, CQ_ESB_BAR, val); + if (x->last_reg_error) + return false; + + /* END BAR */ + phys_map_get(chip_id, XIVE_END, 0, (uint64_t *)&x->end_base, &end_size); + if (x->end_size > end_size) { + xive_err(x, "END table is larger than default: " + "0x%012llx > 0x%012llx\n", x->end_size, end_size); + return false; + } + + val = (uint64_t)x->end_base | CQ_BAR_VALID | CQ_BAR_64K | + SETFIELD(CQ_BAR_RANGE, 0ull, ilog2(x->end_size) - 24); + xive_regwx(x, CQ_END_BAR, val); + if (x->last_reg_error) + return false; + + xive_dbg(x, "IC: %14p [0x%012llx]\n", x->ic_base, x->ic_size); + xive_dbg(x, "TM: %14p [0x%012llx]\n", x->tm_base, x->tm_size); + xive_dbg(x, "NVP: %14p [0x%012llx]\n", x->nvp_base, x->nvp_size); + xive_dbg(x, "ESB: %14p [0x%012llx]\n", x->esb_base, x->esb_size); + xive_dbg(x, "END: %14p [0x%012llx]\n", x->end_base, x->end_size); + + return true; +} + +static void xive_dump_mmio(struct xive *x) +{ + prlog(PR_DEBUG, " CQ_CFG_PB_GEN = %016llx\n", + in_be64(x->ic_base + CQ_CFG_PB_GEN)); + prlog(PR_DEBUG, " CQ_MSGSND = %016llx\n", + in_be64(x->ic_base + CQ_MSGSND)); +} + +static const struct { + uint64_t bitmask; + const char *name; +} xive_capabilities[] = { +}; + +static void xive_dump_capabilities(struct xive *x, uint64_t cap_val) +{ + int i; + + xive_dbg(x, "capabilities: %016llx\n", cap_val); + xive_dbg(x, "\tVersion: %lld\n", + GETFIELD(CQ_XIVE_CAP_VERSION, cap_val)); + xive_dbg(x, "\tUser interrupt priorities: [ 1 - %d ]\n", + 1 << GETFIELD(CQ_XIVE_CAP_USER_INT_PRIO, cap_val)); + xive_dbg(x, "\tVP interrupt priorities: [ %d - 8 ]\n", + 1 << GETFIELD(CQ_XIVE_CAP_VP_INT_PRIO, cap_val)); + xive_dbg(x, "\tExtended Blockid bits: %lld\n", + 4 + GETFIELD(CQ_XIVE_CAP_BLOCK_ID_WIDTH, cap_val)); + + for (i = 0; i < ARRAY_SIZE(xive_capabilities); i++) { + if (xive_capabilities[i].bitmask & cap_val) + xive_dbg(x, "\t%s\n", xive_capabilities[i].name); + } +} + +static const struct { + uint64_t bitmask; + const char *name; +} xive_configs[] = { + { CQ_XIVE_CFG_GEN1_TIMA_OS, "Gen1 mode TIMA OS" }, + { CQ_XIVE_CFG_GEN1_TIMA_HYP, "Gen1 mode TIMA Hyp" }, + { CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0, "Gen1 mode TIMA General Hypervisor Block0" }, + { CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS, "Gen1 mode TIMA Crowd disable" }, + { CQ_XIVE_CFG_GEN1_END_ESX, "Gen1 mode END ESx" }, +}; + +static void xive_dump_configuration(struct xive *x, const char *prefix, + uint64_t cfg_val) +{ + int i ; + + xive_dbg(x, "%s configuration: %016llx\n", prefix, cfg_val); + xive_dbg(x, "\tHardwired Thread Id range: %lld bits\n", + 7 + GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, cfg_val)); + xive_dbg(x, "\tUser Interrupt priorities: [ 1 - %d ]\n", + 1 << GETFIELD(CQ_XIVE_CFG_USER_INT_PRIO, cfg_val)); + xive_dbg(x, "\tVP Interrupt priorities: [ 0 - %d ]\n", xive_max_prio(x)); + xive_dbg(x, "\tBlockId bits: %lld bits\n", + 4 + GETFIELD(CQ_XIVE_CFG_BLOCK_ID_WIDTH, cfg_val)); + if (CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE & cfg_val) + xive_dbg(x, "\tHardwired BlockId: %lld\n", + GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val)); + + for (i = 0; i < ARRAY_SIZE(xive_configs); i++) { + if (xive_configs[i].bitmask & cfg_val) + xive_dbg(x, "\t%s\n", xive_configs[i].name); + } +} + +/* + * Default XIVE configuration + */ +#define XIVE_CONFIGURATION \ + (SETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 0ull, CQ_XIVE_CFG_THREADID_8BITS) | \ + SETFIELD(CQ_XIVE_CFG_VP_INT_PRIO, 0ull, CQ_XIVE_CFG_INT_PRIO_8)) + +/* + * Gen1 configuration for tests (QEMU) + */ +#define XIVE_CONFIGURATION_GEN1 \ + (SETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 0ull, CQ_XIVE_CFG_THREADID_7BITS) | \ + SETFIELD(CQ_XIVE_CFG_VP_INT_PRIO, 0ull, CQ_XIVE_CFG_INT_PRIO_8) | \ + CQ_XIVE_CFG_GEN1_TIMA_OS | \ + CQ_XIVE_CFG_GEN1_TIMA_HYP | \ + CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 | \ + CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS | \ + CQ_XIVE_CFG_GEN1_END_ESX) + +static void xive_config_reduced_priorities_fixup(struct xive *x) +{ + if (xive_cfg_vp_prio_shift(x) < CQ_XIVE_CFG_INT_PRIO_8 && + x->quirks & XIVE_QUIRK_BROKEN_PRIO_CHECK) { + uint64_t val = xive_regr(x, PC_ERR1_CFG1); + + val &= ~PC_ERR1_CFG1_INTERRUPT_INVALID_PRIO; + xive_dbg(x, "workaround for reduced priorities. " + "PC_ERR1_CFG1=%016llx\n", val); + xive_regw(x, PC_ERR1_CFG1, val); + } +} + +static bool xive_config_init(struct xive *x) +{ + uint64_t cap_val; + + cap_val = xive_regr(x, CQ_XIVE_CAP); + xive_dump_capabilities(x, cap_val); + + x->generation = GETFIELD(CQ_XIVE_CAP_VERSION, cap_val); + + /* + * Allow QEMU to override version for tests + */ + if (x->generation != XIVE_GEN2 && !chip_quirk(QUIRK_QEMU)) { + xive_err(x, "Invalid XIVE controller version %d\n", + x->generation); + return false; + } + + x->config = xive_regr(x, CQ_XIVE_CFG); + xive_dump_configuration(x, "default", x->config); + + /* Start with default settings */ + x->config = x->generation == XIVE_GEN1 ? XIVE_CONFIGURATION_GEN1 : + XIVE_CONFIGURATION; + + if (x->quirks & XIVE_QUIRK_THREADID_7BITS) + x->config = SETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, x->config, + CQ_XIVE_CFG_THREADID_7BITS); + + /* + * Hardwire the block ID. The default value is the topology ID + * of the chip which is different from the block. + */ + x->config |= CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE | + SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, x->block_id); + + xive_dump_configuration(x, "new", x->config); + xive_regw(x, CQ_XIVE_CFG, x->config); + if (xive_regr(x, CQ_XIVE_CFG) != x->config) { + xive_err(x, "configuration setting failed\n"); + } + + /* + * Disable error reporting in the FIR for info errors from the VC. + */ + xive_regw(x, CQ_FIRMASK_OR, CQ_FIR_VC_INFO_ERROR_0_2); + + /* + * Mask CI Load and Store to bad location, as IPI trigger + * pages may be mapped to user space, and a read on the + * trigger page causes a checkstop + */ + xive_regw(x, CQ_FIRMASK_OR, CQ_FIR_PB_RCMDX_CI_ERR1); + + /* + * VP space settings. P9 mode is 19bits. + */ + x->vp_shift = x->generation == XIVE_GEN1 ? + VP_SHIFT_GEN1 : VP_SHIFT_GEN2; + + /* + * VP ids for HW threads. These values are hardcoded in the + * CAM line of the HW context + * + * POWER10 |chip|0000000000000001|threadid| + * 28bits 4 16 8 + * + * POWER9 |chip|000000000001|thrdid | + * 23bits 4 12 7 + */ + + /* TODO (cosmetic): set VP ids for HW threads only once */ + xive_threadid_shift = 7 + GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, + x->config); + + xive_hw_vp_base = 1 << xive_threadid_shift; + xive_hw_vp_count = 1 << xive_threadid_shift; + + xive_dbg(x, "store EOI is %savailable\n", + XIVE_CAN_STORE_EOI(x) ? "" : "not "); + + xive_config_reduced_priorities_fixup(x); + + return true; +} + +/* Set Translation tables : 1 block per chip */ +static bool xive_setup_set_xlate(struct xive *x) +{ + unsigned int i; + + /* Configure ESBs */ + xive_regw(x, CQ_TAR, + CQ_TAR_AUTOINC | SETFIELD(CQ_TAR_SELECT, 0ull, CQ_TAR_ESB)); + if (x->last_reg_error) + return false; + for (i = 0; i < XIVE_MAX_BLOCKS; i++) { + xive_regw(x, CQ_TDR, CQ_TDR_VALID | + SETFIELD(CQ_TDR_BLOCK_ID, 0ull, x->block_id)); + if (x->last_reg_error) + return false; + } + + /* Configure ENDs */ + xive_regw(x, CQ_TAR, + CQ_TAR_AUTOINC | SETFIELD(CQ_TAR_SELECT, 0ull, CQ_TAR_END)); + if (x->last_reg_error) + return false; + for (i = 0; i < XIVE_MAX_BLOCKS; i++) { + xive_regw(x, CQ_TDR, CQ_TDR_VALID | + SETFIELD(CQ_TDR_BLOCK_ID, 0ull, x->block_id)); + if (x->last_reg_error) + return false; + } + + /* Configure NVPs */ + xive_regw(x, CQ_TAR, + CQ_TAR_AUTOINC | SETFIELD(CQ_TAR_SELECT, 0ull, CQ_TAR_NVPG)); + if (x->last_reg_error) + return false; + for (i = 0; i < XIVE_MAX_BLOCKS; i++) { + xive_regw(x, CQ_TDR, CQ_TDR_VALID | + SETFIELD(CQ_TDR_BLOCK_ID, 0ull, x->block_id)); + if (x->last_reg_error) + return false; + } + return true; +} + +static bool xive_prealloc_tables(struct xive *x) +{ + uint32_t i; + uint32_t pbase, pend; + + /* ESB has 4 entries per byte */ + x->sbe_base = local_alloc(x->chip_id, XIVE_ESB_SIZE, XIVE_ESB_SIZE); + if (!x->sbe_base) { + xive_err(x, "Failed to allocate SBE\n"); + return false; + } + + /* PQs are initialized to 0b01 which corresponds to "ints off" */ + memset(x->sbe_base, 0x55, XIVE_ESB_SIZE); + xive_dbg(x, "SBE at %p size 0x%lx\n", x->sbe_base, XIVE_ESB_SIZE); + + /* EAS entries are 8 bytes */ + x->eat_base = local_alloc(x->chip_id, XIVE_EAT_SIZE, XIVE_EAT_SIZE); + if (!x->eat_base) { + xive_err(x, "Failed to allocate EAS\n"); + return false; + } + + /* + * We clear the entries (non-valid). They will be initialized + * when actually used + */ + memset(x->eat_base, 0, XIVE_EAT_SIZE); + xive_dbg(x, "EAT at %p size 0x%lx\n", x->eat_base, XIVE_EAT_SIZE); + + /* Indirect END table. Limited to one top page. */ + x->end_ind_size = ALIGN_UP(XIVE_END_TABLE_SIZE, PAGE_SIZE); + if (x->end_ind_size > PAGE_SIZE) { + xive_err(x, "END indirect table is too big !\n"); + return false; + } + x->end_ind_base = local_alloc(x->chip_id, x->end_ind_size, + x->end_ind_size); + if (!x->end_ind_base) { + xive_err(x, "Failed to allocate END indirect table\n"); + return false; + } + memset(x->end_ind_base, 0, x->end_ind_size); + xive_dbg(x, "ENDi at %p size 0x%llx #%ld entries\n", x->end_ind_base, + x->end_ind_size, XIVE_END_COUNT); + x->end_ind_count = XIVE_END_TABLE_SIZE / XIVE_VSD_SIZE; + + /* Indirect VP table. Limited to one top page. */ + x->vp_ind_size = ALIGN_UP(XIVE_VP_TABLE_SIZE(x), PAGE_SIZE); + if (x->vp_ind_size > PAGE_SIZE) { + xive_err(x, "VP indirect table is too big !\n"); + return false; + } + x->vp_ind_base = local_alloc(x->chip_id, x->vp_ind_size, + x->vp_ind_size); + if (!x->vp_ind_base) { + xive_err(x, "Failed to allocate VP indirect table\n"); + return false; + } + xive_dbg(x, "VPi at %p size 0x%llx #%ld entries\n", x->vp_ind_base, + x->vp_ind_size, XIVE_VP_COUNT(x)); + x->vp_ind_count = XIVE_VP_TABLE_SIZE(x) / XIVE_VSD_SIZE; + memset(x->vp_ind_base, 0, x->vp_ind_size); + + /* Allocate pages for the VP ids representing HW threads */ + pbase = xive_hw_vp_base / VP_PER_PAGE; + pend = (xive_hw_vp_base + xive_hw_vp_count) / VP_PER_PAGE; + + xive_dbg(x, "Allocating pages %d to %d of VPs (for %d VPs)\n", + pbase, pend, xive_hw_vp_count); + for (i = pbase; i <= pend; i++) { + void *page; + u64 vsd; + + /* Indirect entries have a VSD format */ + page = local_alloc(x->chip_id, PAGE_SIZE, PAGE_SIZE); + if (!page) { + xive_err(x, "Failed to allocate VP page\n"); + return false; + } + xive_dbg(x, "VP%d at %p size 0x%x\n", i, page, PAGE_SIZE); + memset(page, 0, PAGE_SIZE); + vsd = ((uint64_t)page) & VSD_ADDRESS_MASK; + + vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); + vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); + vsd |= VSD_FIRMWARE; + x->vp_ind_base[i] = cpu_to_be64(vsd); + } + + /* + * Allocate page for cache and sync injection (512 * 128 hw + * threads) + one extra page for future use + */ + x->sync_inject_size = PAGE_SIZE + PAGE_SIZE; + x->sync_inject = local_alloc(x->chip_id, x->sync_inject_size, + x->sync_inject_size); + if (!x->sync_inject) { + xive_err(x, "Failed to allocate sync pages\n"); + return false; + } + + /* Allocate the queue overflow pages */ + x->q_ovf = local_alloc(x->chip_id, VC_QUEUE_COUNT * PAGE_SIZE, PAGE_SIZE); + if (!x->q_ovf) { + xive_err(x, "Failed to allocate queue overflow\n"); + return false; + } + return true; +} + +static void xive_add_provisioning_properties(void) +{ + beint32_t chips[XIVE_MAX_CHIPS]; + uint32_t i, count; + + dt_add_property_cells(xive_dt_node, + "ibm,xive-provision-page-size", PAGE_SIZE); + + count = 1 << xive_chips_alloc_bits; + for (i = 0; i < count; i++) + chips[i] = cpu_to_be32(xive_block_to_chip[i]); + dt_add_property(xive_dt_node, "ibm,xive-provision-chips", + chips, 4 * count); +} + +static void xive_create_mmio_dt_node(struct xive *x) +{ + uint64_t tb = (uint64_t)x->tm_base; + uint32_t stride = 1u << x->tm_shift; + + xive_dt_node = dt_new_addr(dt_root, "interrupt-controller", tb); + assert(xive_dt_node); + + dt_add_property_u64s(xive_dt_node, "reg", + tb + 0 * stride, stride, + tb + 1 * stride, stride, + tb + 2 * stride, stride, + tb + 3 * stride, stride); + + dt_add_property_strings(xive_dt_node, "compatible", + "ibm,opal-xive-pe", "ibm,opal-intc"); + + dt_add_property_cells(xive_dt_node, "ibm,xive-eq-sizes", + 12, 16, 21, 24); + + dt_add_property_cells(xive_dt_node, "ibm,xive-#priorities", + xive_cfg_vp_prio(x)); + + dt_add_property(xive_dt_node, "single-escalation-support", NULL, 0); + + if (XIVE_CAN_STORE_EOI(x)) + dt_add_property(xive_dt_node, "store-eoi", NULL, 0); + + xive_add_provisioning_properties(); + +} + +static void xive_setup_forward_ports(struct xive *x, struct proc_chip *remote_chip) +{ + struct xive *remote_xive = remote_chip->xive; + uint64_t base = SETFIELD(VSD_MODE, 0ull, VSD_MODE_FORWARD); + + if (!xive_set_vsd(x, VST_ESB, remote_xive->block_id, + base | ((uint64_t)remote_xive->esb_base) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->esb_size) - 12))) + goto error; + + /* EAS: No remote */ + + if (!xive_set_vsd(x, VST_END, remote_xive->block_id, + base | ((uint64_t)remote_xive->end_base) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->end_size) - 12))) + goto error; + + if (!xive_set_vsd(x, VST_NVP, remote_xive->block_id, + base | ((uint64_t)remote_xive->nvp_base) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->nvp_size) - 12))) + goto error; + + /* NVG: not used */ + /* NVC: not used */ + + if (!xive_set_vsd(x, VST_IC, remote_xive->chip_id, + base | ((uint64_t)remote_xive->ic_base) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->ic_size) - 12))) + goto error; + + if (!xive_set_vsd(x, VST_SYNC, remote_xive->chip_id, + base | ((uint64_t)remote_xive->sync_inject) | + SETFIELD(VSD_TSIZE, 0ull, ilog2(x->sync_inject_size) - 12))) + goto error; + + /* ERQ: No remote */ + + return; + + error: + xive_err(x, "Failure configuring forwarding ports\n"); +} + +static void late_init_one_xive(struct xive *x) +{ + struct proc_chip *chip; + + /* We need to setup the cross-chip forward ports. Let's + * iterate all chip and set them up accordingly + */ + for_each_chip(chip) { + /* We skip ourselves or chips without a xive */ + if (chip->xive == x || !chip->xive) + continue; + + /* Setup our forward ports to that chip */ + xive_setup_forward_ports(x, chip); + } +} + +static bool xive_check_ipi_free(struct xive *x, uint32_t irq, uint32_t count) +{ + uint32_t i, idx = GIRQ_TO_IDX(irq); + + for (i = 0; i < count; i++) + if (bitmap_tst_bit(*x->ipi_alloc_map, idx + i)) + return false; + return true; +} + +uint32_t xive2_alloc_hw_irqs(uint32_t chip_id, uint32_t count, + uint32_t align) +{ + struct proc_chip *chip = get_chip(chip_id); + struct xive *x; + uint32_t base, i; + + assert(chip); + assert(is_pow2(align)); + + x = chip->xive; + assert(x); + + lock(&x->lock); + + /* Allocate the HW interrupts */ + base = x->int_hw_bot - count; + base &= ~(align - 1); + if (base < x->int_ipi_top) { + xive_err(x, + "HW alloc request for %d interrupts aligned to %d failed\n", + count, align); + unlock(&x->lock); + return XIVE_IRQ_ERROR; + } + if (!xive_check_ipi_free(x, base, count)) { + xive_err(x, "HWIRQ boot allocator request overlaps dynamic allocator\n"); + unlock(&x->lock); + return XIVE_IRQ_ERROR; + } + + x->int_hw_bot = base; + + /* Initialize the corresponding EAS entries to sane defaults, + * IE entry is valid, not routed and masked, EQ data is set + * to the GIRQ number. + */ + for (i = 0; i < count; i++) { + struct xive_eas *eas = xive_get_eas(x, base + i); + + eas->w = xive_set_field64(EAS_VALID, 0, 1) | + xive_set_field64(EAS_MASKED, 0, 1) | + xive_set_field64(EAS_END_DATA, 0, base + i); + } + + unlock(&x->lock); + return base; +} + +uint32_t xive2_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, + uint32_t align) +{ + struct proc_chip *chip = get_chip(chip_id); + struct xive *x; + uint32_t base, i; + + assert(chip); + assert(is_pow2(align)); + + x = chip->xive; + assert(x); + + lock(&x->lock); + + /* Allocate the IPI interrupts */ + base = x->int_ipi_top + (align - 1); + base &= ~(align - 1); + if (base >= x->int_hw_bot) { + xive_err(x, + "IPI alloc request for %d interrupts aligned to %d failed\n", + count, align); + unlock(&x->lock); + return XIVE_IRQ_ERROR; + } + if (!xive_check_ipi_free(x, base, count)) { + xive_err(x, "IPI boot allocator request overlaps dynamic allocator\n"); + unlock(&x->lock); + return XIVE_IRQ_ERROR; + } + + x->int_ipi_top = base + count; + + /* Initialize the corresponding EAS entries to sane defaults, + * IE entry is valid, not routed and masked, END data is set + * to the GIRQ number. + */ + for (i = 0; i < count; i++) { + struct xive_eas *eas = xive_get_eas(x, base + i); + + eas->w = xive_set_field64(EAS_VALID, 0, 1) | + xive_set_field64(EAS_MASKED, 0, 1) | + xive_set_field64(EAS_END_DATA, 0, base + i); + } + + unlock(&x->lock); + return base; +} + +void *xive2_get_trigger_port(uint32_t girq) +{ + uint32_t idx = GIRQ_TO_IDX(girq); + struct xive *x; + + /* Find XIVE on which the EAS resides */ + x = xive_from_isn(girq); + if (!x) + return NULL; + + if (GIRQ_IS_ESCALATION(girq)) { + /* There is no trigger page for escalation interrupts */ + return NULL; + } else { + /* Make sure it's an IPI on that chip */ + if (girq < x->int_base || + girq >= x->int_ipi_top) + return NULL; + + return x->esb_base + idx * XIVE_ESB_PAGE_SIZE; + } +} + +/* + * Notify Port page (writes only, w/data), separated into two + * categories, both sent to VC: + * - IPI queue (Addr bit 52 = 0) (for NPU) + * - HW queue (Addr bit 52 = 1) + */ +uint64_t xive2_get_notify_port(uint32_t chip_id, uint32_t ent) +{ + struct proc_chip *chip = get_chip(chip_id); + struct xive *x; + uint32_t offset = 0; + + assert(chip); + x = chip->xive; + assert(x); + + /* This is where we can assign a different HW queue to a different + * source by offsetting into the cache lines of the notify port + * + * For now we keep it very basic, this will have to be looked at + * again on real HW with some proper performance analysis. + * + * Here's what Florian says on the matter: + * + * << + * The first 2k of the notify port page can all be used for PCIe triggers + * + * However the idea would be that we try to use the first 4 cache lines to + * balance the PCIe Interrupt requests to use the least used snoop buses + * (we went from 2 to 4 snoop buses for P9). snoop 0 is heavily used + * (I think TLBIs are using that in addition to the normal addresses), + * snoop 3 is used for all Int commands, so I think snoop 2 (CL 2 in the + * page) is the least used overall. So we probably should that one for + * the Int commands from PCIe. + * + * In addition, our EAS cache supports hashing to provide "private" cache + * areas for the PHBs in the shared 1k EAS cache. This allows e.g. to avoid + * that one "thrashing" PHB thrashes the EAS cache for everyone, or provide + * a PHB with a private area that would allow high cache hits in case of a + * device using very few interrupts. The hashing is based on the offset within + * the cache line. So using that, you can e.g. set the EAS cache up so that + * IPIs use 512 entries, the x16 PHB uses 256 entries and the x8 PHBs 128 + * entries each - or IPIs using all entries and sharing with PHBs, so PHBs + * would use 512 entries and 256 entries respectively. + * + * This is a tuning we would probably do later in the lab, but as a "prep" + * we should set up the different PHBs such that they are using different + * 8B-aligned offsets within the cache line, so e.g. + * PH4_0 addr 0x100 (CL 2 DW0 + * PH4_1 addr 0x108 (CL 2 DW1) + * PH4_2 addr 0x110 (CL 2 DW2) + * etc. + * >> + * + * I'm using snoop1 for PHB0 and snoop2 for everybody else. + */ + + /* Florian adds : + * + * we just set them up for a start to have different offsets + * within the cache line so that we could use the allocation + * restrictions that can be enforced in the interrupt + * controller + * + * P10 might now be randomizing the cache line bits in HW to + * balance snoop bus usage + * + * TODO (phb5) : implement "address based triggers" (DD2.0?) + * + * The PHBs would no longer target the notify port page but + * the "base ESB MMIO address" of the ESB/EAS range they are + * allocated. Needs a XIVE API change for the PHBs. + */ + switch(ent) { + case XIVE_HW_SRC_PHBn(0): + offset = 0x800; + break; + case XIVE_HW_SRC_PHBn(1): + offset = 0x908; + break; + case XIVE_HW_SRC_PHBn(2): + offset = 0x910; + break; + case XIVE_HW_SRC_PHBn(3): + offset = 0x918; + break; + case XIVE_HW_SRC_PHBn(4): + offset = 0x920; + break; + case XIVE_HW_SRC_PHBn(5): + offset = 0x928; + break; + case XIVE_HW_SRC_PSI: + offset = 0x930; + break; + default: + assert(false); + return 0; + } + + return ((uint64_t)x->ic_base) + + (XIVE_NOTIFY_PGOFF << x->ic_shift) + offset; +} + +/* Manufacture the powerbus packet bits 32:63 */ +__attrconst uint32_t xive2_get_notify_base(uint32_t girq) +{ + return (GIRQ_TO_BLK(girq) << 28) | GIRQ_TO_IDX(girq); +} + +static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, + uint8_t *out_prio, uint32_t *out_lirq) +{ + struct xive_eas *eas; + struct xive *x, *end_x; + struct xive_end *end; + uint32_t end_blk, end_idx; + uint32_t vp_blk, vp_idx; + uint32_t prio, server; + bool is_escalation = GIRQ_IS_ESCALATION(isn); + + /* Find XIVE on which the EAS resides */ + x = xive_from_isn(isn); + if (!x) + return false; + /* Grab the EAS */ + eas = xive_get_eas(x, isn); + if (!eas) + return false; + if (!xive_get_field64(EAS_VALID, eas->w) && !is_escalation) { + xive_err(x, "ISN %x lead to invalid EAS !\n", isn); + return false; + } + + if (out_lirq) + *out_lirq = xive_get_field64(EAS_END_DATA, eas->w); + + /* Find the END and its xive instance */ + end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); + end_idx = xive_get_field64(EAS_END_INDEX, eas->w); + end_x = xive_from_vc_blk(end_blk); + + /* This can fail if the interrupt hasn't been initialized yet + * but it should also be masked, so fail silently + */ + if (!end_x) + goto pick_default; + end = xive_get_end(end_x, end_idx); + if (!end) + goto pick_default; + + /* XXX Check valid and format 0 */ + + /* No priority conversion, return the actual one ! */ + if (xive_get_field64(EAS_MASKED, eas->w)) + prio = 0xff; + else + prio = xive_get_field32(END_W7_F0_PRIORITY, end->w7); + if (out_prio) + *out_prio = prio; + + vp_blk = xive_get_field32(END_W6_VP_BLOCK, end->w6); + vp_idx = xive_get_field32(END_W6_VP_OFFSET, end->w6); + server = VP2PIR(vp_blk, vp_idx); + + if (out_target) + *out_target = server; + + xive_vdbg(end_x, "END info for ISN %x: prio=%d, server=0x%x (VP %x/%x)\n", + isn, prio, server, vp_blk, vp_idx); + return true; + +pick_default: + xive_vdbg(end_x, "END info for ISN %x: Using masked defaults\n", isn); + + if (out_prio) + *out_prio = 0xff; + /* Pick a random default, me will be fine ... */ + if (out_target) + *out_target = mfspr(SPR_PIR); + return true; +} + +static inline bool xive_end_for_target(uint32_t target, uint8_t prio, + uint32_t *out_end_blk, + uint32_t *out_end_idx) +{ + struct xive *x; + struct xive_nvp *vp; + uint32_t vp_blk, vp_idx; + uint32_t end_blk, end_idx; + + if (prio > xive_max_prio(one_xive)) + return false; + + /* Get the VP block/index from the target word */ + if (!xive_decode_vp(target, &vp_blk, &vp_idx, NULL, NULL)) + return false; + + /* Grab the target VP's XIVE */ + x = xive_from_pc_blk(vp_blk); + if (!x) + return false; + + /* Find the VP structrure where we stashed the END number */ + vp = xive_get_vp(x, vp_idx); + if (!vp) + return false; + + end_blk = xive_get_field32(NVP_W5_VP_END_BLOCK, vp->w5); + end_idx = xive_get_field32(NVP_W5_VP_END_INDEX, vp->w5); + + /* Currently the END block and VP block should be the same */ + if (end_blk != vp_blk) { + xive_err(x, "end_blk != vp_blk (%d vs. %d) for target 0x%08x/%d\n", + end_blk, vp_blk, target, prio); + assert(false); + } + + if (out_end_blk) + *out_end_blk = end_blk; + if (out_end_idx) + *out_end_idx = end_idx + prio; + + return true; +} + +static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, + uint8_t prio, uint32_t lirq, + bool synchronous) +{ + struct xive *x; + struct xive_eas *eas, new_eas; + uint32_t end_blk, end_idx; + bool is_escalation = GIRQ_IS_ESCALATION(isn); + int64_t rc; + + /* Find XIVE on which the EAS resides */ + x = xive_from_isn(isn); + if (!x) + return OPAL_PARAMETER; + /* Grab the EAS */ + eas = xive_get_eas(x, isn); + if (!eas) + return OPAL_PARAMETER; + if (!xive_get_field64(EAS_VALID, eas->w) && !is_escalation) { + xive_err(x, "ISN %x lead to invalid EAS !\n", isn); + return OPAL_PARAMETER; + } + + lock(&x->lock); + + /* Read existing EAS */ + new_eas = *eas; + + /* Are we masking ? */ + if (prio == 0xff && !is_escalation) { + new_eas.w = xive_set_field64(EAS_MASKED, new_eas.w, 1); + xive_vdbg(x, "ISN %x masked !\n", isn); + + /* Put prio 7 in the END */ + prio = xive_max_prio(x); + } else { + /* Unmasking */ + new_eas.w = xive_set_field64(EAS_MASKED, new_eas.w, 0); + xive_vdbg(x, "ISN %x unmasked !\n", isn); + + /* For normal interrupt sources, keep track of which ones + * we ever enabled since the last reset + */ + if (!is_escalation) + bitmap_set_bit(*x->int_enabled_map, GIRQ_TO_IDX(isn)); + } + + /* If prio isn't 0xff, re-target the EAS. First find the END + * correponding to the target + */ + if (prio != 0xff) { + if (!xive_end_for_target(target, prio, &end_blk, &end_idx)) { + xive_err(x, "Can't find END for target/prio 0x%x/%d\n", + target, prio); + unlock(&x->lock); + return OPAL_PARAMETER; + } + + /* Try to update it atomically to avoid an intermediary + * stale state + */ + new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); + new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); + } + new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, lirq); + + xive_vdbg(x,"ISN %x routed to end %x/%x lirq=%08x EAS=%016llx !\n", + isn, end_blk, end_idx, lirq, new_eas.w); + + /* Updating the cache differs between real EAS and escalation + * EAS inside an END + */ + if (is_escalation) { + rc = xive_escalation_ive_cache_update(x, x->block_id, + GIRQ_TO_IDX(isn), &new_eas, synchronous); + } else { + sync(); + *eas = new_eas; + rc = xive_easc_scrub(x, x->block_id, GIRQ_TO_IDX(isn)); + } + + unlock(&x->lock); + return rc; +} + +static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked) +{ + void *mmio_base = s->esb_mmio + (1ul << s->esb_shift) * idx; + uint32_t offset; + + /* XXX FIXME: A quick mask/umask can make us shoot an interrupt + * more than once to a queue. We need to keep track better + */ + if (s->flags & XIVE_SRC_EOI_PAGE1) + mmio_base += 1ull << (s->esb_shift - 1); + if (masked) + offset = XIVE_ESB_SET_PQ_01; + else + offset = XIVE_ESB_SET_PQ_00; + + in_be64(mmio_base + offset); +} + +#define XIVE_SYNC_IPI 0x000 +#define XIVE_SYNC_HW 0x080 +#define XIVE_SYNC_NxC 0x100 +#define XIVE_SYNC_INT 0x180 +#define XIVE_SYNC_OS_ESC 0x200 +#define XIVE_SYNC_POOL_ESC 0x280 +#define XIVE_SYNC_HARD_ESC 0x300 + +static int64_t xive_sync(struct xive *x __unused) +{ + uint64_t r; + void *sync_base; + + lock(&x->lock); + + sync_base = x->ic_base + (XIVE_SYNC_POLL_PGOFF << x->ic_shift); + + out_be64(sync_base + XIVE_SYNC_IPI, 0); + out_be64(sync_base + XIVE_SYNC_HW, 0); + out_be64(sync_base + XIVE_SYNC_NxC, 0); + out_be64(sync_base + XIVE_SYNC_INT, 0); + out_be64(sync_base + XIVE_SYNC_OS_ESC, 0); + out_be64(sync_base + XIVE_SYNC_POOL_ESC, 0); + out_be64(sync_base + XIVE_SYNC_HARD_ESC, 0); + + /* XXX Add timeout */ + for (;;) { + r = xive_regr(x, VC_ENDC_SYNC_DONE); + if ((r & VC_ENDC_SYNC_POLL_DONE) == VC_ENDC_SYNC_POLL_DONE) + break; + cpu_relax(); + } + xive_regw(x, VC_ENDC_SYNC_DONE, r & ~VC_ENDC_SYNC_POLL_DONE); + + /* + * Do a read after clearing the sync done bit to prevent any + * race between CI write and next sync command + */ + xive_regr(x, VC_ENDC_SYNC_DONE); + + unlock(&x->lock); + return 0; +} + +static int64_t __xive_set_irq_config(struct irq_source *is, uint32_t girq, + uint64_t vp, uint8_t prio, uint32_t lirq, + bool update_esb, bool sync) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + uint32_t old_target, vp_blk; + u8 old_prio; + int64_t rc; + + /* Grab existing target */ + if (!xive_get_irq_targetting(girq, &old_target, &old_prio, NULL)) + return OPAL_PARAMETER; + + /* Let XIVE configure the END. We do the update without the + * synchronous flag, thus a cache update failure will result + * in us returning OPAL_BUSY + */ + rc = xive_set_irq_targetting(girq, vp, prio, lirq, false); + if (rc) + return rc; + + /* Do we need to update the mask ? */ + if (old_prio != prio && (old_prio == 0xff || prio == 0xff)) { + /* The source has special variants of masking/unmasking */ + if (update_esb) { + /* Ensure it's enabled/disabled in the source + * controller + */ + xive_update_irq_mask(s, girq - s->esb_base, + prio == 0xff); + } + } + + /* + * Synchronize the source and old target XIVEs to ensure that + * all pending interrupts to the old target have reached their + * respective queue. + * + * WARNING: This assumes the VP and it's queues are on the same + * XIVE instance ! + */ + if (!sync) + return OPAL_SUCCESS; + xive_sync(s->xive); + if (xive_decode_vp(old_target, &vp_blk, NULL, NULL, NULL)) { + struct xive *x = xive_from_pc_blk(vp_blk); + if (x) + xive_sync(x); + } + + return OPAL_SUCCESS; +} + +static int64_t xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio, + uint32_t lirq, bool update_esb) +{ + struct irq_source *is = irq_find_source(girq); + + return __xive_set_irq_config(is, girq, vp, prio, lirq, update_esb, + true); +} + +static void xive_source_interrupt(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + if (!s->orig_ops || !s->orig_ops->interrupt) + return; + s->orig_ops->interrupt(is, isn); +} + +static uint64_t xive_source_attributes(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + if (!s->orig_ops || !s->orig_ops->attributes) + return IRQ_ATTR_TARGET_LINUX; + return s->orig_ops->attributes(is, isn); +} + +static char *xive_source_name(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + if (!s->orig_ops || !s->orig_ops->name) + return NULL; + return s->orig_ops->name(is, isn); +} + +static const struct irq_source_ops xive_irq_source_ops = { + .interrupt = xive_source_interrupt, + .attributes = xive_source_attributes, + .name = xive_source_name, +}; + +static void __xive_register_source(struct xive *x, struct xive_src *s, + uint32_t base, uint32_t count, + uint32_t shift, void *mmio, uint32_t flags, + bool secondary, void *data, + const struct irq_source_ops *orig_ops) +{ + s->esb_base = base; + s->esb_shift = shift; + s->esb_mmio = mmio; + s->flags = flags; + s->orig_ops = orig_ops; + s->xive = x; + s->is.start = base; + s->is.end = base + count; + s->is.ops = &xive_irq_source_ops; + s->is.data = data; + + __register_irq_source(&s->is, secondary); +} + +void xive2_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, + void *mmio, uint32_t flags, void *data, + const struct irq_source_ops *ops) +{ + struct xive_src *s; + struct xive *x = xive_from_isn(base); + + assert(x); + + s = malloc(sizeof(struct xive_src)); + assert(s); + __xive_register_source(x, s, base, count, shift, mmio, flags, + false, data, ops); +} + +void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, + const struct irq_source_ops *ops) +{ + struct xive_src *s; + struct xive *x = xive_from_isn(base); + uint32_t base_idx = GIRQ_TO_IDX(base); + void *mmio_base; + uint32_t flags = XIVE_SRC_EOI_PAGE1 | XIVE_SRC_TRIGGER_PAGE; + + assert(x); + assert(base >= x->int_base && (base + count) <= x->int_ipi_top); + + s = malloc(sizeof(struct xive_src)); + assert(s); + + if (XIVE_CAN_STORE_EOI(x)) + flags |= XIVE_SRC_STORE_EOI; + + /* Callbacks assume the MMIO base corresponds to the first + * interrupt of that source structure so adjust it + */ + mmio_base = x->esb_base + (1ul << XIVE_ESB_SHIFT) * base_idx; + __xive_register_source(x, s, base, count, XIVE_ESB_SHIFT, mmio_base, + flags, false, data, ops); +} + +static void xive_set_quirks(struct xive *x, struct proc_chip *chip __unused) +{ + uint64_t quirks = 0; + + /* This extension is dropped for P10 */ + if (proc_gen == proc_gen_p10) + quirks |= XIVE_QUIRK_THREADID_7BITS; + + /* Broken check on invalid priority when reduced priorities is in use */ + if (proc_gen == proc_gen_p10) + quirks |= XIVE_QUIRK_BROKEN_PRIO_CHECK; + + xive_dbg(x, "setting XIVE quirks to %016llx\n", quirks); + x->quirks = quirks; +} + +static struct xive *init_one_xive(struct dt_node *np) +{ + struct xive *x; + struct proc_chip *chip; + uint32_t flags; + + x = zalloc(sizeof(struct xive)); + assert(x); + x->x_node = np; + x->xscom_base = dt_get_address(np, 0, NULL); + x->chip_id = dt_get_chip_id(np); + + /* "Allocate" a new block ID for the chip */ + x->block_id = xive_block_count++; + assert (x->block_id < XIVE_MAX_CHIPS); + xive_block_to_chip[x->block_id] = x->chip_id; + init_lock(&x->lock); + + chip = get_chip(x->chip_id); + assert(chip); + + xive_notice(x, "Initializing XIVE block ID %d...\n", x->block_id); + chip->xive = x; + + xive_set_quirks(x, chip); + + list_head_init(&x->donated_pages); + + /* Base interrupt numbers and allocator init */ + + x->int_base = BLKIDX_TO_GIRQ(x->block_id, 0); + x->int_count = x->int_base + XIVE_INT_COUNT; + x->int_hw_bot = x->int_count; + x->int_ipi_top = x->int_base; + + if (x->int_ipi_top < XIVE_INT_FIRST) + x->int_ipi_top = XIVE_INT_FIRST; + + /* Allocate a few bitmaps */ + x->end_map = local_alloc(x->chip_id, BITMAP_BYTES(xive_end_bitmap_size(x)), PAGE_SIZE); + assert(x->end_map); + memset(x->end_map, 0, BITMAP_BYTES(xive_end_bitmap_size(x))); + + /* + * Allocate END index 0 to make sure it can not be used as an + * END base for a VP. This is the criteria to know if a VP was + * allocated. + */ + bitmap_set_bit(*x->end_map, 0); + + x->int_enabled_map = local_alloc(x->chip_id, BITMAP_BYTES(XIVE_INT_COUNT), PAGE_SIZE); + assert(x->int_enabled_map); + memset(x->int_enabled_map, 0, BITMAP_BYTES(XIVE_INT_COUNT)); + x->ipi_alloc_map = local_alloc(x->chip_id, BITMAP_BYTES(XIVE_INT_COUNT), PAGE_SIZE); + assert(x->ipi_alloc_map); + memset(x->ipi_alloc_map, 0, BITMAP_BYTES(XIVE_INT_COUNT)); + + xive_dbg(x, "Handling interrupts [%08x..%08x]\n", + x->int_base, x->int_count - 1); + + /* Setup the IC BARs */ + if (!xive_configure_ic_bars(x)) + goto fail; + + /* Some basic global inits such as page sizes etc... */ + if (!xive_config_init(x)) + goto fail; + + /* Configure the set translations for MMIO */ + if (!xive_setup_set_xlate(x)) + goto fail; + + /* Dump some MMIO registers for diagnostics */ + xive_dump_mmio(x); + + /* Pre-allocate a number of tables */ + if (!xive_prealloc_tables(x)) + goto fail; + + /* Setup the XIVE structures BARs */ + if (!xive_configure_bars(x)) + goto fail; + + /* + * Configure local tables in VSDs (forward ports will be + * handled later) + */ + if (!xive_set_local_tables(x)) + goto fail; + + /* Register built-in source controllers (aka IPIs) */ + flags = XIVE_SRC_EOI_PAGE1 | XIVE_SRC_TRIGGER_PAGE; + if (XIVE_CAN_STORE_EOI(x)) + flags |= XIVE_SRC_STORE_EOI; + __xive_register_source(x, &x->ipis, x->int_base, + x->int_hw_bot - x->int_base, XIVE_ESB_SHIFT, + x->esb_base, flags, true, NULL, NULL); + + /* Register escalation sources (ENDs) + * + * The ESe PQ bits are used for coalescing and the END ESB for + * interrupt management. The word 4&5 of the END is the EAS + * for the escalation source and the indexing is the same as + * the END. + * + * This is an OPAL primary source, IPIs are secondary. + */ + __xive_register_source(x, &x->esc_irqs, + MAKE_ESCALATION_GIRQ(x->block_id, 0), + XIVE_END_COUNT, XIVE_END_SHIFT, + x->end_base, XIVE_SRC_EOI_PAGE1, + false, NULL, NULL); + + + return x; + fail: + xive_err(x, "Initialization failed...\n"); + + /* Should this be fatal ? */ + //assert(false); + return NULL; +} + +static void xive_reset_enable_thread(struct cpu_thread *c) +{ + struct proc_chip *chip = get_chip(c->chip_id); + struct xive *x = chip->xive; + uint32_t fc, bit; + uint64_t enable; + + /* Get fused core number */ + fc = (c->pir >> 3) & 0xf; + + /* Get bit in register */ + bit = c->pir & 0x3f; + + /* Get which register to access */ + if (fc < 8) { + xive_regw(x, TCTXT_EN0_RESET, PPC_BIT(bit)); + xive_regw(x, TCTXT_EN0_SET, PPC_BIT(bit)); + + enable = xive_regr(x, TCTXT_EN0); + if (!(enable & PPC_BIT(bit))) + xive_cpu_err(c, "Failed to enable thread\n"); + } else { + xive_regw(x, TCTXT_EN1_RESET, PPC_BIT(bit)); + xive_regw(x, TCTXT_EN1_SET, PPC_BIT(bit)); + + enable = xive_regr(x, TCTXT_EN1); + if (!(enable & PPC_BIT(bit))) + xive_cpu_err(c, "Failed to enable thread\n"); + } +} + +void xive2_cpu_callin(struct cpu_thread *cpu) +{ + struct xive_cpu_state *xs = cpu->xstate; + uint8_t old_w2 __unused, w2 __unused; + + if (!xs) + return; + + /* Reset the HW thread context and enable it */ + xive_reset_enable_thread(cpu); + + /* Set VT to 1 */ + old_w2 = in_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2); + out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0x80); + w2 = in_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2); + + xive_cpu_vdbg(cpu, "Initialized TIMA VP=%x/%x W01=%016llx W2=%02x->%02x\n", + xs->vp_blk, xs->vp_idx, + in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS), + old_w2, w2); +} + +#ifdef XIVE_EXTRA_CHECK_INIT_CACHE +#define CHECK_INIT_CACHE_LOOP 0x100 +static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) +{ + struct xive_nvp vp = {0}; + uint32_t i; + + /* + * SIMICS checks the value of reserved fields + */ + if (chip_quirk(QUIRK_SIMICS)) + return; + + for (i = 0; i < CHECK_INIT_CACHE_LOOP; i++) { + struct xive_nvp *vp_m = xive_get_vp(x, idx); + + memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); + sync(); + vp.w1 = (i << 16) | i; + assert(!xive_nxc_cache_update(x, blk, idx, &vp, true)); + if (!xive_check_nxc_update(x, idx, &vp)) { + xive_dbg(x, "NXC update test failed at %d iterations\n", i); + return; + } + } + xive_dbg(x, "NXC update test passed for %d/0x%x\n", blk, idx); +} +#else +static inline void xive_special_cache_check(struct xive *x __unused, + uint32_t blk __unused, + uint32_t idx __unused) +{ +} +#endif + +static void xive_init_cpu_exploitation(struct xive_cpu_state *xs) +{ + struct xive_end end; + struct xive_nvp vp; + struct xive *x_vp, *x_end; + int i; + + /* Grab the XIVE where the VP resides. It could be different from + * the local chip XIVE if not using block group mode + */ + x_vp = xive_from_pc_blk(xs->vp_blk); + assert(x_vp); + + /* Grab the XIVE where the END resides. It should be the same + * as the VP. + */ + x_end = xive_from_vc_blk(xs->end_blk); + assert(x_end); + + xive_init_hw_end(&end); + + /* Use the cache watch to update all ENDs reserved for HW VPs */ + lock(&x_end->lock); + for (i = 0; i < xive_cfg_vp_prio(x_end); i++) + xive_endc_cache_update(x_end, xs->end_blk, xs->end_idx + i, + &end, true); + unlock(&x_end->lock); + + /* Initialize/enable the VP */ + xive_init_default_vp(&vp, xs->end_blk, xs->end_idx); + + /* Use the cache watch to write it out */ + lock(&x_vp->lock); + xive_special_cache_check(x_vp, xs->vp_blk, xs->vp_idx); + xive_nxc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, &vp, true); + unlock(&x_vp->lock); +} + +static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) +{ + uint64_t xa, val; + int64_t rc; + + xive_cpu_vdbg(c, "Setting up special BAR\n"); + xa = XSCOM_ADDR_P10_NCU(pir_to_core_id(c->pir), P10_NCU_SPEC_BAR); + val = (uint64_t)x->tm_base | P10_NCU_SPEC_BAR_ENABLE; + if (x->tm_shift == 16) + val |= P10_NCU_SPEC_BAR_256K; + xive_cpu_vdbg(c, "NCU_SPEC_BAR_XA[%08llx]=%016llx\n", xa, val); + rc = xscom_write(c->chip_id, xa, val); + if (rc) { + xive_cpu_err(c, "Failed to setup NCU_SPEC_BAR\n"); + /* XXXX what do do now ? */ + } +} + +void xive2_late_init(void) +{ + prlog(PR_INFO, "SLW: Configuring self-restore for NCU_SPEC_BAR\n"); + /* + * TODO (p10): need P10 stop state engine and fix for STOP11 + */ +} + +static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) +{ + struct xive *x; + + /* VP ids for HW threads are pre-allocated */ + xs->vp_blk = PIR2VP_BLK(c->pir); + xs->vp_idx = PIR2VP_IDX(c->pir); + + /* For now we use identical block IDs for VC and PC but that might + * change. We allocate the ENDs on the same XIVE as the VP. + */ + xs->end_blk = xs->vp_blk; + + /* Grab the XIVE where the END resides. It could be different from + * the local chip XIVE if not using block group mode + */ + x = xive_from_vc_blk(xs->end_blk); + assert(x); + + /* Allocate a set of ENDs for that VP */ + xs->end_idx = xive_alloc_end_set(x, true); + assert(!XIVE_ALLOC_IS_ERR(xs->end_idx)); +} + +static void xive_init_cpu(struct cpu_thread *c) +{ + struct proc_chip *chip = get_chip(c->chip_id); + struct xive *x = chip->xive; + struct xive_cpu_state *xs; + + if (!x) + return; + + /* + * Each core pair (EX) needs this special BAR setup to have the + * right powerbus cycle for the TM area (as it has the same address + * on all chips so it's somewhat special). + * + * Because we don't want to bother trying to figure out which core + * of a pair is present we just do the setup for each of them, which + * is harmless. + */ + if (cpu_is_thread0(c)) + xive_configure_ex_special_bar(x, c); + + /* Initialize the state structure */ + c->xstate = xs = local_alloc(c->chip_id, sizeof(struct xive_cpu_state), 1); + assert(xs); + memset(xs, 0, sizeof(struct xive_cpu_state)); + xs->xive = x; + + init_lock(&xs->lock); + + /* Shortcut to TM HV ring */ + xs->tm_ring1 = x->tm_base + (1u << x->tm_shift); + + /* Provision a VP id and some ENDs for a HW thread */ + xive_provision_cpu(xs, c); + + xive_init_cpu_exploitation(xs); +} + +static uint64_t xive_convert_irq_flags(uint64_t iflags) +{ + uint64_t oflags = 0; + + if (iflags & XIVE_SRC_STORE_EOI) + oflags |= OPAL_XIVE_IRQ_STORE_EOI; + + /* OPAL_XIVE_IRQ_TRIGGER_PAGE is only meant to be set if + * the interrupt has a *separate* trigger page. + */ + if ((iflags & XIVE_SRC_EOI_PAGE1) && + (iflags & XIVE_SRC_TRIGGER_PAGE)) + oflags |= OPAL_XIVE_IRQ_TRIGGER_PAGE; + + if (iflags & XIVE_SRC_LSI) + oflags |= OPAL_XIVE_IRQ_LSI; + + return oflags; +} + +static int64_t opal_xive_get_irq_info(uint32_t girq, + beint64_t *out_flags, + beint64_t *out_eoi_page, + beint64_t *out_trig_page, + beint32_t *out_esb_shift, + beint32_t *out_src_chip) +{ + struct irq_source *is = irq_find_source(girq); + struct xive_src *s = container_of(is, struct xive_src, is); + uint32_t idx; + uint64_t mm_base; + uint64_t eoi_page = 0, trig_page = 0; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + if (is == NULL || out_flags == NULL) + return OPAL_PARAMETER; + assert(is->ops == &xive_irq_source_ops); + + if (out_flags) + *out_flags = cpu_to_be64(xive_convert_irq_flags(s->flags)); + + idx = girq - s->esb_base; + + if (out_esb_shift) + *out_esb_shift = cpu_to_be32(s->esb_shift); + + mm_base = (uint64_t)s->esb_mmio + (1ull << s->esb_shift) * idx; + + /* The EOI page can either be the first or second page */ + if (s->flags & XIVE_SRC_EOI_PAGE1) { + uint64_t p1off = 1ull << (s->esb_shift - 1); + eoi_page = mm_base + p1off; + } else + eoi_page = mm_base; + + /* The trigger page, if it exists, is always the first page */ + if (s->flags & XIVE_SRC_TRIGGER_PAGE) + trig_page = mm_base; + + if (out_eoi_page) + *out_eoi_page = cpu_to_be64(eoi_page); + if (out_trig_page) + *out_trig_page = cpu_to_be64(trig_page); + if (out_src_chip) + *out_src_chip = cpu_to_be32(GIRQ_TO_CHIP(girq)); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_get_irq_config(uint32_t girq, + beint64_t *out_vp, + uint8_t *out_prio, + beint32_t *out_lirq) +{ + uint32_t vp; + uint32_t lirq; + uint8_t prio; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (xive_get_irq_targetting(girq, &vp, &prio, &lirq)) { + *out_vp = cpu_to_be64(vp); + *out_prio = prio; + *out_lirq = cpu_to_be32(lirq); + return OPAL_SUCCESS; + } else + return OPAL_PARAMETER; +} + +static int64_t opal_xive_set_irq_config(uint32_t girq, + uint64_t vp, + uint8_t prio, + uint32_t lirq) +{ + /* + * This variant is meant for a XIVE-aware OS, thus it will + * *not* affect the ESB state of the interrupt. If used with + * a prio of FF, the EAS will be masked. In that case the + * races have to be handled by the OS. + */ + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + return xive_set_irq_config(girq, vp, prio, lirq, false); +} + +static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, + beint64_t *out_qpage, + beint64_t *out_qsize, + beint64_t *out_qeoi_page, + beint32_t *out_escalate_irq, + beint64_t *out_qflags) +{ + uint32_t blk, idx; + struct xive *x; + struct xive_end *end; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (!xive_end_for_target(vp, prio, &blk, &idx)) + return OPAL_PARAMETER; + + x = xive_from_vc_blk(blk); + if (!x) + return OPAL_PARAMETER; + + end = xive_get_end(x, idx); + if (!end) + return OPAL_PARAMETER; + + if (out_escalate_irq) { + uint32_t esc_idx = idx; + + /* If escalations are routed to a single queue, fix up + * the escalation interrupt number here. + */ + if (xive_get_field32(END_W0_UNCOND_ESCALATE, end->w0)) + esc_idx |= xive_escalation_prio(x); + *out_escalate_irq = + cpu_to_be32(MAKE_ESCALATION_GIRQ(blk, esc_idx)); + } + + /* If this is a single-escalation gather queue, that's all + * there is to return + */ + if (xive_get_field32(END_W0_SILENT_ESCALATE, end->w0)) { + if (out_qflags) + *out_qflags = 0; + if (out_qpage) + *out_qpage = 0; + if (out_qsize) + *out_qsize = 0; + if (out_qeoi_page) + *out_qeoi_page = 0; + return OPAL_SUCCESS; + } + + if (out_qpage) { + if (xive_get_field32(END_W0_ENQUEUE, end->w0)) + *out_qpage = cpu_to_be64( + ((uint64_t)xive_get_field32(END_W2_EQ_ADDR_HI, end->w2) << 32) | + xive_get_field32(END_W3_EQ_ADDR_LO, end->w3)); + else + *out_qpage = 0; + } + if (out_qsize) { + if (xive_get_field32(END_W0_ENQUEUE, end->w0)) + *out_qsize = cpu_to_be64(xive_get_field32(END_W3_QSIZE, end->w3) + 12); + else + *out_qsize = 0; + } + if (out_qeoi_page) { + *out_qeoi_page = cpu_to_be64( + (uint64_t)x->end_base + idx * XIVE_ESB_PAGE_SIZE); + } + if (out_qflags) { + *out_qflags = 0; + if (xive_get_field32(END_W0_VALID, end->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ENABLED); + if (xive_get_field32(END_W0_UCOND_NOTIFY, end->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ALWAYS_NOTIFY); + if (xive_get_field32(END_W0_ESCALATE_CTL, end->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ESCALATE); + } + + return OPAL_SUCCESS; +} + +static void xive_cleanup_end(struct xive_end *end) +{ + end->w0 = xive_set_field32(END_W0_FIRMWARE1, 0, xive_end_is_firmware1(end)); + end->w1 = xive_set_field32(END_W1_ESe_Q, 0, 1) | + xive_set_field32(END_W1_ESn_Q, 0, 1); + end->w2 = end->w3 = end->w4 = end->w5 = end->w6 = end->w7 = 0; +} + +static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, + uint64_t qpage, + uint64_t qsize, + uint64_t qflags) +{ + uint32_t blk, idx; + struct xive *x; + struct xive_end *old_end; + struct xive_end end; + uint32_t vp_blk, vp_idx; + bool group; + int64_t rc; + + if (!xive_end_for_target(vp, prio, &blk, &idx)) + return OPAL_PARAMETER; + + x = xive_from_vc_blk(blk); + if (!x) + return OPAL_PARAMETER; + + old_end = xive_get_end(x, idx); + if (!old_end) + return OPAL_PARAMETER; + + /* If this is a silent escalation queue, it cannot be + * configured directly + */ + if (xive_get_field32(END_W0_SILENT_ESCALATE, old_end->w0)) + return OPAL_PARAMETER; + + /* This shouldn't fail or xive_end_for_target would have + * failed already + */ + if (!xive_decode_vp(vp, &vp_blk, &vp_idx, NULL, &group)) + return OPAL_PARAMETER; + + /* + * Make a local copy which we will later try to commit using + * the cache watch facility + */ + end = *old_end; + + if (qflags & OPAL_XIVE_EQ_ENABLED) { + switch(qsize) { + /* Supported sizes */ + case 12: + case 16: + case 21: + case 24: + end.w3 = cpu_to_be32(qpage & END_W3_EQ_ADDR_LO); + end.w2 = cpu_to_be32((qpage >> 32) & END_W2_EQ_ADDR_HI); + end.w3 = xive_set_field32(END_W3_QSIZE, end.w3, qsize - 12); + end.w0 = xive_set_field32(END_W0_ENQUEUE, end.w0, 1); + break; + case 0: + end.w2 = end.w3 = 0; + end.w0 = xive_set_field32(END_W0_ENQUEUE, end.w0, 0); + break; + default: + return OPAL_PARAMETER; + } + + /* Ensure the priority and target are correctly set (they will + * not be right after allocation + */ + end.w6 = xive_set_field32(END_W6_VP_BLOCK, 0, vp_blk) | + xive_set_field32(END_W6_VP_OFFSET, 0, vp_idx); + end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0, prio); + /* XXX Handle group i bit when needed */ + + /* Always notify flag */ + if (qflags & OPAL_XIVE_EQ_ALWAYS_NOTIFY) + end.w0 = xive_set_field32(END_W0_UCOND_NOTIFY, end.w0, 1); + else + end.w0 = xive_set_field32(END_W0_UCOND_NOTIFY, end.w0, 0); + + /* Escalation flag */ + if (qflags & OPAL_XIVE_EQ_ESCALATE) + end.w0 = xive_set_field32(END_W0_ESCALATE_CTL, end.w0, 1); + else + end.w0 = xive_set_field32(END_W0_ESCALATE_CTL, end.w0, 0); + + /* Unconditionally clear the current queue pointer, set + * generation to 1 and disable escalation interrupts. + */ + end.w1 = xive_set_field32(END_W1_GENERATION, 0, 1) | + xive_set_field32(END_W1_ES, 0, xive_get_field32(END_W1_ES, old_end->w1)); + + /* Enable. We always enable backlog for an enabled queue + * otherwise escalations won't work. + */ + end.w0 = xive_set_field32(END_W0_VALID, end.w0, 1); + end.w0 = xive_set_field32(END_W0_BACKLOG, end.w0, 1); + } else + xive_cleanup_end(&end); + + /* Update END, non-synchronous */ + lock(&x->lock); + rc = xive_endc_cache_update(x, blk, idx, &end, false); + unlock(&x->lock); + + return rc; +} + +static int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, + beint32_t *out_qtoggle, + beint32_t *out_qindex) +{ + uint32_t blk, idx; + struct xive *x; + struct xive_end *end; + int64_t rc; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (!out_qtoggle || !out_qindex || + !xive_end_for_target(vp, prio, &blk, &idx)) + return OPAL_PARAMETER; + + x = xive_from_vc_blk(blk); + if (!x) + return OPAL_PARAMETER; + + end = xive_get_end(x, idx); + if (!end) + return OPAL_PARAMETER; + + /* Scrub the queue */ + lock(&x->lock); + rc = xive_endc_scrub(x, blk, idx); + unlock(&x->lock); + if (rc) + return rc; + + /* We don't do disable queues */ + if (!xive_get_field32(END_W0_VALID, end->w0)) + return OPAL_WRONG_STATE; + + *out_qtoggle = cpu_to_be32(xive_get_field32(END_W1_GENERATION, end->w1)); + *out_qindex = cpu_to_be32(xive_get_field32(END_W1_PAGE_OFF, end->w1)); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, + uint32_t qtoggle, uint32_t qindex) +{ + uint32_t blk, idx; + struct xive *x; + struct xive_end *end, new_end; + int64_t rc; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (!xive_end_for_target(vp, prio, &blk, &idx)) + return OPAL_PARAMETER; + + x = xive_from_vc_blk(blk); + if (!x) + return OPAL_PARAMETER; + + end = xive_get_end(x, idx); + if (!end) + return OPAL_PARAMETER; + + /* We don't do disable queues */ + if (!xive_get_field32(END_W0_VALID, end->w0)) + return OPAL_WRONG_STATE; + + new_end = *end; + + new_end.w1 = xive_set_field32(END_W1_GENERATION, new_end.w1, qtoggle); + new_end.w1 = xive_set_field32(END_W1_PAGE_OFF, new_end.w1, qindex); + + lock(&x->lock); + rc = xive_endc_cache_update(x, blk, idx, &new_end, false); + unlock(&x->lock); + + return rc; +} + +static int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr) +{ + struct proc_chip *c = get_chip(chip_id); + struct list_node *n; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + if (!c) + return OPAL_PARAMETER; + if (!c->xive) + return OPAL_PARAMETER; + if (addr & 0xffff) + return OPAL_PARAMETER; + + n = (struct list_node *)addr; + lock(&c->xive->lock); + list_add(&c->xive->donated_pages, n); + unlock(&c->xive->lock); + return OPAL_SUCCESS; +} + +static int64_t opal_xive_get_vp_info(uint64_t vp_id, + beint64_t *out_flags, + beint64_t *out_cam_value, + beint64_t *out_report_cl_pair, + beint32_t *out_chip_id) +{ + struct xive *x; + struct xive_nvp *vp; + uint32_t blk, idx; + bool group; + + if (!xive_decode_vp(vp_id, &blk, &idx, NULL, &group)) + return OPAL_PARAMETER; + /* We don't do groups yet */ + if (group) + return OPAL_PARAMETER; + x = xive_from_pc_blk(blk); + if (!x) + return OPAL_PARAMETER; + vp = xive_get_vp(x, idx); + if (!vp) + return OPAL_PARAMETER; + + if (out_flags) { + uint32_t end_blk, end_idx; + struct xive_end *end; + struct xive *end_x; + *out_flags = 0; + + /* + * We would like to a way to stash a SW bit in the VP + * to know whether silent escalation is enabled or + * not, but unlike what happens with ENDs, the PC + * cache watch doesn't implement the reserved bit in + * the VPs... so we have to go look at END 7 instead. + */ + + /* Grab END for prio 7 to check for silent escalation */ + if (!xive_end_for_target(vp_id, xive_escalation_prio(x), + &end_blk, &end_idx)) + return OPAL_PARAMETER; + + end_x = xive_from_vc_blk(end_blk); + if (!end_x) + return OPAL_PARAMETER; + + end = xive_get_end(x, end_idx); + if (!end) + return OPAL_PARAMETER; + if (xive_get_field32(NVP_W0_VALID, vp->w0)) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_ENABLED); + if (xive_get_field32(END_W0_SILENT_ESCALATE, end->w0)) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_SINGLE_ESCALATION); + } + + if (out_cam_value) { + uint64_t cam_value; + + cam_value = (blk << x->vp_shift) | idx; + + *out_cam_value = cpu_to_be64(cam_value); + } + + if (out_report_cl_pair) { + uint64_t report_cl_pair; + + report_cl_pair = ((uint64_t)(be32_to_cpu(vp->w6) & 0x0fffffff)) << 32; + report_cl_pair |= be32_to_cpu(vp->w7) & 0xffffff00; + + *out_report_cl_pair = cpu_to_be64(report_cl_pair); + } + + if (out_chip_id) + *out_chip_id = cpu_to_be32(xive_block_to_chip[blk]); + + return OPAL_SUCCESS; +} + +static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) +{ + uint32_t blk, idx, i; + struct xive_end *end_orig; + struct xive_end end; + struct xive *x; + int64_t rc; + + /* Get base END block */ + if (!xive_end_for_target(vp_id, 0, &blk, &idx)) { + prlog(PR_ERR, "%s: Invalid VP 0x%08llx\n", __func__, vp_id); + return OPAL_PARAMETER; + } + x = xive_from_vc_blk(blk); + if (!x) { + prlog(PR_ERR, "%s: VP 0x%08llx has invalid block %d\n", __func__, + vp_id, blk); + return OPAL_PARAMETER; + } + + /* Grab prio 7 */ + end_orig = xive_get_end(x, idx + xive_escalation_prio(x)); + if (!end_orig) { + xive_err(x, "Failed to get silent gather END 0x%x for VP 0x%08llx\n", + idx + xive_escalation_prio(x), vp_id); + return OPAL_PARAMETER; + } + + /* If trying to enable silent gather, make sure prio 7 is not + * already enabled as a normal queue + */ + if (enable && xive_get_field32(END_W0_VALID, end_orig->w0) && + !xive_get_field32(END_W0_SILENT_ESCALATE, end_orig->w0)) { + xive_err(x, "silent gather END 0x%x already in use\n", + idx + xive_escalation_prio(x)); + return OPAL_PARAMETER; + } + + end = *end_orig; + + if (enable) { + /* W0: Enabled and "s" set, no other bit */ + end.w0 = xive_set_field32(END_W0_FIRMWARE1, end.w0, 0); + end.w0 = xive_set_field32(END_W0_VALID, end.w0, 1); + end.w0 = xive_set_field32(END_W0_SILENT_ESCALATE, end.w0, 1); + end.w0 = xive_set_field32(END_W0_ESCALATE_CTL, end.w0, 1); + end.w0 = xive_set_field32(END_W0_BACKLOG, end.w0, 1); + + /* Set new "N" for END escalation (vs. ESB) */ + end.w0 = xive_set_field32(END_W0_ESCALATE_END, end.w0, 1); + + /* W1: Mark ESn as 01, ESe as 00 */ + end.w1 = xive_set_field32(END_W1_ESn_P, end.w1, 0); + end.w1 = xive_set_field32(END_W1_ESn_Q, end.w1, 1); + end.w1 = xive_set_field32(END_W1_ESe, end.w1, 0); + } else if (xive_get_field32(END_W0_SILENT_ESCALATE, end.w0)) + xive_cleanup_end(&end); + + if (!memcmp(end_orig, &end, sizeof(end))) + rc = 0; + else + rc = xive_endc_cache_update(x, blk, idx + xive_escalation_prio(x), + &end, false); + if (rc) + return rc; + + /* Mark/unmark all other prios with the new "u" bit and update + * escalation + */ + for (i = 0; i < xive_cfg_vp_prio(x); i++) { + if (i == xive_escalation_prio(x)) + continue; + end_orig = xive_get_end(x, idx + i); + if (!end_orig) + continue; + end = *end_orig; + if (enable) { + /* Set "u" bit */ + end.w0 = xive_set_field32(END_W0_UNCOND_ESCALATE, end.w0, 1); + + /* Set new "N" for END escalation (vs. ESB) */ + /* TODO (Gen2+) : use ESB escalation configuration */ + end.w0 = xive_set_field32(END_W0_ESCALATE_END, end.w0, 1); + + /* Re-route escalation interrupt (previous + * route is lost !) to the gather queue + */ + end.w4 = xive_set_field32(END_W4_END_BLOCK, end.w4, blk); + end.w4 = xive_set_field32(END_W4_ESC_END_INDEX, + end.w4, idx + xive_escalation_prio(x)); + } else if (xive_get_field32(END_W0_UNCOND_ESCALATE, end.w0)) { + /* Clear the "u" bit, disable escalations if it was set */ + end.w0 = xive_set_field32(END_W0_UNCOND_ESCALATE, end.w0, 0); + end.w0 = xive_set_field32(END_W0_ESCALATE_CTL, end.w0, 0); + } + if (!memcmp(end_orig, &end, sizeof(end))) + continue; + rc = xive_endc_cache_update(x, blk, idx + i, &end, false); + if (rc) + break; + } + + return rc; +} + +static int64_t opal_xive_set_vp_info(uint64_t vp_id, + uint64_t flags, + uint64_t report_cl_pair) +{ + struct xive *x; + struct xive_nvp *vp, vp_new; + uint32_t blk, idx; + bool group; + int64_t rc; + + if (!xive_decode_vp(vp_id, &blk, &idx, NULL, &group)) + return OPAL_PARAMETER; + /* We don't do groups yet */ + if (group) + return OPAL_PARAMETER; + if (report_cl_pair & 0xff) + return OPAL_PARAMETER; + x = xive_from_pc_blk(blk); + if (!x) + return OPAL_PARAMETER; + vp = xive_get_vp(x, idx); + if (!vp) + return OPAL_PARAMETER; + + lock(&x->lock); + + vp_new = *vp; + if (flags & OPAL_XIVE_VP_ENABLED) { + vp_new.w0 = xive_set_field32(NVP_W0_VALID, vp_new.w0, 1); + vp_new.w6 = cpu_to_be32(report_cl_pair >> 32); + vp_new.w7 = cpu_to_be32(report_cl_pair & 0xffffffff); + + if (flags & OPAL_XIVE_VP_SINGLE_ESCALATION) + rc = xive_setup_silent_gather(vp_id, true); + else + rc = xive_setup_silent_gather(vp_id, false); + } else { + /* + * TODO (kvm): disabling a VP invalidates the associated ENDs. + * + * The loads then return all 1s which can be an issue for the + * Linux code to handle. + */ + + vp_new.w0 = vp_new.w6 = vp_new.w7 = 0; + rc = xive_setup_silent_gather(vp_id, false); + } + + if (rc) { + if (rc != OPAL_BUSY) + xive_dbg(x, "Silent gather setup failed with err %lld\n", rc); + goto bail; + } + + rc = xive_nxc_cache_update(x, blk, idx, &vp_new, false); + if (rc) + goto bail; + + /* When disabling, we scrub clean (invalidate the entry) so + * we can avoid cache ops in alloc/free + */ + if (!(flags & OPAL_XIVE_VP_ENABLED)) + xive_nxc_scrub_clean(x, blk, idx); + +bail: + unlock(&x->lock); + return rc; +} + +static int64_t opal_xive_get_vp_state(uint64_t vp_id, beint64_t *out_state) +{ + struct xive *x; + struct xive_nvp *vp; + uint32_t blk, idx; + int64_t rc; + bool group; + + if (!out_state || !xive_decode_vp(vp_id, &blk, &idx, NULL, &group)) + return OPAL_PARAMETER; + if (group) + return OPAL_PARAMETER; + x = xive_from_pc_blk(blk); + if (!x) + return OPAL_PARAMETER; + vp = xive_get_vp(x, idx); + if (!vp) + return OPAL_PARAMETER; + + /* Scrub the vp */ + lock(&x->lock); + rc = xive_nxc_scrub(x, blk, idx); + unlock(&x->lock); + if (rc) + return rc; + + if (!xive_get_field32(NVP_W0_VALID, vp->w0)) + return OPAL_WRONG_STATE; + + /* + * return a state matching the layout of WORD 0-1 of the TIMA + * as this is expected by current implementation. + */ + *out_state = cpu_to_be64(((uint64_t) 0x0) << 54 | + (uint64_t)xive_get_field32(NVP_W2_CPPR, vp->w2) << 48 | + (uint64_t)xive_get_field32(NVP_W2_IPB, vp->w2) << 40 | + (uint64_t)xive_get_field32(NVP_W2_LSMFB, vp->w2) << 32); + + return OPAL_SUCCESS; +} + +static void *xive_cpu_get_tima(struct cpu_thread *c) +{ + struct xive_cpu_state *xs = c->xstate; + struct xive *x = xs->xive; + + return x->ic_tm_direct_base + ((c->pir & 0xff) << x->ic_shift); +} + +static void xive_cleanup_cpu_tima(struct cpu_thread *c) +{ + struct xive_cpu_state *xs __unused = c->xstate; + void *cpu_tm_base = xive_cpu_get_tima(c); + uint8_t old_w2 __unused, w2 __unused; + + /* Reset the HW context */ + xive_reset_enable_thread(c); + + /* Set VT to 1 */ + old_w2 = in_8(cpu_tm_base + TM_QW3_HV_PHYS + TM_WORD2); + out_8(cpu_tm_base + TM_QW3_HV_PHYS + TM_WORD2, 0x80); + w2 = in_8(cpu_tm_base + TM_QW3_HV_PHYS + TM_WORD2); + + /* Dump HV state */ + xive_cpu_vdbg(c, "[reset] VP TIMA VP=%x/%x W01=%016llx W2=%02x->%02x\n", + xs->vp_blk, xs->vp_idx, + in_be64(cpu_tm_base + TM_QW3_HV_PHYS), + old_w2, w2); +} + +static int64_t xive_vc_ind_cache_kill(struct xive *x, uint64_t type) +{ + uint64_t val; + + /* We clear the whole thing */ + xive_regw(x, VC_AT_MACRO_KILL_MASK, 0); + xive_regw(x, VC_AT_MACRO_KILL, VC_AT_MACRO_KILL_VALID | + SETFIELD(VC_AT_MACRO_KILL_VSD, 0ull, type)); + + /* XXX Add timeout */ + for (;;) { + val = xive_regr(x, VC_AT_MACRO_KILL); + if (!(val & VC_AT_MACRO_KILL_VALID)) + break; + } + return 0; +} + +static int64_t xive_pc_ind_cache_kill(struct xive *x) +{ + uint64_t val; + + /* We clear the whole thing */ + xive_regw(x, PC_AT_KILL_MASK, 0); + xive_regw(x, PC_AT_KILL, PC_AT_KILL_VALID | + SETFIELD(VC_AT_MACRO_KILL_VSD, 0ull, VST_NVP)); + + /* XXX Add timeout */ + for (;;) { + val = xive_regr(x, PC_AT_KILL); + if (!(val & PC_AT_KILL_VALID)) + break; + } + return 0; +} + +static void xive_cleanup_vp_ind(struct xive *x) +{ + int i; + + xive_dbg(x, "Cleaning up %d VP ind entries...\n", x->vp_ind_count); + for (i = 0; i < x->vp_ind_count; i++) { + if (be64_to_cpu(x->vp_ind_base[i]) & VSD_FIRMWARE) { + xive_dbg(x, " %04x ... skip (firmware)\n", i); + continue; + } + if (x->vp_ind_base[i] != 0) { + x->vp_ind_base[i] = 0; + xive_dbg(x, " %04x ... cleaned\n", i); + } + } + xive_pc_ind_cache_kill(x); +} + +static void xive_cleanup_end_ind(struct xive *x) +{ + int i; + + xive_dbg(x, "Cleaning up %d END ind entries...\n", x->end_ind_count); + for (i = 0; i < x->end_ind_count; i++) { + if (be64_to_cpu(x->end_ind_base[i]) & VSD_FIRMWARE) { + xive_dbg(x, " %04x ... skip (firmware)\n", i); + continue; + } + if (x->end_ind_base[i] != 0) { + x->end_ind_base[i] = 0; + xive_dbg(x, " %04x ... cleaned\n", i); + } + } + xive_vc_ind_cache_kill(x, VST_END); +} + +static void xive_reset_one(struct xive *x) +{ + struct cpu_thread *c; + bool end_firmware; + int i; + + xive_notice(x, "Resetting one xive...\n"); + + lock(&x->lock); + + /* Check all interrupts are disabled */ + i = bitmap_find_one_bit(*x->int_enabled_map, 0, XIVE_INT_COUNT); + if (i >= 0) + xive_warn(x, "Interrupt %d (and maybe more) not disabled" + " at reset !\n", i); + + /* Reset IPI allocation */ + xive_dbg(x, "freeing alloc map %p/%p\n", + x->ipi_alloc_map, *x->ipi_alloc_map); + memset(x->ipi_alloc_map, 0, BITMAP_BYTES(XIVE_INT_COUNT)); + + xive_dbg(x, "Resetting ENDs...\n"); + + /* Reset all allocated ENDs and free the user ones */ + bitmap_for_each_one(*x->end_map, xive_end_bitmap_size(x), i) { + struct xive_end end0; + struct xive_end *end; + int j; + + if (i == 0) + continue; + end_firmware = false; + for (j = 0; j < xive_cfg_vp_prio(x); j++) { + uint32_t idx = (i << xive_cfg_vp_prio_shift(x)) | j; + + end = xive_get_end(x, idx); + if (!end) + continue; + + /* We need to preserve the firmware bit, otherwise + * we will incorrectly free the ENDs that are reserved + * for the physical CPUs + */ + if (xive_get_field32(END_W0_VALID, end->w0)) { + if (!xive_end_is_firmware1(end)) + xive_dbg(x, "END 0x%x:0x%x is valid at reset: %08x %08x\n", + x->block_id, idx, end->w0, end->w1); + end0 = *end; + xive_cleanup_end(&end0); + xive_endc_cache_update(x, x->block_id, idx, &end0, true); + } + if (xive_end_is_firmware1(end)) + end_firmware = true; + } + if (!end_firmware) + bitmap_clr_bit(*x->end_map, i); + } + + /* Take out all VPs from HW and reset all CPPRs to 0 */ + for_each_present_cpu(c) { + if (c->chip_id != x->chip_id) + continue; + if (!c->xstate) + continue; + xive_cleanup_cpu_tima(c); + } + + /* Reset all user-allocated VPs. This is inefficient, we should + * either keep a bitmap of allocated VPs or add an iterator to + * the buddy which is trickier but doable. + */ + for (i = 0; i < XIVE_VP_COUNT(x); i++) { + struct xive_nvp *vp; + struct xive_nvp vp0 = {0}; + + /* Ignore the physical CPU VPs */ + if (i >= xive_hw_vp_count && + i < (xive_hw_vp_base + xive_hw_vp_count)) + continue; + + /* Is the VP valid ? */ + vp = xive_get_vp(x, i); + if (!vp || !xive_get_field32(NVP_W0_VALID, vp->w0)) + continue; + + /* Clear it */ + xive_dbg(x, "VP 0x%x:0x%x is valid at reset\n", x->block_id, i); + xive_nxc_cache_update(x, x->block_id, i, &vp0, true); + } + + /* Forget about remaining donated pages */ + list_head_init(&x->donated_pages); + + /* And cleanup donated indirect VP and END pages */ + xive_cleanup_vp_ind(x); + xive_cleanup_end_ind(x); + + /* The rest must not be called with the lock held */ + unlock(&x->lock); + + /* Re-configure VPs */ + for_each_present_cpu(c) { + struct xive_cpu_state *xs = c->xstate; + + if (c->chip_id != x->chip_id || !xs) + continue; + + xive_init_cpu_exploitation(xs); + } +} + +static void xive_reset_mask_source_cb(struct irq_source *is, + void *data __unused) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + struct xive *x; + uint32_t isn; + + if (is->ops != &xive_irq_source_ops) + return; + + /* Skip escalation sources */ + if (GIRQ_IS_ESCALATION(is->start)) + return; + + x = s->xive; + + /* Iterate all interrupts */ + for (isn = is->start; isn < is->end; isn++) { + /* Has it ever been enabled ? */ + if (!bitmap_tst_bit(*x->int_enabled_map, GIRQ_TO_IDX(isn))) + continue; + /* Mask it and clear the enabled map bit */ + xive_vdbg(x, "[reset] disabling source 0x%x\n", isn); + __xive_set_irq_config(is, isn, 0, 0xff, isn, true, false); + bitmap_clr_bit(*x->int_enabled_map, GIRQ_TO_IDX(isn)); + } +} + +void xive2_cpu_reset(void) +{ + struct cpu_thread *c = this_cpu(); + struct xive_cpu_state *xs = c->xstate; + + out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_CPPR, 0); + + in_be64(xs->tm_ring1 + TM_SPC_PULL_POOL_CTX); +} + +static int64_t __xive_reset(uint64_t version) +{ + struct proc_chip *chip; + + xive_mode = version; + + /* Mask all interrupt sources */ + irq_for_each_source(xive_reset_mask_source_cb, NULL); + + /* For each XIVE do a sync... */ + for_each_chip(chip) { + if (!chip->xive) + continue; + xive_sync(chip->xive); + } + + /* For each XIVE reset everything else... */ + for_each_chip(chip) { + if (!chip->xive) + continue; + xive_reset_one(chip->xive); + } + + /* Cleanup global VP allocator */ + buddy_reset(xive_vp_buddy); + + /* + * We reserve the whole range of VP ids for HW threads. + */ + assert(buddy_reserve(xive_vp_buddy, xive_hw_vp_base, xive_threadid_shift)); + + return OPAL_SUCCESS; +} + +/* Called by fast reboot */ +int64_t xive2_reset(void) +{ + if (xive_mode == XIVE_MODE_NONE) + return OPAL_SUCCESS; + return __xive_reset(XIVE_MODE_EXPL); +} + +static int64_t opal_xive_reset(uint64_t version) +{ + prlog(PR_DEBUG, "XIVE reset, version: %d...\n", (int)version); + + if (version != XIVE_MODE_EXPL) { + prerror("ignoring version %lld at reset. " + "XIVE exploitation mode is the default\n", version); + } + + return __xive_reset(XIVE_MODE_EXPL); +} + +static int64_t opal_xive_free_vp_block(uint64_t vp_base) +{ + uint32_t blk, idx, i, j, count; + uint8_t order; + bool group; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (!xive_decode_vp(vp_base, &blk, &idx, &order, &group)) + return OPAL_PARAMETER; + if (group) + return OPAL_PARAMETER; + if (blk) + return OPAL_PARAMETER; + if (order < (xive_chips_alloc_bits + 1)) + return OPAL_PARAMETER; + if (idx & ((1 << (order - xive_chips_alloc_bits)) - 1)) + return OPAL_PARAMETER; + + count = 1 << order; + for (i = 0; i < count; i++) { + uint32_t vp_id = vp_base + i; + uint32_t blk, idx, end_blk, end_idx; + struct xive *x; + struct xive_nvp *vp; + + if (!xive_decode_vp(vp_id, &blk, &idx, NULL, NULL)) { + prerror("Couldn't decode VP id %u\n", vp_id); + return OPAL_INTERNAL_ERROR; + } + x = xive_from_pc_blk(blk); + if (!x) { + prerror("Instance not found for deallocated VP" + " block %d\n", blk); + return OPAL_INTERNAL_ERROR; + } + vp = xive_get_vp(x, idx); + if (!vp) { + prerror("VP not found for deallocation !"); + return OPAL_INTERNAL_ERROR; + } + + /* VP must be disabled */ + if (xive_get_field32(NVP_W0_VALID, vp->w0)) { + prlog(PR_ERR, "freeing active VP %d\n", vp_id); + return OPAL_XIVE_FREE_ACTIVE; + } + + /* Not populated */ + if (vp->w5 == 0) + continue; + + end_blk = xive_get_field32(NVP_W5_VP_END_BLOCK, vp->w5); + end_idx = xive_get_field32(NVP_W5_VP_END_INDEX, vp->w5); + + lock(&x->lock); + + /* Ensure ENDs are disabled and cleaned up. Ideally the caller + * should have done it but we double check it here + */ + for (j = 0; j < xive_cfg_vp_prio(x); j++) { + struct xive *end_x = xive_from_vc_blk(end_blk); + struct xive_end end, *orig_end = xive_get_end(end_x, end_idx + j); + + if (!xive_get_field32(END_W0_VALID, orig_end->w0)) + continue; + + prlog(PR_WARNING, "freeing VP %d with queue %d active\n", + vp_id, j); + end = *orig_end; + xive_cleanup_end(&end); + xive_endc_cache_update(x, end_blk, end_idx + j, &end, true); + } + + /* Mark it not populated so we don't try to free it again */ + vp->w5 = 0; + + if (end_blk != blk) { + prerror("Block mismatch trying to free ENDs\n"); + unlock(&x->lock); + return OPAL_INTERNAL_ERROR; + } + + xive_free_end_set(x, end_idx); + unlock(&x->lock); + } + + xive_free_vps(vp_base); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_alloc_vp_block(uint32_t alloc_order) +{ + uint32_t vp_base, ends, count, i; + int64_t rc; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + prlog(PR_TRACE, "opal_xive_alloc_vp_block(%d)\n", alloc_order); + + vp_base = xive_alloc_vps(alloc_order); + if (XIVE_ALLOC_IS_ERR(vp_base)) { + if (vp_base == XIVE_ALLOC_NO_IND) + return OPAL_XIVE_PROVISIONING; + return OPAL_RESOURCE; + } + + /* Allocate ENDs and initialize VPs */ + count = 1 << alloc_order; + for (i = 0; i < count; i++) { + uint32_t vp_id = vp_base + i; + uint32_t blk, idx; + struct xive *x; + struct xive_nvp *vp; + + if (!xive_decode_vp(vp_id, &blk, &idx, NULL, NULL)) { + prerror("Couldn't decode VP id %u\n", vp_id); + return OPAL_INTERNAL_ERROR; + } + x = xive_from_pc_blk(blk); + if (!x) { + prerror("Instance not found for allocated VP" + " block %d\n", blk); + rc = OPAL_INTERNAL_ERROR; + goto fail; + } + vp = xive_get_vp(x, idx); + if (!vp) { + prerror("VP not found after allocation !"); + rc = OPAL_INTERNAL_ERROR; + goto fail; + } + + /* Allocate ENDs, if fails, free the VPs and return */ + lock(&x->lock); + ends = xive_alloc_end_set(x, false); + unlock(&x->lock); + if (XIVE_ALLOC_IS_ERR(ends)) { + if (ends == XIVE_ALLOC_NO_IND) + rc = OPAL_XIVE_PROVISIONING; + else + rc = OPAL_RESOURCE; + goto fail; + } + + /* Initialize the VP structure. We don't use a cache watch + * as we have made sure when freeing the entries to scrub + * it out of the cache. + */ + memset(vp, 0, sizeof(*vp)); + + /* Store the END base of the VP in W5 (new in p10) */ + xive_vp_set_end_base(vp, blk, ends); + } + return vp_base; + fail: + opal_xive_free_vp_block(vp_base); + + return rc; +} + +static int64_t xive_try_allocate_irq(struct xive *x) +{ + int idx, base_idx, max_count, girq; + struct xive_eas *eas; + + lock(&x->lock); + + base_idx = x->int_ipi_top - x->int_base; + max_count = x->int_hw_bot - x->int_ipi_top; + + idx = bitmap_find_zero_bit(*x->ipi_alloc_map, base_idx, max_count); + if (idx < 0) { + unlock(&x->lock); + return OPAL_RESOURCE; + } + bitmap_set_bit(*x->ipi_alloc_map, idx); + girq = x->int_base + idx; + + /* Mark the EAS valid. Don't bother with the HW cache, it's + * still masked anyway, the cache will be updated when unmasked + * and configured. + */ + eas = xive_get_eas(x, girq); + if (!eas) { + bitmap_clr_bit(*x->ipi_alloc_map, idx); + unlock(&x->lock); + return OPAL_PARAMETER; + } + eas->w = xive_set_field64(EAS_VALID, 0, 1) | + xive_set_field64(EAS_MASKED, 0, 1) | + xive_set_field64(EAS_END_DATA, 0, girq); + unlock(&x->lock); + + return girq; +} + +static int64_t opal_xive_allocate_irq(uint32_t chip_id) +{ + struct proc_chip *chip; + bool try_all = false; + int64_t rc; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (chip_id == OPAL_XIVE_ANY_CHIP) { + try_all = true; + chip_id = this_cpu()->chip_id; + } + chip = get_chip(chip_id); + if (!chip) + return OPAL_PARAMETER; + + /* Try initial target chip */ + if (!chip->xive) + rc = OPAL_PARAMETER; + else + rc = xive_try_allocate_irq(chip->xive); + if (rc >= 0 || !try_all) + return rc; + + /* Failed and we try all... do so */ + for_each_chip(chip) { + if (!chip->xive) + continue; + rc = xive_try_allocate_irq(chip->xive); + if (rc >= 0) + break; + } + return rc; +} + +static int64_t opal_xive_free_irq(uint32_t girq) +{ + struct irq_source *is = irq_find_source(girq); + struct xive_src *s = container_of(is, struct xive_src, is); + struct xive *x = xive_from_isn(girq); + struct xive_eas *eas; + uint32_t idx; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + if (!x || !is) + return OPAL_PARAMETER; + + idx = GIRQ_TO_IDX(girq); + + lock(&x->lock); + + eas = xive_get_eas(x, girq); + if (!eas) { + unlock(&x->lock); + return OPAL_PARAMETER; + } + + /* Mask the interrupt source */ + xive_update_irq_mask(s, girq - s->esb_base, true); + + /* Mark the EAS masked and invalid */ + eas->w = xive_set_field64(EAS_VALID, 0, 1) | + xive_set_field64(EAS_MASKED, 0, 1); + xive_easc_scrub(x, x->block_id, idx); + + /* Free it */ + if (!bitmap_tst_bit(*x->ipi_alloc_map, idx)) { + unlock(&x->lock); + return OPAL_PARAMETER; + } + bitmap_clr_bit(*x->ipi_alloc_map, idx); + bitmap_clr_bit(*x->int_enabled_map, idx); + unlock(&x->lock); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_dump_tm(uint32_t offset, const char *n, uint32_t pir) +{ + struct cpu_thread *c = find_cpu_by_pir(pir); + struct xive_cpu_state *xs; + struct xive *x; + void *cpu_tm_base; + uint64_t v0,v1; + + if (!c) + return OPAL_PARAMETER; + xs = c->xstate; + if (!xs || !xs->tm_ring1) + return OPAL_INTERNAL_ERROR; + x = xs->xive; + cpu_tm_base = xive_cpu_get_tima(c); + + lock(&x->lock); + v0 = in_be64(cpu_tm_base + offset); + if (offset == TM_QW3_HV_PHYS) { + v1 = in_8(cpu_tm_base + offset + 8); + v1 <<= 56; + } else { + v1 = in_be32(cpu_tm_base + offset + 8); + v1 <<= 32; + } + prlog(PR_INFO, "CPU[%04x]: TM state for QW %s\n", pir, n); + prlog(PR_INFO, "CPU[%04x]: NSR CPPR IPB LSMFB ACK# INC AGE PIPR" + " W2 W3\n", pir); + prlog(PR_INFO, "CPU[%04x]: %02x %02x %02x %02x %02x " + "%02x %02x %02x %08x %08x\n", pir, + (uint8_t)(v0 >> 58) & 0xff, (uint8_t)(v0 >> 48) & 0xff, + (uint8_t)(v0 >> 40) & 0xff, (uint8_t)(v0 >> 32) & 0xff, + (uint8_t)(v0 >> 24) & 0xff, (uint8_t)(v0 >> 16) & 0xff, + (uint8_t)(v0 >> 8) & 0xff, (uint8_t)(v0 ) & 0xff, + (uint32_t)(v1 >> 32) & 0xffffffff, + (uint32_t)(v1 & 0xffffffff)); + unlock(&x->lock); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_dump_vp(uint32_t vp_id) +{ + uint32_t blk, idx; + uint8_t order; + bool group; + struct xive *x; + struct xive_nvp *vp; + uint32_t *vpw; + + if (!xive_decode_vp(vp_id, &blk, &idx, &order, &group)) + return OPAL_PARAMETER; + + x = xive_from_vc_blk(blk); + if (!x) + return OPAL_PARAMETER; + vp = xive_get_vp(x, idx); + if (!vp) + return OPAL_PARAMETER; + lock(&x->lock); + + xive_nxc_scrub_clean(x, blk, idx); + + vpw = ((uint32_t *)vp) + (group ? 8 : 0); + prlog(PR_INFO, "VP[%08x]: 0..3: %08x %08x %08x %08x\n", vp_id, + vpw[0], vpw[1], vpw[2], vpw[3]); + prlog(PR_INFO, "VP[%08x]: 4..7: %08x %08x %08x %08x\n", vp_id, + vpw[4], vpw[5], vpw[6], vpw[7]); + unlock(&x->lock); + + return OPAL_SUCCESS; +} + +static int64_t opal_xive_sync_irq_src(uint32_t girq) +{ + struct xive *x = xive_from_isn(girq); + + if (!x) + return OPAL_PARAMETER; + return xive_sync(x); +} + +static int64_t opal_xive_sync_irq_target(uint32_t girq) +{ + uint32_t target, vp_blk; + struct xive *x; + + if (!xive_get_irq_targetting(girq, &target, NULL, NULL)) + return OPAL_PARAMETER; + if (!xive_decode_vp(target, &vp_blk, NULL, NULL, NULL)) + return OPAL_PARAMETER; + x = xive_from_pc_blk(vp_blk); + if (!x) + return OPAL_PARAMETER; + return xive_sync(x); +} + +static int64_t opal_xive_sync(uint32_t type, uint32_t id) +{ + int64_t rc = OPAL_SUCCESS;; + + if (type & XIVE_SYNC_EAS) + rc = opal_xive_sync_irq_src(id); + if (rc) + return rc; + if (type & XIVE_SYNC_QUEUE) + rc = opal_xive_sync_irq_target(id); + if (rc) + return rc; + + /* Add more ... */ + + return rc; +} + +static int64_t opal_xive_dump(uint32_t type, uint32_t id) +{ + switch (type) { + case XIVE_DUMP_TM_HYP: + return opal_xive_dump_tm(TM_QW3_HV_PHYS, "PHYS", id); + case XIVE_DUMP_TM_POOL: + return opal_xive_dump_tm(TM_QW2_HV_POOL, "POOL", id); + case XIVE_DUMP_TM_OS: + return opal_xive_dump_tm(TM_QW1_OS, "OS ", id); + case XIVE_DUMP_TM_USER: + return opal_xive_dump_tm(TM_QW0_USER, "USER", id); + case XIVE_DUMP_VP: + return opal_xive_dump_vp(id); + default: + return OPAL_PARAMETER; + } +} + +static void xive_init_globals(void) +{ + uint32_t i; + + for (i = 0; i < XIVE_MAX_CHIPS; i++) + xive_block_to_chip[i] = XIVE_INVALID_CHIP; +} + +void xive2_init(void) +{ + struct dt_node *np; + struct proc_chip *chip; + struct cpu_thread *cpu; + bool first = true; + + /* Look for xive nodes and do basic inits */ + dt_for_each_compatible(dt_root, np, "ibm,power10-xive-x") { + struct xive *x; + + /* Initialize some global stuff */ + if (first) + xive_init_globals(); + + /* Create/initialize the xive instance */ + x = init_one_xive(np); + if (first) + one_xive = x; + first = false; + } + if (first) + return; + + /* + * P8 emulation is not supported on P10 anymore. Exploitation + * is the default XIVE mode. We might introduce a GEN2 mode. + */ + xive_mode = XIVE_MODE_EXPL; + + /* Init VP allocator */ + xive_init_vp_allocator(); + + /* Create a device-tree node for Linux use */ + xive_create_mmio_dt_node(one_xive); + + /* Some inits must be done after all xive have been created + * such as setting up the forwarding ports + */ + for_each_chip(chip) { + if (chip->xive) + late_init_one_xive(chip->xive); + } + + /* Initialize per-cpu structures */ + for_each_present_cpu(cpu) { + xive_init_cpu(cpu); + } + + /* Calling boot CPU */ + xive2_cpu_callin(this_cpu()); + + /* Register XIVE exploitation calls */ + opal_register(OPAL_XIVE_RESET, opal_xive_reset, 1); + opal_register(OPAL_XIVE_GET_IRQ_INFO, opal_xive_get_irq_info, 6); + opal_register(OPAL_XIVE_GET_IRQ_CONFIG, opal_xive_get_irq_config, 4); + opal_register(OPAL_XIVE_SET_IRQ_CONFIG, opal_xive_set_irq_config, 4); + opal_register(OPAL_XIVE_GET_QUEUE_INFO, opal_xive_get_queue_info, 7); + opal_register(OPAL_XIVE_SET_QUEUE_INFO, opal_xive_set_queue_info, 5); + opal_register(OPAL_XIVE_DONATE_PAGE, opal_xive_donate_page, 2); + opal_register(OPAL_XIVE_ALLOCATE_IRQ, opal_xive_allocate_irq, 1); + opal_register(OPAL_XIVE_FREE_IRQ, opal_xive_free_irq, 1); + opal_register(OPAL_XIVE_ALLOCATE_VP_BLOCK, opal_xive_alloc_vp_block, 1); + opal_register(OPAL_XIVE_FREE_VP_BLOCK, opal_xive_free_vp_block, 1); + opal_register(OPAL_XIVE_GET_VP_INFO, opal_xive_get_vp_info, 5); + opal_register(OPAL_XIVE_SET_VP_INFO, opal_xive_set_vp_info, 3); + opal_register(OPAL_XIVE_SYNC, opal_xive_sync, 2); + opal_register(OPAL_XIVE_DUMP, opal_xive_dump, 2); + opal_register(OPAL_XIVE_GET_QUEUE_STATE, opal_xive_get_queue_state, 4); + opal_register(OPAL_XIVE_SET_QUEUE_STATE, opal_xive_set_queue_state, 4); + opal_register(OPAL_XIVE_GET_VP_STATE, opal_xive_get_vp_state, 2); +} diff --git a/include/xive.h b/include/xive.h index 477d3801d..dc1b25d03 100644 --- a/include/xive.h +++ b/include/xive.h @@ -63,4 +63,33 @@ void xive_source_mask(struct irq_source *is, uint32_t isn); void xive_cpu_reset(void); void xive_late_init(void); +/* + * POWER10 + */ + +/* + * StoreEOI requires the OS to enforce load-after-store ordering and + * the PHB5 should be configured in Address-based trigger mode with PQ + * state bit offloading. + */ +#define XIVE2_STORE_EOI_ENABLED 1 + +void xive2_init(void); +int64_t xive2_reset(void); + +uint32_t xive2_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align); +uint32_t xive2_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align); +uint64_t xive2_get_notify_port(uint32_t chip_id, uint32_t ent); +__attrconst uint32_t xive2_get_notify_base(uint32_t girq); +void xive2_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, + void *mmio, uint32_t flags, void *data, + const struct irq_source_ops *ops); +void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, + const struct irq_source_ops *ops); +void xive2_cpu_callin(struct cpu_thread *cpu); +void *xive2_get_trigger_port(uint32_t girq); + +void xive2_cpu_reset(void); +void xive2_late_init(void); + #endif /* XIVE_H */ diff --git a/include/xive2-regs.h b/include/xive2-regs.h new file mode 100644 index 000000000..6697f036e --- /dev/null +++ b/include/xive2-regs.h @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * XIVE2: eXternal Interrupt Virtualization Engine. POWER10 interrupt + * controller + * + * Copyright (c) 2019, IBM Corporation. + */ + +#ifndef XIVE2_REGS_H +#define XIVE2_REGS_H + +#include + +/* + * CQ Common Queue (PowerBus bridge) Registers + */ + +/* XIVE Capabilities */ +#define X_CQ_XIVE_CAP 0x02 +#define CQ_XIVE_CAP 0x010 +#define CQ_XIVE_CAP_VERSION PPC_BITMASK(0,3) +/* 4:6 reserved */ +#define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8,9) +#define CQ_XIVE_CAP_USER_INT_PRIO_1 0 +#define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1 +#define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2 +#define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3 +#define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10,11) +#define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0 +#define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1 +#define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2 +#define CQ_XIVE_CAP_VP_INT_PRIO_8 3 +#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12,13) + +/* XIVE Configuration */ +#define X_CQ_XIVE_CFG 0x03 +#define CQ_XIVE_CFG 0x018 + +/* 0:7 reserved */ +#define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8,9) +#define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10,11) +#define CQ_XIVE_CFG_INT_PRIO_1 0 +#define CQ_XIVE_CFG_INT_PRIO_2 1 +#define CQ_XIVE_CFG_INT_PRIO_4 2 +#define CQ_XIVE_CFG_INT_PRIO_8 3 +#define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12,13) +#define CQ_XIVE_CFG_BLOCK_ID_4BITS 0 +#define CQ_XIVE_CFG_BLOCK_ID_5BITS 1 +#define CQ_XIVE_CFG_BLOCK_ID_6BITS 2 +#define CQ_XIVE_CFG_BLOCK_ID_7BITS 3 +#define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14,15) +#define CQ_XIVE_CFG_THREADID_7BITS 0 +#define CQ_XIVE_CFG_THREADID_8BITS 1 +#define CQ_XIVE_CFG_THREADID_9BITS 2 +#define CQ_XIVE_CFG_THREADID_10BITs 3 +#define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16) +#define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17,23) + +#define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24) +#define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25) +#define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */ +#define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */ +#define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28) /* END ESx stores + are dropped */ + +/* Interrupt Controller Base Address Register - 512 pages (32M) */ +#define X_CQ_IC_BAR 0x08 +#define CQ_IC_BAR 0x040 +#define CQ_IC_BAR_VALID PPC_BIT(0) +#define CQ_IC_BAR_64K PPC_BIT(1) +/* 2:7 reserved */ +#define CQ_IC_BAR_ADDR PPC_BITMASK(8,42) +/* 43:63 reserved */ + +/* Thread Management Base Address Register - 4 pages */ +#define X_CQ_TM_BAR 0x09 +#define CQ_TM_BAR 0x048 +#define CQ_TM_BAR_VALID PPC_BIT(0) +#define CQ_TM_BAR_64K PPC_BIT(1) +#define CQ_TM_BAR_ADDR PPC_BITMASK(8,49) + +/* ESB Base Address Register */ +#define X_CQ_ESB_BAR 0x0A +#define CQ_ESB_BAR 0x050 +#define CQ_BAR_VALID PPC_BIT(0) +#define CQ_BAR_64K PPC_BIT(1) +/* 2:7 reserved */ +#define CQ_BAR_ADDR PPC_BITMASK(8,39) +#define CQ_BAR_SET_DIV PPC_BITMASK(56,58) +#define CQ_BAR_RANGE PPC_BITMASK(59,63) + /* 0 (16M) - 16 (16T) */ + +/* END Base Address Register */ +#define X_CQ_END_BAR 0x0B +#define CQ_END_BAR 0x058 + +/* NVPG Base Address Register */ +#define X_CQ_NVPG_BAR 0x0C +#define CQ_NVPG_BAR 0x060 + +/* NVC Base Address Register */ +#define X_CQ_NVC_BAR 0x0D +#define CQ_NVC_BAR 0x068 + +/* Table Address Register */ +#define X_CQ_TAR 0x0E +#define CQ_TAR 0x070 +#define CQ_TAR_AUTOINC PPC_BIT(0) +#define CQ_TAR_SELECT PPC_BITMASK(12,15) +#define CQ_TAR_ESB 0 /* 0 - 15 */ +#define CQ_TAR_END 2 /* 0 - 15 */ +#define CQ_TAR_NVPG 3 /* 0 - 15 */ +#define CQ_TAR_NVC 5 /* 0 - 15 */ +#define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28,31) + +/* Table Data Register */ +#define X_CQ_TDR 0x0F +#define CQ_TDR 0x078 +/* for the NVPG, NVC, ESB, END Set Translation Tables */ +#define CQ_TDR_VALID PPC_BIT(0) +#define CQ_TDR_BLOCK_ID PPC_BITMASK(60,63) + +/* + * Processor Cores Enabled for MsgSnd + * Identifies which of the 32 possible core chiplets are enabled and + * available to receive the MsgSnd command + */ +#define X_CQ_MSGSND 0x10 +#define CQ_MSGSND 0x080 + +/* Interrupt Unit Reset Control */ +#define X_CQ_RST_CTL 0x12 +#define CQ_RST_CTL 0x090 +#define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */ +#define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */ +#define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */ +#define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */ +#define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */ + +/* PowerBus General Configuration */ +#define X_CQ_CFG_PB_GEN 0x14 +#define CQ_CFG_PB_GEN 0x0A0 + +/* FIR + * (And-Mask) + * (Or-Mask) + */ +#define X_CQ_FIR 0x30 +#define X_CQ_FIR_AND 0x31 +#define X_CQ_FIR_OR 0x32 +#define CQ_FIR 0x180 +#define CQ_FIR_AND 0x188 +#define CQ_FIR_OR 0x190 +#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) +#define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61,63) + +/* FIR Mask + * (And-Mask) + * (Or-Mask) + */ +#define X_CQ_FIRMASK 0x33 +#define X_CQ_FIRMASK_AND 0x34 +#define X_CQ_FIRMASK_OR 0x35 +#define CQ_FIRMASK 0x198 +#define CQ_FIRMASK_AND 0x1A0 +#define CQ_FIRMASK_OR 0x1A8 + +/* + * VC0 + */ + +/* VSD table address */ +#define X_VC_VSD_TABLE_ADDR 0x100 +#define VC_VSD_TABLE_ADDR 0x000 +#define VC_VSD_TABLE_AUTOINC PPC_BIT(0) +#define VC_VSD_TABLE_SELECT PPC_BITMASK(12,15) +#define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28,31) + +/* VSD table data */ +#define X_VC_VSD_TABLE_DATA 0x101 +#define VC_VSD_TABLE_DATA 0x008 + +/* AIB AT macro indirect kill */ +#define X_VC_AT_MACRO_KILL 0x102 +#define VC_AT_MACRO_KILL 0x010 +#define VC_AT_MACRO_KILL_VALID PPC_BIT(0) +#define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12,15) +#define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28,31) +#define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48,60) + +/* AIB AT macro indirect kill mask (same bit definitions) */ +#define X_VC_AT_MACRO_KILL_MASK 0x103 +#define VC_AT_MACRO_KILL_MASK 0x018 + +/* Remote IRQs and ERQs configuration [n] (n = 0:6) */ +#define X_VC_QUEUES_CFG_REM0 0x117 + +#define VC_QUEUES_CFG_REM0 0x0B8 +#define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38) +#define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42,47) + +/* + * VC1 + */ + +/* ESBC cache flush control trigger */ +#define X_VC_ESBC_FLUSH_CTRL 0x140 +#define VC_ESBC_FLUSH_CTRL 0x200 +#define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) +#define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) + +/* ESBC cache flush poll trigger */ +#define X_VC_ESBC_FLUSH_POLL 0x141 +#define VC_ESBC_FLUSH_POLL 0x208 +#define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0,3) +#define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4,31) /* 28-bit */ +#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35) +#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */ + +/* EASC flush control register */ +#define X_VC_EASC_FLUSH_CTRL 0x160 +#define VC_EASC_FLUSH_CTRL 0x300 +#define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) +#define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) + +/* EASC flush poll register */ +#define X_VC_EASC_FLUSH_POLL 0x161 +#define VC_EASC_FLUSH_POLL 0x308 +#define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0,3) +#define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4,31) /* 28-bit */ +#define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35) +#define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */ + +/* + * VC2 + */ + +/* ENDC flush control register */ +#define X_VC_ENDC_FLUSH_CTRL 0x180 +#define VC_ENDC_FLUSH_CTRL 0x400 +#define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) +#define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) +#define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) +#define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) + +/* ENDC flush poll register */ +#define X_VC_ENDC_FLUSH_POLL 0x181 +#define VC_ENDC_FLUSH_POLL 0x408 +#define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4,7) +#define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8,31) /* 24-bit */ +#define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36,39) +#define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40,63) /* 24-bit */ + +/* ENDC Sync done */ +#define X_VC_ENDC_SYNC_DONE 0x184 +#define VC_ENDC_SYNC_DONE 0x420 +#define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0,6) +#define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0) +#define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1) +#define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2) +#define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3) +#define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4) +#define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5) +#define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6) +#define VC_QUEUE_COUNT 7 + +/* ENDC cache watch specification 0 */ +#define X_VC_ENDC_WATCH0_SPEC 0x1A0 +#define VC_ENDC_WATCH0_SPEC 0x500 +#define VC_ENDC_WATCH_CONFLICT PPC_BIT(0) +#define VC_ENDC_WATCH_FULL PPC_BIT(8) +#define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) +#define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63) + +/* ENDC cache watch data 0 */ +#define X_VC_ENDC_WATCH0_DATA0 0x1A4 + +#define VC_ENDC_WATCH0_DATA0 0x520 + +/* + * PC LSB1 + */ + +/* VSD table address register */ +#define X_PC_VSD_TABLE_ADDR 0x200 +#define PC_VSD_TABLE_ADDR 0x000 +#define PC_VSD_TABLE_AUTOINC PPC_BIT(0) +#define PC_VSD_TABLE_SELECT PPC_BITMASK(12,15) +#define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28,31) + +/* VSD table data register */ +#define X_PC_VSD_TABLE_DATA 0x201 +#define PC_VSD_TABLE_DATA 0x008 + +/* AT indirect kill register */ +#define X_PC_AT_KILL 0x202 +#define PC_AT_KILL 0x010 +#define PC_AT_KILL_VALID PPC_BIT(0) +#define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24,27) +/* Only NVP, NVG, NVC */ +#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28,31) +#define PC_AT_KILL_OFFSET PPC_BITMASK(48,60) + +/* AT indirect kill mask register */ +#define X_PC_AT_KILL_MASK 0x203 +#define PC_AT_KILL_MASK 0x018 +#define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24,27) +#define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28,31) +#define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48,60) + +/* Error1 configuration register 0 */ +#define X_PC_ERR1_CFG0 0x2C8 +#define PC_ERR1_CFG0 0x640 + +/* Error1 configuration register 1 */ +#define X_PC_ERR1_CFG1 0x2C9 +#define PC_ERR1_CFG1 0x648 +#define PC_ERR1_CFG1_INTERRUPT_INVALID_PRIO PPC_BIT(3) +/* + * PC LSB2 + */ + +/* NxC Cache flush control */ +#define X_PC_NXC_FLUSH_CTRL 0x280 +#define PC_NXC_FLUSH_CTRL 0x400 +#define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) +#define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) +#define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) +#define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) + +/* NxC Cache flush poll */ +#define X_PC_NXC_FLUSH_POLL 0x281 +#define PC_NXC_FLUSH_POLL 0x408 +#define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2,3) +#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0 +#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2 +#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3 +#define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4,7) +#define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8,31) /* 24-bit */ +#define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34,35) /* 0: Ignore */ +#define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36,39) +#define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40,63) /* 24-bit */ + +/* NxC Cache Watch 0 Specification */ +#define X_PC_NXC_WATCH0_SPEC 0x2A0 +#define PC_NXC_WATCH0_SPEC 0x500 +#define PC_NXC_WATCH_CONFLICT PPC_BIT(0) +#define PC_NXC_WATCH_FULL PPC_BIT(8) +#define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27) +#define PC_NXC_WATCH_NXC_NVP 0 +#define PC_NXC_WATCH_NXC_NVG 2 +#define PC_NXC_WATCH_NXC_NVC 3 +#define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) +#define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63) + +/* NxC Cache Watch 0 Data */ +#define X_PC_NXC_WATCH0_DATA0 0x2A4 + +#define PC_NXC_WATCH0_DATA0 0x520 + +/* + * TCTXT Registers + */ + +/* Physical Thread Enable0 register */ +#define X_TCTXT_EN0 0x300 +#define TCTXT_EN0 0x000 + +/* Physical Thread Enable0 Set register */ +#define X_TCTXT_EN0_SET 0x302 +#define TCTXT_EN0_SET 0x010 + +/* Physical Thread Enable0 Reset register */ +#define X_TCTXT_EN0_RESET 0x303 +#define TCTXT_EN0_RESET 0x018 + +/* Physical Thread Enable1 register */ +#define X_TCTXT_EN1 0x304 +#define TCTXT_EN1 0x020 + +/* Physical Thread Enable1 Set register */ +#define X_TCTXT_EN1_SET 0x306 +#define TCTXT_EN1_SET 0x030 + +/* Physical Thread Enable1 Reset register */ +#define X_TCTXT_EN1_RESET 0x307 +#define TCTXT_EN1_RESET 0x038 + +/* + * VSD Tables + */ +#define VST_ESB 0 +#define VST_EAS 1 /* No used by PC */ +#define VST_END 2 +#define VST_NVP 3 +#define VST_NVG 4 +#define VST_NVC 5 +#define VST_IC 6 /* No used by PC */ +#define VST_SYNC 7 +#define VST_ERQ 8 /* No used by PC */ + +/* Bits in a VSD entry. + * + * Note: the address is naturally aligned, we don't use a PPC_BITMASK, + * but just a mask to apply to the address before OR'ing it in. + * + * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the + * VSD and is only meant to be used in indirect mode ! + */ +#define VSD_MODE PPC_BITMASK(0,1) +#define VSD_MODE_SHARED 1 +#define VSD_MODE_EXCLUSIVE 2 +#define VSD_MODE_FORWARD 3 +#define VSD_FIRMWARE PPC_BIT(2) /* Read warning */ +#define VSD_FIRMWARE2 PPC_BIT(3) /* unused */ +#define VSD_RESERVED PPC_BITMASK(4,7) /* P10 reserved */ +#define VSD_ADDRESS_MASK 0x00fffffffffff000ull +#define VSD_MIGRATION_REG PPC_BITMASK(52,55) +#define VSD_INDIRECT PPC_BIT(56) +#define VSD_TSIZE PPC_BITMASK(59,63) + +/* EAS + * + * One per interrupt source. Targets that interrupt to a given END + * and provides the corresponding logical interrupt number (END data) + * + * We also map this structure to the escalation descriptor inside + * an END, though in that case the valid and masked bits are not used. + */ +struct xive_eas { + beint64_t w; +#define EAS_VALID PPC_BIT(0) +#define EAS_END_BLOCK PPC_BITMASK(4,7) /* Destination END block# */ +#define EAS_END_INDEX PPC_BITMASK(8,31) /* Destination END index */ +#define EAS_MASKED PPC_BIT(32) /* Masked */ +#define EAS_END_DATA PPC_BITMASK(33,63) /* Data written to the EQ */ +}; + +/* EQ */ +struct xive_end { + beint32_t w0; +#define END_W0_VALID PPC_BIT32(0) /* "v" bit */ +#define END_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */ +#define END_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */ +#define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */ +#define END_W0_BACKLOG PPC_BIT32(8) /* "b" bit */ +#define END_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */ +#define END_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */ +#define END_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */ +#define END_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */ +#define END_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */ + beint32_t w1; +#define END_W1_ES PPC_BITMASK32(0,3) +#define END_W1_ESn PPC_BITMASK32(0,1) +#define END_W1_ESn_P PPC_BIT32(0) +#define END_W1_ESn_Q PPC_BIT32(1) +#define END_W1_ESe PPC_BITMASK32(2,3) +#define END_W1_ESe_P PPC_BIT32(2) +#define END_W1_ESe_Q PPC_BIT32(3) +#define END_W1_GEN_FLIPPED PPC_BIT32(8) +#define END_W1_GENERATION PPC_BIT32(9) +#define END_W1_PAGE_OFF PPC_BITMASK32(10,31) + beint32_t w2; +#define END_W2_RESERVED PPC_BITMASK32(4,7) +#define END_W2_EQ_ADDR_HI PPC_BITMASK32(8,31) + beint32_t w3; +#define END_W3_EQ_ADDR_LO PPC_BITMASK32(0,24) +#define END_W3_QSIZE PPC_BITMASK32(28,31) + beint32_t w4; +#define END_W4_END_BLOCK PPC_BITMASK32(4,7) /* N:1 */ +#define END_W4_ESC_END_INDEX PPC_BITMASK32(8,31) /* N:1 */ +#define END_W4_ESB_BLOCK PPC_BITMASK32(0,3) /* N:0 */ +#define END_W4_ESC_ESB_INDEX PPC_BITMASK32(4,31) /* N:0 */ + beint32_t w5; +#define END_W5_ESC_END_DATA PPC_BITMASK32(1,31) + beint32_t w6; +#define END_W6_FORMAT_BIT PPC_BIT32(0) +#define END_W6_VP_BLOCK PPC_BITMASK32(4,7) +#define END_W6_VP_OFFSET PPC_BITMASK32(8,31) +#define END_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13,31) + beint32_t w7; +#define END_W7_TOPO PPC_BITMASK32(0,3) /* Owned by HW */ +#define END_W7_F0_PRIORITY PPC_BITMASK32(8,15) +#define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4,31) +}; +#define xive_end_is_firmware1(end) \ + xive_get_field32(END_W0_FIRMWARE1, (end)->w0) + +/* Notification Virtual Processor (NVP) */ +struct xive_nvp { + beint32_t w0; +#define NVP_W0_VALID PPC_BIT32(0) +#define NVP_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */ + beint32_t w1; + beint32_t w2; +#define NVP_W2_CPPR PPC_BITMASK32(0, 7) +#define NVP_W2_IPB PPC_BITMASK32(8, 15) +#define NVP_W2_LSMFB PPC_BITMASK32(16, 23) + beint32_t w3; + beint32_t w4; +#define NVP_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */ +#define NVP_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */ +#define NVP_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */ +#define NVP_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */ + beint32_t w5; +#define NVP_W5_PSIZE PPC_BITMASK32(0, 1) +#define NVP_W5_VP_END_BLOCK PPC_BITMASK32(4, 7) +#define NVP_W5_VP_END_INDEX PPC_BITMASK32(8, 31) + beint32_t w6; + beint32_t w7; +}; + +/* Notification Virtual Group or Crowd (NVG/NVC) */ +struct xive_nvgc { + beint32_t w0; +#define NVGC_W0_VALID PPC_BIT32(0) + beint32_t w1; + beint32_t w2; + beint32_t w3; + beint32_t w4; + beint32_t w5; + beint32_t w6; + beint32_t w7; +}; + +/* + * Thread Interrupt Management Area + * + * In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2 + * mode (P10), the CAM line is slightly different as the VP space was + * increased. + */ +#define TM10_QW0W2_VU PPC_BIT32(0) +#define TM10_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31) +#define TM10_QW1W2_VO PPC_BIT32(0) +#define TM10_QW1W2_HO PPC_BIT32(1) +#define TM10_QW1W2_NO PPC_BIT32(2) +#define TM10_QW1W2_OS_CAM PPC_BITMASK32(4, 31) +#define TM10_QW2W2_VP PPC_BIT32(0) +#define TM10_QW2W2_HP PPC_BIT32(1) +#define TM10_QW2W2_NP PPC_BIT32(2) +#define TM10_QW2W2_POOL_CAM PPC_BITMASK32(4, 31) +#define TM10_QW3W2_VT PPC_BIT32(0) +#define TM10_QW3W2_HT PPC_BIT32(1) +#define TM10_QW3W2_NT PPC_BIT32(2) +#define TM10_QW3W2_LP PPC_BIT32(6) +#define TM10_QW3W2_LE PPC_BIT32(7) + +#endif /* XIVE2_REGS_H */ From patchwork Wed Aug 4 07:21:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513229 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:22:58 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma06fra.de.ibm.com with ESMTP id 3a4wshyvd0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:22:58 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747Mtfl49480102 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:22:55 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 19EB4AE058; Wed, 4 Aug 2021 07:22:55 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1931DAE04D; Wed, 4 Aug 2021 07:22:54 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:53 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:09 +0530 Message-Id: <20210804072137.1147875-32-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 9YvRNdt2yjRXTqy_eJnGQRHNq18Am6zx X-Proofpoint-GUID: 9YvRNdt2yjRXTqy_eJnGQRHNq18Am6zx X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 31/59] psi/p10: Activate 64K ESB pages X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 7 ++++--- include/psi.h | 5 +++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 26677a3b2..991ea3b1f 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -753,8 +753,7 @@ static void psi_init_p10_interrupts(struct psi *psi) { struct proc_chip *chip; u64 val; - /* TODO (clg) : fix ESB page size to 64k when ready */ - uint32_t esb_shift = 12; + uint32_t esb_shift = 16; /* Grab chip */ chip = get_chip(psi->chip_id); @@ -764,10 +763,12 @@ static void psi_init_p10_interrupts(struct psi *psi) /* Configure the CI BAR */ phys_map_get(chip->id, PSIHB_ESB, 0, &val, NULL); val |= PSIHB_ESB_CI_VALID; + if (esb_shift == 16) + val |= PSIHB10_ESB_CI_64K; out_be64(psi->regs + PSIHB_ESB_CI_BASE, val); val = in_be64(psi->regs + PSIHB_ESB_CI_BASE); - psi->esb_mmio = (void *)(val & ~PSIHB_ESB_CI_VALID); + psi->esb_mmio = (void *)(val & ~(PSIHB_ESB_CI_VALID|PSIHB10_ESB_CI_64K)); prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", psi->chip_id, psi->esb_mmio); diff --git a/include/psi.h b/include/psi.h index a7104ef0b..dbf94b4b3 100644 --- a/include/psi.h +++ b/include/psi.h @@ -94,9 +94,10 @@ #define PSIHB_IRQ_METHOD PPC_BIT(0) #define PSIHB_IRQ_RESET PPC_BIT(1) #define PSIHB_ESB_CI_BASE 0x60 -#define PSIHB_ESB_CI_VALID 1 +#define PSIHB10_ESB_CI_64K PPC_BIT(1) +#define PSIHB_ESB_CI_VALID PPC_BIT(63) #define PSIHB_ESB_NOTIF_ADDR 0x68 -#define PSIHB_ESB_NOTIF_VALID 1 +#define PSIHB_ESB_NOTIF_VALID PPC_BIT(63) #define PSIHB_IVT_OFFSET 0x70 #define PSIHB_IVT_OFF_SHIFT 32 /* From patchwork Wed Aug 4 07:21:10 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:22:55 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:55 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:10 +0530 Message-Id: <20210804072137.1147875-33-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1bikO7BHm7NLMnL_a90ZrFZQ5w08r2m8 X-Proofpoint-GUID: 1bikO7BHm7NLMnL_a90ZrFZQ5w08r2m8 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxlogscore=868 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 32/59] psi/p10: Activate StoreEOI X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 15 ++++++++++++++- include/psi.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 991ea3b1f..291422539 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -749,11 +749,14 @@ static const struct irq_source_ops psi_p10_irq_ops = { .name = psi_p9_irq_name, }; +#define PSIHB10_CAN_STORE_EOI(x) XIVE2_STORE_EOI_ENABLED + static void psi_init_p10_interrupts(struct psi *psi) { struct proc_chip *chip; u64 val; uint32_t esb_shift = 16; + uint32_t flags = XIVE_SRC_LSI; /* Grab chip */ chip = get_chip(psi->chip_id); @@ -772,6 +775,16 @@ static void psi_init_p10_interrupts(struct psi *psi) prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", psi->chip_id, psi->esb_mmio); + /* Store EOI */ + if (PSIHB10_CAN_STORE_EOI(psi)) { + val = in_be64(psi->regs + PSIHB_CR); + val |= PSIHB10_CR_STORE_EOI; + out_be64(psi->regs + PSIHB_CR, val); + prlog(PR_DEBUG, "PSI[0x%03x]: store EOI is enabled\n", + psi->chip_id); + flags |= XIVE_SRC_STORE_EOI; + } + /* Grab and configure the notification port */ val = xive2_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); val |= PSIHB_ESB_NOTIF_VALID; @@ -788,7 +801,7 @@ static void psi_init_p10_interrupts(struct psi *psi) psi->chip_id, 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf); xive2_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, - esb_shift, psi->esb_mmio, XIVE_SRC_LSI, + esb_shift, psi->esb_mmio, flags, psi, &psi_p10_irq_ops); /* Reset irq handling and switch to ESB mode */ diff --git a/include/psi.h b/include/psi.h index dbf94b4b3..ac7afa09f 100644 --- a/include/psi.h +++ b/include/psi.h @@ -41,6 +41,7 @@ #define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5) #define PSIHB_CR_FSP_RESET PPC_BIT(6) #define PSIHB_CR_PSIHB_RESET PPC_BIT(7) +#define PSIHB10_CR_STORE_EOI PPC_BIT(12) #define PSIHB_CR_PSI_IRQ PPC_BIT(16) /* PSIHB interrupt */ #define PSIHB_CR_FSP_IRQ PPC_BIT(17) /* FSP interrupt */ #define PSIHB_CR_FSP_LINK_ACTIVE PPC_BIT(18) /* FSP link active */ From patchwork Wed Aug 4 07:21:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513234 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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Wed, 4 Aug 2021 07:22:57 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:56 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:11 +0530 Message-Id: <20210804072137.1147875-34-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: d2GnbxF15S6zwb-NSqvo6RWWBiVBnpaR X-Proofpoint-ORIG-GUID: SjlxOVTB87V_apISP3NKcvmxm46oNGDe X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 33/59] hw/phb5: Add initial support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Jordan Niethe Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Jordan Niethe The PHB5 logic on P10 is pretty close to the P9's version. So we keep our base phb4 implementation and just add the few changes within if statements. Signed-off-by: Jordan Niethe [clg: misc cleanups and fixes ] Signed-off-by: Cédric Le Goater [Fixed compilation issue - Vasant] Signed-off-by: Vasant Hegde [Nick: Unify PHB4/PHB5 drivers ] Signed-off-by: Nicholas Piggin [Mikey: set default lane eq settings for phb5] Signed-off-by: Michael Neuling [FB: squash commits + small cleanup ] Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- core/hmi.c | 4 + core/init.c | 2 +- .../opal-pci-set-phb-capi-mode-93.rst | 5 +- hw/capp.c | 11 +- hw/phb4.c | 200 ++++++++++++++---- hw/phys-map.c | 48 ++--- include/opal-api.h | 3 +- include/phb4-regs.h | 10 +- include/phb4.h | 22 +- include/phys-map.h | 4 + 10 files changed, 217 insertions(+), 92 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 35b609047..9363cc5fb 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -602,6 +602,10 @@ static void find_capp_checkstop_reason(int flat_chip_id, uint64_t reg; int64_t rc; + /* CAPP exists on P8 and P9 only */ + if (proc_gen != proc_gen_p8 && proc_gen != proc_gen_p9) + return; + /* Find the CAPP on the chip associated with the HMI. */ for_each_phb(phb) { /* get the CAPP info */ diff --git a/core/init.c b/core/init.c index e38969554..a8bac28a8 100644 --- a/core/init.c +++ b/core/init.c @@ -1364,7 +1364,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Probe PHB3 on P8 */ probe_phb3(); - /* Probe PHB4 on P9 */ + /* Probe PHB4 on P9 and PHB5 on P10 */ probe_phb4(); /* Probe NPUs */ diff --git a/doc/opal-api/opal-pci-set-phb-capi-mode-93.rst b/doc/opal-api/opal-pci-set-phb-capi-mode-93.rst index ffc4c6dc9..130e382b5 100644 --- a/doc/opal-api/opal-pci-set-phb-capi-mode-93.rst +++ b/doc/opal-api/opal-pci-set-phb-capi-mode-93.rst @@ -66,10 +66,11 @@ Notes allocate extra 16/8 dma read engines to the PHB depending on its stack (stack 0/ stack 1). This is needed to improve the Direct-GPU DMA read performance for the Mellanox CX5 card. -* Mode `OPAL_PHB_CAPI_MODE_PCIE` not yet supported on Power-9. +* Mode `OPAL_PHB_CAPI_MODE_PCIE` not supported on Power-9. * Requesting mode `OPAL_PHB_CAPI_MODE_CAPI` on Power-9 will disable fast-reboot. * Modes `OPAL_PHB_CAPI_MODE_DMA`, `OPAL_PHB_CAPI_MODE_SNOOP_OFF` are - not supported on Power-9 yet. + not supported on Power-9. +* CAPI is only supported on Power-8 and Power-9. Return Codes ------------ diff --git a/hw/capp.c b/hw/capp.c index dde8c52f6..a1aa1caa9 100644 --- a/hw/capp.c +++ b/hw/capp.c @@ -42,15 +42,12 @@ int preload_capp_ucode(void) uint64_t rc; int ret; + /* CAPI is supported on P8 and P9 only */ p = dt_find_compatible_node(dt_root, NULL, "ibm,power8-pbcq"); - - if (!p) { + if (!p) p = dt_find_compatible_node(dt_root, NULL, "ibm,power9-pbcq"); - if (!p) { - prlog(PR_INFO, "CAPI: WARNING: no compat thing found\n"); - return OPAL_SUCCESS; - } - } + if (!p) + return OPAL_SUCCESS; chip = get_chip(dt_get_chip_id(p)); diff --git a/hw/phb4.c b/hw/phb4.c index 31f9fa250..e074fa2a3 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -142,6 +142,16 @@ static bool pci_eeh_mmio; static bool pci_retry_all; static int rx_err_max = PHB4_RX_ERR_MAX; +static inline bool is_phb4(void) +{ + return (proc_gen == proc_gen_p9); +} + +static inline bool is_phb5(void) +{ + return (proc_gen == proc_gen_p10); +} + /* Note: The "ASB" name is historical, practically this means access via * the XSCOM backdoor */ @@ -988,7 +998,7 @@ static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg, * XXX Add timeout... */ /* XXX SIMICS is nasty... */ - if ((reg == PHB_TCE_KILL || reg == PHB_DMARD_SYNC) && + if ((reg == PHB_TCE_KILL || reg == PHB_DMA_READ_WRITE_SYNC) && chip_quirk(QUIRK_SIMICS)) return OPAL_SUCCESS; @@ -1084,7 +1094,17 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type, } /* Start DMA sync process */ - out_be64(p->regs + PHB_DMARD_SYNC, PHB_DMARD_SYNC_START); + if (is_phb5()){ + val = in_be64(p->regs + PHB_DMA_READ_WRITE_SYNC) & + (PHB_DMA_READ_SYNC_COMPLETE | + PHB_DMA_WRITE_SYNC_COMPLETE); + out_be64(p->regs + PHB_DMA_READ_WRITE_SYNC, + val | PHB_DMA_READ_SYNC_START); + + } else { + out_be64(p->regs + PHB_DMA_READ_WRITE_SYNC, + PHB_DMA_READ_SYNC_START); + } /* Wait for kill to complete */ rc = phb4_wait_bit(p, PHB_Q_DMA_R, PHB_Q_DMA_R_TCE_KILL_STATUS, 0); @@ -1092,9 +1112,9 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type, return rc; /* Wait for DMA sync to complete */ - return phb4_wait_bit(p, PHB_DMARD_SYNC, - PHB_DMARD_SYNC_COMPLETE, - PHB_DMARD_SYNC_COMPLETE); + return phb4_wait_bit(p, PHB_DMA_READ_WRITE_SYNC, + PHB_DMA_READ_SYNC_COMPLETE, + PHB_DMA_READ_SYNC_COMPLETE); } /* phb4_ioda_reset - Reset the IODA tables @@ -3537,7 +3557,11 @@ static void phb4_int_unmask_all(struct phb4 *p) { /* Init_126..130 - Re-enable error interrupts */ out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0xca8880cc00000000ull); - out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2008400e08200000ull); + + if (is_phb5()) + out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x200850be08200020ull); + else + out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2008400e08200000ull); out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE, 0xc40038fc01804070ull); out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE, 0x00006100008000a8ull); out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE, 0x60510050c0000000ull); @@ -4162,6 +4186,10 @@ static int64_t phb4_get_capp_info(int chip_id, struct phb *phb, struct phb4 *p = phb_to_phb4(phb); uint32_t offset; + /* Not even supposed to be here on P10, but doesn't hurt */ + if (is_phb5()) + return OPAL_UNSUPPORTED; + if (chip_id != p->chip_id) return OPAL_PARAMETER; @@ -4364,8 +4392,11 @@ static void phb4_init_capp_errors(struct phb4 *p) out_be64(p->regs + 0x0cb0, 0x35777073ff000000ull); } - /* - * The capi indicator is over the 8 most significant bits on p9 (and +/* + * The capi, NBW and ASN indicators are used only on P9 to flag some + * types of incoming traffic for the PHB and have been removed on P10. + * + * The capi indicator is over the 8 most significant bits (and * not 16). We stay away from bits 59 (TVE select), 60 and 61 (MSI) * * For the mask, we keep bit 59 in, as capi messages must hit TVE#0. @@ -4689,6 +4720,10 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, struct capp *capp = p->capp; uint64_t reg, ret; + /* No CAPI on P10. OpenCAPI only */ + if (is_phb5()) + return OPAL_UNSUPPORTED; + /* cant do a mode switch when capp is in recovery mode */ ret = capp_xscom_read(capp, CAPP_ERR_STATUS_CTRL, ®); if (ret != OPAL_SUCCESS) @@ -4954,7 +4989,7 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_19 - Interrupt Notify Base Index */ out_be64(p->regs + PHB_INT_NOTIFY_INDEX, - xive_get_notify_base(p->base_msi)); + xive2_get_notify_base(p->base_msi)); /* Init_19x - Not in spec: Initialize source ID */ PHBDBG(p, "Reset state SRC_ID: %016llx\n", @@ -4979,9 +5014,11 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_24 - CRW Base Address Reg */ /* See enable_capi_mode() */ - /* Init_25 - ASN Compare/Mask */ - out_be64(p->regs + PHB_ASN_CMPM, ((u64)ASNIND << 48) | - ((u64)ASNMASK << 32) | PHB_ASN_CMPM_ENABLE); + if (is_phb4()) { + /* Init_25 - ASN Compare/Mask - P9 only */ + out_be64(p->regs + PHB_ASN_CMPM, ((u64)ASNIND << 48) | + ((u64)ASNMASK << 32) | PHB_ASN_CMPM_ENABLE); + } /* Init_26 - CAPI Compare/Mask */ /* See enable_capi_mode() */ @@ -5123,18 +5160,26 @@ static void phb4_init_errors(struct phb4 *p) /* Init_73..81 - TXE errors */ out_be64(p->regs + 0x0d08, 0x0000000000000000ull); + /* Errata: Clear bit 17, otherwise a CFG write UR/CA will incorrectly * freeze a "random" PE (whatever last PE did an MMIO) */ - out_be64(p->regs + 0x0d28, 0x0000000a00000000ull); - if (phb4_is_dd20(p)) { - out_be64(p->regs + 0x0d00, 0xf3acff0ff7ddfff0ull); - out_be64(p->regs + 0x0d18, 0xf3acff0ff7ddfff0ull); - out_be64(p->regs + 0x0d30, 0xdfffbd05f7ddfff0ull); /* XXX CAPI has diff. value */ - } else { + if (is_phb5()) { + out_be64(p->regs + 0x0d28, 0x0000500a00000000ull); out_be64(p->regs + 0x0d00, 0xffffffffffffffffull); out_be64(p->regs + 0x0d18, 0xffffff0fffffffffull); - out_be64(p->regs + 0x0d30, 0xdff7bd05f7ddfff0ull); + out_be64(p->regs + 0x0d30, 0xdff7af41f7ddffdfull); + } else { + out_be64(p->regs + 0x0d28, 0x0000000a00000000ull); + if (phb4_is_dd20(p)) { + out_be64(p->regs + 0x0d00, 0xf3acff0ff7ddfff0ull); + out_be64(p->regs + 0x0d18, 0xf3acff0ff7ddfff0ull); + out_be64(p->regs + 0x0d30, 0xdfffbd05f7ddfff0ull); /* XXX CAPI has diff. value */ + } else { + out_be64(p->regs + 0x0d00, 0xffffffffffffffffull); + out_be64(p->regs + 0x0d18, 0xffffff0fffffffffull); + out_be64(p->regs + 0x0d30, 0xdff7bd05f7ddfff0ull); + } } out_be64(p->regs + 0x0d40, 0x0000000000000000ull); @@ -5241,7 +5286,7 @@ static void phb4_init_hw(struct phb4 *p) { uint64_t val, creset; - PHBDBG(p, "Initializing PHB4...\n"); + PHBDBG(p, "Initializing PHB...\n"); /* Init_1 - Sync reset * @@ -5288,6 +5333,18 @@ static void phb4_init_hw(struct phb4 *p) out_be64(p->regs + PHB_PCIE_DLP_CTL, val); } + if (is_phb5()) { + /* disable scaled flow control for now. SW527785 */ + PHBDBG(p, "LINK: Disabling scaled flow control\n"); + val = in_be64(p->regs + PHB_PCIE_DLP_CTL); + val |= PHB_PCIE_DLP_CTL_SFC_DISABLE; + out_be64(p->regs + PHB_PCIE_DLP_CTL, val); + + /* lane equalization settings need to be tuned on P10 */ + out_be64(p->regs + PHB_PCIE_PDL_PHY_EQ_CNTL, + 0x80F4FFFFFF0F9C00); + } + /* Init_14 - Clear link training */ phb4_pcicfg_write32(&p->phb, 0, 0x78, 0x07FE0000 | p->max_link_speed); @@ -5698,6 +5755,13 @@ static __be64 lane_eq_default[8] = { CPU_TO_BE64(0x7777777777777777UL), CPU_TO_BE64(0x7777777777777777UL), }; +static __be64 lane_eq_phb5_default[8] = { + CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), + CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), + CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), + CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), +}; + static void phb4_create(struct dt_node *np) { const struct dt_property *prop; @@ -5816,7 +5880,10 @@ static void phb4_create(struct dt_node *np) } } else { PHBDBG(p, "Using default lane equalization settings\n"); - p->lane_eq = lane_eq_default; + if (is_phb5()) + p->lane_eq = lane_eq_phb5_default; + else + p->lane_eq = lane_eq_default; } if (p->lane_eq) { PHBDBG(p, "Override lane equalization settings:\n"); @@ -5830,7 +5897,10 @@ static void phb4_create(struct dt_node *np) * 2K or 4K interrupts ... for now we just use 4K but that * needs to be fixed */ - irq_base = xive_alloc_hw_irqs(p->chip_id, p->num_irqs, p->num_irqs); + if (is_phb5()) + irq_base = xive2_alloc_hw_irqs(p->chip_id, p->num_irqs, p->num_irqs); + else + irq_base = xive_alloc_hw_irqs(p->chip_id, p->num_irqs, p->num_irqs); if (irq_base == XIVE_IRQ_ERROR) { PHBERR(p, "Failed to allocate %d interrupt sources\n", p->num_irqs); @@ -5838,8 +5908,6 @@ static void phb4_create(struct dt_node *np) } p->base_msi = irq_base; p->base_lsi = irq_base + p->num_irqs - 8; - p->irq_port = xive_get_notify_port(p->chip_id, - XIVE_HW_SRC_PHBn(p->index)); p->num_pes = p->max_num_pes; /* Allocate the SkiBoot internal in-memory tables for the PHB */ @@ -5854,7 +5922,8 @@ static void phb4_create(struct dt_node *np) phb4_init_hw(p); /* init capp that might get attached to the phb */ - phb4_init_capp(p); + if (is_phb4()) + phb4_init_capp(p); /* Compute XIVE source flags depending on PHB revision */ irq_flags = 0; @@ -5863,13 +5932,23 @@ static void phb4_create(struct dt_node *np) else irq_flags |= XIVE_SRC_TRIGGER_PAGE; - /* Register all interrupt sources with XIVE */ - xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16, - p->int_mmio, irq_flags, NULL, NULL); + if (is_phb5()) { + /* Register all interrupt sources with XIVE */ + xive2_register_hw_source(p->base_msi, p->num_irqs - 8, 16, + p->int_mmio, irq_flags, NULL, NULL); - xive_register_hw_source(p->base_lsi, 8, 16, - p->int_mmio + ((p->num_irqs - 8) << 16), - XIVE_SRC_LSI, p, &phb4_lsi_ops); + xive2_register_hw_source(p->base_lsi, 8, 16, + p->int_mmio + ((p->num_irqs - 8) << 16), + XIVE_SRC_LSI, p, &phb4_lsi_ops); + } else { + /* Register all interrupt sources with XIVE */ + xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16, + p->int_mmio, irq_flags, NULL, NULL); + + xive_register_hw_source(p->base_lsi, 8, 16, + p->int_mmio + ((p->num_irqs - 8) << 16), + XIVE_SRC_LSI, p, &phb4_lsi_ops); + } /* Platform additional setup */ if (platform.pci_setup_phb) @@ -5889,6 +5968,7 @@ static void phb4_create(struct dt_node *np) static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint32_t nest_base, uint32_t pci_base) { + enum phys_map_type phys_mmio64, phys_mmio32, phys_xive_esb, phys_reg_spc; uint32_t pci_stack, nest_stack, etu_base, gcid, phb_num, stk_index; uint64_t val, phb_bar = 0, irq_bar = 0, bar_en; uint64_t mmio0_bar = 0, mmio0_bmask, mmio0_sz; @@ -5902,12 +5982,27 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, unsigned int max_link_speed; int rc; + assert(is_phb5() || is_phb4()); /* Sanity check */ + gcid = dt_get_chip_id(stk_node); stk_index = dt_prop_get_u32(stk_node, "reg"); phb_num = dt_prop_get_u32(stk_node, "ibm,phb-index"); path = dt_get_path(stk_node); - prlog(PR_INFO, "PHB: Chip %d Found PHB4 PBCQ%d Stack %d at %s\n", - gcid, pec_index, stk_index, path); + if (is_phb5()) { + phys_mmio64 = PHB5_64BIT_MMIO; + phys_mmio32 = PHB5_32BIT_MMIO; + phys_xive_esb = PHB5_XIVE_ESB; + phys_reg_spc = PHB5_REG_SPC; + prlog(PR_INFO, "PHB: Chip %d Found PHB5 PBCQ%d Stack %d at %s\n", + gcid, pec_index, stk_index, path); + } else { + phys_mmio64 = PHB4_64BIT_MMIO; + phys_mmio32 = PHB4_32BIT_MMIO; + phys_xive_esb = PHB4_XIVE_ESB; + phys_reg_spc = PHB4_REG_SPC; + prlog(PR_INFO, "PHB: Chip %d Found PHB4 PBCQ%d Stack %d at %s\n", + gcid, pec_index, stk_index, path); + } free(path); pci_stack = pci_base + 0x40 * (stk_index + 1); @@ -5921,7 +6016,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, bar_en = 0; /* Initialize PHB register BAR */ - phys_map_get(gcid, PHB4_REG_SPC, phb_num, &phb_bar, NULL); + phys_map_get(gcid, phys_reg_spc, phb_num, &phb_bar, NULL); rc = xscom_write(gcid, nest_stack + XPEC_NEST_STK_PHB_REG_BAR, phb_bar << 8); @@ -5935,18 +6030,18 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, bar_en |= XPEC_NEST_STK_BAR_EN_PHB; /* Same with INT BAR (ESB) */ - phys_map_get(gcid, PHB4_XIVE_ESB, phb_num, &irq_bar, NULL); + phys_map_get(gcid, phys_xive_esb, phb_num, &irq_bar, NULL); xscom_write(gcid, nest_stack + XPEC_NEST_STK_IRQ_BAR, irq_bar << 8); bar_en |= XPEC_NEST_STK_BAR_EN_INT; /* Same with MMIO windows */ - phys_map_get(gcid, PHB4_64BIT_MMIO, phb_num, &mmio0_bar, &mmio0_sz); + phys_map_get(gcid, phys_mmio64, phb_num, &mmio0_bar, &mmio0_sz); mmio0_bmask = (~(mmio0_sz - 1)) & 0x00FFFFFFFFFFFFFFULL; xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0, mmio0_bar << 8); xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0_MASK, mmio0_bmask << 8); - phys_map_get(gcid, PHB4_32BIT_MMIO, phb_num, &mmio1_bar, &mmio1_sz); + phys_map_get(gcid, phys_mmio32, phb_num, &mmio1_bar, &mmio1_sz); mmio1_bmask = (~(mmio1_sz - 1)) & 0x00FFFFFFFFFFFFFFULL; xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1, mmio1_bar << 8); xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1_MASK, mmio1_bmask << 8); @@ -5994,7 +6089,10 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, if (!np) return; - dt_add_property_strings(np, "compatible", "ibm,power9-pciex", "ibm,ioda3-phb"); + if (is_phb5()) + dt_add_property_strings(np, "compatible", "ibm,power10-pciex", "ibm,ioda3-phb"); + else + dt_add_property_strings(np, "compatible", "ibm,power9-pciex", "ibm,ioda3-phb"); dt_add_property_strings(np, "device_type", "pciex"); dt_add_property_u64s(np, "reg", phb_bar, 0x1000, @@ -6078,12 +6176,24 @@ void probe_phb4(void) rx_err_max = MAX(rx_err_max, 0); rx_err_max = MIN(rx_err_max, 255); } - prlog(PR_DEBUG, "PHB4: Maximum RX errors during training: %d\n", rx_err_max); - /* Look for PBCQ XSCOM nodes */ - dt_for_each_compatible(dt_root, np, "ibm,power9-pbcq") - phb4_probe_pbcq(np); - /* Look for newly created PHB nodes */ - dt_for_each_compatible(dt_root, np, "ibm,power9-pciex") - phb4_create(np); + if (is_phb5()) { + prlog(PR_DEBUG, "PHB5: Maximum RX errors during training: %d\n", rx_err_max); + /* Look for PBCQ XSCOM nodes */ + dt_for_each_compatible(dt_root, np, "ibm,power10-pbcq") + phb4_probe_pbcq(np); + + /* Look for newly created PHB nodes */ + dt_for_each_compatible(dt_root, np, "ibm,power10-pciex") + phb4_create(np); + } else { + prlog(PR_DEBUG, "PHB4: Maximum RX errors during training: %d\n", rx_err_max); + /* Look for PBCQ XSCOM nodes */ + dt_for_each_compatible(dt_root, np, "ibm,power9-pbcq") + phb4_probe_pbcq(np); + + /* Look for newly created PHB nodes */ + dt_for_each_compatible(dt_root, np, "ibm,power9-pciex") + phb4_create(np); + } } diff --git a/hw/phys-map.c b/hw/phys-map.c index b8fff0a4f..d6ff99fd8 100644 --- a/hw/phys-map.c +++ b/hw/phys-map.c @@ -33,36 +33,36 @@ static const struct phys_map_entry phys_map_table_p10[] = { /* TODO: Figure out GPU memory */ /* 0 TB offset @ MMIO 0x0006000000000000ull */ - { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull }, - { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull }, - { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull }, - { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull }, - { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull }, - { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull }, - { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull }, - { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull }, - { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull }, - { PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull }, - { PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull }, - { PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull }, - { PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull }, - { PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull }, - { PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull }, - { PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull }, - { PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull }, - { PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull }, - { PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull }, - { PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull }, - { PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull }, + { PHB5_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull }, + { PHB5_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull }, + { PHB5_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull }, + { PHB5_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull }, + { PHB5_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull }, + { PHB5_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull }, + { PHB5_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull }, + { PHB5_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull }, + { PHB5_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull }, + { PHB5_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull }, + { PHB5_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull }, + { PHB5_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull }, + { PHB5_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull }, + { PHB5_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull }, + { PHB5_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull }, + { PHB5_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull }, + { PHB5_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull }, + { PHB5_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull }, + { PHB5_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull }, + { PHB5_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull }, + { PHB5_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull }, { RESV , 0, 0x000600c3c0600000ull, 0x0000003c3fa00000ull }, /* 1 TB offset */ { RESV , 1, 0x0006010000000000ull, 0x0000010000000000ull }, /* 2 TB offset */ - { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull }, - { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull }, - { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull }, + { PHB5_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull }, + { PHB5_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull }, + { PHB5_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull }, { RESV , 2, 0x000602c000000000ull, 0x0000004000000000ull }, /* 3 TB offset */ diff --git a/include/opal-api.h b/include/opal-api.h index 9cba35c7d..eb6d83527 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -799,7 +799,8 @@ enum { enum { OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2, - OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3 + OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3, + OPAL_PHB_ERROR_DATA_TYPE_PHB5 = 3 /* TODO change this */ }; enum { diff --git a/include/phb4-regs.h b/include/phb4-regs.h index b6e778744..03b53ae01 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -53,9 +53,11 @@ #define PHB_M64_AOMASK 0x1d0 #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_NXLATE_PREFIX 0x1f8 -#define PHB_DMARD_SYNC 0x200 -#define PHB_DMARD_SYNC_START PPC_BIT(0) -#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) +#define PHB_DMA_READ_WRITE_SYNC 0x200 +#define PHB_DMA_READ_SYNC_START PPC_BIT(0) +#define PHB_DMA_READ_SYNC_COMPLETE PPC_BIT(1) +#define PHB_DMA_WRITE_SYNC_START PPC_BIT(2) /* PHB5 */ +#define PHB_DMA_WRITE_SYNC_COMPLETE PPC_BIT(3) /* PHB5 */ #define PHB_RTC_INVALIDATE 0x208 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) @@ -274,6 +276,7 @@ #define PHB_PCIE_DLP_CTL 0x1A78 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) +#define PHB_PCIE_DLP_CTL_SFC_DISABLE PPC_BIT(60) #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) @@ -293,6 +296,7 @@ #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 +#define PHB_PCIE_PDL_PHY_EQ_CNTL 0x1B38 /* Error */ #define PHB_REGB_ERR_STATUS 0x1C00 diff --git a/include/phb4.h b/include/phb4.h index abba2d9c6..217f68462 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -154,9 +154,9 @@ struct phb4_err { #define PHB4_ETU_IN_RESET 0x00000020 struct phb4 { - unsigned int index; /* 0..5 index inside p9 */ + unsigned int index; /* 0..5 index inside p9/p10 */ unsigned int flags; - unsigned int chip_id; /* Chip ID (== GCID on p9) */ + unsigned int chip_id; /* Chip ID (== GCID on p9/p10) */ unsigned int pec; bool broken; unsigned int rev; /* 00MMmmmm */ @@ -245,16 +245,20 @@ static inline void phb4_set_err_pending(struct phb4 *p, bool pending) p->err_pending = pending; } -#define PHB4_PER_CHIP 6 /* Max 6 PHBs per chip on p9 */ -#define PHB4_MAX_PHBS_PER_CHIP_P9 PHB4_PER_CHIP -#define PHB4_MAX_PHBS_PER_CHIP_P9P 0x10 /* extra for virt PHBs */ +#define MAX_PHBS_PER_CHIP_P10 6 /* Max 6 PHBs per chip on p10 */ +#define MAX_PHBS_PER_CHIP_P9 6 /* Max 6 PHBs per chip on p9 */ +#define MAX_PHBS_PER_CHIP_P9P 0x10 /* extra for virt PHBs */ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) { - if (PVR_TYPE(mfspr(SPR_PVR)) == PVR_TYPE_P9) - return chip_id * PHB4_MAX_PHBS_PER_CHIP_P9 + index; - else - return chip_id * PHB4_MAX_PHBS_PER_CHIP_P9P + index; + if (proc_gen == proc_gen_p10) { + return chip_id * MAX_PHBS_PER_CHIP_P10 + index; + } else { + if (PVR_TYPE(mfspr(SPR_PVR)) == PVR_TYPE_P9) + return chip_id * MAX_PHBS_PER_CHIP_P9 + index; + else + return chip_id * MAX_PHBS_PER_CHIP_P9P + index; + } } void phb4_pec2_dma_engine_realloc(struct phb4 *p); diff --git a/include/phys-map.h b/include/phys-map.h index a3394c0d0..1dd337a56 100644 --- a/include/phys-map.h +++ b/include/phys-map.h @@ -20,6 +20,10 @@ enum phys_map_type { PHB4_32BIT_MMIO, PHB4_XIVE_ESB, PHB4_REG_SPC, + PHB5_64BIT_MMIO, + PHB5_32BIT_MMIO, + PHB5_XIVE_ESB, + PHB5_REG_SPC, NPU_OCAPI_MMIO, XIVE_VC, XIVE_PC, From patchwork Wed Aug 4 07:21:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Wed, 04 Aug 2021 07:23:03 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747N0ht56558012 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:00 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AC63EAE04D; Wed, 4 Aug 2021 07:23:00 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 701ABAE057; Wed, 4 Aug 2021 07:22:59 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:22:59 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:12 +0530 Message-Id: <20210804072137.1147875-35-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: TDM0QdyhpLe40NMOzvCB3yuzEPWHYjDD X-Proofpoint-GUID: TDM0QdyhpLe40NMOzvCB3yuzEPWHYjDD X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 34/59] xive/p10: Add option flags to the XIVE exploitation mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Change sligthly the semantic of the parameter of the opal_xive_reset() OPAL call to configure the interrupt mode of the machine and, at the same time, to configure the associated options. These options only apply to the XIVE exploitation mode. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/hw/xive2.c b/hw/xive2.c index a7bfdcbde..4ddcf184f 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -171,6 +171,14 @@ static enum { XIVE_MODE_NONE, } xive_mode = XIVE_MODE_NONE; +/* + * The XIVE exploitation mode options indicates the active features and + * is part of the mode parameter of the opal_xive_reset() call + */ +static uint64_t xive_expl_options; + +#define XIVE_EXPL_ALL_OPTIONS 0 + /* * Each source controller has one of these. There's one embedded in * the XIVE struct for IPIs @@ -3896,11 +3904,11 @@ void xive2_cpu_reset(void) in_be64(xs->tm_ring1 + TM_SPC_PULL_POOL_CTX); } -static int64_t __xive_reset(uint64_t version) +static int64_t __xive_reset(uint64_t mode) { struct proc_chip *chip; - xive_mode = version; + xive_mode = mode; /* Mask all interrupt sources */ irq_for_each_source(xive_reset_mask_source_cb, NULL); @@ -3938,13 +3946,20 @@ int64_t xive2_reset(void) return __xive_reset(XIVE_MODE_EXPL); } -static int64_t opal_xive_reset(uint64_t version) +static int64_t opal_xive_reset(uint64_t mode) { - prlog(PR_DEBUG, "XIVE reset, version: %d...\n", (int)version); + prlog(PR_DEBUG, "XIVE reset. mode = %llx\n", mode); - if (version != XIVE_MODE_EXPL) { - prerror("ignoring version %lld at reset. " - "XIVE exploitation mode is the default\n", version); + if (!(mode & XIVE_MODE_EXPL)) { + prlog(PR_NOTICE, "No emulation mode. XIVE exploitation mode " + "is the default\n"); + } + + xive_expl_options = mode & ~XIVE_MODE_EXPL; + if (xive_expl_options & ~XIVE_EXPL_ALL_OPTIONS) { + prerror("invalid XIVE exploitation mode option %016llx\n", + xive_expl_options); + return OPAL_PARAMETER; } return __xive_reset(XIVE_MODE_EXPL); From patchwork Wed Aug 4 07:21:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=nMlDC5Ee; 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Wed, 4 Aug 2021 07:23:01 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:00 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:13 +0530 Message-Id: <20210804072137.1147875-36-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: oNZTjSpEaSvzVnBYAprUBmccFeiaGwnU X-Proofpoint-GUID: oNZTjSpEaSvzVnBYAprUBmccFeiaGwnU X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=986 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 35/59] hw/phb5: Add support for PQ offloading X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater The POWER9 DD2.0 introduced a StoreEOI operation which had benefits over the LoadEOI operation : less latency and improved performance for interrupt handling. Because of load vs. store ordering issues in some cases, it had to be deactivates. The POWER10 processor has a set of new features in the XIVE2 and the PHB5 controllers to address this problem. At the interrupt controller level, XIVE2 adds a new load offset to the ESB page which offers the capability to order loads after stores. It should be enforced by the OS when doing loads if StoreEOI is to be used. But this is not enough. The firmware should also carefully configure the PHB interrupt sources to make sure that operations on the PQ state bits of a source are routed to a single logic unit : the XIVE2 IC. The PHB5 introduces a new configuration PQ disable (bit 9) bit for this purpose. It disables the check of the PQ state bits when processing new MSI interrupts. When set, the PHB ignores its local PQ state bits and forwards unconditionally any MSI trigger to the XIVE2 interrupt controller. The XIVE2 IC knows from the trigger message that the PQ bits have not been checked and performs the check using the local PQ bits. This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level. This requires a new XIVE interface to register a HW interrupt source using the IC ESB pages of the allocated HW interrupt numbers, and not the ESB pages of the HW source. This is what this change proposes for MSIs, LSI still being handled the old way. PQ disable is a requirement for StoreEOI. Signed-off-by: Cédric Le Goater [FB: port to phb4.c] Signed-off-by: Frederic Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/phb4.c | 47 ++++++++++++++++++++++++++++++++++++++------- hw/xive2.c | 40 +++++++++++++++++++++++++++++++++++--- include/phb4-regs.h | 1 + include/xive.h | 2 ++ 4 files changed, 80 insertions(+), 10 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index e074fa2a3..d2d9f9ec0 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -136,8 +136,6 @@ static void phb4_init_hw(struct phb4 *p); #define PHBLOGCFG(p, fmt, a...) do {} while (0) #endif -#define PHB4_CAN_STORE_EOI(p) XIVE_STORE_EOI_ENABLED - static bool pci_eeh_mmio; static bool pci_retry_all; static int rx_err_max = PHB4_RX_ERR_MAX; @@ -152,6 +150,24 @@ static inline bool is_phb5(void) return (proc_gen == proc_gen_p10); } +/* PQ offloading on the XIVE IC. */ +static inline bool phb_pq_disable(struct phb4 *p __unused) +{ + if (is_phb5()) + return 1; + + return false; +} + +static inline bool phb_can_store_eoi(struct phb4 *p) +{ + if (is_phb5()) + /* PQ offloading is required for StoreEOI */ + return XIVE2_STORE_EOI_ENABLED && phb_pq_disable(p); + + return XIVE_STORE_EOI_ENABLED; +} + /* Note: The "ASB" name is historical, practically this means access via * the XSCOM backdoor */ @@ -5366,8 +5382,12 @@ static void phb4_init_hw(struct phb4 *p) val = PHB_CTRLR_IRQ_PGSZ_64K; val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); - if (PHB4_CAN_STORE_EOI(p)) + if (phb_pq_disable(p)) + val |= PHB_CTRLR_IRQ_PQ_DISABLE; + if (phb_can_store_eoi(p)) { val |= PHB_CTRLR_IRQ_STORE_EOI; + PHBDBG(p, "store EOI is enabled\n"); + } if (!pci_eeh_mmio) val |= PHB_CTRLR_MMIO_EEH_DISABLE; @@ -5927,16 +5947,29 @@ static void phb4_create(struct dt_node *np) /* Compute XIVE source flags depending on PHB revision */ irq_flags = 0; - if (PHB4_CAN_STORE_EOI(p)) + if (phb_can_store_eoi(p)) irq_flags |= XIVE_SRC_STORE_EOI; else irq_flags |= XIVE_SRC_TRIGGER_PAGE; if (is_phb5()) { - /* Register all interrupt sources with XIVE */ - xive2_register_hw_source(p->base_msi, p->num_irqs - 8, 16, - p->int_mmio, irq_flags, NULL, NULL); + /* + * Register sources with XIVE. If offloading is on, use the + * ESB pages of the XIVE IC for the MSI sources instead of the + * ESB pages of the PHB. + */ + if (phb_pq_disable(p)) { + xive2_register_esb_source(p->base_msi, p->num_irqs - 8); + } else { + xive2_register_hw_source(p->base_msi, + p->num_irqs - 8, 16, + p->int_mmio, irq_flags, + NULL, NULL); + } + /* + * LSI sources always use the ESB pages of the PHB. + */ xive2_register_hw_source(p->base_lsi, 8, 16, p->int_mmio + ((p->num_irqs - 8) << 16), XIVE_SRC_LSI, p, &phb4_lsi_ops); diff --git a/hw/xive2.c b/hw/xive2.c index 4ddcf184f..3f4958fce 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -2579,8 +2579,8 @@ void xive2_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, false, data, ops); } -void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, - const struct irq_source_ops *ops) +static void __xive2_register_esb_source(uint32_t base, uint32_t count, + void *data, const struct irq_source_ops *ops) { struct xive_src *s; struct xive *x = xive_from_isn(base); @@ -2589,7 +2589,6 @@ void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, uint32_t flags = XIVE_SRC_EOI_PAGE1 | XIVE_SRC_TRIGGER_PAGE; assert(x); - assert(base >= x->int_base && (base + count) <= x->int_ipi_top); s = malloc(sizeof(struct xive_src)); assert(s); @@ -2605,6 +2604,41 @@ void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, flags, false, data, ops); } +/* + * Check that IPI sources have interrupt numbers in the IPI interrupt + * number range + */ +void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, + const struct irq_source_ops *ops) +{ + struct xive *x = xive_from_isn(base); + + assert(x); + assert(base >= x->int_base && (base + count) <= x->int_ipi_top); + + __xive2_register_esb_source(base, count, data, ops); +} + +/* + * Some HW sources (PHB) can disable the use of their own ESB pages + * and offload all the checks on ESB pages of the IC. The interrupt + * numbers are not necessarily in the IPI range. + */ +void xive2_register_esb_source(uint32_t base, uint32_t count) +{ + __xive2_register_esb_source(base, count, NULL, NULL); +} + +uint64_t xive2_get_esb_base(uint32_t base) +{ + struct xive *x = xive_from_isn(base); + uint32_t base_idx = GIRQ_TO_IDX(base); + + assert(x); + + return (uint64_t) x->esb_base + (1ul << XIVE_ESB_SHIFT) * base_idx; +} + static void xive_set_quirks(struct xive *x, struct proc_chip *chip __unused) { uint64_t quirks = 0; diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 03b53ae01..139522814 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -101,6 +101,7 @@ #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 +#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* PHB5 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) diff --git a/include/xive.h b/include/xive.h index dc1b25d03..faaef2aeb 100644 --- a/include/xive.h +++ b/include/xive.h @@ -86,6 +86,8 @@ void xive2_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, const struct irq_source_ops *ops); void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data, const struct irq_source_ops *ops); +void xive2_register_esb_source(uint32_t base, uint32_t count); +uint64_t xive2_get_esb_base(uint32_t girq); void xive2_cpu_callin(struct cpu_thread *cpu); void *xive2_get_trigger_port(uint32_t girq); From patchwork Wed Aug 4 07:21:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=FMkFczKJ; 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Wed, 4 Aug 2021 07:23:03 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:02 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:14 +0530 Message-Id: <20210804072137.1147875-37-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: r_zuURzM72AGXJmAnB3s7NnhInVDRnkT X-Proofpoint-GUID: r_zuURzM72AGXJmAnB3s7NnhInVDRnkT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 36/59] hw/phb5: Add support for 'Address-Based Interrupt Trigger' mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater The PHB5 introduces a new Address-Based Interrupt mode which extends the notification offloading to the ESB pages. When ABT is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB triggers the interrupt using directly the IC ESB page of the interrupt number and does not use the notify page of the IC anymore. The PHB interrrupt configuration under ABT is a little different. The 'Interrupt Notify Base Address' register points to the base address of the IC ESB pages and not to the notify page of the IC anymore as on P9. The 'Interrupt Notify Base Index' register is unused. This should improve overall performance. The P10 IC can handle higher interrupt rates compared to P9 and the PHB latency should be improved under ABT. Debug is easier as the interrupt number is now exposed on the PowerBUS. Signed-off-by: Cédric Le Goater [FB: port to phb4.c] Signed-off-by: Frederic Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/phb4.c | 63 ++++++++++++++++++++++++++++++++++++++++----- hw/xive2.c | 6 ----- include/phb4-regs.h | 2 ++ 3 files changed, 59 insertions(+), 12 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index d2d9f9ec0..d2fc274b3 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -159,6 +159,18 @@ static inline bool phb_pq_disable(struct phb4 *p __unused) return false; } +/* + * Use the ESB page of the XIVE IC for event notification. Latency + * improvement. + */ +static inline bool phb_abt_mode(struct phb4 *p __unused) +{ + if (is_phb5()) + return 1; + + return false; +} + static inline bool phb_can_store_eoi(struct phb4 *p) { if (is_phb5()) @@ -5000,12 +5012,49 @@ static const struct phb_ops phb4_ops = { static void phb4_init_ioda3(struct phb4 *p) { - /* Init_18 - Interrupt Notify Base Address */ - out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port); + if (is_phb5()) { + /* + * When ABT is on, the MSIs on the PHB use the PQ state bits + * of the IC and MSI triggers from the PHB are forwarded + * directly to the IC ESB page. However, the LSIs are still + * controlled locally on the PHB and LSI triggers use a + * special offset for trigger injection. + */ + if (phb_abt_mode(p)) { + uint64_t mmio_base = xive2_get_esb_base(p->base_msi); + + PHBDBG(p, "Using ABT mode. ESB: 0x%016llx\n", mmio_base); + + /* Init_18 - Interrupt Notify Base Address */ + out_be64(p->regs + PHB_INT_NOTIFY_ADDR, + PHB_INT_NOTIFY_ADDR_64K | mmio_base); + + /* Interrupt Notify Base Index is unused */ + } else { + p->irq_port = xive2_get_notify_port(p->chip_id, + XIVE_HW_SRC_PHBn(p->index)); + + PHBDBG(p, "Using IC notif page at 0x%016llx\n", + p->irq_port); - /* Init_19 - Interrupt Notify Base Index */ - out_be64(p->regs + PHB_INT_NOTIFY_INDEX, - xive2_get_notify_base(p->base_msi)); + /* Init_18 - Interrupt Notify Base Address */ + out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port); + + /* Init_19 - Interrupt Notify Base Index */ + out_be64(p->regs + PHB_INT_NOTIFY_INDEX, + xive2_get_notify_base(p->base_msi)); + } + + } else { /* p9 */ + p->irq_port = xive_get_notify_port(p->chip_id, + XIVE_HW_SRC_PHBn(p->index)); + /* Init_18 - Interrupt Notify Base Address */ + out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port); + + /* Init_19 - Interrupt Notify Base Index */ + out_be64(p->regs + PHB_INT_NOTIFY_INDEX, + xive_get_notify_base(p->base_msi)); + } /* Init_19x - Not in spec: Initialize source ID */ PHBDBG(p, "Reset state SRC_ID: %016llx\n", @@ -5384,6 +5433,8 @@ static void phb4_init_hw(struct phb4 *p) val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); if (phb_pq_disable(p)) val |= PHB_CTRLR_IRQ_PQ_DISABLE; + if (phb_abt_mode(p)) + val |= PHB_CTRLR_IRQ_ABT_MODE; if (phb_can_store_eoi(p)) { val |= PHB_CTRLR_IRQ_STORE_EOI; PHBDBG(p, "store EOI is enabled\n"); @@ -5958,7 +6009,7 @@ static void phb4_create(struct dt_node *np) * ESB pages of the XIVE IC for the MSI sources instead of the * ESB pages of the PHB. */ - if (phb_pq_disable(p)) { + if (phb_pq_disable(p) || phb_abt_mode(p)) { xive2_register_esb_source(p->base_msi, p->num_irqs - 8); } else { xive2_register_hw_source(p->base_msi, diff --git a/hw/xive2.c b/hw/xive2.c index 3f4958fce..cba050fa1 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -2141,12 +2141,6 @@ uint64_t xive2_get_notify_port(uint32_t chip_id, uint32_t ent) * * P10 might now be randomizing the cache line bits in HW to * balance snoop bus usage - * - * TODO (phb5) : implement "address based triggers" (DD2.0?) - * - * The PHBs would no longer target the notify port page but - * the "base ESB MMIO address" of the ESB/EAS range they are - * allocated. Needs a XIVE API change for the PHBs. */ switch(ent) { case XIVE_HW_SRC_PHBn(0): diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 139522814..99633e103 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -97,11 +97,13 @@ #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) #define PHB_ETU_ERR_SUMMARY 0x2c8 #define PHB_INT_NOTIFY_ADDR 0x300 +#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* PHB5 */ #define PHB_INT_NOTIFY_INDEX 0x308 #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* PHB5 */ +#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* PHB5 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) From patchwork Wed Aug 4 07:21:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:23:09 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma01fra.de.ibm.com with ESMTP id 3a4x58qtws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:23:08 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747N6uR35258846 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:06 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4F79CAE059; Wed, 4 Aug 2021 07:23:06 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1C29DAE063; Wed, 4 Aug 2021 07:23:05 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:04 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:15 +0530 Message-Id: <20210804072137.1147875-38-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: guwxLAQZ_1DBiB--nSPpA5Oz_jX6JFFd X-Proofpoint-ORIG-GUID: guwxLAQZ_1DBiB--nSPpA5Oz_jX6JFFd X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 37/59] psi/p10: Introduce xive2_source_mask() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Commit fa161cd89fbf ("hw/psi-p9: Mask OPAL-owned LSIs without handlers") introduced xive_source_mask(). Do the same for P10. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 11 ++++++++++- hw/xive2.c | 7 +++++++ include/xive.h | 2 ++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 291422539..e9b8e2ea7 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -564,7 +564,16 @@ static void psi_p9_mask_unhandled_irq(struct irq_source *is, uint32_t isn) * have a handler for the interrupt then it needs to be masked to * prevent the IRQ from locking up the thread which handles it. */ - xive_source_mask(is, isn); + switch (proc_gen) { + case proc_gen_p9: + xive_source_mask(is, isn); + break; + case proc_gen_p10: + xive2_source_mask(is, isn); + return; + default: + assert(false); + } } diff --git a/hw/xive2.c b/hw/xive2.c index cba050fa1..f565be1fd 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -2532,6 +2532,13 @@ static char *xive_source_name(struct irq_source *is, uint32_t isn) return s->orig_ops->name(is, isn); } +void xive2_source_mask(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + xive_update_irq_mask(s, isn - s->esb_base, true); +} + static const struct irq_source_ops xive_irq_source_ops = { .interrupt = xive_source_interrupt, .attributes = xive_source_attributes, diff --git a/include/xive.h b/include/xive.h index faaef2aeb..8d5fbeddb 100644 --- a/include/xive.h +++ b/include/xive.h @@ -91,6 +91,8 @@ uint64_t xive2_get_esb_base(uint32_t girq); void xive2_cpu_callin(struct cpu_thread *cpu); void *xive2_get_trigger_port(uint32_t girq); +void xive2_source_mask(struct irq_source *is, uint32_t isn); + void xive2_cpu_reset(void); void xive2_late_init(void); From patchwork Wed Aug 4 07:21:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Wed, 04 Aug 2021 07:23:10 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747N8s454985110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:08 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2A1C0AE05F; Wed, 4 Aug 2021 07:23:08 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA003AE061; Wed, 4 Aug 2021 07:23:06 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:06 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:16 +0530 Message-Id: <20210804072137.1147875-39-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 3zDHeqGWTHxvPAVOR3rnVMhRw_fx4acs X-Proofpoint-GUID: 3zDHeqGWTHxvPAVOR3rnVMhRw_fx4acs X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=990 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 38/59] psi/p10: Mask all sources at init X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/psi.c b/hw/psi.c index e9b8e2ea7..954b7bf68 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -766,6 +766,8 @@ static void psi_init_p10_interrupts(struct psi *psi) u64 val; uint32_t esb_shift = 16; uint32_t flags = XIVE_SRC_LSI; + struct irq_source *is; + int isn; /* Grab chip */ chip = get_chip(psi->chip_id); @@ -813,6 +815,11 @@ static void psi_init_p10_interrupts(struct psi *psi) esb_shift, psi->esb_mmio, flags, psi, &psi_p10_irq_ops); + /* Mask all sources */ + is = irq_find_source(psi->interrupt); + for (isn = is->start; isn < is->end; isn++) + xive2_source_mask(is, isn); + /* Reset irq handling and switch to ESB mode */ out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); From patchwork Wed Aug 4 07:21:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513240 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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Wed, 04 Aug 2021 07:23:12 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747N9Xl51708334 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:10 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE52BAE05D; Wed, 4 Aug 2021 07:23:09 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C7A3AE04D; Wed, 4 Aug 2021 07:23:08 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:08 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:17 +0530 Message-Id: <20210804072137.1147875-40-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: vqgvnx500m3ksSLw1aGzx6bMKW8SpZte X-Proofpoint-ORIG-GUID: vqgvnx500m3ksSLw1aGzx6bMKW8SpZte X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 39/59] xive/p10: Introduce new capability bits X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater These bits control the availability of interrupt features : StoreEOI, PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE exploitation mode. These bits can be set at early boot time of the system to activate/deactivate a feature for testing purposes. The default value should be '1'. The 'XIVE exploitation mode' bit is a software bit that skiboot could use to disable the XIVE OS interface and propose a P8 style XICS interface instead. There are no plans for that for the moment. The 'PHB PQ_disable', 'PHB Address-Based Trigger' bits are only used by the PHB5 driver and we deduce their availability from the capabilities of the first XIVE chip. If called from a PHB4 driver, the capabilities should be set to false. Signed-off-by: Cédric Le Goater [FB: port to phb4.c] Signed-off-by: Frederic Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/phb4.c | 4 ++-- hw/xive2.c | 56 ++++++++++++++++++++++++++++++++++++++------ include/xive.h | 5 +++- include/xive2-regs.h | 6 +++++ 4 files changed, 61 insertions(+), 10 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index d2fc274b3..de314b13f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -154,7 +154,7 @@ static inline bool is_phb5(void) static inline bool phb_pq_disable(struct phb4 *p __unused) { if (is_phb5()) - return 1; + return xive2_cap_phb_pq_disable(); return false; } @@ -166,7 +166,7 @@ static inline bool phb_pq_disable(struct phb4 *p __unused) static inline bool phb_abt_mode(struct phb4 *p __unused) { if (is_phb5()) - return 1; + return xive2_cap_phb_abt(); return false; } diff --git a/hw/xive2.c b/hw/xive2.c index f565be1fd..0005a8314 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -224,6 +224,7 @@ struct xive { struct dt_node *x_node; enum xive_generation generation; + uint64_t capabilities; uint64_t config; uint64_t xscom_base; @@ -341,8 +342,6 @@ struct xive { uint64_t quirks; }; -#define XIVE_CAN_STORE_EOI(x) XIVE2_STORE_EOI_ENABLED - /* First XIVE unit configured on the system */ static struct xive *one_xive; @@ -1509,6 +1508,10 @@ static const struct { uint64_t bitmask; const char *name; } xive_capabilities[] = { + { CQ_XIVE_CAP_PHB_PQ_DISABLE, "PHB PQ disable mode support" }, + { CQ_XIVE_CAP_PHB_ABT, "PHB address based trigger mode support" }, + { CQ_XIVE_CAP_EXPLOITATION_MODE, "Exploitation mode" }, + { CQ_XIVE_CAP_STORE_EOI, "StoreEOI mode support" }, }; static void xive_dump_capabilities(struct xive *x, uint64_t cap_val) @@ -1584,6 +1587,13 @@ static void xive_dump_configuration(struct xive *x, const char *prefix, CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS | \ CQ_XIVE_CFG_GEN1_END_ESX) +static bool xive_has_cap(struct xive *x, uint64_t cap) +{ + return !!x && !!(x->capabilities & cap); +} + +#define XIVE_CAN_STORE_EOI(x) xive_has_cap(x, CQ_XIVE_CAP_STORE_EOI) + static void xive_config_reduced_priorities_fixup(struct xive *x) { if (xive_cfg_vp_prio_shift(x) < CQ_XIVE_CFG_INT_PRIO_8 && @@ -1599,12 +1609,10 @@ static void xive_config_reduced_priorities_fixup(struct xive *x) static bool xive_config_init(struct xive *x) { - uint64_t cap_val; - - cap_val = xive_regr(x, CQ_XIVE_CAP); - xive_dump_capabilities(x, cap_val); + x->capabilities = xive_regr(x, CQ_XIVE_CAP); + xive_dump_capabilities(x, x->capabilities); - x->generation = GETFIELD(CQ_XIVE_CAP_VERSION, cap_val); + x->generation = GETFIELD(CQ_XIVE_CAP_VERSION, x->capabilities); /* * Allow QEMU to override version for tests @@ -4420,6 +4428,40 @@ static void xive_init_globals(void) xive_block_to_chip[i] = XIVE_INVALID_CHIP; } +/* + * The global availability of some capabilities used in other drivers + * (PHB, PSI) is deduced from the capabilities of the first XIVE chip + * of the system. It should be common to all chips. + */ +bool xive2_cap_phb_pq_disable(void) +{ + return xive_has_cap(one_xive, CQ_XIVE_CAP_PHB_PQ_DISABLE); +} + +bool xive2_cap_phb_abt(void) +{ + if (!xive_has_cap(one_xive, CQ_XIVE_CAP_PHB_ABT)) + return false; + + /* + * We need 'PQ disable' to use ABT mode, else the OS will use + * two different sets of ESB pages (PHB and IC) to control the + * interrupt sources. Can not work. + */ + if (!xive2_cap_phb_pq_disable()) { + prlog_once(PR_ERR, "ABT mode is set without PQ disable. " + "Ignoring bogus configuration\n"); + return false; + } + + return true; +} + +bool xive2_cap_store_eoi(void) +{ + return xive_has_cap(one_xive, CQ_XIVE_CAP_STORE_EOI); +} + void xive2_init(void) { struct dt_node *np; diff --git a/include/xive.h b/include/xive.h index 8d5fbeddb..1a8a2e027 100644 --- a/include/xive.h +++ b/include/xive.h @@ -72,9 +72,12 @@ void xive_late_init(void); * the PHB5 should be configured in Address-based trigger mode with PQ * state bit offloading. */ -#define XIVE2_STORE_EOI_ENABLED 1 +#define XIVE2_STORE_EOI_ENABLED xive2_cap_store_eoi() void xive2_init(void); +bool xive2_cap_phb_pq_disable(void); +bool xive2_cap_phb_abt(void); +bool xive2_cap_store_eoi(void); int64_t xive2_reset(void); uint32_t xive2_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align); diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 6697f036e..79c36ebca 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -32,6 +32,12 @@ #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12,13) +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) +/* 62:63 reserved */ + /* XIVE Configuration */ #define X_CQ_XIVE_CFG 0x03 #define CQ_XIVE_CFG 0x018 From patchwork Wed Aug 4 07:21:18 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:23:11 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6618EAE057; Wed, 4 Aug 2021 07:23:10 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:10 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:18 +0530 Message-Id: <20210804072137.1147875-41-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 6xHhmdBw4HNaSk2RKVLPpzs2h8jyHCp7 X-Proofpoint-GUID: 9lWTzG06yTxiqF1N4m-Y1jtLNv6muwms X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 40/59] hw/psi-p10: Configure interrupt offset before notify addr X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is we'll send an interrupt trigger notification to the XIVE with the wrong interrupt vector (0..15). This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by registering and masking all the PSI interrupts after we've configured the ESB BAR, but before configuring the notification address and offset. Signed-off-by: Oliver O'Halloran Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 954b7bf68..de074ce4a 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -796,16 +796,6 @@ static void psi_init_p10_interrupts(struct psi *psi) flags |= XIVE_SRC_STORE_EOI; } - /* Grab and configure the notification port */ - val = xive2_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); - val |= PSIHB_ESB_NOTIF_VALID; - out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); - - /* Setup interrupt offset */ - val = xive2_get_notify_base(psi->interrupt); - val <<= 32; - out_be64(psi->regs + PSIHB_IVT_OFFSET, val); - /* Register sources */ prlog(PR_DEBUG, "PSI[0x%03x]: Interrupts sources registered for P10 DD%i.%i\n", @@ -820,6 +810,16 @@ static void psi_init_p10_interrupts(struct psi *psi) for (isn = is->start; isn < is->end; isn++) xive2_source_mask(is, isn); + /* Setup interrupt offset */ + val = xive2_get_notify_base(psi->interrupt); + val <<= 32; + out_be64(psi->regs + PSIHB_IVT_OFFSET, val); + + /* Grab and configure the notification port */ + val = xive2_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); + val |= PSIHB_ESB_NOTIF_VALID; + out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); + /* Reset irq handling and switch to ESB mode */ out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); From patchwork Wed Aug 4 07:21:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 4 Aug 2021 07:23:12 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:12 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:19 +0530 Message-Id: <20210804072137.1147875-42-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 61MLkJ3-45ZEAzlPXy0Ycvi3704GwlNR X-Proofpoint-GUID: 61MLkJ3-45ZEAzlPXy0Ycvi3704GwlNR X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 41/59] xive/p10: Configure XIVE for fused cores X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 17 ++++++++++++++++- include/xive2-regs.h | 12 ++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/hw/xive2.c b/hw/xive2.c index 0005a8314..67b497082 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1594,6 +1594,19 @@ static bool xive_has_cap(struct xive *x, uint64_t cap) #define XIVE_CAN_STORE_EOI(x) xive_has_cap(x, CQ_XIVE_CAP_STORE_EOI) +static void xive_config_fused_core(struct xive *x) +{ + uint64_t val = xive_regr(x, TCTXT_CFG); + + if (this_cpu()->is_fused_core) { + val |= TCTXT_CFG_FUSE_CORE_EN; + xive_dbg(x, "configured for fused cores. " + "PC_TCTXT_CFG=%016llx\n", val); + } else + val &= ~TCTXT_CFG_FUSE_CORE_EN; + xive_regw(x, TCTXT_CFG, val); +} + static void xive_config_reduced_priorities_fixup(struct xive *x) { if (xive_cfg_vp_prio_shift(x) < CQ_XIVE_CFG_INT_PRIO_8 && @@ -1686,6 +1699,8 @@ static bool xive_config_init(struct xive *x) xive_dbg(x, "store EOI is %savailable\n", XIVE_CAN_STORE_EOI(x) ? "" : "not "); + xive_config_fused_core(x); + xive_config_reduced_priorities_fixup(x); return true; @@ -2981,7 +2996,7 @@ static void xive_init_cpu(struct cpu_thread *c) * of a pair is present we just do the setup for each of them, which * is harmless. */ - if (cpu_is_thread0(c)) + if (cpu_is_thread0(c) || cpu_is_core_chiplet_primary(c)) xive_configure_ex_special_bar(x, c); /* Initialize the state structure */ diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 79c36ebca..6295dd191 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -392,6 +392,18 @@ #define X_TCTXT_EN1_RESET 0x307 #define TCTXT_EN1_RESET 0x038 +/* TCTXT Config register */ +#define X_TCTXT_CFG 0x328 +#define TCTXT_CFG 0x140 +#define TCTXT_CFG_FUSE_CORE_EN PPC_BIT(0) +#define TCTXT_CFG_PHYP_CORE_MODE PPC_BIT(1) /* O:Linux 1:pHyp */ +#define TCTXT_CFG_GEN1_HYP_TARGET_DIS PPC_BIT(4) +#define TCTXT_CFG_GEN1_OS_ST_ACK PPC_BIT(5) +#define TCTXT_CFG_GEN1_OGEN_FINE PPC_BIT(6) +#define TCTXT_CFG_INT_MSGSND_DIS PPC_BIT(17) +#define TCTXT_CFG_HOSTBOOT_MODE PPC_BIT(20) +#define TCTXT_CFG_COMPLEX_STORE_DIS PPC_BITMASK(25, 27) + /* * VSD Tables */ From patchwork Wed Aug 4 07:21:20 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:23:14 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:13 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:20 +0530 Message-Id: <20210804072137.1147875-43-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: _vVj2dFEO0NZcbsOZNbGeuiq4O7_R_vh X-Proofpoint-GUID: _vVj2dFEO0NZcbsOZNbGeuiq4O7_R_vh X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 42/59] xive/p10: Add automatic Context Save and Restore support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater The save-restore feature is forced when available. It would have been better to introduce some negotiation but the CAM line value is returned by get_vp_info() before the save-restore feature can be enabled by KVM in xive_native_enable_vp(). This is compatible with the current KVM implementation for P9. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ include/opal-api.h | 1 + include/xive2-regs.h | 8 +++++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/xive2.c b/hw/xive2.c index 67b497082..7ece64251 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1512,6 +1512,7 @@ static const struct { { CQ_XIVE_CAP_PHB_ABT, "PHB address based trigger mode support" }, { CQ_XIVE_CAP_EXPLOITATION_MODE, "Exploitation mode" }, { CQ_XIVE_CAP_STORE_EOI, "StoreEOI mode support" }, + { CQ_XIVE_CAP_VP_SAVE_RESTORE, "VP Context Save and Restore" }, }; static void xive_dump_capabilities(struct xive *x, uint64_t cap_val) @@ -1543,6 +1544,8 @@ static const struct { { CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0, "Gen1 mode TIMA General Hypervisor Block0" }, { CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS, "Gen1 mode TIMA Crowd disable" }, { CQ_XIVE_CFG_GEN1_END_ESX, "Gen1 mode END ESx" }, + { CQ_XIVE_CFG_EN_VP_SAVE_RESTORE, "VP Context Save and Restore" }, + { CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT, "VP Context Save and Restore strict" }, }; static void xive_dump_configuration(struct xive *x, const char *prefix, @@ -1594,6 +1597,11 @@ static bool xive_has_cap(struct xive *x, uint64_t cap) #define XIVE_CAN_STORE_EOI(x) xive_has_cap(x, CQ_XIVE_CAP_STORE_EOI) +static bool xive_cfg_save_restore(struct xive *x) +{ + return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE); +} + static void xive_config_fused_core(struct xive *x) { uint64_t val = xive_regr(x, TCTXT_CFG); @@ -1654,6 +1662,14 @@ static bool xive_config_init(struct xive *x) x->config |= CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE | SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, x->block_id); + /* + * Enable "VP Context Save and Restore" by default. it is + * compatible with KVM which currently does the context + * save&restore in the entry/exit path of the vCPU + */ + if (x->capabilities & CQ_XIVE_CAP_VP_SAVE_RESTORE) + x->config |= CQ_XIVE_CFG_EN_VP_SAVE_RESTORE; + xive_dump_configuration(x, "new", x->config); xive_regw(x, CQ_XIVE_CFG, x->config); if (xive_regr(x, CQ_XIVE_CFG) != x->config) { @@ -1903,6 +1919,9 @@ static void xive_create_mmio_dt_node(struct xive *x) if (XIVE_CAN_STORE_EOI(x)) dt_add_property(xive_dt_node, "store-eoi", NULL, 0); + if (xive_cfg_save_restore(x)) + dt_add_property(xive_dt_node, "vp-save-restore", NULL, 0); + xive_add_provisioning_properties(); } @@ -3470,6 +3489,8 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, return OPAL_PARAMETER; if (xive_get_field32(NVP_W0_VALID, vp->w0)) *out_flags |= cpu_to_be64(OPAL_XIVE_VP_ENABLED); + if (xive_cfg_save_restore(x)) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_SAVE_RESTORE); if (xive_get_field32(END_W0_SILENT_ESCALATE, end->w0)) *out_flags |= cpu_to_be64(OPAL_XIVE_VP_SINGLE_ESCALATION); } @@ -3479,6 +3500,13 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, cam_value = (blk << x->vp_shift) | idx; + /* + * If save-restore is enabled, force the CAM line + * value with the H bit. + */ + if (xive_cfg_save_restore(x)) + cam_value |= TM10_QW1W2_HO; + *out_cam_value = cpu_to_be64(cam_value); } @@ -3626,6 +3654,10 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id, if (!vp) return OPAL_PARAMETER; + /* Consistency check. */ + if ((flags & OPAL_XIVE_VP_SAVE_RESTORE) && !xive_cfg_save_restore(x)) + return OPAL_PARAMETER; + lock(&x->lock); vp_new = *vp; @@ -3638,6 +3670,22 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id, rc = xive_setup_silent_gather(vp_id, true); else rc = xive_setup_silent_gather(vp_id, false); + + /* + * Prepare NVP to be HW owned for automatic save-restore + */ + if (xive_cfg_save_restore(x)) { + /* + * Set NVP privilege level. Default to OS. + * This check only makes sense for KVM guests + * currently. We would need an extra flag to + * distinguish from pool level. + */ + vp_new.w0 = xive_set_field32(NVP_W0_VPRIV, vp_new.w0, 0); + + vp_new.w2 = xive_set_field32(NVP_W2_CPPR, vp_new.w2, 0xFF); + vp_new.w0 = xive_set_field32(NVP_W0_HW, vp_new.w0, 1); + } } else { /* * TODO (kvm): disabling a VP invalidates the associated ENDs. diff --git a/include/opal-api.h b/include/opal-api.h index eb6d83527..d7b301a30 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1177,6 +1177,7 @@ enum { enum { OPAL_XIVE_VP_ENABLED = 0x00000001, OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002, + OPAL_XIVE_VP_SAVE_RESTORE = 0x00000004, }; /* "Any chip" replacement for chip ID for allocation functions */ diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 6295dd191..ad1a9b79f 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -31,7 +31,7 @@ #define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2 #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12,13) - +#define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38) #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) @@ -68,6 +68,10 @@ #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */ #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28) /* END ESx stores are dropped */ +#define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */ +#define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */ + +#define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */ /* Interrupt Controller Base Address Register - 512 pages (32M) */ #define X_CQ_IC_BAR 0x08 @@ -508,6 +512,8 @@ struct xive_end { struct xive_nvp { beint32_t w0; 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Wed, 4 Aug 2021 07:23:15 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:15 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:21 +0530 Message-Id: <20210804072137.1147875-44-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: vTZcWfiwRR9IaglhiLQ8FReKApsG_wM_ X-Proofpoint-GUID: vTZcWfiwRR9IaglhiLQ8FReKApsG_wM_ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=919 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 43/59] xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flag X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater StoreEOI (the capability to EOI with a store) requires load-after-store ordering in some cases to be reliable. P10 introduced a new offset for load operations to enforce correct ordering and the XIVE driver has the required support since kernel 5.8, commit b1f9be9392f0. OPAL on P10 will advertise support of StoreEOI with a new flag. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 2 +- include/opal-api.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/xive2.c b/hw/xive2.c index 7ece64251..2291e9379 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -3040,7 +3040,7 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags) uint64_t oflags = 0; if (iflags & XIVE_SRC_STORE_EOI) - oflags |= OPAL_XIVE_IRQ_STORE_EOI; + oflags |= OPAL_XIVE_IRQ_STORE_EOI2; /* OPAL_XIVE_IRQ_TRIGGER_PAGE is only meant to be set if * the interrupt has a *separate* trigger page. diff --git a/include/opal-api.h b/include/opal-api.h index d7b301a30..348fda8c6 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1164,6 +1164,7 @@ enum { OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* DD1.0 workaround */ OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* DD1.0 workaround */ OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, /* DD1.0 workaround */ + OPAL_XIVE_IRQ_STORE_EOI2 = 0x00000040, }; /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */ From patchwork Wed Aug 4 07:21:22 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:23:17 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:17 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:22 +0530 Message-Id: <20210804072137.1147875-45-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: EdFY0m7bWmdsRDgj083ZesPCzRtjBUpm X-Proofpoint-GUID: EdFY0m7bWmdsRDgj083ZesPCzRtjBUpm X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 44/59] xive/p10: Activate split mode for PHB ESBs when PQ_disable is available X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater 1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs. This is sufficient to keep all the PHB ESBs in cache and avoid ESB cache misses during IO interrupt processing. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 25 +++++++++++++++++++++++++ include/xive2-regs.h | 5 +++++ 2 files changed, 30 insertions(+) diff --git a/hw/xive2.c b/hw/xive2.c index 2291e9379..0f9c93d6a 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1602,6 +1602,29 @@ static bool xive_cfg_save_restore(struct xive *x) return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE); } +/* + * When PQ_disable is available, configure the ESB cache to improve + * performance for PHB ESBs. + * + * split_mode : + * 1/3rd of the cache is reserved for PHB ESBs and the rest to + * IPIs. This is sufficient to keep all the PHB ESBs in cache and + * avoid ESB cache misses during IO interrupt processing. + */ +static void xive_config_esb_cache(struct xive *x) +{ + uint64_t val = xive_regr(x, VC_ESBC_CFG); + + if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { + val |= VC_ESBC_CFG_SPLIT_MODE; + xive_dbg(x, "ESB cache configured with split mode. " + "VC_ESBC_CFG=%016llx\n", val); + } else + val &= ~VC_ESBC_CFG_SPLIT_MODE; + + xive_regw(x, VC_ESBC_CFG, val); +} + static void xive_config_fused_core(struct xive *x) { uint64_t val = xive_regr(x, TCTXT_CFG); @@ -1717,6 +1740,8 @@ static bool xive_config_init(struct xive *x) xive_config_fused_core(x); + xive_config_esb_cache(x); + xive_config_reduced_priorities_fixup(x); return true; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index ad1a9b79f..4638c3d89 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -227,6 +227,11 @@ #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35) #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */ +/* ESBC configuration */ +#define X_VC_ESBC_CFG 0x148 +#define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) + /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 #define VC_EASC_FLUSH_CTRL 0x300 From patchwork Wed Aug 4 07:21:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:23:22 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma05fra.de.ibm.com with ESMTP id 3a4x58fvg4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:23:22 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NKZ453936536 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:20 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4F5C1AE05D; Wed, 4 Aug 2021 07:23:20 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1F198AE064; Wed, 4 Aug 2021 07:23:19 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:18 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:23 +0530 Message-Id: <20210804072137.1147875-46-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VyZGnSn-dRStB42Qj9UZ28GX-bk-81kH X-Proofpoint-GUID: VyZGnSn-dRStB42Qj9UZ28GX-bk-81kH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=665 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 45/59] xive/p10: Activate has_array when PQ_disable is available X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater hash_array is an Internal cache hashing optimization. It tracks for ESBs where the original trigger came from so that we avoid getting the EAS into the cache twice. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 11 ++++++++--- include/xive2-regs.h | 2 ++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/xive2.c b/hw/xive2.c index 0f9c93d6a..1ad1f138d 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1610,15 +1610,20 @@ static bool xive_cfg_save_restore(struct xive *x) * 1/3rd of the cache is reserved for PHB ESBs and the rest to * IPIs. This is sufficient to keep all the PHB ESBs in cache and * avoid ESB cache misses during IO interrupt processing. + * + * hash_array_enable : + * Internal cache hashing optimization. The hash_array tracks for + * ESBs where the original trigger came from so that we avoid + * getting the EAS into the cache twice. */ static void xive_config_esb_cache(struct xive *x) { uint64_t val = xive_regr(x, VC_ESBC_CFG); if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { - val |= VC_ESBC_CFG_SPLIT_MODE; - xive_dbg(x, "ESB cache configured with split mode. " - "VC_ESBC_CFG=%016llx\n", val); + val |= VC_ESBC_CFG_SPLIT_MODE | VC_ESBC_CFG_HASH_ARRAY_ENABLE; + xive_dbg(x, "ESB cache configured with split mode " + "and hash array. VC_ESBC_CFG=%016llx\n", val); } else val &= ~VC_ESBC_CFG_SPLIT_MODE; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 4638c3d89..c2ed265f6 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -230,6 +230,8 @@ /* ESBC configuration */ #define X_VC_ESBC_CFG 0x148 #define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_HASH_ARRAY_ENABLE PPC_BIT(40) +#define VC_ESBC_CFG_HASH_STORE_MODE PPC_BITMASK(41,42) #define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) /* EASC flush control register */ From patchwork Wed Aug 4 07:21:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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Wed, 04 Aug 2021 07:23:24 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NM4V27197762 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:22 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 26D92AE067; Wed, 4 Aug 2021 07:23:22 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D338DAE059; Wed, 4 Aug 2021 07:23:20 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:20 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:24 +0530 Message-Id: <20210804072137.1147875-47-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: KHYo0A74b9Ob-ZIIn1En2bKQbIFDJOEO X-Proofpoint-GUID: KHYo0A74b9Ob-ZIIn1En2bKQbIFDJOEO X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=837 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 46/59] xive/p10: Tune max_entries_in_modified when split_mode is on X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater This reduces the number of entries currently modified in the ESB cache. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 1 + include/xive2-regs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/xive2.c b/hw/xive2.c index 1ad1f138d..56b02fc67 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1622,6 +1622,7 @@ static void xive_config_esb_cache(struct xive *x) if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { val |= VC_ESBC_CFG_SPLIT_MODE | VC_ESBC_CFG_HASH_ARRAY_ENABLE; + val = SETFIELD(VC_ESBC_CFG_MAX_ENTRIES_IN_MODIFIED, val, 0xE); xive_dbg(x, "ESB cache configured with split mode " "and hash array. VC_ESBC_CFG=%016llx\n", val); } else diff --git a/include/xive2-regs.h b/include/xive2-regs.h index c2ed265f6..1f7a3e721 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -233,6 +233,7 @@ #define VC_ESBC_CFG_HASH_ARRAY_ENABLE PPC_BIT(40) #define VC_ESBC_CFG_HASH_STORE_MODE PPC_BITMASK(41,42) #define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) +#define VC_ESBC_CFG_MAX_ENTRIES_IN_MODIFIED PPC_BITMASK(59,63) /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 From patchwork Wed Aug 4 07:21:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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Wed, 04 Aug 2021 07:23:26 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NNOp54329836 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:23 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C2AA7AE063; Wed, 4 Aug 2021 07:23:23 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 93E3BAE057; Wed, 4 Aug 2021 07:23:22 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:22 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:25 +0530 Message-Id: <20210804072137.1147875-48-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: KNNLWox0QbO0vlxyU7P_vUoC3Vio4FDx X-Proofpoint-GUID: KNNLWox0QbO0vlxyU7P_vUoC3Vio4FDx X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 47/59] xive/p10: Change alignment of the queue overflow pages X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater The Memory Coherence Directory uses 16M "granule" to track shared copies of a cache line. If any cache line within the 16M range gets touched by someone outside of the group, the MCD forces accesses to any cache line within the range to include everyone that might have a shared copy. Allocate the queue overflow pages and use a 16M alignment to avoid sharing with other structures and reduce traffic on the PowerBus. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/xive2.c b/hw/xive2.c index 56b02fc67..a7b45a005 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1492,6 +1492,8 @@ static bool xive_configure_bars(struct xive *x) xive_dbg(x, "NVP: %14p [0x%012llx]\n", x->nvp_base, x->nvp_size); xive_dbg(x, "ESB: %14p [0x%012llx]\n", x->esb_base, x->esb_size); xive_dbg(x, "END: %14p [0x%012llx]\n", x->end_base, x->end_size); + xive_dbg(x, "OVF: %14p [0x%012x]\n", x->q_ovf, + VC_QUEUE_COUNT * PAGE_SIZE); return true; } @@ -1898,8 +1900,22 @@ static bool xive_prealloc_tables(struct xive *x) return false; } - /* Allocate the queue overflow pages */ - x->q_ovf = local_alloc(x->chip_id, VC_QUEUE_COUNT * PAGE_SIZE, PAGE_SIZE); + /* + * The Memory Coherence Directory uses 16M "granule" to track + * shared copies of a cache line. If any cache line within the + * 16M range gets touched by someone outside of the group, the + * MCD forces accesses to any cache line within the range to + * include everyone that might have a shared copy. + */ +#define QUEUE_OVF_ALIGN (16 << 20) /* MCD granule size */ + + /* + * Allocate the queue overflow pages and use a 16M alignment + * to avoid sharing with other structures and reduce traffic + * on the PowerBus. + */ + x->q_ovf = local_alloc(x->chip_id, VC_QUEUE_COUNT * PAGE_SIZE, + QUEUE_OVF_ALIGN); if (!x->q_ovf) { xive_err(x, "Failed to allocate queue overflow\n"); return false; From patchwork Wed Aug 4 07:21:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Wed, 04 Aug 2021 07:23:28 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747KUbE28901792 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:20:30 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6A4B0AE04D; Wed, 4 Aug 2021 07:23:25 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 37AF5AE051; Wed, 4 Aug 2021 07:23:24 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:23 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:26 +0530 Message-Id: <20210804072137.1147875-49-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 9lWxN43SMD2Hqd2Fe6eG56pqpu2opOYC X-Proofpoint-GUID: 9lWxN43SMD2Hqd2Fe6eG56pqpu2opOYC X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 mlxlogscore=934 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 48/59] hw/phb5: Update PHB numbering to allow for virtual PHBs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Make room for a per-chip numbering of virtual PHBs used by opencapi. We can have up to 12 opencapi PHBs (two per PAU) on P10. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- include/phb4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/phb4.h b/include/phb4.h index 217f68462..0bbfc926c 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -245,9 +245,9 @@ static inline void phb4_set_err_pending(struct phb4 *p, bool pending) p->err_pending = pending; } -#define MAX_PHBS_PER_CHIP_P10 6 /* Max 6 PHBs per chip on p10 */ #define MAX_PHBS_PER_CHIP_P9 6 /* Max 6 PHBs per chip on p9 */ #define MAX_PHBS_PER_CHIP_P9P 0x10 /* extra for virt PHBs */ +#define MAX_PHBS_PER_CHIP_P10 0x12 /* 6 PCI + 12 opencapi */ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) { From patchwork Wed Aug 4 07:21:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513247 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:23:29 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma01fra.de.ibm.com with ESMTP id 3a4x58qtx5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:23:29 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NRDO56623506 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:27 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E9DAAE061; Wed, 4 Aug 2021 07:23:27 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D77CCAE05D; Wed, 4 Aug 2021 07:23:25 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:25 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:27 +0530 Message-Id: <20210804072137.1147875-50-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: foxuNv6n_9pUwC3eV48Wyi23w6ngpFlj X-Proofpoint-GUID: foxuNv6n_9pUwC3eV48Wyi23w6ngpFlj X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 mlxlogscore=778 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 49/59] phb5: Activate StoreEOI for LSIs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/phb4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index de314b13f..6700c7fbb 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -6023,7 +6023,7 @@ static void phb4_create(struct dt_node *np) */ xive2_register_hw_source(p->base_lsi, 8, 16, p->int_mmio + ((p->num_irqs - 8) << 16), - XIVE_SRC_LSI, p, &phb4_lsi_ops); + XIVE_SRC_LSI | irq_flags, p, &phb4_lsi_ops); } else { /* Register all interrupt sources with XIVE */ xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16, From patchwork Wed Aug 4 07:21:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=ENBQuDO2; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gfjw45yd3z9sX5 for ; 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Wed, 4 Aug 2021 07:23:27 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:27 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:28 +0530 Message-Id: <20210804072137.1147875-51-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Qdz5XsOG_FSrkmTgc2Cllk9NKlVob9HP X-Proofpoint-GUID: Qdz5XsOG_FSrkmTgc2Cllk9NKlVob9HP X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxlogscore=791 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 50/59] phb5: Add register inits specific to Gen5 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Update init sequence to take into account Gen5. Define default equlization settings if HDAT is not used. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 18 +++++++++++++----- include/phb4-regs.h | 6 ++++-- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 6700c7fbb..0e98042ce 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5387,8 +5387,12 @@ static void phb4_init_hw(struct phb4 *p) out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1])); out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2])); out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3])); - out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4])); - out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL40, be64_to_cpu(p->lane_eq[4])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL41, be64_to_cpu(p->lane_eq[5])); + if (is_phb5()) { + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL50, be64_to_cpu(p->lane_eq[6])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL51, be64_to_cpu(p->lane_eq[7])); + } } if (!p->lane_eq_en) { /* Read modify write and set to 2 bits */ @@ -5830,7 +5834,7 @@ static __be64 lane_eq_phb5_default[8] = { CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), - CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), + CPU_TO_BE64(0x9999999999999999UL), CPU_TO_BE64(0x9999999999999999UL), }; static void phb4_create(struct dt_node *np) @@ -5842,7 +5846,7 @@ static void phb4_create(struct dt_node *np) struct dt_node *iplp; char *path; uint32_t irq_base, irq_flags; - int i; + int i, eq_reg_count; int chip_id; chip_id = dt_prop_get_u32(np, "ibm,chip-id"); @@ -5942,7 +5946,11 @@ static void phb4_create(struct dt_node *np) /* Check for lane equalization values from HB or HDAT */ p->lane_eq_en = true; p->lane_eq = dt_prop_get_def_size(np, "ibm,lane-eq", NULL, &lane_eq_len); - lane_eq_len_req = 6 * 8; + if (is_phb5()) + eq_reg_count = 8; + else + eq_reg_count = 6; + lane_eq_len_req = eq_reg_count * 8; if (p->lane_eq) { if (lane_eq_len < lane_eq_len_req) { PHBERR(p, "Device-tree has ibm,lane-eq too short: %ld" diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 99633e103..8ab78c377 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -295,8 +295,10 @@ #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 -#define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 -#define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL40 0x1AF0 +#define PHB_PCIE_LANE_EQ_CNTL41 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL50 0x1B00 +#define PHB_PCIE_LANE_EQ_CNTL51 0x1B08 #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 #define PHB_PCIE_PDL_PHY_EQ_CNTL 0x1B38 From patchwork Wed Aug 4 07:21:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:23:33 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma03ams.nl.ibm.com with ESMTP id 3a4x590r5y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Aug 2021 07:23:33 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NUAg47513890 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:30 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 879CEAE04D; Wed, 4 Aug 2021 07:23:30 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 58AD1AE051; Wed, 4 Aug 2021 07:23:29 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:29 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:29 +0530 Message-Id: <20210804072137.1147875-52-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Vp9jnA4vs2hIG_IH95e62M4DJBOZOJ_3 X-Proofpoint-GUID: Vp9jnA4vs2hIG_IH95e62M4DJBOZOJ_3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=877 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 51/59] phb5: Enable Gen5 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Michael Neuling Registers for Gen5 have been initialized in a previous patch. So let's activate it! Signed-off-by: Michael Neuling Signed-off-by: Vasant Hegde --- hw/phb4.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 0e98042ce..9bc8d47ee 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3008,12 +3008,16 @@ static int64_t phb4_poll_link(struct pci_slot *slot) static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) { - unsigned int max_link_speed; + unsigned int max_link_speed, hw_max_link_speed; struct proc_chip *chip; chip = get_chip(p->chip_id); + hw_max_link_speed = 4; + if (is_phb5()) + hw_max_link_speed = 5; + /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */ - max_link_speed = 4; + max_link_speed = hw_max_link_speed; if (p->rev == PHB4_REV_NIMBUS_DD20 && ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) max_link_speed = 3; @@ -3033,8 +3037,8 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) } if (pcie_max_link_speed) max_link_speed = pcie_max_link_speed; - if (max_link_speed > 4) /* clamp to 4 */ - max_link_speed = 4; + if (max_link_speed > hw_max_link_speed) + max_link_speed = hw_max_link_speed; return max_link_speed; } From patchwork Wed Aug 4 07:21:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=e+PPArua; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GfjwH1nBwz9sT6 for ; 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Wed, 4 Aug 2021 07:23:31 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:30 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:30 +0530 Message-Id: <20210804072137.1147875-53-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tuQgZvjICeUlvT2w7jis_amX0ShGoMdQ X-Proofpoint-GUID: tuQgZvjICeUlvT2w7jis_amX0ShGoMdQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=744 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 52/59] phb5: Workaround for PCI bug HW551382 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat The workaround forces a state machine deep in the PHB to start from scratch and to block its evolution until after the link has been reset. It applies on all paths where the link can go down unexpectedly, though it's probably useless on the creset path, since we're going to deep-reset the PHB anyway. But it doesn't hurt and it keeps the set/unset path symmetrical. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 35 +++++++++++++++++++++++++++++++++++ include/phb4-regs.h | 2 +- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 9bc8d47ee..e30339fab 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3072,6 +3072,18 @@ static void phb4_assert_perst(struct pci_slot *slot, bool assert) phb4_pcicfg_write16(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, linkctl); } +static void set_sys_disable_detect(struct phb4 *p, bool set) +{ + uint64_t val; + + val = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL); + if (set) + val |= PHB_PCIE_DLP_SYS_DISABLEDETECT; + else + val &= ~PHB_PCIE_DLP_SYS_DISABLEDETECT; + out_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL, val); +} + static int64_t phb4_hreset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -3088,6 +3100,12 @@ static int64_t phb4_hreset(struct pci_slot *slot) return OPAL_SUCCESS; } + /* circumvention for HW551382 */ + if (is_phb5()) { + PHBINF(p, "HRESET: Workaround for HW551382\n"); + set_sys_disable_detect(p, true); + } + PHBDBG(p, "HRESET: Prepare for link down\n"); phb4_prepare_link_change(slot, false); /* fall through */ @@ -3120,6 +3138,8 @@ static int64_t phb4_hreset(struct pci_slot *slot) pci_slot_set_state(slot, PHB4_SLOT_HRESET_DELAY2); return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB4_SLOT_HRESET_DELAY2: + if (is_phb5()) + set_sys_disable_detect(p, false); pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot); default: @@ -3146,6 +3166,12 @@ static int64_t phb4_freset(struct pci_slot *slot) phb4_prepare_link_change(slot, false); if (!p->skip_perst) { + /* circumvention for HW551382 */ + if (is_phb5()) { + PHBINF(p, "FRESET: Workaround for HW551382\n"); + set_sys_disable_detect(p, true); + } + PHBDBG(p, "FRESET: Assert\n"); phb4_assert_perst(slot, true); pci_slot_set_state(slot, PHB4_SLOT_FRESET_ASSERT_DELAY); @@ -3169,6 +3195,9 @@ static int64_t phb4_freset(struct pci_slot *slot) if (pci_tracing) phb4_link_trace(p, PHB_PCIE_DLP_LTSSM_L0, 3000); + if (is_phb5()) + set_sys_disable_detect(p, false); + pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot); default: @@ -3398,6 +3427,12 @@ static int64_t phb4_creset(struct pci_slot *slot) p->creset_start_time = mftb(); + /* circumvention for HW551382 */ + if (is_phb5()) { + PHBINF(p, "CRESET: Workaround for HW551382\n"); + set_sys_disable_detect(p, true); + } + phb4_prepare_link_change(slot, false); /* Clear error inject register, preventing recursive errors */ xscom_write(p->chip_id, p->pe_xscom + 0x2, 0x0); diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 8ab78c377..85d2cf2ea 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -275,7 +275,7 @@ #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) - +#define PHB_PCIE_DLP_SYS_DISABLEDETECT PPC_BIT(12) #define PHB_PCIE_DLP_CTL 0x1A78 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) From patchwork Wed Aug 4 07:21:31 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:23:32 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:32 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:31 +0530 Message-Id: <20210804072137.1147875-54-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: HDOZ638P8hvFDfoUP4puKFjAGWK8t_Dk X-Proofpoint-GUID: HDOZ638P8hvFDfoUP4puKFjAGWK8t_Dk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=946 adultscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 53/59] phb4: Cleanup PEC config discovery in CAPI mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Small cleanup when reading the PEC config when setting up CAPI, in preparation for P10. Scom addresses vary between P9 and P10 and we'll be accessing more than one PCI chiplet. No functional change. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 17 +++++++++-------- include/phb4-regs.h | 10 +++++++--- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index e30339fab..8857a8ab5 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -4282,7 +4282,7 @@ static int64_t phb4_get_capp_info(int chip_id, struct phb *phb, static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) { - uint64_t reg; + uint64_t addr, reg; uint32_t offset; uint8_t link_width_x16 = 1; @@ -4293,9 +4293,10 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) /* Check if PEC2 is in x8 or x16 mode. * PEC0 is always in x16 */ - xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, ®); - link_width_x16 = ((reg & XPEC_PCI2_IOVALID_MASK) == - XPEC_PCI2_IOVALID_X16); + addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + link_width_x16 = ((reg & XPEC_P9_PCI_IOVALID_MASK) == + XPEC_P9_PCI_IOVALID_X16); } /* APC Master PowerBus Control Register */ @@ -4515,7 +4516,7 @@ static void phb4_init_capp_errors(struct phb4 *p) static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, uint32_t capp_eng) { - uint64_t reg, start_addr, end_addr, stq_eng, dma_eng; + uint64_t addr, reg, start_addr, end_addr, stq_eng, dma_eng; uint64_t mbt0, mbt1; int i, window_num = -1; @@ -4553,9 +4554,9 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, if (p->index == CAPP1_PHB_INDEX) { /* Check if PEC is in x8 or x16 mode */ - xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, ®); - - if ((reg & XPEC_PCI2_IOVALID_MASK) == XPEC_PCI2_IOVALID_X16) { + addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + if ((reg & XPEC_P9_PCI_IOVALID_MASK) == XPEC_P9_PCI_IOVALID_X16) { /* PBCQ is operating as a x16 stack * - The maximum number of engines give to CAPP will be * 14 and will be assigned in the order of STQ 15 to 2. diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 85d2cf2ea..b4a94c056 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -385,9 +385,13 @@ /* PCI Chiplet Config Register */ -#define XPEC_PCI2_CPLT_CONF1 0x000000000F000009ULL -#define XPEC_PCI2_IOVALID_MASK PPC_BITMASK(4, 6) -#define XPEC_PCI2_IOVALID_X16 PPC_BIT(4) +#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL +#define XPEC_P9_PCI_CPLT_CONF1 0x000000000D000009ULL +#define XPEC_P9_PCI_IOVALID_MASK PPC_BITMASK(4, 6) +#define XPEC_P9_PCI_IOVALID_X16 PPC_BIT(4) +#define XPEC_P9_PCI_LANE_CFG PPC_BITMASK(10, 11) +#define XPEC_P10_PCI_CPLT_CONF1 0x0000000008000009ULL +#define XPEC_P10_PCI_LANE_CFG PPC_BITMASK(0, 1) /* * IODA3 on-chip tables From patchwork Wed Aug 4 07:21:32 2021 Content-Type: text/plain; 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Wed, 4 Aug 2021 07:23:34 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:34 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:32 +0530 Message-Id: <20210804072137.1147875-55-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7C6UtxvzeShPi7ewkEKy84GvXTB7_I1G X-Proofpoint-GUID: 7C6UtxvzeShPi7ewkEKy84GvXTB7_I1G X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 54/59] phb4/5: Fix PHB link width detection to avoid useless retrainings X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat On P9 and P10, the PCI express controller (PEC) controls a set of 16 lanes, which can be grouped to form link(s) of various width (4, 8 or 16 lanes). A PCI host bridge (PHB) is handling each link. How many PHBs are active in each PEC is configurable per chip and vary between 2 chips in a system. Therefore PHBs have different link width. The link width of the PHB is used to check if the link is trained optimally and can cause link training retries if that's not the case. We were reading the max link width of a PHB from the link capability register of the PCI express capability of the root bridge. But that value is always an overshoot as it needs to accommodate any PEC configuration. It was hard to fault on P9, as a PEC needs to be trifurcated to start noticing a difference and the device-supported width can also mask it. But on P10, it's also noticeable on bifurcated configuration so it's a bit easier to spot. For example, on P10, PHB0 reports a supported width of 16 in its link capability register because that's what is needed in case of no furcation, but if the PEC is bifurcated or trifurcated, only 8 lanes are wired. So we won't be able to train at more than x8. If we believe the PHB is x16-capable, then we'll retrain the link, potentially several times, thinking it's not optimal, which is a waste of time. This patch finds out the real maximum link width of each PHB, which may require to go check the PEC configuration. The logic is the same on P9 and P10 though the hardware implementations differ slightly. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 91 ++++++++++++++++++++++++++++++++++++++++++++------ include/phb4.h | 1 + 2 files changed, 81 insertions(+), 11 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 8857a8ab5..b173e25ca 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2726,18 +2726,14 @@ static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) uint64_t reg; uint32_t id; uint16_t bdfn, lane_errs; - uint8_t trained_speed, phb_speed, dev_speed, target_speed, rx_errs; - uint8_t trained_width, phb_width, dev_width, target_width; + uint8_t trained_speed, dev_speed, target_speed, rx_errs; + uint8_t trained_width, dev_width, target_width; bool optimal_speed, optimal_width, optimal, retry_enabled, rx_err_ok; /* Current trained state */ phb4_get_link_info(slot, &trained_speed, &trained_width); - /* Get PHB capability */ - /* NOTE: phb_speed will account for the software speed limit */ - phb4_get_info(slot->phb, 0, &phb_speed, &phb_width); - /* Get device capability */ bdfn = 0x0100; /* bus=1 dev=0 device=0 */ /* Since this is the first access, we need to wait for CRS */ @@ -2746,9 +2742,9 @@ static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) phb4_get_info(slot->phb, bdfn, &dev_speed, &dev_width); /* Work out if we are optimally trained */ - target_speed = MIN(phb_speed, dev_speed); + target_speed = MIN(p->max_link_speed, dev_speed); optimal_speed = (trained_speed >= target_speed); - target_width = MIN(phb_width, dev_width); + target_width = MIN(p->max_link_width, dev_width); optimal_width = (trained_width >= target_width); optimal = optimal_width && optimal_speed; retry_enabled = (phb4_chip_retry_workaround() && @@ -2764,9 +2760,11 @@ static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) DEVICE(id), optimal ? "Optimal" : "Degraded", retry_enabled ? "enabled" : "disabled"); PHBDBG(p, "LINK: Speed Train:GEN%i PHB:GEN%i DEV:GEN%i%s\n", - trained_speed, phb_speed, dev_speed, optimal_speed ? "" : " *"); + trained_speed, p->max_link_speed, dev_speed, + optimal_speed ? "" : " *"); PHBDBG(p, "LINK: Width Train:x%02i PHB:x%02i DEV:x%02i%s\n", - trained_width, phb_width, dev_width, optimal_width ? "" : " *"); + trained_width, p->max_link_width, dev_width, + optimal_width ? "" : " *"); PHBDBG(p, "LINK: RX Errors Now:%i Max:%i Lane:0x%04x%s\n", rx_errs, rx_err_max, lane_errs, rx_err_ok ? "" : " *"); @@ -3043,6 +3041,75 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) return max_link_speed; } +static unsigned int __phb4_get_max_link_width(struct phb4 *p) +{ + uint64_t addr, reg; + unsigned int lane_config, width = 16; + + /* + * On P9, only PEC2 is configurable (no-/bi-/tri-furcation) + */ + switch (p->pec) { + case 0: + width = 16; + break; + case 1: + width = 8; + break; + case 2: + addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + lane_config = GETFIELD(XPEC_P9_PCI_LANE_CFG, reg); + + if (lane_config == 0b10 && p->index >= 4) + width = 4; + else + width = 8; + } + return width; +} + +static unsigned int __phb5_get_max_link_width(struct phb4 *p) +{ + uint64_t addr, reg; + unsigned int lane_config, width = 16; + + /* + * On P10, the 2 PECs are identical and each can have a + * different furcation, so we always need to check the PEC + * config + */ + addr = XPEC_P10_PCI_CPLT_CONF1 + p->pec * XPEC_PCI_CPLT_OFFSET; + xscom_read(p->chip_id, addr, ®); + lane_config = GETFIELD(XPEC_P10_PCI_LANE_CFG, reg); + + switch (lane_config) { + case 0b00: + width = 16; + break; + case 0b01: + width = 8; + break; + case 0b10: + if (p->index == 0 || p->index == 3) + width = 8; + else + width = 4; + break; + default: + PHBERR(p, "Unexpected PEC lane config value %#x\n", + lane_config); + } + return width; +} + +static unsigned int phb4_get_max_link_width(struct phb4 *p) +{ + if (is_phb5()) + return __phb5_get_max_link_width(p); + else + return __phb4_get_max_link_width(p); +} static void phb4_assert_perst(struct pci_slot *slot, bool assert) { @@ -5981,7 +6048,9 @@ static void phb4_create(struct dt_node *np) goto failed; p->max_link_speed = phb4_get_max_link_speed(p, np); - PHBINF(p, "Max link speed: GEN%i\n", p->max_link_speed); + p->max_link_width = phb4_get_max_link_width(p); + PHBINF(p, "Max link speed: GEN%i, max link width %i\n", + p->max_link_speed, p->max_link_width); /* Check for lane equalization values from HB or HDAT */ p->lane_eq_en = true; diff --git a/include/phb4.h b/include/phb4.h index 0bbfc926c..4f1fb31c5 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -197,6 +197,7 @@ struct phb4 { bool lane_eq_en; unsigned int max_link_speed; unsigned int dt_max_link_speed; + unsigned int max_link_width; uint64_t mrt_size; uint64_t mbt_size; From patchwork Wed Aug 4 07:21:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Igmjde4F; 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Wed, 4 Aug 2021 07:23:35 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:35 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:33 +0530 Message-Id: <20210804072137.1147875-56-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: lPSoMGBr71iXn9__zxDvdtCNFW_VEnjF X-Proofpoint-GUID: lPSoMGBr71iXn9__zxDvdtCNFW_VEnjF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxlogscore=841 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 55/59] phb5: Fix PHB max link speed definition on P10 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Not all PHBs are capable of GEN5 speed on P10. In all PEC configurations, the first PHB is the only one which can handle GEN5. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index b173e25ca..79083d4a1 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3011,10 +3011,10 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) chip = get_chip(p->chip_id); hw_max_link_speed = 4; - if (is_phb5()) + if (is_phb5() && (p->index == 0 || p->index == 3)) hw_max_link_speed = 5; - /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */ + /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> hw default */ max_link_speed = hw_max_link_speed; if (p->rev == PHB4_REV_NIMBUS_DD20 && ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) From patchwork Wed Aug 4 07:21:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 4 Aug 2021 07:23:37 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:34 +0530 Message-Id: <20210804072137.1147875-57-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: d_L5ffHWMMSnyQZ0o8Y4cLLjgGAOoPKW X-Proofpoint-GUID: d_L5ffHWMMSnyQZ0o8Y4cLLjgGAOoPKW X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 56/59] libpore: P10 stop-api support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm , Pratik Rajesh Sampat Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Pratik Rajesh Sampat Update libpore with P10 STOP API. Add minor changes to make P9 stop-api and P10 stop-api to co-exist in OPAL. These calls are required for STOP11 support on P10. STIOP0,2,3 on P10 does not lose full core state or scoms. stop-api based restore of SPRs or xscoms required only for STOP11 on P10. STOP11 on P10 will be a limited lab test/stress feature and not a product feature. (Same case as P9) Co-authored-by: Pratik Rajesh Sampat Signed-off-by: Pratik Rajesh Sampat Co-authored-by: Vaidyanathan Srinivasan Signed-off-by: Vaidyanathan Srinivasan Co-authored-by: Ryan Grimm Signed-off-by: Ryan Grimm Signed-off-by: Vasant Hegde --- core/direct-controls.c | 31 +- hw/slw.c | 86 +- include/p10_stop_api.H | 239 +++ libpore/Makefile.inc | 2 +- libpore/p10_cpu_reg_restore_instruction.H | 88 + libpore/p10_hcd_header_defs.H | 152 ++ libpore/p10_hcd_memmap_base.H | 463 ++++++ libpore/p10_hcd_memmap_homer.H | 94 ++ libpore/p10_hcd_memmap_occ_sram.H | 174 ++ libpore/p10_hcode_image_defines.H | 462 ++++++ libpore/p10_stop_api.C | 1816 +++++++++++++++++++++ libpore/p10_stop_api.H | 238 +++ libpore/p10_stop_data_struct.H | 162 ++ libpore/p10_stop_util.C | 190 +++ libpore/p10_stop_util.H | 123 ++ 15 files changed, 4311 insertions(+), 9 deletions(-) create mode 100644 include/p10_stop_api.H create mode 100644 libpore/p10_cpu_reg_restore_instruction.H create mode 100644 libpore/p10_hcd_header_defs.H create mode 100644 libpore/p10_hcd_memmap_base.H create mode 100644 libpore/p10_hcd_memmap_homer.H create mode 100644 libpore/p10_hcd_memmap_occ_sram.H create mode 100644 libpore/p10_hcode_image_defines.H create mode 100644 libpore/p10_stop_api.C create mode 100644 libpore/p10_stop_api.H create mode 100644 libpore/p10_stop_data_struct.H create mode 100644 libpore/p10_stop_util.C create mode 100644 libpore/p10_stop_util.H diff --git a/core/direct-controls.c b/core/direct-controls.c index f7509dde0..37bcf9826 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -602,14 +602,37 @@ static int p10_core_set_special_wakeup(struct cpu_thread *cpu) * CORE_GATED will be unset on a successful special * wakeup of the core which indicates that the core is * out of stop state. If CORE_GATED is still set then - * raise error. + * check SPWU register and raise error only if SPWU_DONE + * is not set, else print a warning and consider SPWU + * operation as successful. + * This is in conjunction with a micocode bug, which + * calls out the fact that SPW can succeed in the case + * the core is gated but SPWU_HYP bit is set. */ if (p10_core_is_gated(cpu)) { + if(xscom_read(chip_id, spwu_addr, &val)) { + prlog(PR_ERR, "Core %u:%u:" + " unable to read QME_SPWU_HYP\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + if (val & P10_SPWU_DONE) { + /* + * If SPWU DONE bit is set then + * SPWU operation is complete + */ + prlog(PR_DEBUG, "Special wakeup on " + "%u:%u: core remains gated while" + " SPWU_HYP DONE set\n", + chip_id, core_id); + return 0; + } /* Deassert spwu for this strange error */ xscom_write(chip_id, spwu_addr, 0); - prlog(PR_ERR, "Failed special wakeup on %u:%u" - " core remains gated.\n", - chip_id, core_id); + prlog(PR_ERR, + "Failed special wakeup on %u:%u" + " core remains gated.\n", + chip_id, core_id); return OPAL_HARDWARE; } else { return 0; diff --git a/hw/slw.c b/hw/slw.c index 9e676af74..56ba05b0a 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -24,7 +25,7 @@ #include #include -#include +#include #include #include @@ -220,6 +221,30 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) return true; } +static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read P10_QME_SPWU_HYP\n"); + return false; + } + if (tmp & P10_SPWU_REQ) + prlog(PR_WARNING, + "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", + core, tmp); + + return true; +} + + static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) { uint64_t tmp; @@ -872,6 +897,31 @@ static void slw_late_init_p9(struct proc_chip *chip) } } +static void slw_late_init_p10(struct proc_chip *chip) +{ + struct cpu_thread *c; + int rc; + + prlog(PR_INFO, "SLW: Configuring self-restore for HRMOR\n"); + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + /* + * Clear HRMOR. Need to update only for thread + * 0 of each core. Doing it anyway for all threads + */ + rc = proc_stop_save_cpureg((void *)chip->homer_base, + PROC_STOP_SPR_HRMOR, 0, + c->pir); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", + c->pir, rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + } + } +} + /* Add device tree properties to describe idle states */ void add_cpu_idle_state_properties(void) { @@ -971,7 +1021,7 @@ void add_cpu_idle_state_properties(void) xive_late_init(); nx_p9_rng_late_init(); } else if (chip->type == PROC_CHIP_P10) { - /* TODO (p10): need P10 stop state engine */ + slw_late_init_p10(chip); xive2_late_init(); } } @@ -1380,6 +1430,20 @@ static void slw_init_chip_p9(struct proc_chip *chip) } +static void slw_init_chip_p10(struct proc_chip *chip) +{ + struct cpu_thread *c; + + prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); + + /* At power ON setup inits for power-mgt */ + for_each_available_core_in_chip(c, chip->id) + slw_set_overrides_p10(chip, c); + + +} + + static bool slw_image_check_p9(struct proc_chip *chip) { @@ -1575,8 +1639,13 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) wakeup_engine_state,chip->id); return OPAL_INTERNAL_ERROR; } - rc = p9_stop_save_cpureg((void *)chip->homer_base, + if (proc_gen == proc_gen_p9) { + rc = p9_stop_save_cpureg((void *)chip->homer_base, + sprn, val, cpu_pir); + } else { + rc = proc_stop_save_cpureg((void *)chip->homer_base, sprn, val, cpu_pir); + } } else if (proc_gen == proc_gen_p8) { int spr_is_supported = 0; @@ -1640,7 +1709,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); - } else if (proc_gen >= proc_gen_p9) { + } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); if(slw_image_check_p9(chip)) @@ -1648,6 +1717,15 @@ void slw_init(void) if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) slw_late_init_p9(chip); } + } else if (proc_gen == proc_gen_p10) { + for_each_chip(chip) { + slw_init_chip_p10(chip); + if(slw_image_check_p9(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { + slw_late_init_p10(chip); + } + } } add_cpu_idle_state_properties(); } diff --git a/include/p10_stop_api.H b/include/p10_stop_api.H new file mode 100644 index 000000000..2bcf03a45 --- /dev/null +++ b/include/p10_stop_api.H @@ -0,0 +1,239 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/utils/stopreg/p10_stop_api.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2021 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __P10_STOP_IMAGE_API_ +#define __P10_STOP_IMAGE_API_ + +#include + +#ifdef __SKIBOOT__ + #include + #include +#endif + +/// +/// @file p10_stop_api.H +/// @brief describes STOP API which create/manipulate STOP image. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP + +#ifdef __cplusplus +namespace stopImageSection +{ +#endif + +/** + * @brief all SPRs and MSR for which register restore is to be supported. + * @note STOP API design has built in support to accomodate 8 register of + * scope core and thread each. + */ +typedef enum +{ + PROC_STOP_SPR_DAWR = 180, // thread register + PROC_STOP_SPR_CIABR = 187, // thread register + PROC_STOP_SPR_DAWRX = 188, // thread register + PROC_STOP_SPR_HSPRG0 = 304, // thread register + PROC_STOP_SPR_HRMOR = 313, // core register + PROC_STOP_SPR_LPCR = 318, // thread register + PROC_STOP_SPR_HMEER = 337, // core register + PROC_STOP_SPR_PTCR = 464, // core register + PROC_STOP_SPR_USPRG0 = 496, // thread register + PROC_STOP_SPR_USPRG1 = 497, // thread register + PROC_STOP_SPR_URMOR = 505, // core register + PROC_STOP_SPR_SMFCTRL = 511, // thread register + PROC_STOP_SPR_LDBAR = 850, // thread register + PROC_STOP_SPR_PSSCR = 855, // thread register + PROC_STOP_SPR_PMCR = 884, // core register + PROC_STOP_SPR_HID = 1008, // core register + PROC_STOP_SPR_MSR = 2000, // thread register + +} CpuReg_p10_t; + +// /** +// * @brief lists all the bad error codes. +// */ +// typedef enum +// { +// STOP_SAVE_SUCCESS = 0, +// STOP_SAVE_ARG_INVALID_IMG = 1, +// STOP_SAVE_ARG_INVALID_REG = 2, +// STOP_SAVE_ARG_INVALID_THREAD = 3, +// STOP_SAVE_ARG_INVALID_MODE = 4, +// STOP_SAVE_ARG_INVALID_CORE = 5, +// STOP_SAVE_SPR_ENTRY_NOT_FOUND = 6, +// STOP_SAVE_SPR_ENTRY_UPDATE_FAILED = 7, +// STOP_SAVE_SCOM_INVALID_OPERATION = 8, +// STOP_SAVE_SCOM_INVALID_SECTION = 9, +// STOP_SAVE_SCOM_INVALID_ADDRESS = 10, +// STOP_SAVE_SCOM_INVALID_CHIPLET = 11, +// STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED = 12, +// STOP_SAVE_INVALID_FUSED_CORE_STATUS = 13, +// STOP_SAVE_FAIL = 14, // for internal failure within firmware. +// STOP_SAVE_SPR_ENTRY_MISSING = 15, +// STOP_SAVE_MAX_ENTRY_REACHED = 16, +// STOP_SAVE_SPR_BIT_POS_RESERVE = 17, +// } StopReturnCode_t; + +/** + * @brief summarizes all operations supported on scom entries of STOP image. + */ +typedef enum +{ + //enum members which are project agnostic + PROC_STOP_SCOM_OP_MIN = 0, + PROC_STOP_SCOM_APPEND = 1, + PROC_STOP_SCOM_REPLACE = 2, + PROC_STOP_SCOM_OR = 3, + PROC_STOP_SCOM_AND = 4, + PROC_STOP_SCOM_NOOP = 5, + PROC_STOP_SCOM_RESET = 6, + PROC_STOP_SCOM_OR_APPEND = 7, + PROC_STOP_SCOM_AND_APPEND = 8, + PROC_STOP_SCOM_OP_MAX = 9, + +} StopReturnCode_p10_t; + +/** + * @brief All subsections that contain scom entries in a STOP image. + */ +typedef enum +{ + PROC_STOP_SECTION_CORE = 1, + PROC_STOP_SECTION_L2 = 1, + PROC_STOP_SECTION_L3 = 2, + PROC_STOP_SECTION_CACHE = 2, +} ScomSection_p10_t; + +/** + * @brief versions pertaining relvant to STOP API. + */ +typedef enum +{ + STOP_API_VER = 0x00, + STOP_API_VER_CONTROL = 0x02, +} VersionList_t; + +/** + * @brief Summarizes bit position allocated to SPRs in save bit mask vector. + */ +typedef enum +{ + BIT_POS_CIABR = 0, + BIT_POS_DAWR = 1, + BIT_POS_DAWRX = 2, + BIT_POS_HSPRG0 = 3, + BIT_POS_LDBAR = 4, + BIT_POS_LPCR = 5, + BIT_POS_PSSCR = 6, + BIT_POS_MSR = 7, + BIT_POS_HID = 21, + BIT_POS_HMEER = 22, + BIT_POS_PMCR = 23, + BIT_POS_PTCR = 24, + BIT_POS_SMFCTRL = 28, + BIT_POS_USPRG0 = 29, + BIT_POS_USPRG1 = 30, +} SprBitPositionList_t; + + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @brief creates SCOM restore entry for a given scom adress in HOMER. + * @param i_pImage points to start address of HOMER image. + * @param i_scomAddress address associated with SCOM restore entry. + * @param i_scomData data associated with SCOM restore entry. + * @param i_operation operation type requested for API. + * @param i_section section of HOMER in which restore entry needs to be created. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for creating SCOM restore entry in HOMER. It is agnostic to + * generation of POWER processor. + */ + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const StopReturnCode_p10_t i_operation, + const ScomSection_p10_t i_section ); + +/** + * @brief initializes self save restore region of HOMER. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_corePos position of the physical core. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for initializing self restore region in HOMER. It is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ); + +/** + * @brief enables self save for a given set of SPRs + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ); + +/** + * @brief creates an SPR restore entry in HOMER + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_regId SPR number to be saved in HOMER + * @param[in] i_regData SPR data to be saved in HOMER + * @param[in] i_pir PIR value associated with core and thread. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_p10_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ); + +/** + * @brief initializes self-save region with specific instruction. + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_corePos physical core's relative position within processor chip. + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, + * error code otherwise. + * @note API is project agnostic and is intended only for use case of HOMER build. + * There is no explicit effort to support any other use case. + */ +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); + +#ifdef __cplusplus +} // extern "C" +}; // namespace stopImageSection ends +#endif //__cplusplus + +#endif //__P10_STOP_IMAGE_API_ diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc index 1060a0492..06d9c8902 100644 --- a/libpore/Makefile.inc +++ b/libpore/Makefile.inc @@ -1,4 +1,4 @@ -LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C +LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o) LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o) diff --git a/libpore/p10_cpu_reg_restore_instruction.H b/libpore/p10_cpu_reg_restore_instruction.H new file mode 100644 index 000000000..4da194d1e --- /dev/null +++ b/libpore/p10_cpu_reg_restore_instruction.H @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/utils/stopreg/p10_cpu_reg_restore_instruction.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p10_cpu_reg_restore_instruction.H +/// @brief enumerates all the opcodes used for SPR restoration. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP + +#ifndef __REG_RESTORE_INSTRUCTION_H +#define __REG_RESTORE_INSTRUCTION_H + +#include + +#ifdef __cplusplus +extern "C" { + +namespace stopImageSection +{ +#endif + +/** + * @brief enumerates opcodes for few instructions. + */ +enum +{ + ORI_OPCODE = 24, + RFI_OPCODE = 19, + RFI_CONST = 50, + MFMSR_CONST = 83, + ORIS_OPCODE = 25, + OPCODE_31 = 31, + XOR_CONST = 316, + RLDICR_OPCODE = 30, + RLDICR_CONST = 1, + MTSPR_CONST1 = 467, + MTMSRD_CONST1 = 178, + MR_R0_TO_R10 = 0x7c0a0378, //mr r10, r0 + MR_R0_TO_R21 = 0x7c150378, //mr r21, r0 + MR_R0_TO_R9 = 0x7c090378, //mr r9, r0 + URMOR_CORRECTION = 0x7d397ba6, + MFSPR_CONST = 339, + BLR_INST = 0x4e800020, + MTSPR_BASE_OPCODE = 0x7c0003a6, + MFSPR_BASE_OPCODE = 0x7c0002a6, + ATTN_OPCODE = 0x00000200, + OPCODE_18 = 18, + SELF_SAVE_FUNC_ADD = 0x2300, + SELF_SAVE_OFFSET = 0x180, + SKIP_SPR_REST_INST = 0x4800001c, //b . +0x01c + MFLR_R30 = 0x7fc802a6, + SKIP_SPR_SELF_SAVE = 0x3bff0020, //addi r31 r31, 0x20 + MTLR_INST = 0x7fc803a6 //mtlr r30 +}; + +#ifdef __cplusplus +} // namespace stopImageSection ends + +} // extern "C" +#endif //__cplusplus + +#endif //__REG_RESTORE_INSTRUCTION_H diff --git a/libpore/p10_hcd_header_defs.H b/libpore/p10_hcd_header_defs.H new file mode 100644 index 000000000..d02a72524 --- /dev/null +++ b/libpore/p10_hcd_header_defs.H @@ -0,0 +1,152 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_hcd_header_defs.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p10_hcd_header_defs.H +/// @brief defines header constants based on file types +/// +/// This header contains those cpp manifest constants required for processing +/// the linker scripts used to generate OCC code images. As these are used +/// by linker scripts as well as by C++ code, these cannot be solely be put +/// into a namespace. Prefixing these with the region name is the attempt +/// to make these globally unique when this header is included in C++ code. +/// +// *HWP HWP Owner: David Du +// *HWP Backup HWP Owner: Greg Still +// *HWP FW Owner: Prem Jha +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM +// + +#ifndef __HCD_HEADER_DEFS_H__ +#define __HCD_HEADER_DEFS_H__ + +/// Macros for generating an Hcode header section +/// +/// The CPP macros HCD_HDR_UINTxx generate equivalent code depending on +/// whether they are being called from assembler (where they actually +/// create the header section data) or from C (where they specifiy a +/// C-structure form of the contents of the header section. +/// +/// In assembler each invocation also creates space in the header section + +#ifdef __ASSEMBLER__ + +// *INDENT-OFF* + .macro hcd_header_uint64, symbol:req, value = 0 + .global \symbol +\symbol\(): + .quad (\value) + .endm + + .macro hcd_header_uint32, symbol:req, value = 0 + .global \symbol + \symbol\(): + .long (\value) + .endm + + .macro hcd_header_uint16, symbol:req, value = 0 + .global \symbol +\symbol\(): + .short (\value) + .endm + + .macro hcd_header_uint8, symbol:req, value = 0 + .global \symbol +\symbol\(): + .byte (\value) + .endm + + .macro hcd_header_uint8_vec, symbol:req, number:req, value = 0 + .global \symbol +\symbol\(): + .rept (\number) + .byte (\value) + .endr + .endm + + .macro hcd_header_attn, symbol:req, number = 1 + .global \symbol +\symbol\(): + .rept (\number) + .long 0x00000200 + .endr + .endm + + .macro hcd_header_attn_pad, align:req + .balignl (\align), 0x00000200 + .endm + + .macro hcd_header_pad, align:req + .balignl (\align), 0 + .endm +// *INDENT-ON* + +#define ULL(x) x +#define HCD_CONST(name, expr) .set name, expr; +#define HCD_CONST64(name, expr) .set name, expr; + +#define HCD_HDR_UINT64(symbol, value) hcd_header_uint64 symbol value +#define HCD_HDR_UINT32(symbol, value) hcd_header_uint32 symbol value +#define HCD_HDR_UINT16(symbol, value) hcd_header_uint16 symbol value +#define HCD_HDR_UINT8(symbol, value) hcd_header_uint8 symbol value +#define HCD_HDR_UINT8_VEC(symbol, number, value) hcd_header_uint8_vec symbol number value +#define HCD_HDR_ATTN(symbol, number) hcd_header_attn symbol number +#define HCD_HDR_ATTN_PAD(align) hcd_header_attn_pad align +#define HCD_HDR_PAD(align) hcd_header_pad align + +#else // NOT __ASSEMBLER__ + +#ifdef __LINKERSCRIPT__ + + #define ULL(x) x + #define POUND_DEFINE #define + #define HCD_CONST(name, expr) POUND_DEFINE name expr + #define HCD_CONST64(name, expr) POUND_DEFINE name expr + +#else + + #define ULL(x) x##ull + #define HCD_CONST(name, expr) enum { name = expr }; + #define HCD_CONST64(name, expr) enum { name = expr }; + + #define HCD_HDR_UINT64(symbol, value) uint64_t symbol + #define HCD_HDR_UINT32(symbol, value) uint32_t symbol + #define HCD_HDR_UINT16(symbol, value) uint16_t symbol + #define HCD_HDR_UINT8(symbol, value) uint8_t symbol + #define HCD_HDR_UINT8_VEC(symbol, number, value) uint8_t symbol[number] + #define HCD_HDR_ATTN(symbol, number) uint32_t symbol[number] + #define HCD_HDR_ATTN_PAD(align) + #define HCD_HDR_PAD(align) + +#endif // __LINKERSCRIPT__ +#endif // __ASSEMBLER__ + +// Stringification + +#define STR_HELPER(x) #x +#define STR(x) STR_HELPER(x) + +#endif // __HCD_HEADER_DEFS_H__ diff --git a/libpore/p10_hcd_memmap_base.H b/libpore/p10_hcd_memmap_base.H new file mode 100644 index 000000000..4dac9c93b --- /dev/null +++ b/libpore/p10_hcd_memmap_base.H @@ -0,0 +1,463 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_hcd_memmap_base.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p10_hcd_memmap_base.H +/// @brief defines region constants shared by different memory components. +/// + +// *HWP HWP Owner: David Du +// *HWP Backup HWP Owner: Greg Still +// *HWP FW Owner: Prem S Jha +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __HCD_MEMMAP_BASE_H__ +#define __HCD_MEMMAP_BASE_H__ + +#include + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// Image Magic Numbers + +HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)) // CPMR_1.0 +HCD_CONST64(QME_MAGIC_NUMBER , ULL(0x514d455f5f312e30)) // QME__1.0 + +HCD_CONST64(XPMR_MAGIC_NUMBER, ULL(0x58504d525f312e30)) // XPMR_1.0 +HCD_CONST64(XGPE_MAGIC_NUMBER, ULL(0x584750455f312e30)) // XGPE_1.0 + +HCD_CONST64(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)) // PPMR_1.0 +HCD_CONST64(PGPE_MAGIC_NUMBER, ULL(0x504750455F312E30)) // PGPE_1.0 + +HCD_CONST(QME_BUILD_VERSION, 0x001) // QME__1.0 +HCD_CONST(XGPE_BUILD_VERSION, 0x001) // XGPE_1.0 +HCD_CONST(PGPE_BUILD_VERSION, 0x001) // PGPE_1.0 + + +HCD_CONST(CPMR_REGION_CHECK_WORD, (0x43504d52)) // CPMR +HCD_CONST(SCOM_REST_MAGIC_WORD, (0x5343))//SC +HCD_CONST(CPMR_BUILD_VER, 1) + + +/// Size constants + +HCD_CONST(HALF_KB, 512) +HCD_CONST(ONE_KB, 1024) +HCD_CONST(HALF_MB, (1024 * 512)) +HCD_CONST(ONE_MB, (1024 * 1024)) +HCD_CONST(TWO_MB, (2 * 1024 * 1024)) + +/// Memory constants + +HCD_CONST(QME_SRAM_SIZE, (64 * ONE_KB)) + +HCD_CONST(HOMER_MEMORY_SIZE, (4 * ONE_MB)) +HCD_CONST(HOMER_OPMR_REGION_NUM, 0) +HCD_CONST(HOMER_XPMR_REGION_NUM, 1) +HCD_CONST(HOMER_CPMR_REGION_NUM, 2) +HCD_CONST(HOMER_PPMR_REGION_NUM, 3) + +/// Chip constants +HCD_CONST(OCC_HOST_AREA_SIZE, ONE_MB) + +HCD_CONST(MAX_THREADS_PER_CORE, 4) +HCD_CONST(MAX_CORES_PER_CHIP, 32) + +HCD_CONST(MAX_QMES_PER_CHIP, 8) +HCD_CONST(MAX_EXES_PER_CHIP, 16) + +HCD_CONST(MAX_QUADS_PER_CHIP, 8) +HCD_CONST(MAX_CACHES_PER_CHIP, 32) + +HCD_CONST(MAX_CORES_PER_QME, 4) +HCD_CONST(MAX_CORES_PER_EX, 2) + +HCD_CONST(MAX_QMES_PER_QUAD, 1) +HCD_CONST(MAX_EXES_PER_QUAD, 2) +HCD_CONST(MAX_CORES_PER_QUAD, 4) +HCD_CONST(MAX_L3_PER_QUAD, 4) + +HCD_CONST(MAX_QUAD_ID_SUPPORTED, 7) +HCD_CONST(MAX_CORE_ID_SUPPORTED, 31) +HCD_CONST(MAX_THREAD_ID_SUPPORTED, 3) + +/// Image build constants + +HCD_CONST(HARDWARE_IMG_SIZE, ONE_MB) + +HCD_CONST(FUSED_CORE_MODE, 0xBB) +HCD_CONST(NONFUSED_CORE_MODE, 0xAA) + +HCD_CONST(SELF_RESTORE_BLR_INST, 0x4e800020) +HCD_CONST(CORE_RESTORE_PAD_OPCODE, 0x00000200) //ATTN Opcode + +HCD_CONST(SCOM_RESTORE_PAD_OPCODE, 0x00000000) //zero pads +HCD_CONST(SCOM_RESTORE_ENTRY_SIZE, 12) //4B address,8B data + +HCD_CONST(QME_BLOCK_READ_LEN, 32) +HCD_CONST(QME_BLK_SIZE_SHIFT, 0x05) + +HCD_CONST(RING_ALIGN_BOUNDARY, 0x08) +HCD_CONST64(DARN_BAR_EN_POS, ULL(0x8000000000000000)) + +//FFDC Region +HCD_CONST(FFDC_REGION_XPMR_BASE_OFFSET, 0xE0000) //Offset wrt to XPMR base +HCD_CONST(FFDC_REGION_SIZE, (80 * ONE_KB)) +//end offset of FFDC region wrt to XPMR base +HCD_CONST(FFDC_REGION_XPMR_END_OFFSET, (FFDC_REGION_XPMR_BASE_OFFSET + + FFDC_REGION_SIZE )) +//--------------------------------------------------------------------------------------- + +//XPMR Header +HCD_CONST(XGPE_BUILD_VER, 1) +HCD_CONST(XPMR_BUILD_VER, 1) +HCD_CONST(XPMR_HEADER_SIZE, 512) +HCD_CONST(XGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(XGPE_HEADER_IMAGE_OFFSET, XGPE_INT_VECTOR_SIZE) +HCD_CONST(XGPE_BOOT_COPIER_OFFSET, 512) +HCD_CONST(XGPE_BOOT_COPIER_LENGTH, ONE_KB) +HCD_CONST(XGPE_BOOT_LOADER_OFFSET, + XGPE_BOOT_COPIER_OFFSET + XGPE_BOOT_COPIER_LENGTH ) +HCD_CONST(XGPE_BOOT_LOADER_LENGTH, ONE_KB) +HCD_CONST(XGPE_HCODE_OFFSET, + XGPE_BOOT_LOADER_OFFSET + XGPE_BOOT_LOADER_LENGTH ) +HCD_CONST(XGPE_SRAM_SIZE, (64 * ONE_KB)) +HCD_CONST(XGPE_HCODE_SIZE, (64 * ONE_KB)) +HCD_CONST(XPMR_BOOT_REGION, (XPMR_HEADER_SIZE + XGPE_BOOT_COPIER_LENGTH + + XGPE_BOOT_LOADER_LENGTH )) + +HCD_CONST(XGPE_HCODE_RESET_ADDR_VAL, 0x40) +HCD_CONST(XGPE_DBG_PTR_AREA_SIZE, 64) + +HCD_CONST(XPMR_MAGIC_WORD_BYTE, 0x00) +HCD_CONST(XPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(XPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(XPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(XPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(XPMR_BUILD_VER_BYTE, 0x1c) +HCD_CONST(XPMR_XGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(XPMR_XGPE_HCODE_LENGTH_BYTE, 0x2c) +HCD_CONST(XPMR_XGPE_BOOT_PROG_CODE_BYTE, 0x30) +HCD_CONST(XPMR_XGPE_SRAM_IMAGE_SIZE_BYTE, 0x34) +HCD_CONST(XGPE_IMAGE_XPMR_OFFSET, + (XGPE_BOOT_LOADER_OFFSET + XGPE_BOOT_LOADER_LENGTH)) + +//--------------------------------------------------------------------------------------- + +/// CPMR Header + +HCD_CONST(CPMR_HOMER_OFFSET, (HOMER_CPMR_REGION_NUM* ONE_MB)) +HCD_CONST(CPMR_HEADER_SIZE, 256) + +HCD_CONST(CPMR_ATTN_WORD0_BYTE, 0x00) +HCD_CONST(CPMR_ATTN_WORD1_BYTE, 0x04) +HCD_CONST(CPMR_MAGIC_NUMBER_BYTE, 0x08) +HCD_CONST(CPMR_BUILD_DATE_BYTE, 0x10) +HCD_CONST(CPMR_BUILD_VER_BYTE, 0x14) +HCD_CONST(CPMR_SELF_RESTORE_VER_BYTE, 0x1C) +HCD_CONST(CPMR_STOP_API_VER_BYTE, 0x1D) +HCD_CONST(CPMR_FUSED_CORE_FLAG, 0x1F) +HCD_CONST(CPMR_QME_HCODE_OFFSET_BYTE, 0x20) +HCD_CONST(CPMR_QME_HCODE_LENGTH_BYTE, 0x24) +HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE, 0x28) +HCD_CONST(CPMR_CORE_COMMON_RING_LENGTH_BYTE, 0x2C) +HCD_CONST(CPMR_QME_LOCAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(CPMR_QME_LOCAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_OFFSET_BYTE, 0x38) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_LENGTH_BYTE, 0x3C) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_OFFSET_BYTE, 0x40) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_LENGTH_BYTE, 0x44) +HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE, 0x48) +HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE, 0x4C) +HCD_CONST(CPMR_MAX_CORE_L2_SCOM_ENTRIES, 0x50) +HCD_CONST(CPMR_MAX_QUAD_L3_SCOM_ENTRIES, 0x54) +HCD_CONST(CPMR_MAX_CORE_L2_SCOM_OFFSET, 0x58) +HCD_CONST(CPMR_MAX_CORE_L2_SCOM_LENGTH, 0x5C) +HCD_CONST(CPMR_MAX_QUAD_SCOM_OFFSET, 0x60) +HCD_CONST(CPMR_MAX_QUAD_SCOM_LENGTH, 0x64) + +/// Self Restore without SMF Support + +HCD_CONST(SELF_RESTORE_CPMR_OFFSET, CPMR_HEADER_SIZE) +HCD_CONST(SELF_RESTORE_INT_SIZE, (8 * ONE_KB)) +HCD_CONST(SELF_RESTORE_FFDC_OFFSET, (224 * ONE_KB)) +HCD_CONST(SELF_RESTORE_FFDC_LENGTH, (32 * ONE_KB)) +HCD_CONST(SELF_RESTORE_FFDC_PER_CORE, 864) +HCD_CONST(SELF_RESTORE_FFDC_PER_CORE_IN_HOMER, 1024) +HCD_CONST(SELF_RESTORE_FFDC_PER_QUAD_IN_HOMER, (SELF_RESTORE_FFDC_PER_CORE_IN_HOMER * 4)) +HCD_CONST(SELF_RESTORE_FFDC_BLK_CNT, 27) + +// Self Restore Region With SMF Support +HCD_CONST(SMF_THREAD_LAUNCHER_SIZE, 1024) +HCD_CONST(SMF_SELF_RESTORE_CODE_SIZE, + (SELF_RESTORE_INT_SIZE + SMF_THREAD_LAUNCHER_SIZE)) + +HCD_CONST(SMF_CORE_RESTORE_THREAD_AREA_SIZE, HALF_KB) +HCD_CONST(SMF_SELF_SAVE_THREAD_AREA_SIZE, 256) +HCD_CONST(SMF_CORE_RESTORE_CORE_AREA_SIZE, HALF_KB) +HCD_CONST(SMF_CORE_SAVE_CORE_AREA_SIZE, HALF_KB) + +HCD_CONST(SMF_SELF_RESTORE_CORE_REGS_SIZE, + MAX_CORES_PER_CHIP * ((SMF_CORE_RESTORE_THREAD_AREA_SIZE* MAX_THREADS_PER_CORE ) + + (SMF_SELF_SAVE_THREAD_AREA_SIZE* MAX_THREADS_PER_CORE ) + + SMF_CORE_RESTORE_CORE_AREA_SIZE + + SMF_CORE_SAVE_CORE_AREA_SIZE )) + +HCD_CONST(SMF_SELF_RESTORE_SIZE_TOTAL, + (SMF_SELF_RESTORE_CODE_SIZE + SMF_SELF_RESTORE_CORE_REGS_SIZE)) +/// Core Scom + +HCD_CONST(SELF_SAVE_RESTORE_REGION_SIZE, (256 * ONE_KB)) +HCD_CONST(SCOM_RESTORE_CPMR_OFFSET, (256 * ONE_KB)) +HCD_CONST(SCOM_RESTORE_HOMER_OFFSET, + (SCOM_RESTORE_CPMR_OFFSET + CPMR_HOMER_OFFSET)) + +HCD_CONST(MAX_CORE_SCOM_ENTRIES, 16) +HCD_CONST(MAX_L2_SCOM_ENTRIES, 32) +HCD_CONST(MAX_L3_SCOM_ENTRIES, 64) +HCD_CONST(MAX_EQ_SCOM_ENTRIES, 16) +HCD_CONST(MAX_SCOM_RESTORE_ENTRIES_PER_CORE, (MAX_CORE_SCOM_ENTRIES + + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES + + MAX_EQ_SCOM_ENTRIES)) + + +HCD_CONST(SCOM_RESTORE_SIZE_PER_CORE, + (SCOM_RESTORE_ENTRY_SIZE* MAX_SCOM_RESTORE_ENTRIES_PER_CORE)) // 128 * 16 +HCD_CONST(SCOM_RESTORE_SIZE_PER_QME, + (SCOM_RESTORE_SIZE_PER_CORE* MAX_CORES_PER_QME)) // 128 * 16 * 4 + +HCD_CONST(SCOM_RESTORE_SIZE_TOTAL, (96 * ONE_KB)) + +HCD_CONST(SCOM_RESTORE_EL_AREA, + MAX_CORE_SCOM_ENTRIES* SCOM_RESTORE_ENTRY_SIZE) +HCD_CONST(SCOM_RESTORE_L2_AREA, + MAX_L2_SCOM_ENTRIES* SCOM_RESTORE_ENTRY_SIZE) +HCD_CONST(SCOM_RESTORE_L3_AREA, + MAX_L3_SCOM_ENTRIES* SCOM_RESTORE_ENTRY_SIZE) +HCD_CONST(SCOM_RESTORE_EQ_AREA, + MAX_EQ_SCOM_ENTRIES* SCOM_RESTORE_ENTRY_SIZE) +HCD_CONST(SCOM_RESTORE_VER, 1) +HCD_CONST(SCOM_RESTORE_L2_CORE, + (MAX_CORE_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES)) +HCD_CONST(SCOM_RESTORE_L3_CACHE, + (MAX_EQ_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES)) +/// QME Image + +HCD_CONST(QME_IMAGE_CPMR_OFFSET, 0x58000) // assumes SCOMs take up the first 96KB of second 256KB +//HCD_CONST(QME_IMAGE_SIZE, 0) +HCD_CONST(QME_INT_VECTOR_SIZE, 384) // 0x180 +HCD_CONST(QME_HCODE_OFFSET, (SELF_SAVE_RESTORE_REGION_SIZE + SCOM_RESTORE_SIZE_TOTAL)) + +/// QME Header + +HCD_CONST(QME_HEADER_CPMR_OFFSET, + (QME_IMAGE_CPMR_OFFSET + QME_INT_VECTOR_SIZE)) +HCD_CONST(QME_HEADER_IMAGE_OFFSET, QME_INT_VECTOR_SIZE) +HCD_CONST(QME_HEADER_SIZE, 128) // 0x80, +0x180=0x200 + +HCD_CONST(QME_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(QME_HCODE_OFFSET_BYTE, 0x08) +HCD_CONST(QME_HCODE_LENGTH_BYTE, 0x0C) +HCD_CONST(QME_COMMON_RING_OFFSET_BYTE, 0x10) +HCD_CONST(QME_OVERRIDE_RING_OFFSET_BYTE, 0x14) +HCD_CONST(QME_COMMON_RING_LENGTH_BYTE, 0x18) +HCD_CONST(QME_LOCAL_PSTATE_OFFSET_BYTE, 0x1C) +HCD_CONST(QME_LOCAL_PSTATE_LENGTH_BYTE, 0x20) +HCD_CONST(QME_SPECIFIC_RING_OFFSET_BYTE, 0x24) +HCD_CONST(QME_SPECIFIC_RING_LENGTH_BYTE, 0x28) +HCD_CONST(QME_QUAD_SCOM_RESTORE_OFFSET_BYTE, 0x2C) +HCD_CONST(QME_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x30) +HCD_CONST(QME_ATTR_TANK_ADDRESS, 0x34) +HCD_CONST(QME_LOCATION_ID_BYTE, 0x38) +HCD_CONST(QME_TIME_BASE, 0x3C) +HCD_CONST(QME_CPMR_HOMER_ADDRESS_BYTE, 0x40) + +HCD_CONST(QME_HCODE_OFF_IMAGE_OFFSET, (QME_HEADER_IMAGE_OFFSET + QME_HCODE_OFFSET_BYTE)) +HCD_CONST(QME_HCODE_LEN_IMAGE_OFFSET, (QME_HEADER_IMAGE_OFFSET + QME_HCODE_LENGTH_BYTE)) + +/// QME Hcode + +HCD_CONST(QME_HCODE_IMAGE_OFFSET, (QME_INT_VECTOR_SIZE + QME_HEADER_SIZE)) // 0x200 +HCD_CONST(QME_HCODE_SIZE, (43 * ONE_KB)) +HCD_CONST(QME_COMMON_RING_SIZE, (5 * ONE_KB)) +HCD_CONST(QME_INST_RING_SIZE, (5 * ONE_KB)) +HCD_CONST(QME_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(QME_DEBUG_PTRS_SIZE, 0x10) +HCD_CONST(QME_DUMP_PTRS_OFFSET, QME_DEBUG_PTRS_OFFSET + QME_DEBUG_PTRS_SIZE) +HCD_CONST(QME_DUMP_PTRS_SIZE, 0x300) +HCD_CONST(QME_ATTR_PTRS_OFFSET, QME_DUMP_PTRS_OFFSET + QME_DUMP_PTRS_SIZE) +HCD_CONST(QME_INSTRUMENTATION_SIZE, HALF_KB) +HCD_CONST(QME_SRAM_HCODE_OFFSET, 0) +HCD_CONST(QME_OVERRIDE_RING_SIZE, (2 * ONE_KB)) + +// QME Hcode + Core Scan + Pstate +HCD_CONST(QME_REGION_SIZE, (128 * ONE_KB)) + +// Debug + +HCD_CONST(CPMR_TRACE_REGION_OFFSET, (512 * ONE_KB)) +HCD_CONST(QME_TRACE_REGION_SIZE, (16 * ONE_KB)) +HCD_CONST(CPMR_TRACE_REGION_SIZE, (QME_TRACE_REGION_SIZE* MAX_QMES_PER_CHIP)) // 192K +HCD_CONST(CPMR_DEBUG_REGION_OFFSET, CPMR_TRACE_REGION_OFFSET + CPMR_TRACE_REGION_SIZE) +HCD_CONST(CPMR_DEBUG_REGION_SIZE, (64 * ONE_KB)) // 192K + 64K = 256K + +HCD_CONST(CACHE_CHIPLET_ID_MIN, 0x20 ) +HCD_CONST(CACHE_CHIPLET_ID_MAX, 0x27 ) + +//--------------------------------------------------------------------------------------- + +/// PPMR Header +HCD_CONST(PPMR_BUILD_VERSION, 1) +HCD_CONST(PPMR_HEADER_SIZE, 512) +HCD_CONST(PGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(PGPE_HEADER_IMAGE_OFFSET, PGPE_INT_VECTOR_SIZE) +HCD_CONST(PGPE_BOOT_COPIER_OFFSET, PPMR_HEADER_SIZE) +HCD_CONST(PGPE_BOOT_COPIER_LENGTH, ONE_KB) +HCD_CONST(PGPE_BOOT_LOADER_OFFSET, + (PGPE_BOOT_COPIER_OFFSET + PGPE_BOOT_COPIER_LENGTH) ) + +HCD_CONST(PGPE_BOOT_LOADER_LENGTH, ONE_KB) +HCD_CONST(PGPE_HCODE_OFFSET, + PGPE_BOOT_LOADER_OFFSET + PGPE_BOOT_LOADER_LENGTH ) +HCD_CONST(PPMR_HOMER_OFFSET, (HOMER_PPMR_REGION_NUM* ONE_MB)) + +HCD_CONST(PPMR_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(PPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(PPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(PPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PPMR_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PPMR_PGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(PPMR_PGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(PPMR_GLOBAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(PPMR_GLOBAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(PPMR_LOCAL_PSTATE_OFFSET_BYTE, 0x38) +HCD_CONST(PPMR_LOCAL_PSTATE_LENGTH_BYTE, 0x3C) +HCD_CONST(PPMR_OCC_PSTATE_OFFSET_BYTE, 0x40) +HCD_CONST(PPMR_OCC_PSTATE_LENGTH_BYTE, 0x44) +HCD_CONST(PPMR_PSTATE_TABLE_OFFSET_BYTE, 0x48) +HCD_CONST(PPMR_PSTATE_TABLE_LENGTH_BYTE, 0x4C) +HCD_CONST(PPMR_PGPE_SRAM_IMAGE_SIZE_BYTE, 0x50) +HCD_CONST(PPMR_PGPE_BOOT_PROG_CODE_BYTE, 0x54) +HCD_CONST(PPMR_WOF_TABLE_OFFSET, 0x58) +HCD_CONST(PPMR_WOF_TABLE_LENGTH, 0x5C) +HCD_CONST(PPMR_AUX_TASK_OFFSET, 0x60) +HCD_CONST(PPMR_AUX_TASK_LENGTH, 0x64) +HCD_CONST(PPMR_DEEP_OP_TRACE_OFFSET, 0x68) +HCD_CONST(PPMR_DEEP_OP_TRACE_LENGTH, 0x6C) + +/// PGPE Boot + +HCD_CONST(PGPE_BOOT_COPIER_PPMR_OFFSET, PPMR_HEADER_SIZE) +HCD_CONST(PGPE_BOOT_COPIER_SIZE, ONE_KB) + +HCD_CONST(PGPE_BOOT_LOADER_PPMR_OFFSET, + (PGPE_BOOT_COPIER_PPMR_OFFSET + PGPE_BOOT_COPIER_SIZE)) +HCD_CONST(PGPE_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(PGPE_BOOT_LOADER_RESET_ADDR_VAL, 0x40) +HCD_CONST(XGPE_BOOT_LOADER_RESET_ADDR_VAL, PGPE_BOOT_LOADER_RESET_ADDR_VAL) + +HCD_CONST(PGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) +/// PGPE Image +HCD_CONST(PGPE_IMAGE_PPMR_OFFSET, + (PGPE_BOOT_LOADER_PPMR_OFFSET + PGPE_BOOT_LOADER_SIZE)) + +HCD_CONST(PGPE_HCODE_RESET_ADDR_VAL, 0x40) +HCD_CONST(PGPE_DBG_PTR_AREA_SIZE, 64) + +/// PGPE Header + +HCD_CONST(PGPE_HEADER_SIZE, 128) + +HCD_CONST(PGPE_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PGPE_SYSTEM_RESET_ADDR_BYTE, 0x08) +HCD_CONST(PGPE_SHARED_SRAM_ADDR_BYTE, 0x0C) +HCD_CONST(PGPE_IVPR_ADDR_BYTE, 0x10) +HCD_CONST(PGPE_SHARED_SRAM_LENGTH_BYTE, 0x14) +HCD_CONST(PGPE_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PGPE_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PGPE_PGPE_FLAGS_BYTE, 0x20) +HCD_CONST(PGPE_PGPE_TIMEBASE_HZ, 0x24) +HCD_CONST(PGPE_GLOBAL_PSTATE_SRAM_ADDR_BYTE, 0x28) +HCD_CONST(PGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(PGPE_GLOBAL_PSTATE_MEM_OFFSET_BYTE, 0x30) +HCD_CONST(PGPE_GLOBAL_PSTATE_PPB_SIZE_BYTE, 0x34) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x38) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_SIZE_BYTE, 0x3C) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x40) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_SIZE_BYTE, 0x44) +HCD_CONST(PGPE_BEACON_ADDR_BYTE, 0x48) +HCD_CONST(PGPE_RESERVE_1, 0x4C) +HCD_CONST(PGPE_WOF_STATE_ADDR_BYTE, 0x50) +HCD_CONST(PGPE_RESERVE_2, 0x54) +HCD_CONST(PGPE_WOF_TABLE_ADDR_BYTE, 0x58) +HCD_CONST(PGPE_WOF_TABLE_LENGTH_BYTE, 0x5C) +HCD_CONST(PGPE_RESERVE_3, 0x60) +HCD_CONST(PGPE_RESERVE_4, 0x64) +HCD_CONST(PGPE_RESERVE_5, 0x68) +HCD_CONST(PGPE_OP_TRACE_PTR_BYTE, 0x6C) +HCD_CONST(PGPE_DEEP_OP_TRACE_MEM_ADDR_BYTE, 0x70) +HCD_CONST(PGPE_DEEP_OP_TRACE_LENGTH_BYTE, 0x74) + +HCD_CONST(PGPE_RESET_ADDR_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_SYSTEM_RESET_ADDR_BYTE)) +HCD_CONST(PGPE_BUILD_DATE_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_DATE_BYTE)) +HCD_CONST(PGPE_BUILD_VER_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_VER_BYTE)) + +//PPMR Misc +HCD_CONST(PPMR_MEM_MASK, 0x80300000) + +/// PGPE Hcode +HCD_CONST(PPMR_BOOT_REGION, (PPMR_HEADER_SIZE + PGPE_BOOT_COPIER_SIZE + PGPE_BOOT_LOADER_SIZE )) +HCD_CONST(PGPE_SRAM_BOOT_REGION, (PPMR_HEADER_SIZE + PGPE_BOOT_LOADER_SIZE )) +HCD_CONST(PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE, (6 * ONE_KB)) +HCD_CONST(PGPE_OCC_SHARED_SRAM_SIZE, (2 * ONE_KB)) +HCD_CONST(PGPE_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(PGPE_DEBUG_PTRS_SIZE, 0x24) + + +/// Pstate Parameter Block + Pstate Table + +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET, (128 * ONE_KB)) +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_SIZE, (8 * ONE_KB)) // this is over allocated +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET, (144 * ONE_KB)) +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_SIZE, (8 * ONE_KB)) // this is over allocated +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(OCC_WOF_TABLES_PPMR_OFFSET, (768 * ONE_KB)) +HCD_CONST(OCC_WOF_TABLES_SIZE, (256 * ONE_KB)) +HCD_CONST(PPMR_RESERVE_PSTATE_TABLE_TO_WOF, + ( OCC_WOF_TABLES_PPMR_OFFSET - ( PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET + PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE ) )) + +HCD_CONST(WOF_TABLE_RESERVE, + OCC_WOF_TABLES_PPMR_OFFSET - (PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET + PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE)) +HCD_CONST(PGPE_AUX_TASK_SIZE, (2 * ONE_KB)) + +#endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/libpore/p10_hcd_memmap_homer.H b/libpore/p10_hcd_memmap_homer.H new file mode 100644 index 000000000..6338bf2dd --- /dev/null +++ b/libpore/p10_hcd_memmap_homer.H @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_hcd_memmap_homer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_homer.H +/// @brief defines region constants of homer. +/// + +// *HWP HWP Owner: David Du +// *HWP Backup HWP Owner: Greg Still +// *HWP FW Owner: Prem S Jha +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __P9_HCD_MEMMAP_HOMER_H__ +#define __P9_HCD_MEMMAP_HOMER_H__ + +#include +#include + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +//-------------------------------------------------------------------- + +/// HOMER + +HCD_CONST(HOMER_BASE_ADDR, 0x80000000) +HCD_CONST(IMG_HDR_ALIGN_SIZE, 128) + +/// OPMR +HCD_CONST(OPMR_REGION_SIZE, ONE_MB ) + + +/// XPMR +HCD_CONST(XPMR_HOMER_OFFSET, (HOMER_XPMR_REGION_NUM* ONE_MB)) +HCD_CONST(HOMER_XPMR_BASE_ADDR, (HOMER_BASE_ADDR + (XPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_XPMR_HEADER_ADDR, HOMER_XPMR_BASE_ADDR) +HCD_CONST(HOMER_XGPE_BOOT_COPIER_ADDR, (HOMER_XPMR_HEADER_ADDR + XPMR_HEADER_SIZE)) +HCD_CONST(XGPE_BOOT_COPIER_SIZE, (ONE_KB)) +HCD_CONST(HOMER_XGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_XPMR_HEADER_ADDR + XPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_XGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_XPMR_HEADER_ADDR + XPMR_BOOT_LOADER_LENGTH_BYTE)) + +/// CPMR + +HCD_CONST(HOMER_CPMR_BASE_ADDR, (HOMER_BASE_ADDR + (CPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_CPMR_HEADER_ADDR, HOMER_CPMR_BASE_ADDR) +HCD_CONST(HOMER_CPMR_TRACE_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_TRACE_REGION_OFFSET)) +HCD_CONST(HOMER_CPMR_DEBUG_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_DEBUG_REGION_OFFSET)) + + +/// PPMR + +HCD_CONST(HOMER_PPMR_BASE_ADDR, (HOMER_BASE_ADDR + (PPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_PPMR_HEADER_ADDR, HOMER_PPMR_BASE_ADDR) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_LENGTH_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_COPIER_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_HEADER_SIZE)) + +HCD_CONST(HOMER_OCC_PSTATE_PARAM_BLOCK_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET)) +HCD_CONST(HOMER_PGPE_PSTATE_OUTPUT_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET)) +HCD_CONST(HOMER_OCC_WOF_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_WOF_TABLES_PPMR_OFFSET)) + +#endif /* __P9_HCD_MEMMAP_HOMER_H__ */ diff --git a/libpore/p10_hcd_memmap_occ_sram.H b/libpore/p10_hcd_memmap_occ_sram.H new file mode 100644 index 000000000..255748bc8 --- /dev/null +++ b/libpore/p10_hcd_memmap_occ_sram.H @@ -0,0 +1,174 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_hcd_memmap_occ_sram.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p10_hcd_memmap_occ_sram.H +/// @brief defines region constants of occ sram. +/// + +// *HWP HWP Owner: David Du +// *HWP Backup HWP Owner: Greg Still +// *HWP FW Owner: Prem S Jha +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: HB, XGPE,PGPE + +#ifndef __HCD_MEMMAP_OCC_SRAM_H__ +#define __HCD_MEMMAP_OCC_SRAM_H__ + +#include +#include + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// OCC SRAM + +HCD_CONST(OCC_SRAM_BASE_ADDR, 0xFFF00000) +HCD_CONST(GPE0_SRAM_BASE_ADDR, 0xFFF01000) +HCD_CONST(GPE1_SRAM_BASE_ADDR, 0xFFF10000) +HCD_CONST(PGPE_SRAM_BASE_ADDR, 0xFFF20000) +HCD_CONST(XGPE_SRAM_BASE_ADDR, 0xFFF30000) +HCD_CONST(OCC_SRAM_SIZE, ONE_MB) +HCD_CONST(OCC_SRAM_END_ADDR, ( OCC_SRAM_BASE_ADDR + OCC_SRAM_SIZE)) + +/// Base Addresses for various debug/trace regions in OCC SRAM +HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_ERR, 0xFFFB4000) +HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_INF, 0xFFFB6000) +HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_IMP, 0xFFFB8000) +HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR, 0xFFF40824) +HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SHARED_SRAM_ADDR_START, + ((PGPE_SRAM_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE) - PGPE_OCC_SHARED_SRAM_SIZE)) + +// Offset to trace buf ptr and trace buffer size from base +HCD_CONST(GPE_DEBUG_PTR_OFFSET, 0x180) + +// Size of various traces regions in OCC SRAM +HCD_CONST(OCC_SRAM_TRACE_BUF_SSX_SIZE_PTR, 0xFFF40828) +HCD_CONST(OCC_SRAM_TRACE_BUF_ERR_SIZE, (8 * ONE_KB)) +HCD_CONST(OCC_SRAM_TRACE_BUF_INF_SIZE, (8 * ONE_KB)) +HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE, (8 * ONE_KB)) + +HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) +HCD_CONST(OCC_SRAM_XGPE_REGION_SIZE, (64 * ONE_KB)) + + +HCD_CONST(PPE_RESET_VECTOR, 0x40) +//-------------------------------------------------------------------------------------- + +/// PGPE Base + +HCD_CONST(OCC_SRAM_PGPE_BASE_ADDR, PGPE_SRAM_BASE_ADDR) +HCD_CONST(OCC_SRAM_PGPE_END_ADDR, + (PGPE_SRAM_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_RESET_ADDR, + (PGPE_SRAM_BASE_ADDR + PGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_HEADER_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + PGPE_INT_VECTOR_SIZE)) +//PGPE image size is sum of various parts hence located here instead of p10_hcd_memmap_base.H +HCD_CONST(PGPE_HCODE_SIZE, (OCC_SRAM_PGPE_REGION_SIZE - ( PGPE_OCC_SHARED_SRAM_SIZE + + PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE + PGPE_SRAM_BOOT_REGION ))) +HCD_CONST(PGPE_IMAGE_SIZE, (PGPE_HCODE_SIZE + PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE + + PGPE_OCC_SHARED_SRAM_SIZE + PGPE_SRAM_BOOT_REGION)) +HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, + (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE)) + + +/// PGPE Boot + +HCD_CONST(OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE, 512) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_END_ADDR - OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR + PGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_PPMR_HEADER_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR - OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_OPTRACE_ADDR, OCC_SRAM_PGPE_BOOT_LOADER_ADDR) +HCD_CONST(OCC_SRAM_PGPE_OPTRACE_SIZE, OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE) + +/// PGPE Copy + +HCD_CONST(OCC_SRAM_PGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_PGPE_IMAGE_LENGTH_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_SRAM_IMAGE_SIZE_BYTE)) + +// Misc constants used in PGPE boot loader and boot copier. +HCD_CONST(PGPE_BOOT_COPY_SUCCESS, 0x42432d53 ) // ASCII code for BC-S +HCD_CONST(PGPE_BOOT_COPIER_FAIL, 0x42432d46 ) // ASCII code for BC-F +HCD_CONST(PGPE_BOOT_LOADER_SUCCESS, 0x424c2d53 ) // ASCII code for BL-S +HCD_CONST(PGPE_BOOT_LOADER_FAIL, 0x424c2d46 ) // ASCII code for BL-F + +//-------------------------------------------------------------------------------------- + +// Misc constants used in XGPE boot loader and boot copier. +HCD_CONST(DIVDE_BY_8, 3) +HCD_CONST(DOUBLE_WORD_SIZE, 8) +HCD_CONST(XGPE_IMG_OFFSET_POS, 40) +HCD_CONST(BOOT_COPIER_LEN_ZERO, 0) +HCD_CONST(ENABLE_TRAP, 0) +HCD_CONST(XGPE_BOOT_COPY_SUCCESS, 0x42432d53 ) // ASCII code for BC-S +HCD_CONST(XGPE_BOOT_COPIER_FAIL, 0x42432d46 ) // ASCII code for BC-F +HCD_CONST(XGPE_BOOT_LOADER_SUCCESS, 0x424c2d53 ) // ASCII code for BL-S +HCD_CONST(XGPE_BOOT_LOADER_FAIL, 0x424c2d46 ) // ASCII code for BL-F + +/// XGPE Base +HCD_CONST(OCC_SRAM_XGPE_SYSTEM_RESET_ADDR, + (XGPE_SRAM_BASE_ADDR + XGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_XGPE_IVPR_ADDR, XGPE_SRAM_BASE_ADDR) +HCD_CONST(OCC_SRAM_XGPE_GPPB_ADDR, + (PGPE_SRAM_BASE_ADDR + PGPE_HEADER_IMAGE_OFFSET + PGPE_GLOBAL_PSTATE_SRAM_ADDR_BYTE)) +HCD_CONST(OCC_SRAM_XGPE_GPPB_LEN, + (PGPE_SRAM_BASE_ADDR + PGPE_HEADER_IMAGE_OFFSET + PGPE_GLOBAL_PSTATE_PPB_SIZE_BYTE)) + +/// XGPE Boot +HCD_CONST(OCC_SRAM_XGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_XGPE_COPY_XPMR_HEADER_SIZE, 512) +HCD_CONST(OCC_SRAM_XGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_END_ADDR - OCC_SRAM_XGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_XGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_XGPE_BOOT_LOADER_ADDR + XGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_XGPE_XPMR_HEADER_ADDR, + (OCC_SRAM_XGPE_BOOT_LOADER_ADDR - OCC_SRAM_XGPE_COPY_XPMR_HEADER_SIZE)) + +/// XGPE Copy +HCD_CONST(OCC_SRAM_XGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_XGPE_XPMR_HEADER_ADDR + XPMR_XGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_XGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_XGPE_XPMR_HEADER_ADDR + XPMR_XGPE_HCODE_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_XGPE_IMAGE_LENGTH_ADDR, + (OCC_SRAM_XGPE_XPMR_HEADER_ADDR + XPMR_XGPE_SRAM_IMAGE_SIZE_BYTE)) +HCD_CONST(OCC_SRAM_XGPE_HCODE_RESET_ADDR, + (XGPE_SRAM_BASE_ADDR + XGPE_HCODE_RESET_ADDR_VAL)) + +#endif /* __HCD_MEMMAP_OCC_SRAM_H__ */ diff --git a/libpore/p10_hcode_image_defines.H b/libpore/p10_hcode_image_defines.H new file mode 100644 index 000000000..6a14cb241 --- /dev/null +++ b/libpore/p10_hcode_image_defines.H @@ -0,0 +1,462 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_hcode_image_defines.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p10_hcode_image_defines.H +/// @brief defines constants associated with hcode image build. +/// +// *HWP HWP Owner: Greg Still +// *HWP FW Owner: Prem S Jha +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: Hostboot: HBRT + +#ifndef __HW_IMG_DEFINE +#define __HW_IMG_DEFINE + +#include +#include +#include +#include + +//-------------------------------------------------------------------------- +// local structs and constants +// ------------------------------------------------------------------------- +#ifndef __ASSEMBLER__ +#ifdef __cplusplus +#ifndef __PPE_PLAT + +#define IMG_HDR_ALIGN_SIZE 32 + +namespace hcodeImageBuild +{ +#endif //__PPE_PLAT +#endif //__cplusplus +#endif //__ASSEMBLER__ + +/** + * CPMR Header + * + * This header is only consumed by Hcode Image Build and + * lab tools, not by PPE code. It is generated with assembler + * primitives during QME build and placed in HOMER by + * Hcode Image Build. + */ + +#ifdef __ASSEMBLER__ +.macro .cpmr_header +.section ".cpmr" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_ATTN ( iv_attnOpcodes, 2); +HCD_HDR_UINT64( iv_cpmrMagicWord, CPMR_MAGIC_NUMBER); +HCD_HDR_UINT32( iv_buildDate, 0); +HCD_HDR_UINT32( iv_version, 0); +HCD_HDR_UINT8_VEC (iv_reserveFlags, 4, 0); +HCD_HDR_UINT8 ( iv_selfRestoreVer, 0); +HCD_HDR_UINT8 ( iv_stopApiVer, 0); +HCD_HDR_UINT8 ( iv_urmorFix, 0); +HCD_HDR_UINT8 ( iv_fusedMode, 0); +HCD_HDR_UINT32( iv_qmeImgOffset, 0); +HCD_HDR_UINT32( iv_qmeImgLength, 0); +HCD_HDR_UINT32( iv_commonRingOffset, 0); +HCD_HDR_UINT32( iv_commonRingLength, 0); +HCD_HDR_UINT32( iv_localPstateOffset, 0); +HCD_HDR_UINT32( iv_localPstateLength, 0); +HCD_HDR_UINT32( iv_specRingOffset, 0); +HCD_HDR_UINT32( iv_specRingLength, 0); +HCD_HDR_UINT32( iv_scomRestoreOffset, 0); +HCD_HDR_UINT32( iv_scomRestoreLength, 0); +HCD_HDR_UINT32( iv_selfRestoreOffset, 0); +HCD_HDR_UINT32( iv_selfRestoreLength, 0); +HCD_HDR_UINT32( iv_maxCoreL2ScomEntry, 0); +HCD_HDR_UINT32( iv_maxEqL3ScomEntry, 0); +HCD_HDR_UINT32( iv_coreL2ScomOffset, 0); +HCD_HDR_UINT32( iv_coreL2ScomLength, 0); +HCD_HDR_UINT32( iv_eqL3ScomOffset, 0); +HCD_HDR_UINT32( iv_eqL3ScomLength, 0); +HCD_HDR_PAD(CPMR_HEADER_SIZE); +#ifdef __ASSEMBLER__ +.endm +#else +} __attribute__((packed, aligned(256))) CpmrHeader_t; +#endif + +/** + * QME Header + * + * The QME header is loaded in the QME SRAM so it is "tight" (little extra space) + * Thus, this "structure" is NOT padded to a specific size and is limited to + * 64B. Also, structure member names are preceded with "g_" as these becoming + * global variables in the QME Hcode. + */ +#ifdef __ASSEMBLER__ +.macro .qme_header +.section ".qme_image_header" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_UINT64( g_qme_magic_number, QME_MAGIC_NUMBER ); +HCD_HDR_UINT32( g_qme_hcode_offset, 0 ); +HCD_HDR_UINT32( g_qme_hcode_length, 0 ); +HCD_HDR_UINT32( g_qme_common_ring_offset, 0 ); +HCD_HDR_UINT32( g_qme_cmn_ring_ovrd_offset, 0 ); +HCD_HDR_UINT32( g_qme_common_ring_length, 0 ); +HCD_HDR_UINT32( g_qme_pstate_region_offset, 0 ); +HCD_HDR_UINT32( g_qme_pstate_region_length, 0 ); +HCD_HDR_UINT32( g_qme_inst_spec_ring_offset, 0 ); +HCD_HDR_UINT32( g_qme_max_spec_ring_length, 0 ); +HCD_HDR_UINT32( g_qme_scom_offset, 0 ); +HCD_HDR_UINT32( g_qme_scom_length, 0 ); +HCD_HDR_UINT32( g_qme_attr_tank_address, 0 ); +HCD_HDR_UINT16( g_qme_location_id, 0 ); +HCD_HDR_UINT16( g_qme_reserved , 0 ); +HCD_HDR_UINT32( g_qme_timebase_hz, 0 ); //Retain next field at 8B boundary +HCD_HDR_UINT64( g_qme_cpmr_PhyAddr, 0 ); +HCD_HDR_UINT64( g_qme_unsec_cpmr_PhyAddr, 0 ); +HCD_HDR_UINT32( g_qme_custom_length, 0 ); +HCD_HDR_UINT32( g_qme_elog_addr, 0 ); +HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); +#ifdef __ASSEMBLER__ +.endm +#else +//QME Header size is 96B +} __attribute__((packed, aligned(32))) QmeHeader_t; +#endif + +#ifndef __ASSEMBLER__ + +typedef struct QMEImageFlags +{ + uint32_t fused_mode : 1; + uint32_t reserved0 : 31; +} QMEImageFlags_t; + +#endif //__ASSEMBLER__ + +#ifdef __ASSEMBLER__ +.macro .ppmr_header +.section ".ppmr" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_UINT64( iv_ppmrMagicWord, PPMR_MAGIC_NUMBER); +HCD_HDR_UINT32( iv_bootCopierOffset, 0); +HCD_HDR_UINT32( iv_reserved1, 0); +HCD_HDR_UINT32( iv_bootLoaderOffset, 0); +HCD_HDR_UINT32( iv_bootLoaderLength, 0); +HCD_HDR_UINT32( iv_buildDate, 0); +HCD_HDR_UINT32( iv_buildVer, 0); +HCD_HDR_UINT64( iv_reserved2, 0); +HCD_HDR_UINT32( iv_hcodeOffset, 0); +HCD_HDR_UINT32( iv_hcodeLength, 0); +HCD_HDR_UINT32( iv_gpspbOffset, 0); +HCD_HDR_UINT32( iv_gpspbLength, 0); +HCD_HDR_UINT32( iv_lpspbOffset, 0); +HCD_HDR_UINT32( iv_lpspbLength, 0); +HCD_HDR_UINT32( iv_opspbOffset, 0); +HCD_HDR_UINT32( iv_opspbLength, 0); +HCD_HDR_UINT32( iv_pstateOffset, 0); +HCD_HDR_UINT32( iv_pstateLength, 0); +HCD_HDR_UINT32( iv_sramSize, 0); +HCD_HDR_UINT32( iv_progCode, 0); +HCD_HDR_UINT32( iv_wofTableOffset, 0); +HCD_HDR_UINT32( iv_wofTableLength, 0); +HCD_HDR_UINT32( iv_deepOptraceOffset, 0); +HCD_HDR_UINT32( iv_deepOptraceLength, 0); + +#ifdef __ASSEMBLER__ +.endm +#else +} __attribute__((packed, aligned(32))) PpmrHeader_t; +#endif + +#ifdef __ASSEMBLER__ +.macro .pgpe_header +.section ".pgpe_hdr" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_UINT64( g_pgpe_magicWord, PGPE_MAGIC_NUMBER); +HCD_HDR_UINT32( g_pgpe_sysResetAddress, 0); +HCD_HDR_UINT32( g_pgpe_sharedSramAddress, 0); +HCD_HDR_UINT32( g_pgpe_ivprAddress, 0); +HCD_HDR_UINT32( g_pgpe_sharedLength, 0); +HCD_HDR_UINT32( g_pgpe_buildDate, 0); +HCD_HDR_UINT32( g_pgpe_buildVer, 0); +HCD_HDR_UINT32( g_pgpe_reserved0, 0); +HCD_HDR_UINT32( g_pgpe_timeBaseHz, 0); +HCD_HDR_UINT32( g_pgpe_gpspbSramAddress, 0); +HCD_HDR_UINT32( g_pgpe_hcodeLength, 0); +HCD_HDR_UINT32( g_pgpe_gpspbMemOffset, 0); +HCD_HDR_UINT32( g_pgpe_gpspbMemLength, 0); +HCD_HDR_UINT32( g_pgpe_genPsTableMemOffset, 0); +HCD_HDR_UINT32( g_pgpe_genPsTableMemLength, 0); +HCD_HDR_UINT32( g_pgpe_opspbTableAddress, 0); +HCD_HDR_UINT32( g_pgpe_opspbTableLength, 0); +HCD_HDR_UINT32( g_pgpe_beaconAddress, 0); +HCD_HDR_UINT32( g_pgpe_reserved1, 0); +HCD_HDR_UINT32( g_pgpe_pgpeWofStateAddress, 0); +HCD_HDR_UINT32( g_pgpe_reserved2, 0); +HCD_HDR_UINT32( g_pgpe_wofTableAddress, 0); +HCD_HDR_UINT32( g_pgpe_wofTableLength, 0); +HCD_HDR_UINT32( g_pgpe_reserved3, 0); +HCD_HDR_UINT32( g_pgpe_reserved4, 0); +HCD_HDR_UINT32( g_pgpe_reserved5, 0); +HCD_HDR_UINT32( g_pgpe_opTracePtr, 0); +HCD_HDR_UINT32( g_pgpe_deepOpTraceMemAddress, 0); +HCD_HDR_UINT32( g_pgpe_deepOpTraceLength, 0); +#ifdef __ASSEMBLER__ +.endm +#else +} __attribute__((packed, aligned(32))) PgpeHeader_t; +#endif + +#ifdef __ASSEMBLER__ +.macro .xpmr_hdr +.section ".xpmr" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_UINT64( iv_xpmrMagicWord, XPMR_MAGIC_NUMBER); +HCD_HDR_UINT32( iv_bootCopierOffset, 0); +HCD_HDR_UINT32( iv_reserve1, 0); +HCD_HDR_UINT32( iv_bootLoaderOffset, 0); +HCD_HDR_UINT32( iv_bootLoaderLength, 0); +HCD_HDR_UINT32( iv_buildDate, 0); +HCD_HDR_UINT32( iv_version, 0); +HCD_HDR_UINT32( iv_reserve2, 0); +HCD_HDR_UINT32( iv_reserve3, 0); +HCD_HDR_UINT32( iv_xgpeHcodeOffset, 0); +HCD_HDR_UINT32( iv_xgpeHcodeLength, 0); +HCD_HDR_UINT32( iv_xgpeBootProgCode, 0); +HCD_HDR_UINT32( iv_xgpeSramSize, 0); +HCD_HDR_PAD(XPMR_HEADER_SIZE); +#ifdef __ASSEMBLER__ +.endm +#else +} __attribute__((packed, aligned(512))) XpmrHeader_t; +#endif + +#ifdef __ASSEMBLER__ +.macro .xgpe_header +.section ".xgpe_header" , "aw" +.balign 8 +#else +typedef struct +{ +#endif +HCD_HDR_UINT64( g_xgpe_magicWord, XGPE_MAGIC_NUMBER); +HCD_HDR_UINT32( g_xgpe_sysResetAddress, 0 ); //FIXME need to add correct address +HCD_HDR_UINT32( g_xgpe_sharedSramAddress, 0 ); //FIXME need to add correct address +HCD_HDR_UINT32( g_xgpe_ivprAddress, 0 ); //FIXME need to add correct address +HCD_HDR_UINT32( g_xgpe_sharedSramLength, 0 ); +HCD_HDR_UINT32( g_xgpe_buildDate, 0 ); +HCD_HDR_UINT32( g_xgpe_buildVer, 0 ); +HCD_HDR_UINT16( g_xgpe_xgpeFlags, 0 ); +HCD_HDR_UINT16( g_xgpe_reserve1, 0 ); +HCD_HDR_UINT32( g_xgpe_timeBaseHz, 0 ); +HCD_HDR_UINT32( g_xgpe_gpspbSramAddress, 0 ); +HCD_HDR_UINT32( g_xgpe_hcodeLength, 0 ); +HCD_HDR_UINT32( g_xgpe_reserve2, 0 ); +HCD_HDR_UINT32( g_xgpe_gpspbLength, 0 ); +HCD_HDR_UINT32( g_xgpe_coreThrottleAssertCnt, 0 ); +HCD_HDR_UINT32( g_xgpe_coreThrottleDeAssertCnt, 0 ); +HCD_HDR_UINT32( g_xgpe_charactControls, 0 ); +HCD_HDR_UINT32( g_xgpe_xgpeOpTracePointer, 0 ); +HCD_HDR_UINT32( g_xgpe_xgpeDeepOpTraceMemAddr, 0 ); +HCD_HDR_UINT32( g_xgpe_xgpeDeepOpTraceLength, 0 ); +HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); +#ifdef __ASSEMBLER__ +.endm +#else +} __attribute__((packed, aligned(32))) XgpeHeader_t; +#endif + +#ifndef __ASSEMBLER__ + +/** + * @brief enumerates all return codes associated with hcode image build. + */ +enum ImgBldRetCode_t +{ + IMG_BUILD_SUCCESS = 0, + BUILD_FAIL_XGPE_IMAGE = 1, + BUILD_FAIL_SELF_REST_IMAGE = 2, + BUILD_FAIL_QME_IMAGE = 3, + BUILD_FAIL_PGPE_IMAGE = 4, + BUILD_FAIL_XGPE_QPMR = 5, + BUILD_FAIL_XGPE_BL1 = 6, + BUILD_FAIL_XGPE_BL2 = 7, + BUILD_FAIL_XGPE_INT_VECT = 8, + BUILD_FAIL_XGPE_HDR = 9, + BUILD_FAIL_XGPE_HCODE = 10, + BUILD_FAIL_XGPE_CMN_RINGS = 11, + BUILD_FAIL_XGPE_SPEC_RINGS = 12, + BUILD_FAIL_CPMR_HDR = 13, + BUILD_FAIL_SRESET_HNDLR = 14, + BUILD_FAIL_THRD_LAUNCHER = 15, + BUILD_FAIL_SPR_RESTORE = 16, + BUILD_FAIL_SCOM_RESTORE = 17, + BUILD_FAIL_QME_IMG_HDR = 18, + BUILD_FAIL_QME_HCODE = 19, + BUILD_FAIL_CMN_RINGS = 20, + BUILD_FAIL_QME_QUAD_PSTATE = 21, + BUILD_FAIL_SPEC_RINGS = 22, + BUILD_FAIL_INT_VECT = 23, + BUILD_FAIL_PGPE_BL1 = 24, + BUILD_FAIL_PGPE_BL2 = 25, + BUILD_FAIL_PGPE_HCODE = 26, + BUILD_FAIL_OVERRIDE = 27, + BUILD_SEC_SIZE_OVERFLOW = 28, + BUILD_FAIL_INVALID_SECTN = 29, + BUILD_FAIL_RING_EXTRACTN = 30, + QME_SRAM_IMG_SIZE_ERR = 31, + XGPE_SRAM_IMG_SIZE_ERR = 32, + PGPE_SRAM_IMG_SIZE_ERR = 33, + BUILD_FAIL_PGPE_PPMR = 34, + BUILD_FAIL_XIP_CUST_ERR = 35, + BUILD_ERR_INTERNAL = 0xffff, +}; + +/** + * @brief models SCOM restore header region. + */ +typedef struct +{ + uint16_t iv_magicMark; + uint8_t iv_version; + uint8_t iv_reserved1; + uint8_t iv_reserved2[4]; + uint16_t iv_coreOffset; + uint16_t iv_coreLength; + uint16_t iv_eqOffset; + uint16_t iv_eqLength; + uint16_t iv_l2Offset; + uint16_t iv_l2Length; + uint16_t iv_l3Offset; + uint16_t iv_l3Length; +} ScomRestoreHeader_t; + +/** + * @brief models a CPU register restoration area in STOP section of homer image. + */ +typedef struct +{ + uint8_t iv_threadRestoreArea[MAX_THREADS_PER_CORE][SMF_CORE_RESTORE_THREAD_AREA_SIZE]; + uint8_t iv_threadSaveArea[MAX_THREADS_PER_CORE][SMF_SELF_SAVE_THREAD_AREA_SIZE]; + uint8_t iv_coreRestoreArea[SMF_CORE_RESTORE_CORE_AREA_SIZE]; + uint8_t iv_coreSaveArea[SMF_CORE_SAVE_CORE_AREA_SIZE]; +} SmfSprRestoreRegion_t; + +/** + * @brief models image section of CPMR in HOMER. + */ +typedef union CPMRSelfRestoreLayout +{ + uint8_t iv_region[SMF_SELF_RESTORE_CODE_SIZE]; + struct + { + CpmrHeader_t iv_CPMRHeader; + uint8_t iv_exe[SMF_SELF_RESTORE_CODE_SIZE - sizeof(CpmrHeader_t)]; + } elements; +} CPMRSelfRestoreLayout_t; + +/** + * @brief models image section associated with core self restore in HOMER. + */ +typedef struct +{ + CPMRSelfRestoreLayout_t iv_CPMR_SR; + uint8_t iv_coreSelfRestore[SMF_SELF_RESTORE_CORE_REGS_SIZE]; + uint8_t iv_reserve[SCOM_RESTORE_CPMR_OFFSET - SMF_SELF_RESTORE_SIZE_TOTAL]; + uint8_t iv_coreScom[SCOM_RESTORE_SIZE_TOTAL]; +} SelfRestoreLayout_t; + +typedef struct +{ + SelfRestoreLayout_t iv_selfRestoreRegion; + uint8_t iv_qmeSramRegion[QME_REGION_SIZE]; +} CPMRLayout_t; + +/** + * @brief models image section associated with PGPE in HOMER. + */ +typedef struct +{ + uint8_t iv_ppmrHeader[PPMR_HEADER_SIZE]; + uint8_t iv_bootCopier[PGPE_BOOT_COPIER_SIZE]; + uint8_t iv_bootLoader[PGPE_BOOT_LOADER_SIZE]; + uint8_t iv_pgpeSramRegion[OCC_SRAM_PGPE_REGION_SIZE]; + uint8_t iv_reserve1[OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - (PPMR_BOOT_REGION + OCC_SRAM_PGPE_REGION_SIZE)]; + uint8_t iv_occPstateParamBlock[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE]; + uint8_t iv_pstateTable[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE]; + uint8_t iv_reserve2[PPMR_RESERVE_PSTATE_TABLE_TO_WOF]; + uint8_t iv_wofTable[OCC_WOF_TABLES_SIZE]; +} PPMRLayout_t; + +/** + * @brief models XPMR in HOMER. + */ +typedef struct +{ + uint8_t iv_xpmrHeader[XPMR_HEADER_SIZE]; + uint8_t iv_bootCopier[XGPE_BOOT_COPIER_LENGTH]; + uint8_t iv_bootLoader[XGPE_BOOT_LOADER_LENGTH]; + uint8_t iv_xgpeSramRegion[XGPE_SRAM_SIZE]; +} XPMRLayout_t; + +/** + * @brief models layout of HOMER. + */ +typedef struct +{ + uint8_t iv_occHostRegion[OCC_HOST_AREA_SIZE]; + XPMRLayout_t iv_xpmrRegion; + uint8_t iv_xpmrReserve[ONE_MB - sizeof( XPMRLayout_t )]; + CPMRLayout_t iv_cpmrRegion; + uint8_t iv_cpmrReserve[ONE_MB - sizeof( CPMRLayout_t )]; + PPMRLayout_t iv_ppmrRegion; + uint8_t iv_ppmrReserve[ONE_MB - sizeof( PPMRLayout_t )]; +} Homerlayout_t; + +#ifdef __cplusplus +#ifndef __PPE_PLAT +}// namespace hcodeImageBuild ends +#endif //__PPE_PLAT +#endif //__cplusplus + +#endif //__ASSEMBLER__ +#endif //__HW_IMG_DEFINE diff --git a/libpore/p10_stop_api.C b/libpore/p10_stop_api.C new file mode 100644 index 000000000..4a8efa7cd --- /dev/null +++ b/libpore/p10_stop_api.C @@ -0,0 +1,1816 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p10/procedures/utils/stopreg/p10_stop_api.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p10_stop_api.C +/// @brief implements STOP API which create/manipulate STOP image. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP + +// *INDENT-OFF* +#ifdef PPC_HYP + #include +#endif + +#include "p10_stop_api.H" +#include "p10_cpu_reg_restore_instruction.H" +#include "p10_stop_data_struct.H" +#include +#include "p10_stop_util.H" +#include "p10_hcode_image_defines.H" +#ifdef __cplusplus +extern "C" { + +using namespace hcodeImageBuild; +namespace stopImageSection +{ +#endif +// a true in the table below means register is of scope thread +// whereas a false meanse register is of scope core. + +const StopSprReg_t g_sprRegister_p10[] = +{ + { PROC_STOP_SPR_CIABR, true, 0 }, + { PROC_STOP_SPR_DAWR, true, 1 }, + { PROC_STOP_SPR_DAWRX, true, 2 }, + { PROC_STOP_SPR_HSPRG0, true, 3 }, + { PROC_STOP_SPR_LDBAR, true, 4, }, + { PROC_STOP_SPR_LPCR, true, 5 }, + { PROC_STOP_SPR_PSSCR, true, 6 }, + { PROC_STOP_SPR_MSR, true, 7 }, + { PROC_STOP_SPR_HRMOR, false, 255 }, + { PROC_STOP_SPR_HID, false, 21 }, + { PROC_STOP_SPR_HMEER, false, 22 }, + { PROC_STOP_SPR_PMCR, false, 23 }, + { PROC_STOP_SPR_PTCR, false, 24 }, + { PROC_STOP_SPR_SMFCTRL, true, 28 }, + { PROC_STOP_SPR_USPRG0, true, 29 }, + { PROC_STOP_SPR_USPRG1, true, 30 }, + { PROC_STOP_SPR_URMOR, false, 255 }, +}; + +const uint32_t MAX_SPR_SUPPORTED_P10 = 17; +const uint32_t DEFAULT_CORE_SCOM_SUPPORTED = 15; +const uint32_t DEFAULT_QUAD_SCOM_SUPPORTED = 255; + +//----------------------------------------------------------------------------- + +/** + * @brief validated input arguments passed to proc_stop_save_cpureg_control. + * @param[in] i_pImage point to start of HOMER + * @param[in] i_coreId id of the core + * @param[in] i_threadId id of the thread + * @param[in] i_saveMaskVector SPR save bit mask vector + * @return STOP_SAVE_SUCCESS if function succeeds, error code otherwise. + */ +STATIC StopReturnCode_t validateArgumentSaveRegMask( void* const i_pImage, + uint32_t const i_coreId, + uint32_t const i_threadId, + uint64_t i_saveMaskVector ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + if( i_coreId > MAX_CORE_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_CORE; + break; + } + + if( i_threadId > MAX_THREAD_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_THREAD; + break; + } + + if( ( 0 == i_saveMaskVector ) || ( BAD_SAVE_MASK & i_saveMaskVector ) ) + { + l_rc = STOP_SAVE_ARG_INVALID_REG; + break; + } + + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief validates input arguments provided by STOP API caller. + * @param[in] i_pImage pointer to beginning of chip's HOMER image. + * @param[in] i_regId SPR register id + * @param[in] i_coreId core id + * @param[in|out] i_pThreadId points to thread id + * @param[in|out] i_pThreadLevelReg points to scope information of SPR + * @return STOP_SAVE_SUCCESS if arguments found valid, error code otherwise. + * @note for register of scope core, function shall force io_threadId to + * zero. + */ +STATIC StopReturnCode_t validateSprImageInputs( void* const i_pImage, + const CpuReg_t i_regId, + const uint32_t i_coreId, + uint32_t* i_pThreadId, + bool* i_pThreadLevelReg ) +{ + uint32_t index = 0; + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + bool sprSupported = false; + *i_pThreadLevelReg = false; + + do + { + if( NULL == i_pImage ) + { + // Error: HOMER image start location is not valid + // Cannot proceed further. So, let us exit. + l_rc = STOP_SAVE_ARG_INVALID_IMG; + MY_ERR( "invalid image location " ); + + break; + } + + // STOP API manages STOP image based on physical core Id. PIR value + // is interpreted to calculate the physical core number and virtual + // thread number. + if( MAX_CORE_ID_SUPPORTED < i_coreId ) + { + // Error: invalid core number. given core number exceeds maximum + // cores supported by chip. + + // Physical core number is calculated based on following formula: + // core id = 4 * quad id (0..5) + core no within quad ( 0..3) + l_rc = STOP_SAVE_ARG_INVALID_CORE; + MY_ERR( "invalid core id " ); + break; + } + + if( MAX_THREAD_ID_SUPPORTED < *i_pThreadId ) + { + //Error: invalid core thread. Given core thread exceeds maximum + //threads supported in a core. + + // 64 bit PIR value is interpreted to calculate virtual thread + // Id. In fuse mode, b61 and b62 gives virtual thread id whereas in + // non fuse mode, b62 and b63 is read to determine the same. + + l_rc = STOP_SAVE_ARG_INVALID_THREAD; + MY_ERR( "invalid thread " ); + break; + } + + for( index = 0; index < MAX_SPR_SUPPORTED_P10; ++index ) + { + if( i_regId == (CpuReg_t )g_sprRegister_p10[index].iv_sprId ) + { + // given register is in the list of register supported + sprSupported = true; + *i_pThreadLevelReg = g_sprRegister_p10[index].iv_isThreadScope; + *i_pThreadId = *i_pThreadLevelReg ? *i_pThreadId : 0; + break; + } + } + + if( !sprSupported ) + { + // Following SPRs are supported + // trace out all registers supported + MY_ERR("Register not supported" ); + // error code to caller. + l_rc = STOP_SAVE_ARG_INVALID_REG; + break; + } + + } + while(0); + + if( l_rc ) + { + MY_ERR( "regId %08d, coreId %d, " + "threadId %d return code 0x%08x", i_regId, + i_coreId, *i_pThreadId, l_rc ); + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates ori instruction code. + * @param[in] i_Rs Source register number + * @param[in] i_Ra destination register number + * @param[in] i_data 16 bit immediate data + * @return returns 32 bit number representing ori instruction. + */ +STATIC uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra, + const uint16_t i_data ) +{ + uint32_t oriInstOpcode = 0; + oriInstOpcode = 0; + oriInstOpcode = ORI_OPCODE << 26; + oriInstOpcode |= i_Rs << 21; + oriInstOpcode |= i_Ra << 16; + oriInstOpcode |= i_data; + + return SWIZZLE_4_BYTE(oriInstOpcode); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates 32 bit key used for SPR lookup in core section. + */ +STATIC uint32_t genKeyForSprLookup( const CpuReg_t i_regId ) +{ + return getOriInstruction( 24, 0, (uint16_t) i_regId ); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates xor instruction code. + * @param[in] i_Rs source register number for xor operation + * @param[in] i_Ra destination register number for xor operation result + * @param[in] i_Rb source register number for xor operation + * @return returns 32 bit number representing xor immediate instruction. + */ +STATIC uint32_t getXorInstruction( const uint16_t i_Ra, const uint16_t i_Rs, + const uint16_t i_Rb ) +{ + uint32_t xorRegInstOpcode; + xorRegInstOpcode = XOR_CONST << 1; + xorRegInstOpcode |= OPCODE_31 << 26; + xorRegInstOpcode |= i_Rs << 21; + xorRegInstOpcode |= i_Ra << 16; + xorRegInstOpcode |= i_Rb << 11; + + return SWIZZLE_4_BYTE(xorRegInstOpcode); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates oris instruction code. + * @param[in] i_Rs source register number + * @param[in] i_Ra destination register number + * @param[in] i_data 16 bit immediate data + * @return returns 32 bit number representing oris immediate instruction. + */ +STATIC uint32_t getOrisInstruction( const uint16_t i_Rs, const uint16_t i_Ra, + const uint16_t i_data ) +{ + uint32_t orisInstOpcode; + orisInstOpcode = 0; + orisInstOpcode = ORIS_OPCODE << 26; + orisInstOpcode |= ( i_Rs & 0x001F ) << 21 | ( i_Ra & 0x001F ) << 16; + orisInstOpcode |= i_data; + + return SWIZZLE_4_BYTE(orisInstOpcode); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mtspr + * @param[in] i_Rs source register number + * @param[in] i_Spr represents spr where data is to be moved. + * @return returns 32 bit number representing mtspr instruction. + */ +STATIC uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) +{ + uint32_t mtsprInstOpcode = 0; + uint32_t temp = (( i_Spr & 0x03FF ) << 11); + mtsprInstOpcode = (uint8_t)i_Rs << 21; + mtsprInstOpcode |= ( temp & 0x0000F800 ) << 5; + mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; + mtsprInstOpcode |= MTSPR_BASE_OPCODE; + + return SWIZZLE_4_BYTE(mtsprInstOpcode); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mfmsr + * @param[in] i_Rt target register for SPR content. + * @return returns 32 bit number representing mfmsr instruction. + */ +STATIC uint32_t getMfmsrInstruction( const uint16_t i_Rt ) +{ + uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | ((MFMSR_CONST)<< 1)); + + return SWIZZLE_4_BYTE(mfmsrInstOpcode); +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates rldicr instruction. + * @param[in] i_Rs source register number + * @param[in] i_Ra destination register number + * @param[in] i_sh bit position by which contents of i_Rs are to be shifted + * @param[in] i_me bit position up to which mask should be 1. + * @return returns 32 bit number representing rldicr instruction. + */ +STATIC uint32_t getRldicrInstruction( const uint16_t i_Ra, const uint16_t i_Rs, + const uint16_t i_sh, uint16_t i_me ) +{ + uint32_t rldicrInstOpcode = 0; + rldicrInstOpcode = ((RLDICR_OPCODE << 26 ) | ( i_Rs << 21 ) | ( i_Ra << 16 )); + rldicrInstOpcode |= ( ( i_sh & 0x001F ) << 11 ) | (RLDICR_CONST << 2 ); + rldicrInstOpcode |= (( i_sh & 0x0020 ) >> 4); + rldicrInstOpcode |= (i_me & 0x001F ) << 6; + rldicrInstOpcode |= (i_me & 0x0020 ); + return SWIZZLE_4_BYTE(rldicrInstOpcode); +} + +//----------------------------------------------------------------------------- + +STATIC uint32_t getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_sprNum ) +{ + uint32_t mfsprInstOpcode = 0; + uint32_t temp = (( i_sprNum & 0x03FF ) << 11); + mfsprInstOpcode = (uint8_t)i_Rt << 21; + mfsprInstOpcode |= (( temp & 0x0000F800 ) << 5); + mfsprInstOpcode |= (( temp & 0x001F0000 ) >> 5); + mfsprInstOpcode |= MFSPR_BASE_OPCODE; + + return SWIZZLE_4_BYTE(mfsprInstOpcode); +} + +//----------------------------------------------------------------------------- + +STATIC uint32_t getBranchLinkRegInstruction(void) +{ + uint32_t branchConstInstOpcode = 0; + branchConstInstOpcode = (( OPCODE_18 << 26 ) | ( SELF_SAVE_FUNC_ADD ) | 0x03 ); + + return SWIZZLE_4_BYTE(branchConstInstOpcode); +} +//----------------------------------------------------------------------------- + +/** + * @brief looks up entry for given SPR in given thread/core section. + * @param[in] i_pThreadSectLoc start of given thread section or core section. + * @param[in] i_lookUpKey search key for lookup of given SPR entry. + * @param[in] i_isThreadReg true if register is of scope thread, false + * otherwise. + * @param[in|out] io_pSprEntryLoc Input: NULL + * Output: location of given entry or end of table. + * @return STOP_SAVE_SUCCESS if entry is found, STOP_SAVE_FAIL in case of + * an error. + */ +STATIC StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, const uint32_t i_lookUpKey, + const bool i_isThreadReg, void** io_pSprEntryLoc ) +{ + StopReturnCode_t l_rc = STOP_SAVE_FAIL; + uint32_t temp = 0; + uint32_t* i_threadSectEnd = NULL; + uint32_t bctr_inst = SWIZZLE_4_BYTE(BLR_INST); + *io_pSprEntryLoc = NULL; + + do + { + if( !i_pThreadSectLoc ) + { + MY_ERR( "Bad SPR Start Location" ); + break; + } + + temp = i_isThreadReg ? (uint32_t)(SMF_CORE_RESTORE_THREAD_AREA_SIZE) : + (uint32_t)(SMF_CORE_RESTORE_CORE_AREA_SIZE); + + i_threadSectEnd = i_pThreadSectLoc + ( temp >> 2 ); + + temp = 0; + + while( ( i_pThreadSectLoc <= i_threadSectEnd ) && + ( temp != bctr_inst ) ) + { + temp = *i_pThreadSectLoc; + + if( ( temp == i_lookUpKey ) || ( temp == bctr_inst ) ) + { + *io_pSprEntryLoc = i_pThreadSectLoc; + l_rc = STOP_SAVE_SUCCESS; + break; + } + + i_pThreadSectLoc = i_pThreadSectLoc + SIZE_PER_SPR_RESTORE_INST; + } + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief updates an SPR STOP image entry. + * @param[in] i_pSprEntryLocation location of entry. + * @param[in] i_regId register Id associated with SPR. + * @param[in] i_regData data needs to be written to SPR entry. + * @return STOP_SAVE_SUCCESS if update works, STOP_SAVE_FAIL otherwise. + */ +STATIC StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, + const CpuReg_t i_regId, + const uint64_t i_regData, + const enum SprEntryUpdateMode i_mode + ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t tempInst = 0; + uint64_t tempRegData = 0; + bool newEntry = true; + uint16_t regRs = 0; //to use R0 for SPR restore insruction generation + uint16_t regRa = 0; + + do + { + if( !i_pSprEntryLocation ) + { + MY_ERR("invalid location of SPR image entry" ); + l_rc = STOP_SAVE_FAIL; + break; + } + + tempInst = genKeyForSprLookup( i_regId ); + + if( *i_pSprEntryLocation == tempInst ) + { + newEntry = false; + } + + //Add SPR search instruction i.e. "ori r0, r0, SPRID" + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + if( INIT_SPR_REGION == i_mode ) + { + //adding inst 'b . + 0x1C' + *i_pSprEntryLocation = SWIZZLE_4_BYTE(SKIP_SPR_REST_INST); + } + else + { + //clear R0 i.e. "xor ra, rs, rb" + tempInst = getXorInstruction( regRs, regRs, regRs ); + *i_pSprEntryLocation = tempInst; + } + + + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + tempRegData = i_regData >> 48; + //get lower order 16 bits of SPR restore value in R0 + tempInst = getOrisInstruction( regRs, regRa, (uint16_t)tempRegData ); + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + tempRegData = ((i_regData >> 32) & 0x0000FFFF ); + //get bit b16-b31 of SPR restore value in R0 + tempInst = getOriInstruction( regRs, regRa, (uint16_t)tempRegData ); + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + //Rotate R0 to left by 32 bit position and zero lower order 32 bits. + //Place the result in R0 + tempInst = getRldicrInstruction(regRa, regRs, 32, 31); + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + tempRegData = ((i_regData >> 16) & 0x000000FFFF ); + //get bit b32-b47 of SPR restore value to R0 + tempInst = getOrisInstruction( regRs, regRa, (uint16_t)tempRegData ); + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + tempRegData = (uint16_t)i_regData; + //get bit b48-b63 of SPR restore value to R0 + tempInst = getOriInstruction( regRs, regRa, (uint16_t)i_regData ); + *i_pSprEntryLocation = tempInst; + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + + if( PROC_STOP_SPR_MSR == i_regId ) + { + //MSR cannot be restored completely with mtmsrd instruction. + //as it does not update ME, LE and HV bits. In self restore code + //inorder to restore MSR, contents of R21 is moved to SRR1. It also + //executes an RFID which causes contents of SRR1 to be copied to + //MSR. This allows copy of LE bit which are specifically interested + //in. Instruction below moves contents of MSR Value (in R0 ) to R21. + tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R21 ); + } + else if ( PROC_STOP_SPR_HRMOR == i_regId ) + { + //Case HRMOR, move contents of R0 to a placeholder GPR (R10) + //Thread Launcher expects HRMOR value in R10 + tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R10 ); + } + else if( PROC_STOP_SPR_URMOR == i_regId ) + { + //Case URMOR, move contents of R0 to a placeholder GPR (R9) + //Thread Launcher expects URMOR value in R9 + tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R9 ); + } + else + { + // Case other SPRs, move contents of R0 to SPR + // For a UV system, even HRMOR is treated like any other SPR. + tempInst = + getMtsprInstruction( 0, (uint16_t)i_regId ); + } + + *i_pSprEntryLocation = tempInst; + + if( newEntry ) + { + i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; + //at the end of SPR restore, add instruction BLR to go back to thread + //launcher. + tempInst = SWIZZLE_4_BYTE(BLR_INST); + *i_pSprEntryLocation = tempInst; + } + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +STATIC StopReturnCode_t initSelfSaveEntry( void* const i_pImage, uint16_t i_sprNum ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t* i_pSprSave = (uint32_t*)i_pImage; + + //ori r0, r0, 0x00nn + *i_pSprSave = getOriInstruction( 0, 0, i_sprNum ); + + i_pSprSave++; + + //addi r31, r31, 0x20 + *i_pSprSave = SWIZZLE_4_BYTE(SKIP_SPR_SELF_SAVE); + i_pSprSave++; + + //nop + *i_pSprSave = getOriInstruction( 0, 0, 0 );; + i_pSprSave++; + + //mtlr, r30 + *i_pSprSave = SWIZZLE_4_BYTE( MTLR_INST ); + i_pSprSave++; + + //blr + *i_pSprSave = SWIZZLE_4_BYTE(BLR_INST); + i_pSprSave++; + + return l_rc; +} + +//----------------------------------------------------------------------------- + +STATIC StopReturnCode_t getSprRegIndexAdjustment( const uint32_t i_saveMaskPos, uint32_t* i_sprAdjIndex ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + + do + { + if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_20 )) || + (( i_saveMaskPos >= SPR_BIT_POS_25 ) && ( i_saveMaskPos <= SPR_BIT_POS_27 )) ) + { + l_rc = STOP_SAVE_SPR_BIT_POS_RESERVE; + break; + } + + if( (i_saveMaskPos > SPR_BIT_POS_20) && (i_saveMaskPos < SPR_BIT_POS_25) ) + { + *i_sprAdjIndex = 12; + } + else if( i_saveMaskPos > SPR_BIT_POS_27 ) + { + *i_sprAdjIndex = 15; + } + else + { + *i_sprAdjIndex = 0; + } + + } + while(0); + + return l_rc; +} + + +//----------------------------------------------------------------------------- + +/** + * @brief returns core region and relative id wrt to quad + * @param[in] i_scomAddress scom address associated with a core + * @param[in] o_scomRegion SCOM region in HOMER + * @param[in] o_coreRelativeInst core relative id + * @return STOP_SAVE_SUCCESS if function succeeds, error code otherwise + */ +STATIC StopReturnCode_t decodeScomAddress( const uint32_t i_scomAddress, uint32_t * o_scomRegion, + uint32_t * o_coreRelativeInst ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t l_regionSelect = ( i_scomAddress & CORE_REGION_MASK ); + uint32_t l_endPoint = ( i_scomAddress & EP_SELECT_MASK ); + l_endPoint = ( l_endPoint >> 16 ); + l_regionSelect = l_regionSelect >> 12; + + if( 1 == l_endPoint ) + { + *o_scomRegion = PROC_STOP_SECTION_L3; + } + else if ( 2 == l_endPoint ) + { + *o_scomRegion = PROC_STOP_SECTION_CORE; + } + + switch( l_regionSelect ) + { + case 8: + *o_coreRelativeInst = 0; + break; + + case 4: + *o_coreRelativeInst = 1; + break; + + case 2: + *o_coreRelativeInst = 2; + break; + + case 1: + *o_coreRelativeInst = 3; + break; + + default: + l_rc = STOP_SAVE_SCOM_INVALID_ADDRESS; + break; + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief validates all the input arguments. + * @param[in] i_pImage pointer to start of HOMER of image for proc chip. + * @param[in] i_scomAddress SCOM address of register. + * @param[in] i_chipletId core or cache chiplet id + * @param[in] i_operation operation requested for SCOM entry. + * @param[in] i_section image section on which operation is to be performed + * @return STOP_SAVE_SUCCESS if arguments found valid, error code otherwise. + * @note Function does not validate that the given SCOM address really + * belongs to the given section. + */ +STATIC StopReturnCode_t validateScomImageInputs( void* const i_pImage, + const uint32_t i_scomAddress, + const uint8_t i_chipletId, + const ScomOperation_t i_operation, + const ScomSection_t i_section ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t l_scomRegion = 0; + uint32_t l_coreId = 0; + + do + { + if( !i_pImage ) + { + //Error Invalid image pointer + l_rc = STOP_SAVE_ARG_INVALID_IMG; + MY_ERR("invalid image location "); + break; + } + + if( 0 == i_scomAddress ) + { + l_rc = STOP_SAVE_SCOM_INVALID_ADDRESS; + MY_ERR("invalid SCOM address"); + break; + } + + if(( CACHE_CHIPLET_ID_MIN > i_chipletId ) || + ( CACHE_CHIPLET_ID_MAX < i_chipletId )) + { + l_rc = STOP_SAVE_SCOM_INVALID_CHIPLET; + MY_ERR("chiplet id not valid"); + break; + } + + if(( PROC_STOP_SCOM_OP_MIN >= i_operation ) || + ( PROC_STOP_SCOM_OP_MAX <= i_operation )) + { + //invalid SCOM image operation requested + l_rc = STOP_SAVE_SCOM_INVALID_OPERATION; + MY_ERR("invalid SCOM image operation"); + break; + } + + l_rc = decodeScomAddress( i_scomAddress, &l_scomRegion, &l_coreId ); + + if( l_rc ) + { + MY_ERR( "Bad Scom Address 0x%08x", i_chipletId ); + break; + } + + if( PROC_STOP_SECTION_CORE == l_scomRegion ) + { + if( ( i_section != PROC_STOP_SECTION_CORE ) || + ( i_section != PROC_STOP_SECTION_L2 ) ) + { + MY_ERR( "SCOM adress doesn't match with section type passed," + " EP : %d , Section Type %d", l_scomRegion, i_section ); + l_rc = STOP_SAVE_SCOM_INVALID_SECTION; + break; + } + } + + if( PROC_STOP_SECTION_L3 == l_scomRegion ) + { + if( ( i_section != PROC_STOP_SECTION_L3 ) || + ( i_section != PROC_STOP_SECTION_CACHE ) ) + { + MY_ERR( "SCOM adress doesn't match with section type passed," + " EP : %d , Section Type %d", l_scomRegion, i_section ); + l_rc = STOP_SAVE_SCOM_INVALID_SECTION; + break; + } + } + } + while(0); + + if( l_rc ) + { + MY_ERR("SCOMAddress 0x%08x chipletId 0x%08x operation" + "0x%08x section 0x%08x", i_scomAddress, i_chipletId, + i_operation, i_section ); + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief determines HOMER region for SCOM restore entry request. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_sectn SCOM restore section + * @param[in] i_instanceId core instance id + * @param[out]o_entryDat meta data pertaining to SCOM restore entry analysis + * @return STOP_SAVE_SUCCESS if HWP succeeds, error code otherwise. + */ +STATIC StopReturnCode_t lookUpScomRestoreRegion( void * i_pImage, const ScomSection_t i_sectn, uint32_t i_instanceId, + ScomEntryDat_t * o_entryDat ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + CpmrHeader_t * l_pCpmrHdr = NULL; + ScomRestoreHeader_t *l_scomHdr = NULL; + uint32_t l_relativeCorePos = 0; + uint32_t l_offset = 0; + uint32_t l_quadId = 0; + uint32_t l_scomLen = 0; + + MY_INF( ">>lookUpScomRestoreRegion" ); + + o_entryDat->iv_subRegionBaseOffset = 0; + o_entryDat->iv_subRegionLength = 0; + l_quadId = ( i_instanceId >> 2 ); + + l_relativeCorePos = i_instanceId % MAX_CORES_PER_QUAD; + l_pCpmrHdr = ( CpmrHeader_t *) ( (uint8_t *) i_pImage + CPMR_HOMER_OFFSET ); + l_scomLen = SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxCoreL2ScomEntry) + + SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxEqL3ScomEntry); + l_scomLen = ( l_scomLen * SCOM_RESTORE_ENTRY_SIZE ); + + l_offset = ( l_scomLen * l_quadId * MAX_CORES_PER_QUAD ) + SCOM_RESTORE_HOMER_OFFSET; + + MY_INF( "QUAD_ID 0x%08x BASE OFFSET 0x%08x", l_quadId, l_offset ); + + l_scomHdr = ( ScomRestoreHeader_t *) ( (uint8_t *) i_pImage + l_offset ); + + if( ( PROC_STOP_SECTION_CORE == i_sectn ) || ( PROC_STOP_SECTION_L2 == i_sectn ) ) + { + MY_INF( "Core Offset 0x%04x", SWIZZLE_2_BYTE(l_scomHdr->iv_coreOffset) ); + l_offset += SWIZZLE_2_BYTE(l_scomHdr->iv_coreOffset); + o_entryDat->iv_subRegionLength = SWIZZLE_2_BYTE(l_scomHdr->iv_coreLength); + l_offset += ( SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxCoreL2ScomEntry) * l_relativeCorePos ); + } + else if( ( PROC_STOP_SECTION_L3 == i_sectn ) || ( PROC_STOP_SECTION_CACHE == i_sectn ) ) + { + MY_INF( "Cache Offset 0x%04x", SWIZZLE_2_BYTE(l_scomHdr->iv_l3Offset) ); + l_offset += SWIZZLE_2_BYTE(l_scomHdr->iv_l3Offset); + o_entryDat->iv_subRegionLength = SWIZZLE_2_BYTE(l_scomHdr->iv_l3Length); + l_offset += ( SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxEqL3ScomEntry) * l_relativeCorePos ); + } + else + { + o_entryDat->iv_subRegionBaseOffset = 0; + l_rc = STOP_SAVE_SCOM_INVALID_SECTION; + } + + if( !l_rc ) + { + o_entryDat->iv_subRegionBaseOffset = l_offset; + } + + MY_INF( "SCOM Section Offset 0x%08x", l_offset ); + + MY_INF( "<> lookUpScomRestoreEntry" ); + + o_pScomDat->iv_slotFound = 0x00; + o_pScomDat->iv_entryOffset = 0x00; + o_pScomDat->iv_lastEntryOffset = 0x00; + o_pScomDat->iv_entryMatchOffset = 0x00; + o_pScomDat->iv_matchFound = 0x00; + l_pCpmrHdr = ( CpmrHeader_t * ) ( (uint8_t *) i_pImage + CPMR_HOMER_OFFSET ); + l_pScomByte = ( uint8_t * )( (uint8_t *) i_pImage + o_pScomDat->iv_subRegionBaseOffset ); + l_pScom = (ScomEntry_t *)( l_pScomByte ); + + switch( i_sectn ) + { + case PROC_STOP_SECTION_CORE: + l_entryLimit = SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxCoreL2ScomEntry); + break; + + case PROC_STOP_SECTION_L3: + l_entryLimit = SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxEqL3ScomEntry); + break; + + default: + l_rc = STOP_SAVE_SCOM_INVALID_SECTION; + break; + } + + if( l_rc ) + { + return l_rc; + } + + for( l_entry = 0; l_entry < l_entryLimit; l_entry++ ) + { + if( !( l_pScom->iv_scomAddress & SWIZZLE_4_BYTE(SCOM_ENTRY_VALID) ) ) + { + o_pScomDat->iv_slotFound = 0x01; + o_pScomDat->iv_entryOffset = l_entry; + break; + } + + l_pScom++; + } + + l_pScom = (ScomEntry_t *)( l_pScomByte ); + + for( l_entry = 0; l_entry < l_entryLimit; l_entry++ ) + { + if( l_pScom->iv_scomAddress & SWIZZLE_4_BYTE(LAST_SCOM_ENTRY) ) + { + o_pScomDat->iv_lastEntryOffset = l_entry; + MY_INF( "SCOM Restore Entry Limit 0x%08x", + o_pScomDat->iv_lastEntryOffset ); + break; + } + l_pScom++; + } + + l_pScom = (ScomEntry_t *)( l_pScomByte ); + + for( l_entry = 0; l_entry < l_entryLimit; l_entry++ ) + { + l_temp = l_pScom->iv_scomAddress & SWIZZLE_4_BYTE(SCOM_ADDR_MASK); + + if( SWIZZLE_4_BYTE((i_scomAddress & SCOM_ADDR_MASK)) == l_temp ) + { + o_pScomDat->iv_entryMatchOffset = l_entry; + o_pScomDat->iv_matchFound = 0x01; + MY_INF( "Existing Entry Slot No 0x%08x", l_entry ); + break; + } + l_pScom++; + } + + o_pScomDat->iv_entryLimit = l_entryLimit; + + MY_INF( "<< lookUpScomRestoreEntry" ); + return l_rc; +} + +//----------------------------------------------------------------------------- + +#define UNUSED(x) (void)(x) + +/** + * @brief edits a SCOM restore entry associated with the given core. + * @param[in] i_pScom points to SCOM restore location + * @param[in] i_scomAddr SCOM address of register. + * @param[in] i_scomData data associated with SCOM register. + * @param[in] i_operation operation to be performed on SCOM entry. + * @param[in] i_pScomDat points to meta data associated with entry analysis + * @return STOP_SAVE_SUCCESS if existing entry is updated, STOP_SAVE_FAIL + * otherwise. + */ +STATIC StopReturnCode_t editScomEntry( uint8_t * i_pScom, uint32_t i_scomAddr, + uint64_t i_scomData, ScomOperation_t i_operation, + ScomEntryDat_t * i_pScomDat ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + ScomEntry_t * l_pScom = (ScomEntry_t *)i_pScom; + UNUSED(i_scomAddr); + + MY_INF( ">> editScomEntry " ); + + l_pScom = l_pScom + i_pScomDat->iv_entryMatchOffset; + + switch( i_operation ) + { + case PROC_STOP_SCOM_OR: + case PROC_STOP_SCOM_OR_APPEND: + l_pScom->iv_scomData |= SWIZZLE_8_BYTE(i_scomData); + break; + + case PROC_STOP_SCOM_AND: + case PROC_STOP_SCOM_AND_APPEND: + l_pScom->iv_scomData &= SWIZZLE_8_BYTE(i_scomData); + break; + + case PROC_STOP_SCOM_REPLACE: + l_pScom->iv_scomData = SWIZZLE_8_BYTE(i_scomData); + break; + + default: + break; + } + + MY_INF( "<< editScomEntry " ); + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief update SCOM restore entry list associated with the given core. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_scomAddr address of SCOM register. + * @param[in] i_scomData data associated with SCOM register. + * @param[in] i_sectn SCOM restore section in HOMER. + * @param[in] i_operation operation type requested on restore entry. + * @param[in] i_pScomDat points entry analysis meta data. + * @return STOP_SAVE_SUCCESS if new entry is added, STOP_SAVE_FAIL otherwise. + */ +STATIC StopReturnCode_t updateScomEntry( void * i_pImage, uint32_t i_scomAddr, + uint64_t i_scomData, const ScomSection_t i_sectn, + ScomOperation_t i_operation, ScomEntryDat_t * i_pScomDat ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + CpmrHeader_t * l_pCpmrHdr = NULL; + ScomEntry_t * l_pScom = NULL; + uint32_t l_maxScomEntry = 0; + l_pCpmrHdr = ( CpmrHeader_t * ) ( (uint8_t *) i_pImage + CPMR_HOMER_OFFSET ); + l_pScom = ( ScomEntry_t * )( (uint8_t *) i_pImage + i_pScomDat->iv_subRegionBaseOffset ); + switch( i_operation ) + { + case PROC_STOP_SCOM_OR_APPEND: + case PROC_STOP_SCOM_AND_APPEND: + case PROC_STOP_SCOM_APPEND: + case PROC_STOP_SCOM_REPLACE: + + l_pScom = l_pScom + i_pScomDat->iv_lastEntryOffset; + + if( i_pScomDat->iv_entryLimit > i_pScomDat->iv_lastEntryOffset ) + { + l_pScom->iv_scomAddress &= ~(SWIZZLE_LAST_SCOM_ENTRY); + l_pScom++; // takes us to offset stored in iv_entryOffset + l_pScom->iv_scomAddress = i_scomAddr & SCOM_ADDR_MASK; + l_pScom->iv_scomAddress |= (SCOM_ENTRY_VALID | LAST_SCOM_ENTRY | SCOM_ENTRY_VER); + + if( PROC_STOP_SECTION_CORE == i_sectn ) + { + l_maxScomEntry = SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxCoreL2ScomEntry); + l_pScom->iv_scomAddress |= CORE_SECTION_ID_CODE; + } + else + { + l_maxScomEntry = SWIZZLE_4_BYTE(l_pCpmrHdr->iv_maxEqL3ScomEntry); + l_pScom->iv_scomAddress |= L3_SECTION_ID_CODE; + } + + l_pScom->iv_scomAddress |= ( l_maxScomEntry << MAX_SCOM_ENTRY_POS ); + l_pScom->iv_scomAddress = SWIZZLE_4_BYTE(l_pScom->iv_scomAddress); + l_pScom->iv_scomData = SWIZZLE_8_BYTE(i_scomData); + + MY_INF( "SCOM Data 0x%08x", SWIZZLE_4_BYTE(l_pScom->iv_scomAddress) ); + } + else + { + MY_ERR( "Current Entry Count 0x%08x More than Max Entry Count 0x%08x", + i_pScomDat->iv_lastEntryOffset, i_pScomDat->iv_entryLimit ); + l_rc = STOP_SAVE_MAX_ENTRY_REACHED; + } + + break; + default: + break; + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_sprBitPos bit position associated with SPR in save mask vector. + * @param[in] i_pSprSaveStart start location of SPR save segment + * @param[in] i_searchLength length of SPR save segment + * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* i_pSprSaveStart, + uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) +{ + int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); + uint32_t l_oriInst = getOriInstruction( 0, 0, i_sprBitPos ); + StopReturnCode_t l_rc = STOP_SAVE_FAIL; + + while( l_saveWordLength > 0 ) + { + if( l_oriInst == *i_pSprSaveStart ) + { + *i_pSaveSprLoc = i_pSprSaveStart; + l_rc = STOP_SAVE_SUCCESS; + break; + } + + i_pSprSaveStart++; + l_saveWordLength--; + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_pSaveReg start of editable location of a SPR save entry. + * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + + do + { + if( !i_pSaveReg ) + { + l_rc = STOP_SAVE_FAIL; + MY_ERR( "Failed to update self save area for SPR 0x%04x", i_sprNum ); + break; + } + + if( PROC_STOP_SPR_MSR == i_sprNum ) + { + *i_pSaveReg = getMfmsrInstruction( 1 ); + } + else + { + *i_pSaveReg = getMfsprInstruction( 1, i_sprNum ); + } + + i_pSaveReg++; + + *i_pSaveReg = getBranchLinkRegInstruction( ); + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +{ + + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t* l_pRestoreStart = NULL; + void* l_pTempLoc = NULL; + Homerlayout_t* l_pHomer = NULL; + SmfSprRestoreRegion_t * l_pSprRest = NULL; + uint32_t l_threadPos = 0; + uint32_t l_lookUpKey = 0; + uint32_t l_sprIndex = 0; + + MY_INF( ">> proc_stop_init_cpureg" ); + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + if( i_corePos > MAX_CORE_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_CORE; + break; + } + + l_pHomer = ( Homerlayout_t * ) i_pImage; + + for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED_P10; l_sprIndex++ ) + { + //Check if a given SPR needs to be self-saved each time on STOP entry + + l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister_p10[l_sprIndex].iv_sprId ); + l_pSprRest = + ( SmfSprRestoreRegion_t * ) &l_pHomer->iv_cpmrRegion.iv_selfRestoreRegion.iv_coreSelfRestore[0]; + + l_pSprRest += i_corePos; + + if( g_sprRegister_p10[l_sprIndex].iv_isThreadScope ) + { + for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) + { + l_pRestoreStart = + (uint32_t*)&l_pSprRest->iv_threadRestoreArea[l_threadPos][0]; + + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister_p10[l_sprIndex].iv_isThreadScope, + &l_pTempLoc ); + + if( l_rc ) + { + MY_ERR( "Thread SPR lookup failed in proc_stop_init_cpureg SPR %d Core %d Thread %d Index %d", + g_sprRegister_p10[l_sprIndex].iv_sprId, i_corePos, l_threadPos, l_sprIndex ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister_p10[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Thread SPR region init failed. Core %d SPR Id %d", + i_corePos, g_sprRegister_p10[l_sprIndex].iv_sprId ); + break; + } + + }//end for thread + + if( l_rc ) + { + break; + } + + }//end if SPR threadscope + else + { + l_pRestoreStart = (uint32_t*)&l_pSprRest->iv_coreRestoreArea[0]; + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister_p10[l_sprIndex].iv_isThreadScope, &l_pTempLoc ); + + if( l_rc ) + { + MY_ERR( "Core SPR lookup failed in proc_stop_init_cpureg" ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister_p10[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Core SPR region init failed. Core %d SPR Id %d SPR Index %d", + i_corePos, g_sprRegister_p10[l_sprIndex].iv_sprId, l_sprIndex ); + break; + } + + }// end else + + }// end for l_sprIndex + + } + while(0); + + MY_INF( "<< proc_stop_init_cpureg" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t l_quadId = 0; + uint32_t l_coreId = 0; + uint32_t l_coreRegion = 0; + uint8_t * l_pScom = NULL; + ScomEntryDat_t l_entryDat; + + MY_INF( ">> proc_stop_save_scom" ); + + do + { + l_quadId = i_scomAddress >> 24; + l_quadId = l_quadId & 0x3F; + + l_rc = validateScomImageInputs( i_pImage, i_scomAddress, + l_quadId, i_operation, i_section ); + if( l_rc ) + { + MY_ERR( "invalid argument: aborting"); + break; + } + + l_rc = decodeScomAddress( i_scomAddress, &l_coreRegion, &l_coreId ); + + if( l_rc ) + { + MY_ERR( "Failed To get Core Details For Address 0x%08x", i_scomAddress ); + break; + } + + //Converting Superchiplet Id to instance number + l_quadId = l_quadId - MIN_SUPERCHIPLET_ID; + + //getting core position relative to the chip + l_coreId += ( l_quadId << 2 ); + + MY_INF( "Quad Id 0x%08x COre Id 0x%08x", l_quadId, l_coreId ); + + // Let us find the start address of SCOM area + + l_rc = lookUpScomRestoreRegion( i_pImage, + i_section, + l_coreId, + &l_entryDat ); + if( l_rc ) + { + MY_ERR( "Failed To Find SCOM Section Requested 0x%08x", + ( uint32_t) i_section ); + break; + } + + l_pScom = (uint8_t *)( (uint8_t *)i_pImage + l_entryDat.iv_subRegionBaseOffset ); + + l_rc = lookUpScomRestoreEntry( i_pImage, + i_section, + i_scomAddress, + &l_entryDat ); + if( l_rc ) + { + MY_ERR( "Failed To Find SCOM Entry Slot 0x%08x", (uint32_t) l_rc ); + break; + } + + switch( i_operation ) + { + case PROC_STOP_SCOM_APPEND: + l_rc = updateScomEntry( i_pImage, + i_scomAddress, + i_scomData, + i_section, + i_operation, + &l_entryDat ); + break; + + case PROC_STOP_SCOM_OR: + case PROC_STOP_SCOM_AND: + //case PROC_STOP_SCOM_NOOP: + + if( l_entryDat.iv_matchFound ) + { + l_rc = editScomEntry( l_pScom, + i_scomAddress, + i_scomData, + i_operation, + &l_entryDat ); + } + + break; + + case PROC_STOP_SCOM_RESET: + + l_rc = lookUpScomRestoreRegion( i_pImage, + PROC_STOP_SECTION_CORE, + l_coreId, + &l_entryDat ); + if( l_rc ) + { + MY_ERR( "Failed To Reset SCOM Section Requested 0x%08x", + ( uint32_t) i_section ); + break; + } + + memset( (uint8_t *)((uint8_t *)i_pImage + l_entryDat.iv_subRegionBaseOffset), + 0x00, l_entryDat.iv_subRegionLength ); + + l_rc = lookUpScomRestoreRegion( i_pImage, + PROC_STOP_SECTION_CACHE, + l_coreId, + &l_entryDat ); + if( l_rc ) + { + MY_ERR( "Failed To Reset SCOM Section Requested 0x%08x", + ( uint32_t) i_section ); + break; + } + + memset( (uint8_t *)((uint8_t *)i_pImage + l_entryDat.iv_subRegionBaseOffset), + 0x00, l_entryDat.iv_subRegionLength ); + + break; + + case PROC_STOP_SCOM_OR_APPEND: + case PROC_STOP_SCOM_AND_APPEND: + case PROC_STOP_SCOM_REPLACE: + + if( l_entryDat.iv_matchFound ) + { + l_rc = editScomEntry( l_pScom, + i_scomAddress, + i_scomData, + i_operation, + &l_entryDat ); + } + else + { + l_rc = updateScomEntry( i_pImage, + i_scomAddress, + i_scomData, + i_section, + i_operation, + &l_entryDat ); + } + + break; + + default: + l_rc = STOP_SAVE_SCOM_INVALID_OPERATION; + break; + } + } + while(0); + + if( l_rc ) + { + MY_ERR("SCOM image operation 0x%08x failed for chiplet 0x%08x addr" + "0x%08x", i_operation, l_quadId , + i_scomAddress ); + } + else + { + + } + + MY_INF( "<< proc_stop_save_scom" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t l_coreId = 0; + uint32_t l_threadId = 0; + uint32_t l_sprPos = 0; + uint32_t l_sprIndex = 0; + uint32_t l_lookupLength = 0; + uint32_t l_lookUpKey = 0; + uint32_t* l_pSaveStart = NULL; + uint32_t* l_pRestoreStart = NULL; + uint32_t* l_pSprSave = NULL; + void* l_pTempLoc = NULL; + uint32_t * l_pTempWord = NULL; + Homerlayout_t* l_pHomer = NULL; + SmfSprRestoreRegion_t * l_pSpr = NULL; + MY_INF(">> proc_stop_save_cpureg_control" ); + + do + { + l_rc = getCoreAndThread_p10( i_pImage, i_pir, &l_coreId, &l_threadId ); + + if( l_rc ) + { + MY_ERR( "Error in getting core no 0x%08x and thread no 0x%08x from PIR 0x%016lx", + l_coreId, l_threadId, i_pir ); + break; + } + + l_rc = validateArgumentSaveRegMask( i_pImage, l_coreId, l_threadId, i_saveRegVector ); + + if( l_rc ) + { + MY_ERR( "Invalid argument rc 0x%08x", (uint32_t) l_rc ); + break; + } + + l_pHomer = ( Homerlayout_t * )i_pImage; + l_pSpr = ( SmfSprRestoreRegion_t *) &l_pHomer->iv_cpmrRegion.iv_selfRestoreRegion.iv_coreSelfRestore[0]; + l_pSpr += l_coreId; + + for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED_P10; l_sprIndex++ ) + { + l_sprPos = g_sprRegister_p10[l_sprIndex].iv_saveMaskPos; + + if( l_sprPos > MAX_SPR_BIT_POS ) + { + continue; + } + + //Check if a given SPR needs to be self-saved each time on STOP entry + + if( i_saveRegVector & ( TEST_BIT_PATTERN >> l_sprPos ) ) + { + + if( g_sprRegister_p10[l_sprIndex].iv_isThreadScope ) + { + l_lookupLength = SMF_SELF_SAVE_THREAD_AREA_SIZE; + l_pSaveStart = + (uint32_t*)&l_pSpr->iv_threadSaveArea[l_threadId][0]; + l_pRestoreStart = + (uint32_t*)&l_pSpr->iv_threadRestoreArea[l_threadId][0]; + } + else + { + l_lookupLength = SMF_CORE_SAVE_CORE_AREA_SIZE; + l_pSaveStart = (uint32_t*)&l_pSpr->iv_coreSaveArea[0]; + l_pRestoreStart = (uint32_t*)&l_pSpr->iv_coreRestoreArea[0]; + } + + // an SPR restore section for given core already exists + l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister_p10[l_sprIndex].iv_sprId ); + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister_p10[l_sprIndex].iv_isThreadScope, &l_pTempLoc ); + + if( l_rc ) + { + //SPR specified in the save mask but there is no restore entry present in the memory + //Self-Save instruction will edit it during STOP entry to make it a valid entry + + l_rc = proc_stop_save_cpureg( i_pImage, + (CpuReg_t)g_sprRegister_p10[l_sprIndex].iv_sprId, + 0x00, //creates a dummy entry + i_pir ); + } + + //Find if SPR-Save eye catcher exist in self-save segment of SPR restore region. + l_rc = lookUpSelfSaveSpr( l_sprPos, l_pSaveStart, l_lookupLength, &l_pSprSave ); + + if( l_rc ) + { + MY_INF( "Failed to find SPR No %02d save entry", l_sprPos ); + l_rc = STOP_SAVE_SPR_ENTRY_MISSING; + break; + } + + l_pSprSave++; //point to next instruction location + + //update specific instructions of self save region to enable saving for SPR + l_rc = updateSelfSaveEntry( l_pSprSave, g_sprRegister_p10[l_sprIndex].iv_sprId ); + + if( l_rc ) + { + MY_ERR( "Failed to update self save instructions for 0x%08x", + (uint32_t) g_sprRegister_p10[l_sprIndex].iv_sprId ); + } + + if( l_pTempLoc ) + { + l_pTempWord = (uint32_t *)l_pTempLoc; + l_pTempWord++; + *l_pTempWord = getXorInstruction( 0, 0, 0 ); + } + + }// end if( i_saveRegVector..) + }// end for + } + while(0); + + MY_INF("<< proc_stop_save_cpureg_control" ); + + return l_rc; + +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; // procedure return code + SmfSprRestoreRegion_t* l_sprRegion = NULL; + Homerlayout_t* l_pHomer = NULL; + + MY_INF(">> proc_stop_save_cpureg" ); + + do + { + uint32_t threadId = 0; + uint32_t coreId = 0; + uint32_t lookUpKey = 0; + void* pSprEntryLocation = NULL; // an offset w.r.t. to start of image + void* pThreadLocation = NULL; + bool threadScopeReg = false; + + l_rc = getCoreAndThread_p10( i_pImage, i_pir, &coreId, &threadId ); + + if( l_rc ) + { + MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016lx", + i_pir); + break; + } + + MY_INF( " PIR 0x%016lx coreId %d threadid %d " + " registerId %d", i_pir, coreId, + threadId, i_regId ); + + // First of all let us validate all input arguments. + l_rc = validateSprImageInputs( i_pImage, + i_regId, + coreId, + &threadId, + &threadScopeReg ); + if( l_rc ) + { + // Error: bad argument traces out error code + MY_ERR("Bad input argument rc %d", l_rc ); + + break; + } + + + l_pHomer = ( Homerlayout_t *) i_pImage; + l_sprRegion = ( SmfSprRestoreRegion_t* )&l_pHomer->iv_cpmrRegion.iv_selfRestoreRegion.iv_coreSelfRestore[0]; + l_sprRegion += coreId; + + if( threadScopeReg ) + { + pThreadLocation = (uint32_t *)&l_sprRegion->iv_threadRestoreArea[threadId][0]; + } + else + { + pThreadLocation = (uint32_t *)&l_sprRegion->iv_coreRestoreArea[0]; + } + + if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) || + ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) ) + { + // table for given core id doesn't exit. It needs to be + // defined. + pSprEntryLocation = pThreadLocation; + } + else + { + // an SPR restore section for given core already exists + lookUpKey = genKeyForSprLookup( i_regId ); + l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, + lookUpKey, + threadScopeReg, + &pSprEntryLocation ); + } + + if( l_rc ) + { + MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId " + "0x%08x regId 0x%08x lookUpKey 0x%08x " + , coreId, threadId, i_regId, lookUpKey ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) pSprEntryLocation, + i_regId, + i_regData, + UPDATE_SPR_ENTRY ); + + if( l_rc ) + { + MY_ERR( " Failed to update the SPR entry of PIR 0x%016lx reg" + "0x%08x", (uint64_t)i_pir, i_regId ); + break; + } + + } + while(0); + + MY_INF("<< proc_stop_save_cpureg" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) +{ + + SmfSprRestoreRegion_t * l_pSelfSave = NULL; + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t* l_pSaveStart = NULL; + Homerlayout_t * l_pHomer = NULL; + uint32_t l_threadPos = 0; + uint32_t l_sprBitPos = 0; + uint32_t l_sprIndexAdj = 0; + + MY_INF(">> proc_stop_init_self_save" ); + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + if( i_corePos > MAX_CORE_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_CORE; + break; + } + + l_pHomer = ( Homerlayout_t* ) i_pImage; + l_pSelfSave = + ( SmfSprRestoreRegion_t *) &l_pHomer->iv_cpmrRegion.iv_selfRestoreRegion.iv_coreSelfRestore[0]; + + l_pSelfSave += i_corePos; + + for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) + { + l_pSaveStart = + (uint32_t*)&l_pSelfSave->iv_threadSaveArea[l_threadPos][0]; + + //Adding instruction 'mflr r30' + *l_pSaveStart = SWIZZLE_4_BYTE(MFLR_R30); + l_pSaveStart++; + + for( l_sprBitPos = 0; l_sprBitPos <= MAX_SPR_BIT_POS; l_sprBitPos++ ) + { + l_rc = getSprRegIndexAdjustment( l_sprBitPos, &l_sprIndexAdj ); + + if( STOP_SAVE_SPR_BIT_POS_RESERVE == l_rc ) + { + //Failed to find SPR index adjustment + continue; + } + + if( !g_sprRegister_p10[l_sprBitPos - l_sprIndexAdj].iv_isThreadScope ) + { + continue; + } + + //Initialize self save region with SPR save entry for each thread + //level SPR + l_rc = initSelfSaveEntry( l_pSaveStart, + g_sprRegister_p10[l_sprBitPos - l_sprIndexAdj].iv_saveMaskPos ); + + if( l_rc ) + { + MY_ERR( "Failed to init thread self-save region for core %d thread %d", + i_corePos, l_threadPos ); + break; + } + + l_pSaveStart++; + l_pSaveStart++; + l_pSaveStart++; + } + + }// for thread = 0; + + if( l_rc ) + { + //breakout if saw an error while init of thread SPR region + break; + } + + l_pSaveStart = + (uint32_t*)&l_pSelfSave->iv_coreSaveArea[0]; + + *l_pSaveStart = SWIZZLE_4_BYTE(MFLR_R30); + l_pSaveStart++; + + for( l_sprBitPos = 0; l_sprBitPos <= MAX_SPR_BIT_POS; l_sprBitPos++ ) + { + l_rc = getSprRegIndexAdjustment( l_sprBitPos, &l_sprIndexAdj ); + + if( STOP_SAVE_SPR_BIT_POS_RESERVE == l_rc ) + { + //Failed to find SPR index adjustment + continue; + } + + if( g_sprRegister_p10[l_sprBitPos - l_sprIndexAdj].iv_isThreadScope ) + { + continue; + } + + //Initialize self save region with SPR save entry for each core + //level SPR + l_rc = initSelfSaveEntry( l_pSaveStart, + g_sprRegister_p10[l_sprBitPos - l_sprIndexAdj].iv_saveMaskPos ); + + if( l_rc ) + { + MY_ERR( "Failed to init core self-save region for core %d thread %d", + i_corePos, l_threadPos ); + break; + } + + l_pSaveStart++; + l_pSaveStart++; + l_pSaveStart++; + } + } + while(0); + + MY_INF("<< proc_stop_init_self_save" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- +#ifdef __cplusplus +} //namespace stopImageSection ends +} //extern "C" +#endif diff --git a/libpore/p10_stop_api.H b/libpore/p10_stop_api.H new file mode 100644 index 000000000..a70d2b281 --- /dev/null +++ b/libpore/p10_stop_api.H @@ -0,0 +1,238 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/utils/stopreg/p10_stop_api.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2021 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __P10_STOP_IMAGE_API_ +#define __P10_STOP_IMAGE_API_ + +#include + +#ifdef __SKIBOOT__ + #include +#endif + +/// +/// @file p10_stop_api.H +/// @brief describes STOP API which create/manipulate STOP image. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP + +#ifdef __cplusplus +namespace stopImageSection +{ +#endif + +/** + * @brief all SPRs and MSR for which register restore is to be supported. + * @note STOP API design has built in support to accomodate 8 register of + * scope core and thread each. + */ +typedef enum +{ + PROC_STOP_SPR_DAWR = 180, // thread register + PROC_STOP_SPR_CIABR = 187, // thread register + PROC_STOP_SPR_DAWRX = 188, // thread register + PROC_STOP_SPR_HSPRG0 = 304, // thread register + PROC_STOP_SPR_HRMOR = 313, // core register + PROC_STOP_SPR_LPCR = 318, // thread register + PROC_STOP_SPR_HMEER = 337, // core register + PROC_STOP_SPR_PTCR = 464, // core register + PROC_STOP_SPR_USPRG0 = 496, // thread register + PROC_STOP_SPR_USPRG1 = 497, // thread register + PROC_STOP_SPR_URMOR = 505, // core register + PROC_STOP_SPR_SMFCTRL = 511, // thread register + PROC_STOP_SPR_LDBAR = 850, // thread register + PROC_STOP_SPR_PSSCR = 855, // thread register + PROC_STOP_SPR_PMCR = 884, // core register + PROC_STOP_SPR_HID = 1008, // core register + PROC_STOP_SPR_MSR = 2000, // thread register + +} CpuReg_t; + +/** + * @brief lists all the bad error codes. + */ +typedef enum +{ + STOP_SAVE_SUCCESS = 0, + STOP_SAVE_ARG_INVALID_IMG = 1, + STOP_SAVE_ARG_INVALID_REG = 2, + STOP_SAVE_ARG_INVALID_THREAD = 3, + STOP_SAVE_ARG_INVALID_MODE = 4, + STOP_SAVE_ARG_INVALID_CORE = 5, + STOP_SAVE_SPR_ENTRY_NOT_FOUND = 6, + STOP_SAVE_SPR_ENTRY_UPDATE_FAILED = 7, + STOP_SAVE_SCOM_INVALID_OPERATION = 8, + STOP_SAVE_SCOM_INVALID_SECTION = 9, + STOP_SAVE_SCOM_INVALID_ADDRESS = 10, + STOP_SAVE_SCOM_INVALID_CHIPLET = 11, + STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED = 12, + STOP_SAVE_INVALID_FUSED_CORE_STATUS = 13, + STOP_SAVE_FAIL = 14, // for internal failure within firmware. + STOP_SAVE_SPR_ENTRY_MISSING = 15, + STOP_SAVE_MAX_ENTRY_REACHED = 16, + STOP_SAVE_SPR_BIT_POS_RESERVE = 17, +} StopReturnCode_t; + +/** + * @brief summarizes all operations supported on scom entries of STOP image. + */ +typedef enum +{ + //enum members which are project agnostic + PROC_STOP_SCOM_OP_MIN = 0, + PROC_STOP_SCOM_APPEND = 1, + PROC_STOP_SCOM_REPLACE = 2, + PROC_STOP_SCOM_OR = 3, + PROC_STOP_SCOM_AND = 4, + PROC_STOP_SCOM_NOOP = 5, + PROC_STOP_SCOM_RESET = 6, + PROC_STOP_SCOM_OR_APPEND = 7, + PROC_STOP_SCOM_AND_APPEND = 8, + PROC_STOP_SCOM_OP_MAX = 9, + +} ScomOperation_t; + +/** + * @brief All subsections that contain scom entries in a STOP image. + */ +typedef enum +{ + PROC_STOP_SECTION_CORE = 1, + PROC_STOP_SECTION_L2 = 1, + PROC_STOP_SECTION_L3 = 2, + PROC_STOP_SECTION_CACHE = 2, +} ScomSection_t; + +/** + * @brief versions pertaining relvant to STOP API. + */ +typedef enum +{ + STOP_API_VER = 0x00, + STOP_API_VER_CONTROL = 0x02, +} VersionList_t; + +/** + * @brief Summarizes bit position allocated to SPRs in save bit mask vector. + */ +typedef enum +{ + BIT_POS_CIABR = 0, + BIT_POS_DAWR = 1, + BIT_POS_DAWRX = 2, + BIT_POS_HSPRG0 = 3, + BIT_POS_LDBAR = 4, + BIT_POS_LPCR = 5, + BIT_POS_PSSCR = 6, + BIT_POS_MSR = 7, + BIT_POS_HID = 21, + BIT_POS_HMEER = 22, + BIT_POS_PMCR = 23, + BIT_POS_PTCR = 24, + BIT_POS_SMFCTRL = 28, + BIT_POS_USPRG0 = 29, + BIT_POS_USPRG1 = 30, +} SprBitPositionList_t; + + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @brief creates SCOM restore entry for a given scom adress in HOMER. + * @param i_pImage points to start address of HOMER image. + * @param i_scomAddress address associated with SCOM restore entry. + * @param i_scomData data associated with SCOM restore entry. + * @param i_operation operation type requested for API. + * @param i_section section of HOMER in which restore entry needs to be created. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for creating SCOM restore entry in HOMER. It is agnostic to + * generation of POWER processor. + */ + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ); + +/** + * @brief initializes self save restore region of HOMER. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_corePos position of the physical core. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for initializing self restore region in HOMER. It is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ); + +/** + * @brief enables self save for a given set of SPRs + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ); + +/** + * @brief creates an SPR restore entry in HOMER + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_regId SPR number to be saved in HOMER + * @param[in] i_regData SPR data to be saved in HOMER + * @param[in] i_pir PIR value associated with core and thread. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ); + +/** + * @brief initializes self-save region with specific instruction. + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_corePos physical core's relative position within processor chip. + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, + * error code otherwise. + * @note API is project agnostic and is intended only for use case of HOMER build. + * There is no explicit effort to support any other use case. + */ +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); + +#ifdef __cplusplus +} // extern "C" +}; // namespace stopImageSection ends +#endif //__cplusplus + +#endif //__P10_STOP_IMAGE_API_ diff --git a/libpore/p10_stop_data_struct.H b/libpore/p10_stop_data_struct.H new file mode 100644 index 000000000..3a16fcda9 --- /dev/null +++ b/libpore/p10_stop_data_struct.H @@ -0,0 +1,162 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p10/procedures/utils/stopreg/p10_stop_data_struct.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p10_stop_data_struct.H +/// @brief describes data structures internal to STOP API. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP +#ifndef __STOP_DATA_STRUCT_ +#define __STOP_DATA_STRUCT_ + +#include "p10_hcd_memmap_base.H" + +#ifdef __SKIBOOT__ + #include +#endif + +#ifdef __FAPI_2_ + #include +#endif + +#ifdef PPC_HYP + + #define STATIC + +#else + + #define STATIC static + +#endif + + +#ifdef __DEBUG_ + #include +#endif + +#ifdef __cplusplus +extern "C" { +namespace stopImageSection +{ +#endif + +/** + * @brief Misc constants pertaining to instruction opcodes. + */ +enum +{ + MAX_SPR_RESTORE_INST = 0x08, + SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), + MAX_THREAD_LEVEL_SPRS = 11, + MAX_CORE_LEVEL_SPRS = 6, + MAX_SPR_BIT_POS = 30, + SPR_BIT_POS_8 = 8, + SPR_BIT_POS_20 = 20, + SPR_BIT_POS_25 = 25, + SPR_BIT_POS_27 = 27, +}; + +/** + * @brief various operations supported on SPR restore entry. + */ +enum SprEntryUpdateMode +{ + INIT_SPR_REGION = 0x01, + UPDATE_SPR_ENTRY = 0x02, +}; + +/** + * @brief models an individual SCOM restore entry. + */ +typedef struct +{ + uint32_t iv_scomAddress; + uint64_t iv_scomData; +} __attribute__((packed)) ScomEntry_t; + +/** + * @brief describes details pertaining to SCOM entry + */ +typedef struct +{ + uint32_t iv_subRegionBaseOffset; + uint32_t iv_subRegionLength; + uint8_t iv_slotFound; + uint8_t iv_lastEntryOffset; + uint16_t iv_entryOffset; + uint8_t iv_entryMatchOffset; + uint8_t iv_matchFound; + uint8_t iv_entryLimit; + uint8_t iv_reserved; +} ScomEntryDat_t; + +/** + * @brief summarizes attributes associated with a SPR register. + */ +typedef struct +{ + uint32_t iv_sprId; + bool iv_isThreadScope; + uint32_t iv_saveMaskPos; +} StopSprReg_t; + +/** + * @brief Misc constants. + */ +enum +{ + SIZE_SCOM_ENTRY = sizeof( ScomEntry_t ), + SCOM_ENTRY_START = 0xDEADDEAD, + BAD_SAVE_MASK = 0x007FF000, + MAX_SPR_INDEX = 31, + TEST_BIT_PATTERN = 0x80000000, + EP_SELECT_MASK = 0x000F0000, + CORE_REGION_MASK = 0x0000F000, + SCOM_ENTRY_VALID = 0x80000000, + LAST_SCOM_ENTRY = 0x40000000, + SWIZZLE_LAST_SCOM_ENTRY = 0x00000040, + SCOM_ADDR_MASK = 0x0000FFFF, + SCOM_ADDR_CHIPLET_MASK = 0x000FFFFF, + SCOM_ENTRY_VER = 0x10000000, //Ver 1.0 + CORE_SECTION_ID_CODE = 0x00000000, //Core Section Id 0 + L3_SECTION_ID_CODE = 0x03000000, //L3 Section Id 3 b4:b7 + MAX_SCOM_ENTRY_POS = 0x10, + MIN_SUPERCHIPLET_ID = 0x20, + +}; + +#ifdef __DEBUG_ + #define MY_ERR( _fmt_, _args_...) printf( "\n"); printf( _fmt_, ##_args_) + #define MY_INF(_fmt_, _args_...) printf( "\n"); printf( _fmt_, ##_args_) +#else + #define MY_ERR( _fmt_, _args_...) + #define MY_INF(_fmt_, _args_...) +#endif + +#ifdef __cplusplus +} // extern "C" + +} //namespace stopImageSection ends +#endif //__cplusplus + +#endif diff --git a/libpore/p10_stop_util.C b/libpore/p10_stop_util.C new file mode 100644 index 000000000..ba3ec1535 --- /dev/null +++ b/libpore/p10_stop_util.C @@ -0,0 +1,190 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p10/procedures/utils/stopreg/p10_stop_util.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p10_stop_util.C +/// @brief implements some utilty functions for STOP API. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP +#ifdef PPC_HYP + #include +#endif + +#include "p10_stop_api.H" +#include "p10_stop_util.H" +#include "p10_stop_data_struct.H" +#include "p10_hcd_memmap_base.H" +#include "p10_hcode_image_defines.H" +#include "stddef.h" + +#ifdef __cplusplus +using namespace hcodeImageBuild; +namespace stopImageSection +{ +#endif + +//----------------------------------------------------------------------- + +/** + * @brief Returns proc chip's fuse mode status. + * @param i_pImage points to start of chip's HOMER image. + * @param o_fusedMode points to fuse mode information. + * @return STOP_SAVE_SUCCESS if functions succeeds, error code otherwise. + */ +STATIC StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint64_t l_cpmrCheckWord = 0; + uint32_t* l_pMagic = NULL; + CpmrHeader_t* l_pCpmr = NULL; + *o_fusedMode = false; + + do + { + + if( !i_pImage ) + { + MY_ERR( "invalid pointer to HOMER image"); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + l_pMagic = (uint32_t*)( (uint8_t*)i_pImage + CPMR_HOMER_OFFSET + 8 ); + l_cpmrCheckWord = SWIZZLE_4_BYTE( *l_pMagic ); + + if( CPMR_REGION_CHECK_WORD != l_cpmrCheckWord ) + { + MY_ERR("corrupt or invalid HOMER image location 0x%016lx", + l_cpmrCheckWord ); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + l_pCpmr = (CpmrHeader_t*)( (uint8_t*)i_pImage + CPMR_HOMER_OFFSET ); + + if( (uint8_t) FUSED_CORE_MODE == l_pCpmr->iv_fusedMode ) + { + *o_fusedMode = true; + break; + } + + if( (uint8_t) NONFUSED_CORE_MODE == l_pCpmr->iv_fusedMode ) + { + break; + } + + MY_ERR("Unexpected value 0x%08x for fused mode. Bad or corrupt " + "HOMER location", l_pCpmr->iv_fusedMode ); + l_rc = STOP_SAVE_INVALID_FUSED_CORE_STATUS ; + + } + while(0); + + return l_rc; +} + +//---------------------------------------------------------------------- + +StopReturnCode_t getCoreAndThread_p10( void* const i_pImage, const uint64_t i_pir, + uint32_t* o_pCoreId, uint32_t* o_pThreadId ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + + do + { + // for SPR restore using 'Virtual Thread' and 'Physical Core' number + // In Fused Mode: + // bit b28 and b31 of PIR give physical core and b29 and b30 gives + // virtual thread id. + // In Non Fused Mode + // bit 28 and b29 of PIR give both logical and physical core number + // whereas b30 and b31 gives logical and virtual thread id. + bool fusedMode = false; + uint8_t coreThreadInfo = (uint8_t)i_pir; + *o_pCoreId = 0; + *o_pThreadId = 0; + l_rc = isFusedMode( i_pImage, &fusedMode ); + + if( l_rc ) + { + MY_ERR(" Checking Fused mode. Read failed 0x%08x", l_rc ); + break; + } + + if( fusedMode ) + { + if( coreThreadInfo & FUSED_CORE_BIT1 ) + { + *o_pThreadId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT2 ) + { + *o_pThreadId += 1; + } + + if( coreThreadInfo & FUSED_CORE_BIT0 ) + { + *o_pCoreId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pCoreId += 1; + } + } + else + { + if( coreThreadInfo & FUSED_CORE_BIT0 ) + { + *o_pCoreId = 2; + } + + if ( coreThreadInfo & FUSED_CORE_BIT1 ) + { + *o_pCoreId += 1; + } + + if( coreThreadInfo & FUSED_CORE_BIT2 ) + { + *o_pThreadId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pThreadId += 1; + } + } + + MY_INF("Core Type %s", fusedMode ? "Fused" : "Un-Fused" ); + //quad field is not affected by fuse mode + *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); + } + while(0); + + return l_rc; +} + +#ifdef __cplusplus +}//namespace stopImageSection ends +#endif diff --git a/libpore/p10_stop_util.H b/libpore/p10_stop_util.H new file mode 100644 index 000000000..7836dbc86 --- /dev/null +++ b/libpore/p10_stop_util.H @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p10/procedures/hwp/lib/p10_stop_util.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __P10_STOP_UTIL_ +#define __P10_STOP_UTIL_ + +#include + +#ifdef _AIX + #define __BYTE_ORDER __BIG_ENDIAN +#elif __SKIBOOT__ + #include +#else + #include +#endif + +#ifndef __PPE_PLAT + #include "p10_stop_api.H" +#endif + +#ifdef FAPI_2 + #include +#endif + +/// +/// @file p10_stop_util.H +/// @brief describes some utilty functions for STOP API. +/// +// *HWP HW Owner : Greg Still +// *HWP FW Owner : Prem Shanker Jha +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP +#ifndef __PPE_PLAT +#ifdef __cplusplus +namespace stopImageSection +{ +#endif +#endif //__PPE_PLAT +/** + * @brief helper function to swizzle given input data + * @note swizles bytes to handle endianess issue. + */ +#if( __BYTE_ORDER == __BIG_ENDIAN ) + +// NOP if it is a big endian system +#define SWIZZLE_2_BYTE(WORD) WORD +#define SWIZZLE_4_BYTE(WORD) WORD +#define SWIZZLE_8_BYTE(WORD) WORD + +#else +#define SWIZZLE_2_BYTE(WORD) \ + ( (((WORD) >> 8) & 0x00FF) | (((WORD) << 8) & 0xFF00) ) + +#define SWIZZLE_4_BYTE(WORD) \ + ( { uint64_t l_tmp64 = WORD; \ + (uint32_t)( (((l_tmp64) >> 24) & 0x000000FF) | (((l_tmp64) >> 8) & 0x0000FF00) | \ + (((l_tmp64) << 8) & 0x00FF0000) | (((l_tmp64) << 24) & 0xFF000000) ) ;\ + }) + +#define SWIZZLE_8_BYTE(WORD) \ + ( (((WORD) >> 56) & 0x00000000000000FF) | \ + (((WORD) >> 40) & 0x000000000000FF00)| \ + (((WORD) >> 24) & 0x0000000000FF0000) | \ + (((WORD) >> 8) & 0x00000000FF000000) | \ + (((WORD) << 8) & 0x000000FF00000000) | \ + (((WORD) << 24) & 0x0000FF0000000000) | \ + (((WORD) << 40) & 0x00FF000000000000) | \ + (((WORD) << 56) & 0xFF00000000000000) ) +#endif + +/** + * @brief enumerates bit(s) positions of interest for PIR. + */ +enum +{ + FUSED_CORE_BIT0 = 0x08, + FUSED_CORE_BIT1 = 0x04, + FUSED_CORE_BIT2 = 0x02, + FUSED_CORE_BIT3 = 0x01, + QUAD_BITS = 0x70, +}; + +#ifndef __PPE_PLAT +/** + * @brief returns core id and thread id by parsing a given PIR. + * @param i_pStopImage points to STOP image associated with a proc chip. + * @param i_pir PIR associated with a core's thread. + * @param o_coreId points to core id value obtained from PIR. + * @param o_threadId points to thread id value obtained from PIR. + * @return SUCCESS if function suceeds, error code otherwise. + */ +StopReturnCode_t getCoreAndThread_p10( void* const i_pStopImage, + const uint64_t i_pir, + uint32_t* o_coreId, + uint32_t* o_threadId ); +#ifdef __cplusplus +} // namespace stopImageSection ends + +#endif +#endif //__PPE_PLAT +#endif From patchwork Wed Aug 4 07:21:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=mY7TwUwK; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gfjwf1KcFz9sX5 for ; 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Wed, 4 Aug 2021 07:23:40 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:39 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:35 +0530 Message-Id: <20210804072137.1147875-58-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: arGzp1tlWGKCjaqCpxEV90UF6y92wefX X-Proofpoint-GUID: arGzp1tlWGKCjaqCpxEV90UF6y92wefX X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 57/59] xive2: Add NCU_SPEC_BAR to stop engine for restore X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pratik Rajesh Sampat Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan P10 Stop engines have apis similar to P9 to set xscom restores after wakeup from deep-sleep states. This xscom restore will be used to support STOP11 on P10. Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Pratik Rajesh Sampat Signed-off-by: Vasant Hegde --- hw/xive2.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/xive2.c b/hw/xive2.c index a7b45a005..aece99a0d 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -20,8 +20,7 @@ #include #include #include -#include /* TODO (p10): need P10 stop state engine */ - +#include /* Verbose debug */ #undef XIVE_VERBOSE_DEBUG @@ -3014,10 +3013,30 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) void xive2_late_init(void) { + struct cpu_thread *c; + prlog(PR_INFO, "SLW: Configuring self-restore for NCU_SPEC_BAR\n"); - /* - * TODO (p10): need P10 stop state engine and fix for STOP11 - */ + for_each_present_cpu(c) { + if(cpu_is_thread0(c)) { + struct proc_chip *chip = get_chip(c->chip_id); + struct xive *x = chip->xive; + uint64_t xa, val, rc; + xa = XSCOM_ADDR_P10_NCU(pir_to_core_id(c->pir), P10_NCU_SPEC_BAR); + val = (uint64_t)x->tm_base | P10_NCU_SPEC_BAR_ENABLE; + /* Bail out if wakeup engine has already failed */ + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { + prlog(PR_ERR, "XIVE proc_stop_api fail detected\n"); + break; + } + rc = proc_stop_save_scom((void *)chip->homer_base, xa, val, + PROC_STOP_SCOM_REPLACE, PROC_STOP_SECTION_L3); + if (rc) { + xive_cpu_err(c, "proc_stop_save_scom failed for NCU_SPEC_BAR rc=%lld\n", + rc); + wakeup_engine_state = WAKEUP_ENGINE_FAILED; + } + } + } } static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) From patchwork Wed Aug 4 07:21:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1513255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; 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Wed, 04 Aug 2021 07:23:46 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1747NgaA24117526 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 4 Aug 2021 07:23:42 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2EB2AE05F; Wed, 4 Aug 2021 07:23:42 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A03E9AE053; Wed, 4 Aug 2021 07:23:41 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:41 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:36 +0530 Message-Id: <20210804072137.1147875-59-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: IJU7b5HYGAbNB8Li1fnR-m2ZXNNpRILi X-Proofpoint-GUID: IJU7b5HYGAbNB8Li1fnR-m2ZXNNpRILi X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 58/59] hw/chiptod: Retry the sync procedure on failure X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ryan Grimm The chiptod sync will sometimes fail and then sync successfully after a retry. So, try an arbitrary 10 numbers of times before we either abort() on main procedure fail or disable threads on secondary procedure fail. Also, put a message on the log if secondaries fail so we have evidence in the log when they aren't enabled. Signed-off-by: Ryan Grimm Signed-off-by: Vasant Hegde --- hw/chiptod.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/chiptod.c b/hw/chiptod.c index 3b57f5f16..fd9414990 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -221,6 +221,8 @@ static uint64_t base_tfmr; static struct lock chiptod_lock = LOCK_UNLOCKED; static bool chiptod_unrecoverable; +#define NUM_SYNC_RETRIES 10 + static void _chiptod_cache_tod_regs(int32_t chip_id) { int i; @@ -892,7 +894,7 @@ static void chiptod_sync_master(void *data) *result = true; return; error: - prerror("Master sync failed! TFMR=0x%016lx\n", mfspr(SPR_TFMR)); + prerror("Master sync failed! TFMR=0x%016lx, retrying...\n", mfspr(SPR_TFMR)); *result = false; } @@ -962,7 +964,7 @@ static void chiptod_sync_slave(void *data) *result = true; return; error: - prerror("Slave sync failed ! TFMR=0x%016lx\n", mfspr(SPR_TFMR)); + prerror("Slave sync failed ! TFMR=0x%016lx, retrying...\n", mfspr(SPR_TFMR)); *result = false; } @@ -1818,6 +1820,7 @@ void chiptod_init(void) { struct cpu_thread *cpu0, *cpu; bool sres; + int i; /* Mambo and qemu doesn't simulate the chiptod */ if (chip_quirk(QUIRK_NO_CHIPTOD)) @@ -1841,10 +1844,14 @@ void chiptod_init(void) prlog(PR_DEBUG, "Base TFMR=0x%016llx\n", base_tfmr); - /* Schedule master sync */ - sres = false; - cpu_wait_job(cpu_queue_job(cpu0, "chiptod_sync_master", + i = NUM_SYNC_RETRIES; + do { + /* Schedule master sync */ + sres = false; + cpu_wait_job(cpu_queue_job(cpu0, "chiptod_sync_master", chiptod_sync_master, &sres), true); + } while (!sres && i--); + if (!sres) { op_display(OP_FATAL, OP_MOD_CHIPTOD, 2); abort(); @@ -1858,13 +1865,19 @@ void chiptod_init(void) if (cpu == cpu0) continue; - /* Queue job */ - sres = false; - cpu_wait_job(cpu_queue_job(cpu, "chiptod_sync_slave", - chiptod_sync_slave, &sres), - true); + i = NUM_SYNC_RETRIES; + do { + /* Queue job */ + sres = false; + cpu_wait_job(cpu_queue_job(cpu, "chiptod_sync_slave", + chiptod_sync_slave, &sres), + true); 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Wed, 4 Aug 2021 07:23:43 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:42 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:37 +0530 Message-Id: <20210804072137.1147875-60-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: inCbtGIIp38fOxTKxq6Z1xynNlikQHAv X-Proofpoint-GUID: inCbtGIIp38fOxTKxq6Z1xynNlikQHAv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 59/59] hw/chiptod: Abort if core frequency is not set X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Reza Arbab Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Vasant Hegde Signed-off-by: Reza Arbab Signed-off-by: Vasant Hegde --- hw/chiptod.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/chiptod.c b/hw/chiptod.c index fd9414990..7c0a1ffc7 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -499,6 +499,12 @@ static void chiptod_setup_base_tfmr(void) core_freq = dt_prop_get_u64(cpu, "ibm,extended-clock-frequency"); else core_freq = dt_prop_get_u32(cpu, "clock-frequency"); + + if (!core_freq) { + prlog(PR_ERR, "CPU clock frequency is not set\n"); + abort(); + } + tod_freq = 32000000; /* Calculate the "Max Cycles Between Steps" value according