From patchwork Tue Aug 3 04:44:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512711 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=Zif31fga; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2Nq4Nzgz9sPf for ; Tue, 3 Aug 2021 14:45:15 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 20B7C82DBE; Tue, 3 Aug 2021 06:44:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="Zif31fga"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5D11E82DBA; Tue, 3 Aug 2021 06:44:57 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7EA4582D94 for ; Tue, 3 Aug 2021 06:44:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pj1-x102b.google.com with SMTP id o44-20020a17090a0a2fb0290176ca3e5a2fso3067703pjo.1 for ; Mon, 02 Aug 2021 21:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cngQFZYovbzEe4VnmQXioi+6TIRiXz1KU/dnuZmFOeE=; b=Zif31fgaXxQPnqg99qYaaOZxxhew43zF7KdOeYvqLzFHXx4jdCGFkvpSwsekrAdrJf jnyVupxv6T9eokzyVmtnl3zhVTD7HimENtAKfKkrKYMMeYBBtezYcBkuq29HuG/ysqKp pDeqtrzNuJ3bqJDczJZjze2CviMvOOzBnta8BAxOFvmCPWVc/F5pw2+Sxf0IGXArxRDS Ht+5dB/IUzcPm5KA4qhx68eiZTZGUAmZJOFvX/ZIN9ijG0YVUmFjnOEk0KzB4XNg7BD/ pcl1skFcRwg1M08kaobT+qcpZpz9N0i8lnnsVgbESi+DRgpr7f+tztCx0Sz2glQAPvNy zBmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cngQFZYovbzEe4VnmQXioi+6TIRiXz1KU/dnuZmFOeE=; b=AxuwZ+6rxaUZFFyB3/VG5qsdJSq6w8xFq9WfAWCs3A3eqQ8pDUszSxdN6NuG8dVfnJ VgtPfmlKglhy94Y4re+mBFmg/ktfvYScHlD55r9BaKGXbvnOVGC8Gf1122lynWj8Qd1U 6ZCBfibUK7CE0khJRQRsU8I7fcEeHFdAlPZAfE2uo5LdS3KAVJX7CyewNGIInpOLc444 Ji3eYQY+bDgy8rH4so213EeyAgSYeyFOcy3EDWD27guzBYhlqwAf7ae6ePw2cd2fs7Yk GyHdHih65obFcz88JX9r7Ueoh0fxF30sPh6rzVsatkIDRseGYCFqN7H37JBm1G1bNIew re+Q== X-Gm-Message-State: AOAM5321uLgiJeLop6BPSIov/uzY+GzsuFrNbMHnTPuIeXc+hgSEXqB1 RLZenY/DWy1aTJ+caZ8jFtSbSw== X-Google-Smtp-Source: ABdhPJylbOCEpS0DfwAZSdK62RUena43mflfAjBqqcrbo+4uZKND8EcZ7P9S6PDoWBIoQIawOniarg== X-Received: by 2002:a17:90a:f310:: with SMTP id ca16mr18205046pjb.181.1627965891796; Mon, 02 Aug 2021 21:44:51 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:44:51 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 1/6] cache: add sifive composable cache driver Date: Tue, 3 Aug 2021 12:44:39 +0800 Message-Id: <20210803044444.14032-2-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This driver is currently responsible for enabling all ccache ways. Composable cache could be configure as RAM or cache, we will use it as RAM at the beginning to put the u-boot SPL there. In u-boot proper phrase, we will use the composable cache as cache, and try to enable the cache ways. Signed-off-by: Zong Li Reviewed-by: Sean Anderson --- drivers/cache/Kconfig | 7 +++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+) create mode 100644 drivers/cache/cache-sifive-ccache.c diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 1e452ad6d9..40f41a817c 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -39,4 +39,11 @@ config NCORE_CACHE controller. The driver initializes cache directories and coherent agent interfaces. +config SIFIVE_CCACHE + bool "SiFive composable cache" + select CACHE + help + This driver is for SiFive Composable L2/L3 cache. It enables cache + ways of composable cache. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index fed50be3f9..ad765774e3 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o +obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c new file mode 100644 index 0000000000..76c0ab26ae --- /dev/null +++ b/drivers/cache/cache-sifive-ccache.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 SiFive + */ + +#include +#include +#include +#include +#include +#include + +#define SIFIVE_CCACHE_CONFIG 0x000 +#define SIFIVE_CCACHE_CONFIG_WAYS GENMASK(15, 8) + +#define SIFIVE_CCACHE_WAY_ENABLE 0x008 + +struct sifive_ccache { + void __iomem *base; +}; + +static int sifive_ccache_enable(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + u32 config; + u32 ways; + + /* Enable all ways of composable cache */ + config = readl(priv->base + SIFIVE_CCACHE_CONFIG); + ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config); + + writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE); + + return 0; +} + +static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->base; + + return 0; +} + +static const struct cache_ops sifive_ccache_ops = { + .enable = sifive_ccache_enable, + .get_info = sifive_ccache_get_info, +}; + +static int sifive_ccache_probe(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id sifive_ccache_ids[] = { + { .compatible = "sifive,fu540-c000-ccache" }, + { .compatible = "sifive,fu740-c000-ccache" }, + {} +}; + +U_BOOT_DRIVER(sifive_ccache) = { + .name = "sifive_ccache", + .id = UCLASS_CACHE, + .of_match = sifive_ccache_ids, + .probe = sifive_ccache_probe, + .priv_auto = sizeof(struct sifive_ccache), + .ops = &sifive_ccache_ops, +}; From patchwork Tue Aug 3 04:44:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512712 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=HaJJA0o0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2P422ddz9sPf for ; Tue, 3 Aug 2021 14:45:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 721B682DD7; Tue, 3 Aug 2021 06:45:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="HaJJA0o0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6428582DBF; Tue, 3 Aug 2021 06:44:59 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 94DD282D58 for ; Tue, 3 Aug 2021 06:44:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pj1-x102d.google.com with SMTP id nh14so16377397pjb.2 for ; Mon, 02 Aug 2021 21:44:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oWHcO61hBMOPHQv5VNe3IA3n3iFtQc01nusTbDjBiGs=; b=HaJJA0o0paZyBDzJ8tb/yDT65EBqZB9TGJfIg45CqQTTaWsOGodEMgL4NDeV/iJ0Qm iFH3vOq0z4FIQTgmUL2GrZgOt1WB5i+ukij9kLMwY5BOqtSLR2972TBQxAQfYxM6hCnJ Q1hxr25roMoAp57jz0dD3agmOkRaA57ylxXWVf80rzUp7Au4ckTUsbQIdwkV9eu3NymF /4vFJvy+a4s1kiIBNtddqm8YImGY76HXqCDUGY9md4YuFk37aN5IWzrwevZDOGPaVxmp +CHTfXj9kI2ve9CZKNRbzFH4otIHieoVENcHcmdOMGMwr/u/nuS5ujx378Bu+kmlifHR gV4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oWHcO61hBMOPHQv5VNe3IA3n3iFtQc01nusTbDjBiGs=; b=FRJ2KFQrZBdS44FHKOe3qvPvgY5c50QepEtm4SKwQg0dF9c8aRPJLoHBluqt61KoWY bSdqyBEbicDg2H5ECzUkr78m4mlB2JroIlg81LVQ0lL4ZxYkLebeSnwzAsI4UIseu1Ie RNj6o0P9c2jdsV9jRf1xrYGHT1X3B45sO0P+Zok1FRtfHaSMfLDHwG6rIaUa58+AiNGg 2lwt+WwxMD8IvnhxU/jfhQ6XBjB1pmxInYdF1oaapO7p+H3MqpbMu3igqjIP9V/l+3uq cH7U4sj1Xyd+vXtGyPUM0I2HXE2N7CI+z9rbPnCLyN3oxUhy0a3psDKy0TcK3AFBOdem v/0g== X-Gm-Message-State: AOAM533Nc8ysBsZYY5SkZfAUcr0Kd/TwjTVBA3h/n4A1AhPVDdwZ9LOi jxs39GDpMnkDlBD5aX9T1PbDHg== X-Google-Smtp-Source: ABdhPJwcDrr4bRdHfqkz4tNEm1WIsIOF/puFIYLPzr6QWnxeiBGnaIAdfDMFnH/9CmRfG7Xoc2s9OA== X-Received: by 2002:a65:44c3:: with SMTP id g3mr296499pgs.233.1627965894080; Mon, 02 Aug 2021 21:44:54 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:44:53 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 2/6] board: sifive: use ccache driver instead of helper function Date: Tue, 3 Aug 2021 12:44:40 +0800 Message-Id: <20210803044444.14032-3-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Invokes the generic cache_enable interface to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li --- arch/riscv/cpu/fu540/Kconfig | 1 + arch/riscv/cpu/fu540/cache.c | 54 ++++++----------------- arch/riscv/cpu/fu740/Kconfig | 1 + arch/riscv/cpu/fu740/cache.c | 52 ++++++---------------- arch/riscv/include/asm/arch-fu540/cache.h | 2 +- arch/riscv/include/asm/arch-fu740/cache.h | 2 +- board/sifive/unleashed/unleashed.c | 10 +---- board/sifive/unmatched/unmatched.c | 9 +--- 8 files changed, 33 insertions(+), 98 deletions(-) diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 05463b2625..8608741779 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,7 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c index 0fc4ef6c00..bc31f664b8 100644 --- a/arch/riscv/cpu/fu540/cache.c +++ b/arch/riscv/cpu/fu540/cache.c @@ -1,55 +1,29 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 SiFive, Inc + * Copyright (C) 2020 - 2021 SiFive, Inc * * Authors: * Pragnesh Patel */ #include -#include -#include -#include +#include +#include -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) +int sifive_ccache_enable_ways(void) { - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu540-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; + struct udevice *dev; + int ret; - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) + return log_msg_ret("Cannot enable cache ways", ret); - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); + ret = cache_enable(dev); + if (ret) + return log_msg_ret("ccache enable failed", ret); - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); return 0; } diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 408195f149..b4cada0ea9 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,7 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c index 680955c9e3..e2782d76c0 100644 --- a/arch/riscv/cpu/fu740/cache.c +++ b/arch/riscv/cpu/fu740/cache.c @@ -7,49 +7,23 @@ */ #include -#include -#include -#include +#include +#include -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) +int sifive_ccache_enable_ways(void) { - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu740-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; + struct udevice *dev; + int ret; - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) + return log_msg_ret("Cannot enable cache ways", ret); - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); + ret = cache_enable(dev); + if (ret) + return log_msg_ret("ccache enable failed", ret); - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); return 0; } diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h index 135a17c679..c252eb64d1 100644 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ b/arch/riscv/include/asm/arch-fu540/cache.h @@ -9,6 +9,6 @@ #ifndef _CACHE_SIFIVE_H #define _CACHE_SIFIVE_H -int cache_enable_ways(void); +int sifive_ccache_enable_ways(void); #endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h index 7d4fe9942b..8c456e3658 100644 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ b/arch/riscv/include/asm/arch-fu740/cache.h @@ -9,6 +9,6 @@ #ifndef _CACHE_SIFIVE_H #define _CACHE_SIFIVE_H -int cache_enable_ways(void); +int sifive_ccache_enable_ways(void); #endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 43027f0b54..12e61ec85f 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -126,14 +126,6 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } - - return 0; + return sifive_ccache_enable_ways(); } diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 2f5629b578..d27c4d3e88 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -23,13 +23,6 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } - return 0; + return sifive_ccache_enable_ways(); } From patchwork Tue Aug 3 04:44:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512713 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=PQC7zYnl; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2PJ2FFVz9sPf for ; Tue, 3 Aug 2021 14:45:40 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 56A3682DC5; Tue, 3 Aug 2021 06:45:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="PQC7zYnl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EB8EA82DDE; Tue, 3 Aug 2021 06:45:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D3F7B82D94 for ; Tue, 3 Aug 2021 06:44:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pj1-x1036.google.com with SMTP id u9-20020a17090a1f09b029017554809f35so2130249pja.5 for ; Mon, 02 Aug 2021 21:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=86CW7lrEF9unpGeRgMuhn5zv2wj8bF9oX5glPtNHP/A=; b=PQC7zYnlRt/HTx36tb4OVOpWF+fDLrpBQBd6Jr8qTAhA28XQfPO8If+DlYXzbP3+B0 Uz261QnVmn/1lnRYP0N3WJjaV+bT1E1Mv1u3iXegqfDWG0akIc63y7lNT7SBWM8u2TNr EMy9fv0QHXynSebFkRV4azs6Fa5EjJI/rCmw0XNxgbP7VKNNUHFI9y0IOt3Hdfnkabfr 6Xaqn2twF2C0hbsEtlTFYEBSvpOM6Jcu5tQl9Jr2zpjCq3iIGd3kZ6JAW2BZAF9qFGxF bEW/ZXAgKAKIVGn9tmG6rOQ1SXvYWktn5d0cbgl9lw74SBKO1MtG5UvrHVN+rlLY13sJ V/dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=86CW7lrEF9unpGeRgMuhn5zv2wj8bF9oX5glPtNHP/A=; b=SAT3A/8ZF2S1vKHbqVEhyV3dmctI7+7j1TRIIfTldAzZkfH0c24TqFgh1cjnCEbDZt GYWj+excgZvZKmJZ/ows8JY/8gvUh0FybRRT74hiLVw8ATDr9PUQTIgASguv7cLZbKGr WI9u0nPm4B4kh40AhiHJL0iNB2Vx/lBVQobj24shnCblJRrLBkPh7jvoRv9yIKHiam8m CWp0gP6zIZEGAEScDtwEDuGpHzCv1hjDL7A4TibPk2p/N3Tk8yqg+MsCZa5G2+OjQ/QG 4d6hBFyte76KkhttqjZLYEY7NFNzRT6onMBdRLrqhcfmcdkSqgF9vQRUH8Nxl56bFp1B MeWA== X-Gm-Message-State: AOAM532UWgfT07wZrMRAoD+JYQDIwyf6h2hxJq+eWjotmVluWhruCGpU Me+SyZAp7ddSpY01tBbpvKcxwQ== X-Google-Smtp-Source: ABdhPJwMg6QD/JTWNYaDeAKiUYzi7r9zb3/ms+2xGPa/UuTka0cPpeSj0hDpY9rHiVSqfZoE6ZMxcQ== X-Received: by 2002:a17:90a:3f87:: with SMTP id m7mr20493079pjc.96.1627965896290; Mon, 02 Aug 2021 21:44:56 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:44:55 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 3/6] riscv: lib: introduce cache_init interface Date: Tue, 3 Aug 2021 12:44:41 +0800 Message-Id: <20210803044444.14032-4-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add an interface for cache initialization. Each platform can overwrite this weak function by their own implementation, such as sifive_cache in this patch. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 5 +++++ arch/riscv/include/asm/cache.h | 1 + arch/riscv/lib/Makefile | 1 + arch/riscv/lib/cache.c | 5 +++++ arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++ 5 files changed, 39 insertions(+) create mode 100644 arch/riscv/lib/sifive_cache.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..ec651fe0a4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config SIFIVE_CACHE + bool + help + This enables the operations to configure SiFive cache + config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ec8fe201d3..6ebb2b4329 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -9,6 +9,7 @@ /* cache */ void cache_flush(void); +int cache_init(void); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..2cd66504c6 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,8 @@ __weak int dcache_status(void) { return 0; } + +__weak int cache_init(void) +{ + return 0; +} diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..94e84e024e --- /dev/null +++ b/arch/riscv/lib/sifive_cache.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 SiFive, Inc + */ + +#include +#include +#include + +int cache_init(void) +{ + struct udevice *dev; + int ret; + + /* Enable ways of ccache */ + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) + return log_msg_ret("Cannot enable cache ways", ret); + + ret = cache_enable(dev); + if (ret) + return log_msg_ret("ccache enable failed", ret); + + return 0; +} From patchwork Tue Aug 3 04:44:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512714 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=I6xgrYue; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2PY23vRz9sPf for ; Tue, 3 Aug 2021 14:45:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 78E9A82DF4; Tue, 3 Aug 2021 06:45:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="I6xgrYue"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C48CA82DE9; Tue, 3 Aug 2021 06:45:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1823682DC5 for ; Tue, 3 Aug 2021 06:45:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pj1-x1031.google.com with SMTP id nh14so16377600pjb.2 for ; Mon, 02 Aug 2021 21:44:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zRR9ccDVNSZ0VlPH5PGeOWvd+q7I8XEofZCeP9L+t3U=; b=I6xgrYueKAi8hbxCCrpEdw4KyVZyX8g3Irb1FCLQzw1cHNY97QFJetW55ov7yconkt 4/RlveZVYVgEwCNt23yUF0eKnGUljsHPmxSklaJrF/rQzknRX5q3ZvuDVkg2vbevnuRY 8elqyXEsYLylnbKOue61jNZXMggpPXXbtUalLsKAOSSi2hiIRdIC3dbwdskVpahn3Dtg /2TyDVnzn0FcOQA7YH6pzRdKsXQLtZFoKLURqtanvpf5NzKfqdzIDF6fBdDDnrEiF1ZO xwy8c0n8u/9V+U59ltlJ7Umq+4/lER9mDiMyVj3q3ClLfq0lXrjuFwgq636mACtXualn cNMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zRR9ccDVNSZ0VlPH5PGeOWvd+q7I8XEofZCeP9L+t3U=; b=esZOuZxboPB1Zm/TV5Qs/PieoiVbWNphahWTJWJmwQ57m34XnDZ7zebV9KPVq8bQyf uHtR1SQ1RNgeoM7RIYkcYI77hhD/URQxyHBzBGajwP34aP1ol2CJiLcCczOK7V1uoIOt RN7c29pJdaF2Mr0PHxwjZxEsuHghntulLsak53iODVI7mfjuGZvU0pamrxWhwtIsDiof RqKhRlERBhrb10qklsHC+bdpdwuRtqEFMzcdpjtb2XqcSgtKhd6z2kCUJkh9wbBkhxW+ /vN7co4BObJxFZ/4eO+g2yPT1OUrBkJRLg7QbrADrNnVe1ic2Ii6W43Z+5y6sYBaETF8 TbkA== X-Gm-Message-State: AOAM531DCJu9M7+MBRx7CNfxXMz6Nzn9jshJNi3NegYGpY9wPsSgPPnN JX/V0zZQudtepTNFWXp/MU2H6w== X-Google-Smtp-Source: ABdhPJwNCHRewv4+XLasjLBGHyHSouyONc9mJAeY8cqwzV8FPv5WArJPh8dHky8MCaeXGGDhORr+FQ== X-Received: by 2002:a17:90a:4cc4:: with SMTP id k62mr2478351pjh.110.1627965898497; Mon, 02 Aug 2021 21:44:58 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:44:58 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 4/6] riscv: sifive: use common cache_init instead of duplicated implementation Date: Tue, 3 Aug 2021 12:44:42 +0800 Message-Id: <20210803044444.14032-5-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean We already extracted the duplicated implementation to common code, so change to use that and drop the original implementation. Signed-off-by: Zong Li --- arch/riscv/cpu/fu540/Kconfig | 1 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 29 ----------------------- arch/riscv/cpu/fu740/Kconfig | 1 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 29 ----------------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ----------- arch/riscv/include/asm/arch-fu740/cache.h | 14 ----------- board/sifive/unleashed/unleashed.c | 4 ++-- board/sifive/unmatched/unmatched.c | 4 ++-- 10 files changed, 6 insertions(+), 92 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 8608741779..1604b412b4 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,7 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 088205ef57..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c deleted file mode 100644 index bc31f664b8..0000000000 --- a/arch/riscv/cpu/fu540/cache.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 - 2021 SiFive, Inc - * - * Authors: - * Pragnesh Patel - */ - -#include -#include -#include - -int sifive_ccache_enable_ways(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(sifive_ccache), - &dev); - if (ret) - return log_msg_ret("Cannot enable cache ways", ret); - - ret = cache_enable(dev); - if (ret) - return log_msg_ret("ccache enable failed", ret); - - return 0; -} diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index b4cada0ea9..049a0a0584 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,7 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 5ef8ac18a7..1d1ad98ba7 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c deleted file mode 100644 index e2782d76c0..0000000000 --- a/arch/riscv/cpu/fu740/cache.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020-2021 SiFive, Inc - * - * Authors: - * Pragnesh Patel - */ - -#include -#include -#include - -int sifive_ccache_enable_ways(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(sifive_ccache), - &dev); - if (ret) - return log_msg_ret("Cannot enable cache ways", ret); - - ret = cache_enable(dev); - if (ret) - return log_msg_ret("ccache enable failed", ret); - - return 0; -} diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h deleted file mode 100644 index c252eb64d1..0000000000 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 SiFive, Inc. - * - * Authors: - * Pragnesh Patel - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int sifive_ccache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h deleted file mode 100644 index 8c456e3658..0000000000 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * - * Authors: - * Pragnesh Patel - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int sifive_ccache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 12e61ec85f..6d697d797d 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include /* @@ -127,5 +127,5 @@ void *board_fdt_blob_setup(void) int board_init(void) { /* enable all cache ways */ - return sifive_ccache_enable_ways(); + return cache_init(); } diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index d27c4d3e88..f4fc2a793d 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #if defined(CONFIG_OF_SEPARATE) @@ -24,5 +24,5 @@ void *board_fdt_blob_setup(void) int board_init(void) { /* enable all cache ways */ - return sifive_ccache_enable_ways(); + return cache_init(); } From patchwork Tue Aug 3 04:44:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512716 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=lmZtGcb0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2Pl2P52z9sPf for ; Tue, 3 Aug 2021 14:46:03 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4509083213; Tue, 3 Aug 2021 06:45:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="lmZtGcb0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4F3BB82DE9; Tue, 3 Aug 2021 06:45:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7D28282DD6 for ; Tue, 3 Aug 2021 06:45:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pl1-x630.google.com with SMTP id e21so22217290pla.5 for ; Mon, 02 Aug 2021 21:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aur7q0cT6oAQ3mkjR5s328lcFOqJdmfn+6HDgZ1xaqQ=; b=lmZtGcb0n0lNP3tAvcn4RS4kto9A+22Cc23n7mabR3pSzm1O/6rc0ntVRv8cHuylwE UwW4sREGiMD2QHHuQnJ79ukV/BpPjcuBae26MXlJknRN8OxDpBse2HwcTVmkTi3fx1bL 0fWxpIj5R5KlpM21w0bDQyQ36xxFbuaKMBUAtkSwyCBrXkC2aY+v2EXls5QUmEvJfvkb l/CAl7628CdBac15N27/A+qK3bhpORVkrPNlYD8rGgdVWHKjTOu9Iy4oqrEWYymaYr6o We4BWQu24jrXStm7BEThUiA08AqLuMmX0YX8X7loGneCX+LhScHOT1j76wx7pNLdNF3a xb2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aur7q0cT6oAQ3mkjR5s328lcFOqJdmfn+6HDgZ1xaqQ=; b=gZKo6lvgKPCL2GIQjp2hzhs/od6dpJRuHdiYXLUwdSZgQRirCN/g67QxQ22ij/0/92 EOwyXzFU2GH/DTm7VCcrdA3KU3eUlBk2lI/IEySwAX/bAl8XLl4FnEuTH6M27+0yvUEs 0B5EE+D+4eNj/R6Ls5D2j24iRZOfUB1+qf8YPMcRVniSb6pxvnMoC5DQ50Niwn+Tr9ZC MULg/I2wvKT/Qz2+NQhX9PeOOawLPF1Z3ch1HLMUHjApdIj2WCDRUKTbBP0j+/WevYQ7 V7a7zDE15a98FBUQU5JsNv6JtWwCC7vjC8Y94gtcL/M9Pami+R+YNM9v+LEg5Sb6XdG5 cDEw== X-Gm-Message-State: AOAM532SjbIUS2x0xB6/KFkdEKIkyVGJxLFvC0+c4GRWm6WCnS4srCAA BUoZn9piVhuruKHhHL+gl91CRQ== X-Google-Smtp-Source: ABdhPJz2Qy/3z6DgkeaJu9B1XTqJ508cTc7I9pJj9VFd+85UtEb/PZm+5NGjxx8KKX1DK+wz0ha8Tw== X-Received: by 2002:a17:90a:c085:: with SMTP id o5mr11283275pjs.9.1627965900705; Mon, 02 Aug 2021 21:45:00 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:45:00 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate folder Date: Tue, 3 Aug 2021 12:44:43 +0800 Message-Id: <20210803044444.14032-6-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Put the platform-related implementation into their own folder respectively. Just leave the common library in the top of lib folder. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/lib/Makefile | 9 ++++----- arch/riscv/lib/andestech/Kconfig | 8 ++++++++ arch/riscv/lib/andestech/Makefile | 7 +++++++ arch/riscv/lib/{ => andestech}/andes_plic.c | 0 arch/riscv/lib/sifive/Kconfig | 8 ++++++++ arch/riscv/lib/sifive/Makefile | 9 +++++++++ arch/riscv/lib/{ => sifive}/sifive_cache.c | 0 arch/riscv/lib/{ => sifive}/sifive_clint.c | 0 9 files changed, 43 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/lib/andestech/Kconfig create mode 100644 arch/riscv/lib/andestech/Makefile rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%) create mode 100644 arch/riscv/lib/sifive/Kconfig create mode 100644 arch/riscv/lib/sifive/Makefile rename arch/riscv/lib/{ => sifive}/sifive_cache.c (100%) rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec651fe0a4..ed1bf2f6c8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -72,6 +72,10 @@ source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +# library-specific options below +source "arch/riscv/lib/sifive/Kconfig" +source "arch/riscv/lib/andestech/Kconfig" + # architecture-specific options below choice @@ -175,18 +179,21 @@ config SIFIVE_CLINT config SPL_SIFIVE_CLINT bool depends on SPL_RISCV_MMODE + select SIFIVE_LIB help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config SIFIVE_CACHE bool + select SIFIVE_LIB help This enables the operations to configure SiFive cache config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE + select ANDESTECH_LIB select REGMAP select SYSCON select SPL_REGMAP if SPL diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 06020fcc2a..f58d1f9819 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,11 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o -obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o -ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o -obj-$(CONFIG_ANDES_PLIC) += andes_plic.o -else +ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),) obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif @@ -42,3 +38,6 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o + +obj-$(CONFIG_SIFIVE_LIB) += sifive/ +obj-$(CONFIG_ANDESTECH_LIB) += andestech/ diff --git a/arch/riscv/lib/andestech/Kconfig b/arch/riscv/lib/andestech/Kconfig new file mode 100644 index 0000000000..75f83a8123 --- /dev/null +++ b/arch/riscv/lib/andestech/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 SiFive, Inc + +config ANDESTECH_LIB + bool + help + This supports the specific libraries for AndesTech platforms diff --git a/arch/riscv/lib/andestech/Makefile b/arch/riscv/lib/andestech/Makefile new file mode 100644 index 0000000000..49f45d0a29 --- /dev/null +++ b/arch/riscv/lib/andestech/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 SiFive, Inc + +ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o +endif diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andestech/andes_plic.c similarity index 100% rename from arch/riscv/lib/andes_plic.c rename to arch/riscv/lib/andestech/andes_plic.c diff --git a/arch/riscv/lib/sifive/Kconfig b/arch/riscv/lib/sifive/Kconfig new file mode 100644 index 0000000000..20574079e9 --- /dev/null +++ b/arch/riscv/lib/sifive/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 SiFive, Inc + +config SIFIVE_LIB + bool + help + This supports the specific libraries for SiFive platforms diff --git a/arch/riscv/lib/sifive/Makefile b/arch/riscv/lib/sifive/Makefile new file mode 100644 index 0000000000..ba120db26a --- /dev/null +++ b/arch/riscv/lib/sifive/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 SiFive, Inc + +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o + +ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) +obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o +endif diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive/sifive_cache.c similarity index 100% rename from arch/riscv/lib/sifive_cache.c rename to arch/riscv/lib/sifive/sifive_cache.c diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive/sifive_clint.c similarity index 100% rename from arch/riscv/lib/sifive_clint.c rename to arch/riscv/lib/sifive/sifive_clint.c From patchwork Tue Aug 3 04:44:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 1512717 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=b1twim/i; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gf2Px5Z24z9sPf for ; Tue, 3 Aug 2021 14:46:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F0ADC82DDB; Tue, 3 Aug 2021 06:45:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="b1twim/i"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CD74C83213; Tue, 3 Aug 2021 06:45:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8E23E82DD8 for ; Tue, 3 Aug 2021 06:45:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=zong.li@sifive.com Received: by mail-pl1-x62c.google.com with SMTP id j3so7113193plx.4 for ; Mon, 02 Aug 2021 21:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kZkLbz+f7/EfirsehKat4rN2RysgLCvVTYIf4Y5dEac=; b=b1twim/i5H64ijkTmcZ/SIooulTK3E6dM7lsmQ2Qwo+3DXcluz28+aRWoWa26jKC1b nBE2jxgwPD9B2My/IEX2u5LowtHOHjZwkWw4L0fqyF/s3Mzf4yOzUUDp12TlBpuFBwXM 4qDqp7oxGL3FI93i2tHEqFMxKBzQyXqGG30Jq8/XybZFPo6nrbDJSq6hPaflezzetMVA 8Pum5BlDoBdzlJAnyFBuj0HKKRVaoCjtT0VN/PgMz8ttoDiJKs6ZNhkGJroPfPcY8xFC S06IyLFV/AH1fzazalpLjZZJKZrwab6UxY3lNSNGkgPGefOMLNaiOg6dyQT5wnCHtYNO w7Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kZkLbz+f7/EfirsehKat4rN2RysgLCvVTYIf4Y5dEac=; b=fSTiY5zbrX0r2zvtsUJtpRrKe/zCUAVZD9j52BMhEBM/ke2bpPcqIJe6rEqQJqYB8s uY25/iswPU0xFyjPOT3RJjbZypTaJU8imrh/5waUlqaLyhVghfyzhY7QcEYDo943nz8x La68fn3uE5epM81VVAVqL3opGnZ31DHfQdw77UPDbFIV5oXYrsXArOY7WBwGOL9UgjBk hvc8XWrP7o5VpXkj3Fb3egwo0OWN73t8Y1F61rp4BJbX5ndPju3xPcN0NnFCBsS2Gwz9 PCvs8/zwEsFmWzbC7fQLXxTeN1kNZacmNxzY2utiG7nApuyrNdocA5H3atxaDN7FB6lE +suA== X-Gm-Message-State: AOAM5331QuMynamSLvlXzw5nbv15b4GeOdJq3DsBun/i1g0yeE9bnsfG oFBScNiUBik+VDqRvsZUXNvH+Q== X-Google-Smtp-Source: ABdhPJzVdv4RYvzAW1gmhRtEUQDm0W0Tbbjp8b3NPRi5mHKkJbhJ1VPtyWl4/wymvskUAa3D4zUNtQ== X-Received: by 2002:a17:902:c651:b029:12c:1ec0:a8b8 with SMTP id s17-20020a170902c651b029012c1ec0a8b8mr5409919pls.40.1627965902984; Mon, 02 Aug 2021 21:45:02 -0700 (PDT) Received: from hsinchu15.internal.sifive.com (59-124-168-89.HINET-IP.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2sm15327998pgv.87.2021.08.02.21.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:45:02 -0700 (PDT) From: Zong Li To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, seanga2@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de Cc: Zong Li Subject: [PATCH v2 6/6] riscv: lib: modify the indent Date: Tue, 3 Aug 2021 12:44:44 +0800 Message-Id: <20210803044444.14032-7-zong.li@sifive.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210803044444.14032-1-zong.li@sifive.com> References: <20210803044444.14032-1-zong.li@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean We usually use a space in function declaration, rather than a tab. Signed-off-by: Zong Li Reviewed-by: Sean Anderson --- arch/riscv/include/asm/cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 6ebb2b4329..b700ff5021 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ #define _ASM_RISCV_CACHE_H /* cache */ -void cache_flush(void); +void cache_flush(void); int cache_init(void); /*