From patchwork Mon Jul 26 07:14:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509859 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB7r2ftYz9sXS for ; Mon, 26 Jul 2021 17:17:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232283AbhGZGgl (ORCPT ); Mon, 26 Jul 2021 02:36:41 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:45968 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231785AbhGZGgi (ORCPT ); Mon, 26 Jul 2021 02:36:38 -0400 X-UUID: 5605339293344bd281eebf37d62955e5-20210726 X-UUID: 5605339293344bd281eebf37d62955e5-20210726 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1555355200; Mon, 26 Jul 2021 15:17:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:00 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 01/12] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC Date: Mon, 26 Jul 2021 15:14:28 +0800 Message-ID: <20210726071439.14248-2-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the binding documentation for topckgen, apmixedsys, infracfg, infracfg_ao, and ethernet subsystem clocks. Signed-off-by: Sam Shih --- .../devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 2 ++ .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++ .../devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 5 files changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index ea827e8763de..3fa755866528 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" + - "mediatek,mt7986-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 6b7e8067e7aa..0502db73686b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index eb3523c7a7be..5f68c30162bf 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -15,6 +15,8 @@ Required Properties: - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" + - "mediatek,mt7986-infracfg", "syscon" + - "mediatek,mt7986-infracfg_ao", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index 30cb645c0e54..0e1184392941 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 5ce7578cf274..b82422bb717f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - "mediatek,mt7629-topckgen" + - "mediatek,mt7986-topckgen", "syscon" - "mediatek,mt8135-topckgen" - "mediatek,mt8167-topckgen", "syscon" - "mediatek,mt8173-topckgen" From patchwork Mon Jul 26 07:14:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509861 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB830Xf3z9sXS for ; Mon, 26 Jul 2021 17:17:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232302AbhGZGgv (ORCPT ); Mon, 26 Jul 2021 02:36:51 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:46260 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232182AbhGZGgt (ORCPT ); Mon, 26 Jul 2021 02:36:49 -0400 X-UUID: 5ba0abe8fe12481c8b3401f29cd58a22-20210726 X-UUID: 5ba0abe8fe12481c8b3401f29cd58a22-20210726 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 479065312; Mon, 26 Jul 2021 15:17:13 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:12 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 02/12] clk: mediatek: add mt7986 clock IDs Date: Mon, 26 Jul 2021 15:14:29 +0800 Message-ID: <20210726071439.14248-3-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MT7986 clock dt-bindings, include topckgen, apmixedsys, infracfg, infracfg_ao, and ethernet subsystem clocks. Signed-off-by: Sam Shih --- include/dt-bindings/clock/mt7986-clk.h | 244 +++++++++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 include/dt-bindings/clock/mt7986-clk.h diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h new file mode 100644 index 000000000000..dd11d0a717bc --- /dev/null +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + */ + +#ifndef _DT_BINDINGS_CLK_MT7986_H +#define _DT_BINDINGS_CLK_MT7986_H + +/* INFRACFG */ + +#define CK_INFRA_CK_F26M 0 +#define CK_INFRA_UART 1 +#define CK_INFRA_ISPI0 2 +#define CK_INFRA_I2C 3 +#define CK_INFRA_ISPI1 4 +#define CK_INFRA_PWM 5 +#define CK_INFRA_66M_MCK 6 +#define CK_INFRA_CK_F32K 7 +#define CK_INFRA_PCIE_CK 8 +#define CK_INFRA_PWM_BCK 9 +#define CK_INFRA_PWM_CK1 10 +#define CK_INFRA_PWM_CK2 11 +#define CK_INFRA_133M_HCK 12 +#define CK_INFRA_EIP_CK 13 +#define CK_INFRA_66M_PHCK 14 +#define CK_INFRA_FAUD_L_CK 15 +#define CK_INFRA_FAUD_AUD_CK 16 +#define CK_INFRA_FAUD_EG2_CK 17 +#define CK_INFRA_I2CS_CK 18 +#define CK_INFRA_MUX_UART0 19 +#define CK_INFRA_MUX_UART1 20 +#define CK_INFRA_MUX_UART2 21 +#define CK_INFRA_NFI_CK 22 +#define CK_INFRA_SPINFI_CK 23 +#define CK_INFRA_MUX_SPI0 24 +#define CK_INFRA_MUX_SPI1 25 +#define CK_INFRA_RTC_32K 26 +#define CK_INFRA_FMSDC_CK 27 +#define CK_INFRA_FMSDC_HCK_CK 28 +#define CK_INFRA_PERI_133M 29 +#define CK_INFRA_133M_PHCK 30 +#define CK_INFRA_USB_SYS_CK 31 +#define CK_INFRA_USB_CK 32 +#define CK_INFRA_USB_XHCI_CK 33 +#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 +#define CK_INFRA_F26M_CK0 35 +#define CK_INFRA_HD_133M 36 +#define CLK_INFRA_NR_CLK 37 + +/* TOPCKGEN */ + +#define CK_TOP_CB_CKSQ_40M 0 +#define CK_TOP_CB_M_416M 1 +#define CK_TOP_CB_M_D2 2 +#define CK_TOP_CB_M_D4 3 +#define CK_TOP_CB_M_D8 4 +#define CK_TOP_M_D8_D2 5 +#define CK_TOP_M_D3_D2 6 +#define CK_TOP_CB_MM_D2 7 +#define CK_TOP_CB_MM_D4 8 +#define CK_TOP_CB_MM_D8 9 +#define CK_TOP_MM_D8_D2 10 +#define CK_TOP_MM_D3_D8 11 +#define CK_TOP_CB_U2_PHYD_CK 12 +#define CK_TOP_CB_APLL2_196M 13 +#define CK_TOP_APLL2_D4 14 +#define CK_TOP_CB_NET1_D4 15 +#define CK_TOP_CB_NET1_D5 16 +#define CK_TOP_NET1_D5_D2 17 +#define CK_TOP_NET1_D5_D4 18 +#define CK_TOP_NET1_D8_D2 19 +#define CK_TOP_NET1_D8_D4 20 +#define CK_TOP_CB_NET2_800M 21 +#define CK_TOP_CB_NET2_D4 22 +#define CK_TOP_NET2_D4_D2 23 +#define CK_TOP_NET2_D3_D2 24 +#define CK_TOP_CB_WEDMCU_760M 25 +#define CK_TOP_WEDMCU_D5_D2 26 +#define CK_TOP_CB_SGM_325M 27 +#define CK_TOP_CB_CKSQ_40M_D2 28 +#define CK_TOP_CB_RTC_32K 29 +#define CK_TOP_CB_RTC_32P7K 30 +#define CK_TOP_NFI1X 31 +#define CK_TOP_USB_EQ_RX250M 32 +#define CK_TOP_USB_TX250M 33 +#define CK_TOP_USB_LN0_CK 34 +#define CK_TOP_USB_CDR_CK 35 +#define CK_TOP_SPINFI_BCK 36 +#define CK_TOP_I2C_BCK 37 +#define CK_TOP_PEXTP_TL 38 +#define CK_TOP_EMMC_250M 39 +#define CK_TOP_EMMC_416M 40 +#define CK_TOP_F_26M_ADC_CK 41 +#define CK_TOP_SYSAXI 42 +#define CK_TOP_NETSYS_WED_MCU 43 +#define CK_TOP_NETSYS_2X 44 +#define CK_TOP_SGM_325M 45 +#define CK_TOP_A1SYS 46 +#define CK_TOP_EIP_B 47 +#define CK_TOP_F26M 48 +#define CK_TOP_AUD_L 49 +#define CK_TOP_A_TUNER 50 +#define CK_TOP_U2U3_REF 51 +#define CK_TOP_U2U3_SYS 52 +#define CK_TOP_U2U3_XHCI 53 +#define CK_TOP_AP2CNN_HOST 54 +#define CK_TOP_NFI1X_SEL 55 +#define CK_TOP_SPINFI_SEL 56 +#define CK_TOP_SPI_SEL 57 +#define CK_TOP_SPIM_MST_SEL 58 +#define CK_TOP_UART_SEL 59 +#define CK_TOP_PWM_SEL 60 +#define CK_TOP_I2C_SEL 61 +#define CK_TOP_PEXTP_TL_SEL 62 +#define CK_TOP_EMMC_250M_SEL 63 +#define CK_TOP_EMMC_416M_SEL 64 +#define CK_TOP_F_26M_ADC_SEL 65 +#define CK_TOP_DRAMC_SEL 66 +#define CK_TOP_DRAMC_MD32_SEL 67 +#define CK_TOP_SYSAXI_SEL 68 +#define CK_TOP_SYSAPB_SEL 69 +#define CK_TOP_ARM_DB_MAIN_SEL 70 +#define CK_TOP_ARM_DB_JTSEL 71 +#define CK_TOP_NETSYS_SEL 72 +#define CK_TOP_NETSYS_500M_SEL 73 +#define CK_TOP_NETSYS_MCU_SEL 74 +#define CK_TOP_NETSYS_2X_SEL 75 +#define CK_TOP_SGM_325M_SEL 76 +#define CK_TOP_SGM_REG_SEL 77 +#define CK_TOP_A1SYS_SEL 78 +#define CK_TOP_CONN_MCUSYS_SEL 79 +#define CK_TOP_EIP_B_SEL 80 +#define CK_TOP_PCIE_PHY_SEL 81 +#define CK_TOP_USB3_PHY_SEL 82 +#define CK_TOP_F26M_SEL 83 +#define CK_TOP_AUD_L_SEL 84 +#define CK_TOP_A_TUNER_SEL 85 +#define CK_TOP_U2U3_SEL 86 +#define CK_TOP_U2U3_SYS_SEL 87 +#define CK_TOP_U2U3_XHCI_SEL 88 +#define CK_TOP_DA_U2_REFSEL 89 +#define CK_TOP_DA_U2_CK_1P_SEL 90 +#define CK_TOP_AP2CNN_HOST_SEL 91 +#define CLK_TOP_NR_CLK 92 + +/* INFRACFG_AO */ + +#define CK_INFRA_UART0_SEL 0 +#define CK_INFRA_UART1_SEL 1 +#define CK_INFRA_UART2_SEL 2 +#define CK_INFRA_SPI0_SEL 3 +#define CK_INFRA_SPI1_SEL 4 +#define CK_INFRA_PWM1_SEL 5 +#define CK_INFRA_PWM2_SEL 6 +#define CK_INFRA_PWM_BSEL 7 +#define CK_INFRA_PCIE_SEL 8 +#define CK_INFRA_GPT_STA 9 +#define CK_INFRA_PWM_HCK 10 +#define CK_INFRA_PWM_STA 11 +#define CK_INFRA_PWM1_CK 12 +#define CK_INFRA_PWM2_CK 13 +#define CK_INFRA_CQ_DMA_CK 14 +#define CK_INFRA_EIP97_CK 15 +#define CK_INFRA_AUD_BUS_CK 16 +#define CK_INFRA_AUD_26M_CK 17 +#define CK_INFRA_AUD_L_CK 18 +#define CK_INFRA_AUD_AUD_CK 19 +#define CK_INFRA_AUD_EG2_CK 20 +#define CK_INFRA_DRAMC_26M_CK 21 +#define CK_INFRA_DBG_CK 22 +#define CK_INFRA_AP_DMA_CK 23 +#define CK_INFRA_SEJ_CK 24 +#define CK_INFRA_SEJ_13M_CK 25 +#define CK_INFRA_THERM_CK 26 +#define CK_INFRA_I2CO_CK 27 +#define CK_INFRA_UART0_CK 28 +#define CK_INFRA_UART1_CK 29 +#define CK_INFRA_UART2_CK 30 +#define CK_INFRA_NFI1_CK 31 +#define CK_INFRA_SPINFI1_CK 32 +#define CK_INFRA_NFI_HCK_CK 33 +#define CK_INFRA_SPI0_CK 34 +#define CK_INFRA_SPI1_CK 35 +#define CK_INFRA_SPI0_HCK_CK 36 +#define CK_INFRA_SPI1_HCK_CK 37 +#define CK_INFRA_FRTC_CK 38 +#define CK_INFRA_MSDC_CK 39 +#define CK_INFRA_MSDC_HCK_CK 40 +#define CK_INFRA_MSDC_133M_CK 41 +#define CK_INFRA_MSDC_66M_CK 42 +#define CK_INFRA_ADC_26M_CK 43 +#define CK_INFRA_ADC_FRC_CK 44 +#define CK_INFRA_FBIST2FPC_CK 45 +#define CK_INFRA_IUSB_133_CK 46 +#define CK_INFRA_IUSB_66M_CK 47 +#define CK_INFRA_IUSB_SYS_CK 48 +#define CK_INFRA_IUSB_CK 49 +#define CK_INFRA_IPCIE_CK 50 +#define CK_INFRA_IPCIE_PIPE_CK 51 +#define CK_INFRA_IPCIER_CK 52 +#define CK_INFRA_IPCIEB_CK 53 +#define CK_INFRA_TRNG_CK 54 +#define CLK_INFRA_AO_NR_CLK 55 + +/* APMIXEDSYS */ + +#define CK_APMIXED_ARMPLL 0 +#define CK_APMIXED_NET2PLL 1 +#define CK_APMIXED_MMPLL 2 +#define CK_APMIXED_SGMPLL 3 +#define CK_APMIXED_WEDMCUPLL 4 +#define CK_APMIXED_NET1PLL 5 +#define CK_APMIXED_MPLL 6 +#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_NR_CLK 8 + +/* SGMIISYS_0 */ + +#define CK_SGM0_TX_EN 0 +#define CK_SGM0_RX_EN 1 +#define CK_SGM0_CK0_EN 2 +#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGMII0_NR_CLK 4 + +/* SGMIISYS_1 */ + +#define CK_SGM1_TX_EN 0 +#define CK_SGM1_RX_EN 1 +#define CK_SGM1_CK1_EN 2 +#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGMII1_NR_CLK 4 + +/* ETHSYS */ + +#define CK_ETH_FE_EN 0 +#define CK_ETH_GP2_EN 1 +#define CK_ETH_GP1_EN 2 +#define CK_ETH_WOCPU1_EN 3 +#define CK_ETH_WOCPU0_EN 4 +#define CLK_ETH_NR_CLK 5 + +#endif /* _DT_BINDINGS_CLK_MT7986_H */ + From patchwork Mon Jul 26 07:14:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509866 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB8R692sz9shx for ; Mon, 26 Jul 2021 17:17:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232434AbhGZGhM (ORCPT ); Mon, 26 Jul 2021 02:37:12 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:46704 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232367AbhGZGhE (ORCPT ); Mon, 26 Jul 2021 02:37:04 -0400 X-UUID: 0e856443db9a4e8bb333924e1b872f71-20210726 X-UUID: 0e856443db9a4e8bb333924e1b872f71-20210726 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1914989587; Mon, 26 Jul 2021 15:17:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:28 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 05/12] dt-bindings: pinctrl: update bindings for MT7986 SoC Date: Mon, 26 Jul 2021 15:14:32 +0800 Message-ID: <20210726071439.14248-6-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This updates bindings for MT7986 pinctrl driver. The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih --- .../bindings/pinctrl/pinctrl-mt7622.txt | 284 ++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt index 7a7aca1ed705..3c42eaad7a5e 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt @@ -4,6 +4,8 @@ Required properties for the root node: - compatible: Should be one of the following "mediatek,mt7622-pinctrl" for MT7622 SoC "mediatek,mt7629-pinctrl" for MT7629 SoC + "mediatek,mt7986a-pinctrl" for MT7986a SoC + "mediatek,mt7986b-pinctrl" for MT7986b SoC - reg: offset and length of the pinctrl space - gpio-controller: Marks the device node as a GPIO controller. @@ -455,6 +457,288 @@ Valid values for groups are: "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 +== Valid values for pins, function and groups on MT7986a == + +Valid values for pins are: +pins can be referenced via the pin names as the below table shown and the +related physical number is also put ahead of those names which helps cross +references to pins between groups to know whether pins assignment conflict +happens among devices try to acquire those available pins. + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "SYS_WATCHDOG" + PIN 1: "WF2G_LED" + PIN 2: "WF5G_LED" + PIN 3: "I2C_SCL" + PIN 4: "I2C_SDA" + PIN 5: "GPIO_0" + PIN 6: "GPIO_1" + PIN 7: "GPIO_2" + PIN 8: "GPIO_3" + PIN 9: "GPIO_4" + PIN 10: "GPIO_5" + PIN 11: "GPIO_6" + PIN 12: "GPIO_7" + PIN 13: "GPIO_8" + PIN 14: "GPIO_9" + PIN 15: "GPIO_10" + PIN 16: "GPIO_11" + PIN 17: "GPIO_12" + PIN 18: "GPIO_13" + PIN 19: "GPIO_14" + PIN 20: "GPIO_15" + PIN 21: "PWM0" + PIN 22: "PWM1" + PIN 23: "SPI0_CLK" + PIN 24: "SPI0_MOSI" + PIN 25: "SPI0_MISO" + PIN 26: "SPI0_CS" + PIN 27: "SPI0_HOLD" + PIN 28: "SPI0_WP" + PIN 29: "SPI1_CLK" + PIN 30: "SPI1_MOSI" + PIN 31: "SPI1_MISO" + PIN 32: "SPI1_CS" + PIN 33: "SPI2_CLK" + PIN 34: "SPI2_MOSI" + PIN 35: "SPI2_MISO" + PIN 36: "SPI2_CS" + PIN 37: "SPI2_HOLD" + PIN 38: "SPI2_WP" + PIN 39: "UART0_RXD" + PIN 40: "UART0_TXD" + PIN 41: "PCIE_PERESET_N" + PIN 42: "UART1_RXD" + PIN 43: "UART1_TXD" + PIN 44: "UART1_CTS" + PIN 45: "UART1_RTS" + PIN 46: "UART2_RXD" + PIN 47: "UART2_TXD" + PIN 48: "UART2_CTS" + PIN 49: "UART2_RTS" + PIN 50: "EMMC_DATA_0" + PIN 51: "EMMC_DATA_1" + PIN 52: "EMMC_DATA_2" + PIN 53: "EMMC_DATA_3" + PIN 54: "EMMC_DATA_4" + PIN 55: "EMMC_DATA_5" + PIN 56: "EMMC_DATA_6" + PIN 57: "EMMC_DATA_7" + PIN 58: "EMMC_CMD" + PIN 59: "EMMC_CK" + PIN 60: "EMMC_DSL" + PIN 61: "EMMC_RSTB" + PIN 62: "PCM_DTX" + PIN 63: "PCM_DRX" + PIN 64: "PCM_CLK" + PIN 65: "PCM_FS" + PIN 66: "MT7531_INT" + PIN 67: "SMI_MDC" + PIN 68: "SMI_MDIO" + PIN 69: "WF0_DIG_RESETB" + PIN 70: "WF0_CBA_RESETB" + PIN 71: "WF0_XO_REQ" + PIN 72: "WF0_TOP_CLK" + PIN 73: "WF0_TOP_DATA" + PIN 74: "WF0_HB1" + PIN 75: "WF0_HB2" + PIN 76: "WF0_HB3" + PIN 77: "WF0_HB4" + PIN 78: "WF0_HB0" + PIN 79: "WF0_HB0_B" + PIN 80: "WF0_HB5" + PIN 81: "WF0_HB6" + PIN 82: "WF0_HB7" + PIN 83: "WF0_HB8" + PIN 84: "WF0_HB9" + PIN 85: "WF0_HB10" + PIN 86: "WF1_DIG_RESETB" + PIN 87: "WF1_CBA_RESETB" + PIN 88: "WF1_XO_REQ" + PIN 89: "WF1_TOP_CLK" + PIN 90: "WF1_TOP_DATA" + PIN 91: "WF1_HB1" + PIN 92: "WF1_HB2" + PIN 93: "WF1_HB3" + PIN 94: "WF1_HB4" + PIN 95: "WF1_HB0" + PIN 96: "WF1_HB0_B" + PIN 97: "WF1_HB5" + PIN 98: "WF1_HB6" + PIN 99: "WF1_HB7" + PIN 100: "WF1_HB8" + +Valid values for function are: + "audio, "emmc", "eth", "i2c", "wifi", "led", "flash", "pcie", + "pwm", "spi", "uart", "watchdog" + +Valid values for groups are: +additional data is put followingly with valid value allowing us to know which +applicable function and which relevant pins (in pin#) are able applied for that +group. + + Valid value function pins (in pin#) + ------------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "pcie_clk" "pcie" 9 + "pcie_wake" "pcie" 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32 + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2" "uart" 29, 30, 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0" "uart" 29, 30, 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "uart0" "uart" 39, 40 + "pcie_pereset" "pcie" 41 + "uart1" "uart" 42, 43, 44, 45 + "uart2" "uart" 46, 47, 48, 49 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, + 56, 57, 57, 59, 60, 61 + "pcm" "audio" 62, 63, 64, 65 + "i2s" "audio" 62, 63, 64, 65 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + +== Valid values for pins, function and groups on MT7986b == + +Valid values for pins are: +pins can be referenced via the pin names as the below table shown and the +related physical number is also put ahead of those names which helps cross +references to pins between groups to know whether pins assignment conflict +happens among devices try to acquire those available pins. + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "SYS_WATCHDOG" + PIN 1: "WF2G_LED" + PIN 2: "WF5G_LED" + PIN 3: "I2C_SCL" + PIN 4: "I2C_SDA" + PIN 5: "GPIO_0" + PIN 6: "GPIO_1" + PIN 7: "GPIO_2" + PIN 8: "GPIO_3" + PIN 9: "GPIO_4" + PIN 10: "GPIO_5" + PIN 11: "GPIO_6" + PIN 12: "GPIO_7" + PIN 13: "GPIO_8" + PIN 14: "GPIO_9" + PIN 15: "GPIO_10" + PIN 16: "GPIO_11" + PIN 17: "GPIO_12" + PIN 18: "GPIO_13" + PIN 19: "GPIO_14" + PIN 20: "GPIO_15" + PIN 21: "PWM0" + PIN 22: "PWM1" + PIN 23: "SPI0_CLK" + PIN 24: "SPI0_MOSI" + PIN 25: "SPI0_MISO" + PIN 26: "SPI0_CS" + PIN 27: "SPI0_HOLD" + PIN 28: "SPI0_WP" + PIN 29: "SPI1_CLK" + PIN 30: "SPI1_MOSI" + PIN 31: "SPI1_MISO" + PIN 32: "SPI1_CS" + PIN 33: "SPI2_CLK" + PIN 34: "SPI2_MOSI" + PIN 35: "SPI2_MISO" + PIN 36: "SPI2_CS" + PIN 37: "SPI2_HOLD" + PIN 38: "SPI2_WP" + PIN 39: "UART0_RXD" + PIN 40: "UART0_TXD" + PIN 66: "MT7531_INT" + PIN 67: "SMI_MDC" + PIN 68: "SMI_MDIO" + PIN 69: "WF0_DIG_RESETB" + PIN 70: "WF0_CBA_RESETB" + PIN 71: "WF0_XO_REQ" + PIN 72: "WF0_TOP_CLK" + PIN 73: "WF0_TOP_DATA" + PIN 74: "WF0_HB1" + PIN 75: "WF0_HB2" + PIN 76: "WF0_HB3" + PIN 77: "WF0_HB4" + PIN 78: "WF0_HB0" + PIN 79: "WF0_HB0_B" + PIN 80: "WF0_HB5" + PIN 81: "WF0_HB6" + PIN 82: "WF0_HB7" + PIN 83: "WF0_HB8" + PIN 84: "WF0_HB9" + PIN 85: "WF0_HB10" + PIN 86: "WF1_DIG_RESETB" + PIN 87: "WF1_CBA_RESETB" + PIN 88: "WF1_XO_REQ" + PIN 89: "WF1_TOP_CLK" + PIN 90: "WF1_TOP_DATA" + PIN 91: "WF1_HB1" + PIN 92: "WF1_HB2" + PIN 93: "WF1_HB3" + PIN 94: "WF1_HB4" + PIN 95: "WF1_HB0" + PIN 96: "WF1_HB0_B" + PIN 97: "WF1_HB5" + PIN 98: "WF1_HB6" + PIN 99: "WF1_HB7" + PIN 100: "WF1_HB8" + +Valid values for function are: + "emmc", "eth", "i2c", "wifi", "led", "flash", "pwm", "spi", + "uart", "watchdog" + +Valid values for groups are: +additional data is put followingly with valid value allowing us to know which +applicable function and which relevant pins (in pin#) are able applied for that +group. + + Valid value function pins (in pin#) + ------------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32 + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2" "uart" 29, 30, 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0" "uart" 29, 30, 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + + Example: pio: pinctrl@10211000 { From patchwork Mon Jul 26 07:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509869 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB8f4tc6z9sj5 for ; Mon, 26 Jul 2021 17:17:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232455AbhGZGhX (ORCPT ); Mon, 26 Jul 2021 02:37:23 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:47042 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232433AbhGZGhN (ORCPT ); Mon, 26 Jul 2021 02:37:13 -0400 X-UUID: 116db2b178a0409fa837d8f4aeb2ce0b-20210726 X-UUID: 116db2b178a0409fa837d8f4aeb2ce0b-20210726 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 95155452; Mon, 26 Jul 2021 15:17:39 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:37 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 07/12] dt-bindings: arm64: dts: mediatek: Add mt7986 series Date: Mon, 26 Jul 2021 15:14:34 +0800 Message-ID: <20210726071439.14248-8-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7986 is Mediatek's new 4-core SoC, which is mainly for wifi-router application. The difference between mt7986a and mt7986b is that some pins do not exist on mt7986b. Signed-off-by: Sam Shih Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 80a05f6fee85..a9a778269684 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -76,6 +76,14 @@ properties: - enum: - mediatek,mt7629-rfb - const: mediatek,mt7629 + - items: + - enum: + - mediatek,mt7986a-rfb + - const: mediatek,mt7986a + - items: + - enum: + - mediatek,mt7986b-rfb + - const: mediatek,mt7986b - items: - enum: - mediatek,mt8127-moose From patchwork Mon Jul 26 07:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509871 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB8h6H8Sz9sjJ for ; Mon, 26 Jul 2021 17:17:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232568AbhGZGhZ (ORCPT ); Mon, 26 Jul 2021 02:37:25 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:47216 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232474AbhGZGhQ (ORCPT ); Mon, 26 Jul 2021 02:37:16 -0400 X-UUID: d36f0eec8eee4997a60d1779e4be62c3-20210726 X-UUID: d36f0eec8eee4997a60d1779e4be62c3-20210726 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1293606712; Mon, 26 Jul 2021 15:17:42 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:40 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 08/12] dt-bindings: rng: mediatek: add mt7986 to mtk rng binding Date: Mon, 26 Jul 2021 15:14:35 +0800 Message-ID: <20210726071439.14248-9-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add RNG binding for MT7986 SoC. Signed-off-by: Sam Shih --- Documentation/devicetree/bindings/rng/mtk-rng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml index 61888e07bda0..bb32491ee8ae 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -21,6 +21,7 @@ properties: - enum: - mediatek,mt7622-rng - mediatek,mt7629-rng + - mediatek,mt7986-rng - mediatek,mt8365-rng - mediatek,mt8516-rng - const: mediatek,mt7623-rng From patchwork Mon Jul 26 07:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509872 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB8n0fLFz9s5R for ; Mon, 26 Jul 2021 17:18:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232474AbhGZGh3 (ORCPT ); Mon, 26 Jul 2021 02:37:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:57288 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232501AbhGZGhU (ORCPT ); Mon, 26 Jul 2021 02:37:20 -0400 X-UUID: 764bdc84f30c41c496b51d4eb1609a3f-20210726 X-UUID: 764bdc84f30c41c496b51d4eb1609a3f-20210726 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2044231903; Mon, 26 Jul 2021 15:17:45 +0800 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 26 Jul 2021 15:17:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:43 +0800 From: Sam Shih To: Rob Herring , Sean Wang , "Linus Walleij" , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [PATCH 09/12] dt-bindings: serial: Add compatible for Mediatek MT7986 Date: Mon, 26 Jul 2021 15:14:36 +0800 Message-ID: <20210726071439.14248-10-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds dt-binding documentation of uart for Mediatek MT7986 SoC Platform. Signed-off-by: Sam Shih --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 64c4fb59acd1..b3a0bfef0d54 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -15,6 +15,7 @@ Required properties: * "mediatek,mt7622-uart" for MT7622 compatible UARTS * "mediatek,mt7623-uart" for MT7623 compatible UARTS * "mediatek,mt7629-uart" for MT7629 compatible UARTS + * "mediatek,mt7986-uart", "mediatek,mt6577-uart" for MT7986 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS From patchwork Mon Jul 26 07:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1509874 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GYB8q2fCBz9sXS for ; Mon, 26 Jul 2021 17:18:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232371AbhGZGhc (ORCPT ); Mon, 26 Jul 2021 02:37:32 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:47410 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232517AbhGZGhW (ORCPT ); Mon, 26 Jul 2021 02:37:22 -0400 X-UUID: a5c4e25166ba4c85813b73fefc1c59b3-20210726 X-UUID: a5c4e25166ba4c85813b73fefc1c59b3-20210726 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1785658365; Mon, 26 Jul 2021 15:17:49 +0800 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:47 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 26 Jul 2021 15:17:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:47 +0800 From: Sam Shih To: Rob Herring , Sean Wang , "Linus Walleij" , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [PATCH 10/12] dt-bindings: watchdog: Add compatible for Mediatek MT7986 Date: Mon, 26 Jul 2021 15:14:37 +0800 Message-ID: <20210726071439.14248-11-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds dt-binding documentation of watchdog for Mediatek MT7986 SoC Platform. Signed-off-by: Sam Shih Acked-by: Rob Herring Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 416d716403f6..a4e31ce96e0e 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 + "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192