From patchwork Fri Jul 23 20:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhc1Xvjz9sXN for ; Sat, 24 Jul 2021 07:06:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231912AbhGWU0W (ORCPT ); Fri, 23 Jul 2021 16:26:22 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57818 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229461AbhGWU0V (ORCPT ); Fri, 23 Jul 2021 16:26:21 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727O-0057Vc-9G; Fri, 23 Jul 2021 20:50:02 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 1/6] dt-bindings: imx6q-pcie: add compatible for IMX8MM support Date: Fri, 23 Jul 2021 13:49:53 -0700 Message-Id: <20210723204958.7186-2-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds the DT binding for IMX8MM support to the existing imx6q-pcie driver which shares most functionality with the IMX8MM. Additionally a 'fsl,ext-osc' property is defined to note use of an external oscillator as ref clock vs the internal PLL. Signed-off-by: Tim Harvey --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d8971ab99274..9886e1344fd3 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -10,6 +10,7 @@ Required properties: - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" - "fsl,imx8mq-pcie" + - "fsl,imx8mm-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -19,6 +20,7 @@ Required properties: - "pcie_phy" Optional properties: +- fsl,ext-osc: use the external oscillator as ref clock (vs internal PLL) - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 @@ -49,7 +51,7 @@ Additional required properties for imx6sx-pcie: PCIE_PHY power domains - power-domain-names: Must be "pcie", "pcie_phy" -Additional required properties for imx7d-pcie and imx8mq-pcie: +Additional required properties for imx7d-pcie, imx8mq-pcie, imx8mm-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain - resets: Must contain phandles to PCIe-related reset lines exposed by SRC IP block From patchwork Fri Jul 23 20:49:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhf18Vhz9sWl for ; Sat, 24 Jul 2021 07:06:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231940AbhGWU0Y (ORCPT ); Fri, 23 Jul 2021 16:26:24 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57824 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231754AbhGWU0Y (ORCPT ); Fri, 23 Jul 2021 16:26:24 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727P-0057Vc-DS; Fri, 23 Jul 2021 20:50:03 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 2/6] dt-bindings: reset: imx8mq: add pcie reset Date: Fri, 23 Jul 2021 13:49:54 -0700 Message-Id: <20210723204958.7186-3-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add the reset used by the pcie driver Signed-off-by: Tim Harvey --- include/dt-bindings/reset/imx8mq-reset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 705870693ec2..20a25ee4a271 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -61,7 +61,8 @@ #define IMX8MQ_RESET_SW_M4C_RST 50 #define IMX8MQ_RESET_SW_M4P_RST 51 #define IMX8MQ_RESET_M4_ENABLE 52 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ 53 -#define IMX8MQ_RESET_NUM 53 +#define IMX8MQ_RESET_NUM 54 #endif From patchwork Fri Jul 23 20:49:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhf6Vthz9sS8 for ; Sat, 24 Jul 2021 07:06:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231948AbhGWU0Z (ORCPT ); Fri, 23 Jul 2021 16:26:25 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57826 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231754AbhGWU0Y (ORCPT ); Fri, 23 Jul 2021 16:26:24 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727Q-0057Vc-Gh; Fri, 23 Jul 2021 20:50:04 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 3/6] PCI: imx6: add IMX8MM support Date: Fri, 23 Jul 2021 13:49:55 -0700 Message-Id: <20210723204958.7186-4-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add IMX8MM support to the existing driver which shares most functionality with the IMX8MM. Signed-off-by: Tim Harvey --- drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 80fc98acf097..8fb36d33a244 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -49,6 +49,7 @@ enum imx6_pcie_variants { IMX6QP, IMX7D, IMX8MQ, + IMX8MM, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -83,6 +84,7 @@ struct imx6_pcie { struct regulator *vpcie; struct regulator *vph; void __iomem *phy_base; + bool ext_osc; /* power domain for pcie */ struct device *pd_pcie; @@ -139,10 +141,29 @@ struct imx6_pcie { #define PCIE_PHY_CMN_REG26 0x98 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC +#define PCIE_PHY_CMN_REG62 0x188 +#define PCIE_PHY_CMN_REG62_PLL_CLK_OUT 0x08 +#define PCIE_PHY_CMN_REG64 0x190 +#define PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM 0x8C +#define PCIE_PHY_CMN_REG75 0x1D4 +#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 +#define PCIE_PHY_TRSV_REG5 0x414 +#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D +#define PCIE_PHY_TRSV_REG6 0x418 +#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF + #define PHY_RX_OVRD_IN_LO 0x1005 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +#define IMX8MM_GPR_PCIE_REF_CLK_SEL (0x3 << 24) +#define IMX8MM_GPR_PCIE_REF_CLK_PLL (0x3 << 24) +#define IMX8MM_GPR_PCIE_REF_CLK_EXT (0x2 << 24) +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -371,6 +392,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) switch (imx6_pcie->drvdata->variant) { case IMX7D: case IMX8MQ: + case IMX8MM: reset_control_assert(imx6_pcie->pciephy_reset); reset_control_assert(imx6_pcie->apps_reset); break; @@ -407,7 +429,6 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) { - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ); return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } @@ -447,6 +468,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX7D: break; case IMX8MQ: + case IMX8MM: ret = clk_prepare_enable(imx6_pcie->pcie_aux); if (ret) { dev_err(dev, "unable to enable pcie_aux clock\n"); @@ -536,6 +558,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) switch (imx6_pcie->drvdata->variant) { case IMX8MQ: + case IMX8MM: reset_control_deassert(imx6_pcie->pciephy_reset); break; case IMX7D: @@ -613,7 +636,74 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { + unsigned int offset; + switch (imx6_pcie->drvdata->variant) { + case IMX8MM: + offset = imx6_pcie_grp_offset(imx6_pcie); + + dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n", + imx6_pcie->ext_osc ? "EXT" : "PLL"); + if (imx6_pcie->ext_osc) { + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + IMX8MM_GPR_PCIE_REF_CLK_SEL); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_SSC_EN, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + IMX8MM_GPR_PCIE_REF_CLK_EXT); + udelay(100); + /* Do the PHY common block reset */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + udelay(200); + } else { + /* Configure the internal PLL as REF clock */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + IMX8MM_GPR_PCIE_REF_CLK_SEL); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_SSC_EN, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + IMX8MM_GPR_PCIE_REF_CLK_PLL); + udelay(100); + /* Configure the PHY */ + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); + /* Do the PHY common block reset */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + udelay(200); + } + /* + * In order to pass the compliance tests. + * Configure the TRSV regiser of iMX8MM PCIe PHY. + */ + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); + writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP, + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG6); + break; case IMX8MQ: /* * TODO: Currently this code assumes external @@ -753,6 +843,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) break; case IMX7D: case IMX8MQ: + case IMX8MM: reset_control_deassert(imx6_pcie->apps_reset); break; } @@ -871,6 +962,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, 0); break; case IMX7D: + case IMX8MM: reset_control_assert(imx6_pcie->apps_reset); break; default: @@ -929,6 +1021,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; + case IMX8MM: case IMX8MQ: clk_disable_unprepare(imx6_pcie->pcie_aux); break; @@ -1024,6 +1117,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); + /* check for EXT osc */ + imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc"); + /* Fetch GPIOs */ imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); imx6_pcie->gpio_active_high = of_property_read_bool(node, @@ -1067,6 +1163,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) "pcie_inbound_axi clock missing or invalid\n"); break; case IMX8MQ: + case IMX8MM: imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), @@ -1202,6 +1299,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX8MQ] = { .variant = IMX8MQ, }, + [IMX8MM] = { + .variant = IMX8MM, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1210,6 +1310,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } , + { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, {}, }; From patchwork Fri Jul 23 20:49:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhd2nWdz9sS8 for ; Sat, 24 Jul 2021 07:06:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231934AbhGWU0X (ORCPT ); Fri, 23 Jul 2021 16:26:23 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57822 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231754AbhGWU0X (ORCPT ); Fri, 23 Jul 2021 16:26:23 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727R-0057Vc-KE; Fri, 23 Jul 2021 20:50:05 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 4/6] reset: imx7: add resets for PCIe Date: Fri, 23 Jul 2021 13:49:56 -0700 Message-Id: <20210723204958.7186-5-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add reset for PCIe clock and PHY. Signed-off-by: Tim Harvey --- drivers/reset/reset-imx7.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 185a333df66c..423707e1fd59 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -191,6 +191,7 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ] = { SRC_PCIEPHY_RCR, BIT(4) }, [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, @@ -234,7 +235,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev, udelay(10); break; + case IMX8MQ_RESET_PCIEPHY_PERST: case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: + case IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ: case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: From patchwork Fri Jul 23 20:49:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhc6qGqz9sWl for ; Sat, 24 Jul 2021 07:06:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229461AbhGWU0W (ORCPT ); Fri, 23 Jul 2021 16:26:22 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57820 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231940AbhGWU0W (ORCPT ); Fri, 23 Jul 2021 16:26:22 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727S-0057Vc-QT; Fri, 23 Jul 2021 20:50:06 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 5/6] arm64: dts: imx8mm: add PCIe support Date: Fri, 23 Jul 2021 13:49:57 -0700 Message-Id: <20210723204958.7186-6-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe node for PCIe support. Signed-off-by: Tim Harvey --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 3bec6b8d52a0..45017f50a11b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1134,6 +1134,10 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x32f00000 0x10000>; + }; }; dma_apbh: dma-controller@33000000 { @@ -1233,5 +1237,37 @@ reg = <0x3d800000 0x400000>; interrupts = ; }; + + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; }; }; From patchwork Fri Jul 23 20:49:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhhg5F5bz9sWw for ; Sat, 24 Jul 2021 07:06:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231754AbhGWU0Z (ORCPT ); Fri, 23 Jul 2021 16:26:25 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57828 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231951AbhGWU0Z (ORCPT ); Fri, 23 Jul 2021 16:26:25 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727T-0057Vc-V6; Fri, 23 Jul 2021 20:50:08 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 6/6] arm64: dts: imx8mm: add gpc iomux compatible Date: Fri, 23 Jul 2021 13:49:58 -0700 Message-Id: <20210723204958.7186-7-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add gpc iomux compatible needed for IMX8MM PCIe. Signed-off-by: Tim Harvey --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 45017f50a11b..a2de42dc5f61 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -519,7 +519,7 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };