From patchwork Fri Jul 23 20:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509380 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhKG0jB4z9sWl for ; Sat, 24 Jul 2021 06:50:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231168AbhGWUJf (ORCPT ); Fri, 23 Jul 2021 16:09:35 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57708 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229461AbhGWUJf (ORCPT ); Fri, 23 Jul 2021 16:09:35 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727O-0057Vc-9G; Fri, 23 Jul 2021 20:50:02 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 1/6] dt-bindings: imx6q-pcie: add compatible for IMX8MM support Date: Fri, 23 Jul 2021 13:49:53 -0700 Message-Id: <20210723204958.7186-2-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the DT binding for IMX8MM support to the existing imx6q-pcie driver which shares most functionality with the IMX8MM. Additionally a 'fsl,ext-osc' property is defined to note use of an external oscillator as ref clock vs the internal PLL. Signed-off-by: Tim Harvey --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d8971ab99274..9886e1344fd3 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -10,6 +10,7 @@ Required properties: - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" - "fsl,imx8mq-pcie" + - "fsl,imx8mm-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -19,6 +20,7 @@ Required properties: - "pcie_phy" Optional properties: +- fsl,ext-osc: use the external oscillator as ref clock (vs internal PLL) - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 @@ -49,7 +51,7 @@ Additional required properties for imx6sx-pcie: PCIE_PHY power domains - power-domain-names: Must be "pcie", "pcie_phy" -Additional required properties for imx7d-pcie and imx8mq-pcie: +Additional required properties for imx7d-pcie, imx8mq-pcie, imx8mm-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain - resets: Must contain phandles to PCIe-related reset lines exposed by SRC IP block From patchwork Fri Jul 23 20:49:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 1509382 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWhKK1BHKz9sWl for ; Sat, 24 Jul 2021 06:50:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231637AbhGWUJi (ORCPT ); Fri, 23 Jul 2021 16:09:38 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57724 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229657AbhGWUJg (ORCPT ); Fri, 23 Jul 2021 16:09:36 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727P-0057Vc-DS; Fri, 23 Jul 2021 20:50:03 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 2/6] dt-bindings: reset: imx8mq: add pcie reset Date: Fri, 23 Jul 2021 13:49:54 -0700 Message-Id: <20210723204958.7186-3-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the reset used by the pcie driver Signed-off-by: Tim Harvey --- include/dt-bindings/reset/imx8mq-reset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 705870693ec2..20a25ee4a271 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -61,7 +61,8 @@ #define IMX8MQ_RESET_SW_M4C_RST 50 #define IMX8MQ_RESET_SW_M4P_RST 51 #define IMX8MQ_RESET_M4_ENABLE 52 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ 53 -#define IMX8MQ_RESET_NUM 53 +#define IMX8MQ_RESET_NUM 54 #endif