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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:11 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 1/6] dm: pci: add option to map virtual system memory base address Date: Thu, 15 Jul 2021 20:53:56 +0200 Message-Id: <20210715185401.301211-2-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE is still used as a virtual, CPU-mapped address instead of being used as physical address. Converting all MIPS boards and generic MIPS code to fix that is not trivial. Due to the approaching deadline for PCI DM conversion, this workaround is required for MIPS boards with PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved. Add a compile-time option to let the PCI uclass core optionally map the DRAM address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- (no changes since v1) drivers/pci/Kconfig | 13 +++++++++++++ drivers/pci/pci-uclass.c | 9 ++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 517cf956ea..c49cb6eac9 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY region type. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on the PCI bus. +config PCI_MAP_SYSTEM_MEMORY + bool "Map local system memory from a virtual base address" + depends on PCI || DM_PCI + depends on MIPS + default n + help + Say Y if base address of system memory is being used as a virtual address + instead of a physical address (e.g. on MIPS). The PCI core will then remap + the virtual memory base address to a physical address when adding the PCI + region of type PCI_REGION_SYS_MEMORY. + This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still + being used as virtual address. + config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" depends on PCI || DM_PCI diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index cb9aa81835..110a12b94b 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1003,10 +1003,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { + phys_addr_t start = bd->bi_dram[i].start; + + if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) + start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + pci_set_region(hose->regions + hose->region_count++, - bd->bi_dram[i].start, - bd->bi_dram[i].start, - bd->bi_dram[i].size, + start, start, bd->bi_dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } From patchwork Thu Jul 15 18:53:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 1505864 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Cs1zNJEo; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GQk7s1wgdz9t23 for ; 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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:13 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 2/6] pci: gt64120: convert to driver model Date: Thu, 15 Jul 2021 20:53:57 +0200 Message-Id: <20210715185401.301211-3-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck Reviewed-by: Simon Glass --- Changes in v2: - add empty line before return statements drivers/pci/pci_gt64120.c | 74 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c index 80f11fedd1..e57fedf036 100644 --- a/drivers/pci/pci_gt64120.c +++ b/drivers/pci/pci_gt64120.c @@ -8,7 +8,7 @@ * Maciej W. Rozycki */ -#include +#include #include #include #include @@ -114,6 +114,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt, return 0; } +#if !IS_ENABLED(CONFIG_DM_PCI) static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 *value) { @@ -175,3 +176,74 @@ void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys, pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); } +#else +static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf, + uint where, ulong *val, + enum pci_size_t size) +{ + struct gt64120_pci_controller *gt = dev_get_priv(dev); + u32 data = 0; + + if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) { + *val = pci_get_ff(size); + return 0; + } + + *val = pci_conv_32_to_size(data, where, size); + + return 0; +} + +static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf, + uint where, ulong val, + enum pci_size_t size) +{ + struct gt64120_pci_controller *gt = dev_get_priv(dev); + u32 data = 0; + + if (size == PCI_SIZE_32) { + data = val; + } else { + u32 old; + + if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old)) + return 0; + + data = pci_conv_size_to_32(old, val, where, size); + } + + gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data); + + return 0; +} + +static int gt64120_pci_probe(struct udevice *dev) +{ + struct gt64120_pci_controller *gt = dev_get_priv(dev); + + gt->regs = dev_remap_addr(dev); + if (!gt->regs) + return -EINVAL; + + return 0; +} + +static const struct dm_pci_ops gt64120_pci_ops = { + .read_config = gt64120_pci_read_config, + .write_config = gt64120_pci_write_config, +}; + +static const struct udevice_id gt64120_pci_ids[] = { + { .compatible = "marvell,pci-gt64120" }, + { } +}; + +U_BOOT_DRIVER(gt64120_pci) = { + .name = "gt64120_pci", + .id = UCLASS_PCI, + .of_match = gt64120_pci_ids, + .ops = >64120_pci_ops, + .probe = gt64120_pci_probe, + .priv_auto = sizeof(struct gt64120_pci_controller), +}; +#endif From patchwork Thu Jul 15 18:53:58 2021 Content-Type: text/plain; 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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:14 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 3/6] pci: msc01: convert to driver model Date: Thu, 15 Jul 2021 20:53:58 +0200 Message-Id: <20210715185401.301211-4-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck Reviewed-by: Simon Glass --- Changes in v2: - add empty line before return statements drivers/pci/pci_msc01.c | 72 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c index 04838200a8..c17da475d0 100644 --- a/drivers/pci/pci_msc01.c +++ b/drivers/pci/pci_msc01.c @@ -4,7 +4,7 @@ * Author: Paul Burton */ -#include +#include #include #include #include @@ -62,6 +62,7 @@ static int msc01_config_access(struct msc01_pci_controller *msc01, return 0; } +#if !IS_ENABLED(CONFIG_DM_PCI) static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 *value) { @@ -123,3 +124,72 @@ void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys, pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); } +#else +static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf, + uint where, ulong *val, enum pci_size_t size) +{ + struct msc01_pci_controller *msc01 = dev_get_priv(dev); + u32 data = 0; + + if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) { + *val = pci_get_ff(size); + return 0; + } + + *val = pci_conv_32_to_size(data, where, size); + + return 0; +} + +static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf, + uint where, ulong val, enum pci_size_t size) +{ + struct msc01_pci_controller *msc01 = dev_get_priv(dev); + u32 data = 0; + + if (size == PCI_SIZE_32) { + data = val; + } else { + u32 old; + + if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old)) + return 0; + + data = pci_conv_size_to_32(old, val, where, size); + } + + msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data); + + return 0; +} + +static int msc01_pci_probe(struct udevice *dev) +{ + struct msc01_pci_controller *msc01 = dev_get_priv(dev); + + msc01->base = dev_remap_addr(dev); + if (!msc01->base) + return -EINVAL; + + return 0; +} + +static const struct dm_pci_ops msc01_pci_ops = { + .read_config = msc01_pci_read_config, + .write_config = msc01_pci_write_config, +}; + +static const struct udevice_id msc01_pci_ids[] = { + { .compatible = "mips,pci-msc01" }, + { } +}; + +U_BOOT_DRIVER(msc01_pci) = { + .name = "msc01_pci", + .id = UCLASS_PCI, + .of_match = msc01_pci_ids, + .ops = &msc01_pci_ops, + .probe = msc01_pci_probe, + .priv_auto = sizeof(struct msc01_pci_controller), +}; +#endif From patchwork Thu Jul 15 18:53:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 1505866 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=YlqtmqNz; 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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:15 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 4/6] MIPS: malta: add DT bindings for PCI host controller Date: Thu, 15 Jul 2021 20:53:59 +0200 Message-Id: <20210715185401.301211-5-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add DT binding for GT64120 and MSC01 PCI controllers. Only GT64120 is enabled by default to support Qemu. The MSC01 node will be dynamically enabled by Malta board code dependent on the plugged core card. Signed-off-by: Daniel Schwierzeck --- (no changes since v1) arch/mips/dts/mti,malta.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts index d339229c2a..ef47a340bb 100644 --- a/arch/mips/dts/mti,malta.dts +++ b/arch/mips/dts/mti,malta.dts @@ -29,4 +29,32 @@ u-boot,dm-pre-reloc; }; }; + + pci0@1bd00000 { + compatible = "mips,pci-msc01"; + device_type = "pci"; + reg = <0x1bd00000 0x2000>; + + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + ranges = <0x01000000 0 0x00000000 0x00000000 0 0x800000 /* I/O */ + 0x02000000 0 0x10000000 0xb0000000 0 0x10000000 /* MEM */>; + + status = "disabled"; + }; + + pci0@1be00000 { + compatible = "marvell,pci-gt64120"; + device_type = "pci"; + reg = <0x1be00000 0x2000>; + + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + ranges = <0x01000000 0 0x00000000 0x00000000 0 0x20000 /* I/O */ + 0x02000000 0 0x10000000 0x10000000 0 0x8000000 /* MEM */>; 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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:16 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 5/6] MIPS: malta: add support for PCI driver model Date: Thu, 15 Jul 2021 20:54:00 +0200 Message-Id: <20210715185401.301211-6-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean As almost all peripherals are connected via PCI dependent on the used core card, PCI setup is always required. Thus run pci_init() including PCI scanning and probing and core card specific setups in board_early_init_r(). Also prepare support for dynamically managing the status of the different PCI DT nodes dependent on used core card via option CONFIG_OF_BOARD_FIXUP. Before this feature can be enabled, the call order of the fix_fdt() init hook in board_init_f needs to be changed. Otherwise rw_fdt_blob points to a read-only NOR flash address. Thus this options needs to stay disabled until the board_init_f problem could be solved. This breaks running the default U-Boot image on real HW using the FPGA core card but Qemu emulation still works. Currently Qemu is more important as MIPS CI tests depend on Malta and the deadline for PCI DM conversion will be enforced soon. Signed-off-by: Daniel Schwierzeck --- Changes in v2: - use dm_pci_clrset_config32() where possible board/imgtec/malta/malta.c | 80 +++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index c04f727961..9af1f92e5d 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -4,7 +4,8 @@ * Copyright (C) 2013 Imagination Technologies */ -#include +#include +#include #include #include #include @@ -24,6 +25,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define MALTA_GT_PATH "/pci0@1be00000" +#define MALTA_MSC_PATH "/pci0@1bd00000" + enum core_card { CORE_UNKNOWN, CORE_LV, @@ -120,10 +124,12 @@ int checkboard(void) return 0; } +#if !IS_ENABLED(CONFIG_DM_ETH) int board_eth_init(struct bd_info *bis) { return pci_eth_init(bis); } +#endif void _machine_restart(void) { @@ -167,6 +173,77 @@ int misc_init_r(void) return 0; } +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +/* + * TODO: currently doesn't work because rw_fdt_blob points to a + * NOR flash address. This needs some changes in board_init_f. + */ +int board_fix_fdt(void *rw_fdt_blob) +{ + int node = -1; + + switch (malta_sys_con()) { + case SYSCON_GT64120: + node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH); + break; + default: + case SYSCON_MSC01: + node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH); + break; + } + + return fdt_status_okay(rw_fdt_blob, node); +} +#endif + +#if IS_ENABLED(CONFIG_DM_PCI) +int board_early_init_r(void) +{ + struct udevice *dev; + int ret; + + pci_init(); + + ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev); + if (ret) + panic("Failed to find PIIX4 PCI bridge\n"); + + /* setup PCI interrupt routing */ + dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10); + dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10); + dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11); + dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11); + + /* mux SERIRQ onto SERIRQ pin */ + dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0, + PCI_CFG_PIIX4_GENCFG_SERIRQ); + + /* enable SERIRQ - Linux currently depends upon this */ + dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0, + PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT); + + ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB, 0, &dev); + if (ret) + panic("Failed to find PIIX4 IDE controller\n"); + + /* enable bus master & IO access */ + dm_pci_clrset_config32(dev, PCI_COMMAND, 0, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* set latency */ + dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); + + /* enable IDE/ATA */ + dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI, + PCI_CFG_PIIX4_IDETIM_IDE); + dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC, + PCI_CFG_PIIX4_IDETIM_IDE); + + return 0; +} +#else void pci_init_board(void) { pci_dev_t bdf; @@ -231,3 +308,4 @@ void pci_init_board(void) pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, PCI_CFG_PIIX4_IDETIM_IDE); } +#endif From patchwork Thu Jul 15 18:54:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 1505868 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[94.134.6.22]) by smtp.gmail.com with ESMTPSA id t17sm2803486edv.75.2021.07.15.11.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jul 2021 11:54:17 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Stefan Roese , Daniel Schwierzeck Subject: [PATCH v2 6/6] MIPS: malta: enable PCI driver model Date: Thu, 15 Jul 2021 20:54:01 +0200 Message-Id: <20210715185401.301211-7-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715185401.301211-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> <20210715185401.301211-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Enable DM_PCI and DM_ETH on MIPS Malta. Signed-off-by: Daniel Schwierzeck --- (no changes since v1) arch/mips/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e54801673b..6b1f10d9a0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,8 +14,11 @@ choice config TARGET_MALTA bool "Support malta" + select BOARD_EARLY_INIT_R select DM select DM_SERIAL + select DM_PCI + select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG @@ -23,6 +26,7 @@ config TARGET_MALTA select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS + select PCI_MAP_SYSTEM_MEMORY select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1