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Thu, 15 Jul 2021 08:54:07 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.61.112]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 15 Jul 2021 08:54:07 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Thu, 15 Jul 2021 14:23:45 +0530 Message-Id: <20210715085345.840351-1-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AncJ86V0BtyXw6Y-b0yisL9XtwhYJEGB X-Proofpoint-ORIG-GUID: AncJ86V0BtyXw6Y-b0yisL9XtwhYJEGB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-15_04:2021-07-14, 2021-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107150064 Subject: [Skiboot] [PATCH] hw/imc: Refactor trace-imc macros X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan Also setup_imc_scoms() moves early in imc_init() to avoid any access of platform specific values before initialization. Signed-off-by: Madhavan Srinivasan Signed-off-by: Vasant Hegde --- hw/imc.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index dab668fe6..7d29ce6f7 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -18,18 +18,24 @@ /* * IMC trace scom values */ -#define IMC_TRACE_SAMPLESEL_VAL 1 /* select cpmc2 */ +#define IMC_TRACE_CPMC1 0 /* select cpmc1 */ +#define IMC_TRACE_CPMC2 1 /* select cpmc2 */ #define IMC_TRACE_CPMCLOAD_VAL 0xfa /* * Value to be loaded into cpmc2 * at sampling start */ -#define IMC_TRACE_CPMC2SEL_VAL 2 /* Event: CPM_32MHZ_CYC */ + +/* Event: CPM_32MHZ_CYC */ +#define IMC_TRACE_CPMC2SEL_VAL 2 +#define IMC_TRACE_CPMC1SEL_VAL 4 + #define IMC_TRACE_BUFF_SIZE 0 /* * b’000’- 4K entries * 64 per * entry = 256K buffersize */ static uint64_t TRACE_IMC_ADDR; static uint64_t CORE_IMC_EVENT_MASK_ADDR; +static uint64_t trace_scom_val; /* * Initialise these with the pdbar and htm scom port address array * at run time, based on the processor version. @@ -547,6 +553,11 @@ static int setup_imc_scoms(void) TRACE_IMC_ADDR = TRACE_IMC_ADDR_P9; pdbar_scom_index = pdbar_scom_index_p9; htm_scom_index = htm_scom_index_p9; + trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_CPMC2, + IMC_TRACE_CPMCLOAD_VAL, + IMC_TRACE_CPMC1SEL_VAL, + IMC_TRACE_CPMC2SEL_VAL, + IMC_TRACE_BUFF_SIZE); return 0; default: prerror("%s: Unknown cpu type\n", __func__); @@ -616,6 +627,11 @@ void imc_init(void) } imc_mambo: + if (setup_imc_scoms()) { + prerror("IMC: Failed to setup the scoms\n"); + goto err; + } + /* Check and remove unsupported imc device types */ check_imc_device_type(dev); @@ -649,11 +665,6 @@ imc_mambo: disable_imc_type_from_dt(dev, IMC_COUNTER_CHIP); } - if (setup_imc_scoms()) { - prerror("IMC: Failed to setup the scoms\n"); - goto err; - } - /* * If the dt_attach_root() fails, "imc-counters" node will not be * seen in the device-tree and hence OS should not make any @@ -816,10 +827,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu int port_id, phys_core_id; int ret; uint32_t htm_addr, trace_addr; - uint64_t trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_SAMPLESEL_VAL, - IMC_TRACE_CPMCLOAD_VAL, 0, - IMC_TRACE_CPMC2SEL_VAL, - IMC_TRACE_BUFF_SIZE); + switch (type) { case OPAL_IMC_COUNTERS_NEST: return OPAL_SUCCESS;