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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id g11sm11098589pgj.3.2021.06.27.05.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jun 2021 05:06:11 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines Date: Sun, 27 Jun 2021 20:06:04 +0800 Message-Id: <20210627120604.11116-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - rebase on qemu/master target/riscv/csr.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fe5628fea6..62b968326c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = riscv_cpu_get_fflags(env); return RISCV_EXCP_NONE; } @@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); @@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno, static RISCVException read_frm(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = env->frm; return RISCV_EXCP_NONE; } @@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif env->frm = val & (FSR_RD >> FSR_RD_SHIFT); @@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno, static RISCVException read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); if (vs(env, csrno) >= 0) { @@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;