From patchwork Tue Jun 22 17:14:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abid Qadeer X-Patchwork-Id: 1495795 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G8Y2r5nPNz9sWH for ; Wed, 23 Jun 2021 03:16:20 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E946B394FC0E for ; Tue, 22 Jun 2021 17:16:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id 8CC733853838 for ; Tue, 22 Jun 2021 17:15:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8CC733853838 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: CDV3fN9VmGqak3PtRLXEN5AS0QsTKiYTxJZrWY49MeevQ2D1aqiewqWKQKFRyg20SJn4d+btW+ RY7SpSv26b0RJS2BsFcvdmm5G7g/hUX7RIBaDF84OTwjj3HroqgZXFnkgD89w7wYgyb0FZx3L/ cQH2D/LTmUtxR/5OolrsOAxSopTsj2Jktw5CZWARd9+TAelsSGIyf9CnFibMV7Mex5AzAKJA3E C9rDeht0rpYYORGV2iJuBRgXy0ENf1hmX0ess3b9IgoVWjzPpirhfKOTS1X74JkC001w5ueZT2 CWA= X-IronPort-AV: E=Sophos;i="5.83,291,1616486400"; d="scan'208";a="62879913" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 22 Jun 2021 09:14:58 -0800 IronPort-SDR: 3z+dwml6BNwlWWZxJVvZzVuPs/nOPBKeAjgEJsIsXY6hqGpZmkAQ2/6xeBlgMDZxNdpZr22N2m jYZkALlkBQ0yO6rIoPI245KUzzzEKSb/lnBPifrOfRRABWlLxgKcy9Dsg8JB0mkeM74APopf1v UKziHZt+2lgHyDODq9HSNBQkDz7ExoOxD0XIvwUTfmD+7mNaiVJ4RhUJ/MnIqYYGjaJvNPLdc1 906FoVnR3j0PFvIjYzLHYU4EJBQ/mSFUZEQI0L8cFrA65xTqPzCF8Jq58w8jlno8ef7bFsuVyT Xj0= From: Hafiz Abid Qadeer To: Subject: [PATCH 1/3] [amdgcn] Update CFI configuration Date: Tue, 22 Jun 2021 18:14:41 +0100 Message-ID: <20210622171443.1287801-2-abidh@codesourcery.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210622171443.1287801-1-abidh@codesourcery.com> References: <20210622171443.1287801-1-abidh@codesourcery.com> MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) To SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ams@codesourcery.com, abidh@codesourcery.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Currently we don't get any call frame information for the amdgcn target. This patch makes necessary adjustments to generate CFI that can work with ROCGDB (ROCm 3.8+). gcc/ * config/gcn/gcn.c (move_callee_saved_registers): Emit CFI notes for prologue register saves. (gcn_debug_unwind_info): Use UI_DWARF2. (gcn_dwarf_register_number): Map DWARF_LINK_REGISTER to DWARF PC. (gcn_dwarf_register_span): DWARF_LINK_REGISTER doesn't span. * config/gcn/gcn.h: (DWARF_FRAME_RETURN_COLUMN): New define. (DWARF_LINK_REGISTER): New define. (FIRST_PSEUDO_REGISTER): Increment. (FIXED_REGISTERS): Add entry for DWARF_LINK_REGISTER. (CALL_USED_REGISTERS): Likewise. (REGISTER_NAMES): Likewise. --- gcc/config/gcn/gcn.c | 82 ++++++++++++++++++++++++++++++++++++++++---- gcc/config/gcn/gcn.h | 10 +++--- 2 files changed, 81 insertions(+), 11 deletions(-) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 283a91fe50a..3ab16548aad 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2649,6 +2649,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, rtx as = gen_rtx_CONST_INT (VOIDmode, STACK_ADDR_SPACE); HOST_WIDE_INT exec_set = 0; int offreg_set = 0; + auto_vec saved_sgprs; start_sequence (); @@ -2665,7 +2666,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, int lane = saved_scalars % 64; if (prologue) - emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane))); + { + emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane))); + saved_sgprs.safe_push (regno); + } else emit_insn (gen_vec_extractv64sisi (reg, vreg, GEN_INT (lane))); @@ -2698,7 +2702,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, gcn_gen_undef (V64SImode), exec)); /* Move vectors. */ - for (regno = FIRST_VGPR_REG, offset = offsets->pretend_size; + for (regno = FIRST_VGPR_REG, offset = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if ((df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno)) || (regno == VGPR_REGNO (6) && saved_scalars > 0) @@ -2719,8 +2723,67 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, } if (prologue) - emit_insn (gen_scatterv64si_insn_1offset_exec (vsp, const0_rtx, reg, - as, const0_rtx, exec)); + { + rtx insn = emit_insn (gen_scatterv64si_insn_1offset_exec + (vsp, const0_rtx, reg, as, const0_rtx, + exec)); + + /* Add CFI metadata. */ + rtx note; + if (regno == VGPR_REGNO (6) || regno == VGPR_REGNO (7)) + { + int start = (regno == VGPR_REGNO (7) ? 64 : 0); + int count = MIN (saved_scalars - start, 64); + int add_lr = (regno == VGPR_REGNO (6) + && df_regs_ever_live_p (LINK_REGNUM)); + int lrdest = -1; + rtvec seq = rtvec_alloc (count + add_lr); + + /* Add an REG_FRAME_RELATED_EXPR entry for each scalar + register that was saved in this batch. */ + for (int idx = 0; idx < count; idx++) + { + int stackaddr = offset + idx * 4; + rtx dest = gen_rtx_MEM (SImode, + gen_rtx_PLUS + (DImode, sp, + GEN_INT (stackaddr))); + rtx src = gen_rtx_REG (SImode, saved_sgprs[start + idx]); + rtx set = gen_rtx_SET (dest, src); + RTX_FRAME_RELATED_P (set) = 1; + RTVEC_ELT (seq, idx) = set; + + if (saved_sgprs[start + idx] == LINK_REGNUM) + lrdest = stackaddr; + } + + /* Add an additional expression for DWARF_LINK_REGISTER if + LINK_REGNUM was saved. */ + if (lrdest != -1) + { + rtx dest = gen_rtx_MEM (DImode, + gen_rtx_PLUS + (DImode, sp, + GEN_INT (lrdest))); + rtx src = gen_rtx_REG (DImode, DWARF_LINK_REGISTER); + rtx set = gen_rtx_SET (dest, src); + RTX_FRAME_RELATED_P (set) = 1; + RTVEC_ELT (seq, count) = set; + } + + note = gen_rtx_SEQUENCE (VOIDmode, seq); + } + else + { + rtx dest = gen_rtx_MEM (V64SImode, + gen_rtx_PLUS (DImode, sp, + GEN_INT (offset))); + rtx src = gen_rtx_REG (V64SImode, regno); + note = gen_rtx_SET (dest, src); + } + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); + } else emit_insn (gen_gatherv64si_insn_1offset_exec (reg, vsp, const0_rtx, as, const0_rtx, @@ -3224,8 +3287,7 @@ gcn_cannot_copy_insn_p (rtx_insn *insn) static enum unwind_info_type gcn_debug_unwind_info () { - /* No support for debug info, yet. */ - return UI_NONE; + return UI_DWARF2; } /* Determine if there is a suitable hardware conversion instruction. @@ -6214,6 +6276,8 @@ gcn_dwarf_register_number (unsigned int regno) return 768; */ else if (regno == SCC_REG) return 128; + else if (regno == DWARF_LINK_REGISTER) + return 16; else if (SGPR_REGNO_P (regno)) { if (regno - FIRST_SGPR_REG < 64) @@ -6243,8 +6307,12 @@ gcn_dwarf_register_span (rtx rtl) if (GET_MODE_SIZE (mode) != 8) return NULL_RTX; - rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); unsigned regno = REGNO (rtl); + + if (regno == DWARF_LINK_REGISTER) + return NULL_RTX; + + rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); XVECEXP (p, 0, 0) = gen_rtx_REG (SImode, regno); XVECEXP (p, 0, 1) = gen_rtx_REG (SImode, regno + 1); diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index eba4646f1bf..4992a4c02ef 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -85,6 +85,7 @@ #define FIRST_PARM_OFFSET(FNDECL) 0 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16) #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM) +#define DWARF_FRAME_RETURN_COLUMN 16 #define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size) #define ACCUMULATE_OUTGOING_ARGS 1 #define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \ @@ -135,7 +136,8 @@ #define WORK_ITEM_ID_Z_REG 162 #define SOFT_ARG_REG 416 #define FRAME_POINTER_REGNUM 418 -#define FIRST_PSEUDO_REGISTER 420 +#define DWARF_LINK_REGISTER 420 +#define FIRST_PSEUDO_REGISTER 421 #define FIRST_PARM_REG 24 #define NUM_PARM_REGS 6 @@ -197,7 +199,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* Other registers. */ \ - 1, 1, 1, 1 \ + 1, 1, 1, 1, 1 \ } #define CALL_USED_REGISTERS { \ @@ -235,7 +237,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* Other registers. */ \ - 1, 1, 1, 1 \ + 1, 1, 1, 1, 1 \ } @@ -514,7 +516,7 @@ enum gcn_address_spaces "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \ "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \ "v254", "v255", \ - "?ap0", "?ap1", "?fp0", "?fp1" } + "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" } #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) From patchwork Tue Jun 22 17:14:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abid Qadeer X-Patchwork-Id: 1495799 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G8Y3T4Y3Jz9sWH for ; Wed, 23 Jun 2021 03:16:53 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ED1E63951840 for ; Tue, 22 Jun 2021 17:16:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id DD15B3948A51 for ; Tue, 22 Jun 2021 17:15:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DD15B3948A51 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: ugOqRGTKv+4uWcooKUs8YhCjI7SPIBC7glJRQQ1q0hnUHgxF1lQwcxcMESXtcpi5dbrDjqJSym S+0/L38q6ww8OZrQwTCjziOSOMbj6CBVbhfp7SqWPlSwnSPpZszAqHWcF4i2NZxt6jCnIiSpa8 w7yOKt8zRmP6BXNWb+3FcjaISuPlwYK6BBQOAUB/i5nX853cRrsYCy5Rifi7UllFx+wpj5sLuE DD9bpzmh0APMy9ECqxI2z5yTvAa/QGMMmhWrqCVH7o4psUxcUqRgRMfiz1OB/W6tnghuohp+c8 YRg= X-IronPort-AV: E=Sophos;i="5.83,291,1616486400"; d="scan'208";a="62667451" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa3.mentor.iphmx.com with ESMTP; 22 Jun 2021 09:15:14 -0800 IronPort-SDR: GUlLQEWFSFvc6SlsFwcAlEfHuUAc9+GOyX4lzmZ9UmyKnzLABP0ywT71a4O6UrC1MzQDvjLU47 NL3rNyEgOJwvfOFHTOHvRLdWm35i9WUhiU1zNDNXzJp5bmBORGm8zpjwF1g6ryOv5a1mIyD8Uu HXSLrn6uUcdEzh9YIrC4uVV7tdsM5ZjEght0AbFt6kn0gxuYFTy4sY4Fzzzj01Q9PedCNBF+Ng NRC7aDe7dV8DfxhHBeYj3MkiUYt+vVDVz0VRRrsD2wg0qy7FnoGg4ebEsigUn5pzVyrvBfO0UU BOQ= From: Hafiz Abid Qadeer To: Subject: [PATCH 2/3] [amdgcn] Use frame pointer for CFA expressions. Date: Tue, 22 Jun 2021 18:14:42 +0100 Message-ID: <20210622171443.1287801-3-abidh@codesourcery.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210622171443.1287801-1-abidh@codesourcery.com> References: <20210622171443.1287801-1-abidh@codesourcery.com> MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ams@codesourcery.com, abidh@codesourcery.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" As size of address is bigger than registers in amdgcn, we are forced to use DW_CFA_def_cfa_expression to make an expression that concatenates multiple registers for the value of the CFA. This then prohibits us from using many of the dwarf ops which expect CFA rule to be a single regsiter plus an offset. Using frame pointer in the CFA rule is only real possibility as it is saved in every frame and it is easy to unwind its value. So unless user gives fomit-frame-pointer, we use frame pointer for the cfi information. This options also has a different default now. gcc/ * common/config/gcn/gcn-common.c (gcn_option_optimization_table): Change OPT_fomit_frame_pointer to -O3. (gcn_expand_prologue): Prefer the frame pointer when emitting CFI. (gcn_frame_pointer_rqd): New function. (TARGET_FRAME_POINTER_REQUIRED): New hook. --- gcc/common/config/gcn/gcn-common.c | 2 +- gcc/config/gcn/gcn.c | 60 +++++++++++++++++++++++------- 2 files changed, 47 insertions(+), 15 deletions(-) diff --git a/gcc/common/config/gcn/gcn-common.c b/gcc/common/config/gcn/gcn-common.c index 305c310f940..695eb467e34 100644 --- a/gcc/common/config/gcn/gcn-common.c +++ b/gcc/common/config/gcn/gcn-common.c @@ -27,7 +27,7 @@ /* Set default optimization options. */ static const struct default_options gcn_option_optimization_table[] = { - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, + { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_NONE, 0, NULL, 0 } }; diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 3ab16548aad..0eac3aa3844 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2900,10 +2900,14 @@ gcn_expand_prologue () rtx adjustment = gen_int_mode (sp_adjust, SImode); rtx insn = emit_insn (gen_addsi3_scalar_carry (sp_lo, sp_lo, adjustment, scc)); - RTX_FRAME_RELATED_P (insn) = 1; - add_reg_note (insn, REG_FRAME_RELATED_EXPR, - gen_rtx_SET (sp, - gen_rtx_PLUS (DImode, sp, adjustment))); + if (!offsets->need_frame_pointer) + { + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_SET (sp, + gen_rtx_PLUS (DImode, sp, + adjustment))); + } emit_insn (gen_addcsi3_scalar_zero (sp_hi, sp_hi, scc)); } @@ -2917,25 +2921,24 @@ gcn_expand_prologue () rtx adjustment = gen_int_mode (fp_adjust, SImode); rtx insn = emit_insn (gen_addsi3_scalar_carry(fp_lo, sp_lo, adjustment, scc)); - RTX_FRAME_RELATED_P (insn) = 1; - add_reg_note (insn, REG_FRAME_RELATED_EXPR, - gen_rtx_SET (fp, - gen_rtx_PLUS (DImode, sp, adjustment))); emit_insn (gen_addcsi3_scalar (fp_hi, sp_hi, (fp_adjust < 0 ? GEN_INT (-1) : const0_rtx), scc, scc)); + + /* Set the CFA to the entry stack address, as an offset from the + frame pointer. This is preferred because the frame pointer is + saved in each frame, whereas the stack pointer is not. */ + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_CFA_DEF_CFA, + gen_rtx_PLUS (DImode, fp, + GEN_INT (-(offsets->pretend_size + + offsets->callee_saves)))); } rtx_insn *seq = get_insns (); end_sequence (); - /* FIXME: Prologue insns should have this flag set for debug output, etc. - but it causes issues for now. - for (insn = seq; insn; insn = NEXT_INSN (insn)) - if (INSN_P (insn)) - RTX_FRAME_RELATED_P (insn) = 1;*/ - emit_insn (seq); } else @@ -3011,6 +3014,16 @@ gcn_expand_prologue () gen_rtx_SET (sp, gen_rtx_PLUS (DImode, sp, dbg_adjustment))); + if (offsets->need_frame_pointer) + { + /* Set the CFA to the entry stack address, as an offset from the + frame pointer. This is necessary when alloca is used, and + harmless otherwise. */ + rtx neg_adjust = gen_int_mode (-offsets->callee_saves, DImode); + add_reg_note (insn, REG_CFA_DEF_CFA, + gen_rtx_PLUS (DImode, fp, neg_adjust)); + } + /* Make sure the flat scratch reg doesn't get optimised away. */ emit_insn (gen_prologue_use (gen_rtx_REG (DImode, FLAT_SCRATCH_REG))); } @@ -3114,6 +3127,23 @@ gcn_expand_epilogue (void) emit_jump_insn (gen_gcn_return ()); } +/* Implement TARGET_FRAME_POINTER_REQUIRED. + + Return true if the frame pointer should not be eliminated. */ + +bool +gcn_frame_pointer_rqd (void) +{ + /* GDB needs the frame pointer in order to unwind properly, + but that's not important for the entry point, unless alloca is used. + It's not important for code execution, so we should repect the + -fomit-frame-pointer flag. */ + return (!flag_omit_frame_pointer + && cfun + && (cfun->calls_alloca + || (cfun->machine && cfun->machine->normal_function))); +} + /* Implement TARGET_CAN_ELIMINATE. Return true if the compiler is allowed to try to replace register number @@ -6373,6 +6403,8 @@ gcn_dwarf_register_span (rtx rtl) #define TARGET_EMUTLS_VAR_INIT gcn_emutls_var_init #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN gcn_expand_builtin +#undef TARGET_FRAME_POINTER_REQUIRED +#define TARGET_FRAME_POINTER_REQUIRED gcn_frame_pointer_rqd #undef TARGET_FUNCTION_ARG #undef TARGET_FUNCTION_ARG_ADVANCE #define TARGET_FUNCTION_ARG_ADVANCE gcn_function_arg_advance From patchwork Tue Jun 22 17:14:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abid Qadeer X-Patchwork-Id: 1495800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G8Y424nPbz9sVp for ; Wed, 23 Jun 2021 03:17:22 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4548D394D822 for ; Tue, 22 Jun 2021 17:17:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id D34BA393C846 for ; Tue, 22 Jun 2021 17:15:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D34BA393C846 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: YP30zO6z691TaxewmwgIaicWrxjSt4/Zg70jMTfzv4XDYCbNgWcj4VBFcyCmT4h5bf1k56UyLy xm5t7+zBDyBHSuj621lzpruyVO5jtwbicyqJpaMHXE1Qrfy6PXE8eQ6+eEYBqdyT/WF+KBsiBi jOGvWXvbxu8/EV/yhBp5n6UMX68Xi7PDW5pBN46QfoOS4xUSAlq5uK1C0/SgAsm/kEKz1FdO+v um6I4JYDfin1tJPz00o30KWbfdv7D4SSgig7uvXv6q/dkZPTnjoBmlrzhUtV3Upm0dlsFq8QYt r48= X-IronPort-AV: E=Sophos;i="5.83,291,1616486400"; d="scan'208";a="62667454" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa3.mentor.iphmx.com with ESMTP; 22 Jun 2021 09:15:15 -0800 IronPort-SDR: HQ6hh9MLtYf72NHEKpNRsNtJmn62X8c4QI5HrbcXwxME5D0NkwiNHEBCLsBp3CtZbTb2tDGnY6 MhScvYg8Fi/cpIxGlAFAv/0qkB8N639JAp7OMMoICh6z1876zbUGGh5R+GPK27nfQ2g2kjFGaC WmPATsPbokTOyOQm9vNqVWRxT/VEanqChv8kTF+C7PB7l9RNS6ztQbzb4YeAxTWlq0CkejBdfN uPazkMWa44Nymm4u7UzWP73lqSaWztnRemsqlnf1TvcwD6Cp8tl82hIr05yDRilQXoyvejhcMa qa8= From: Hafiz Abid Qadeer To: Subject: [PATCH 3/3] [amdgcn] Add hook for DWARF address spaces. Date: Tue, 22 Jun 2021 18:14:43 +0100 Message-ID: <20210622171443.1287801-4-abidh@codesourcery.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210622171443.1287801-1-abidh@codesourcery.com> References: <20210622171443.1287801-1-abidh@codesourcery.com> MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ams@codesourcery.com, abidh@codesourcery.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Map GCN address spaces to the proposed DWARF address spaces defined by AMD at https://llvm.org/docs/AMDGPUUsage.html#amdgpu-dwarf-address-class-mapping-table gcc/ * config/gcn/gcn.c: Include dwarf2.h. (gcn_addr_space_debug): New function. (TARGET_ADDR_SPACE_DEBUG): New hook. --- gcc/config/gcn/gcn.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 0eac3aa3844..25996dc83de 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -50,6 +50,7 @@ #include "varasm.h" #include "intl.h" #include "rtl-iter.h" +#include "dwarf2.h" /* This file should be included last. */ #include "target-def.h" @@ -1497,6 +1498,32 @@ gcn_addr_space_convert (rtx op, tree from_type, tree to_type) gcc_unreachable (); } +/* Implement TARGET_ADDR_SPACE_DEBUG. + + Return the dwarf address space class for each hardware address space. */ + +static int +gcn_addr_space_debug (addr_space_t as) +{ + switch (as) + { + case ADDR_SPACE_DEFAULT: + case ADDR_SPACE_FLAT: + case ADDR_SPACE_SCALAR_FLAT: + case ADDR_SPACE_FLAT_SCRATCH: + return DW_ADDR_none; + case ADDR_SPACE_GLOBAL: + return 1; // DW_ADDR_LLVM_global + case ADDR_SPACE_LDS: + return 3; // DW_ADDR_LLVM_group + case ADDR_SPACE_SCRATCH: + return 4; // DW_ADDR_LLVM_private + case ADDR_SPACE_GDS: + return 0x8000; // DW_ADDR_AMDGPU_region + } + gcc_unreachable (); +} + /* Implement REGNO_MODE_CODE_OK_FOR_BASE_P via gcn.h @@ -6354,6 +6381,8 @@ gcn_dwarf_register_span (rtx rtl) #undef TARGET_ADDR_SPACE_ADDRESS_MODE #define TARGET_ADDR_SPACE_ADDRESS_MODE gcn_addr_space_address_mode +#undef TARGET_ADDR_SPACE_DEBUG +#define TARGET_ADDR_SPACE_DEBUG gcn_addr_space_debug #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \ gcn_addr_space_legitimate_address_p