From patchwork Wed Jun 16 09:23:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Lukas_J=C3=BCnger?= X-Patchwork-Id: 1492840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=greensocs.com header.i=@greensocs.com header.a=rsa-sha256 header.s=mail header.b=XR5OHh98; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G4ft65hhPz9sXN for ; Wed, 16 Jun 2021 19:25:18 +1000 (AEST) Received: from localhost ([::1]:45246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRnQ-0000lO-4C for incoming@patchwork.ozlabs.org; Wed, 16 Jun 2021 05:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRlr-0000iD-7Q; Wed, 16 Jun 2021 05:23:39 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:33650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRlo-0001my-4H; Wed, 16 Jun 2021 05:23:39 -0400 Received: from fornax.fritz.box (b2b-109-90-5-113.unitymedia.biz [109.90.5.113]) by beetle.greensocs.com (Postfix) with ESMTPSA id AC9AD21C28; Wed, 16 Jun 2021 09:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1623835413; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=98EEBdKayFBTpUAm7/9udRdrgrn3/OSIf9oTm7RiJD4=; b=XR5OHh98Y2IbIJSd3AgwJnBe21vAOdqZBSTuqDQlwF///afsPJ8EQtU35qq0xAacy55vUS 2y2utcTmplwOvqaS1f/INGN3Px3wdqyNzSCPMETUnVIsvDd7/IpfXMWlT/hXCpLz46k7SO 1e+zpZXwz4lgCRGZrBalmnTKeZGKWVU= From: =?utf-8?q?Lukas_J=C3=BCnger?= To: qemu-devel@nongnu.org Subject: [PATCH v5 1/2] hw/char: Consistent function names for sifive_uart Date: Wed, 16 Jun 2021 11:23:25 +0200 Message-Id: <20210616092326.59639-2-lukas.juenger@greensocs.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210616092326.59639-1-lukas.juenger@greensocs.com> References: <20210616092326.59639-1-lukas.juenger@greensocs.com> MIME-Version: 1.0 Received-SPF: pass client-ip=5.135.226.135; envelope-from=lukas.juenger@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com, mark.burton@greensocs.com, marcandre.lureau@redhat.com, palmer@dabbelt.com, pbonzini@redhat.com, alistair.francis@wdc.com, Bin Meng , =?utf-8?q?Lukas_J?= =?utf-8?q?=C3=BCnger?= , luc.michel@greensocs.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This cleans up function names in the SiFive UART model. Signed-off-by: Lukas Jünger Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/char/sifive_uart.c | 46 ++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index fe12666789..5df8212961 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -31,7 +31,7 @@ */ /* Returns the state of the IP (interrupt pending) register */ -static uint64_t uart_ip(SiFiveUARTState *s) +static uint64_t sifive_uart_ip(SiFiveUARTState *s) { uint64_t ret = 0; @@ -48,7 +48,7 @@ static uint64_t uart_ip(SiFiveUARTState *s) return ret; } -static void update_irq(SiFiveUARTState *s) +static void sifive_uart_update_irq(SiFiveUARTState *s) { int cond = 0; if ((s->ie & SIFIVE_UART_IE_TXWM) || @@ -63,7 +63,7 @@ static void update_irq(SiFiveUARTState *s) } static uint64_t -uart_read(void *opaque, hwaddr addr, unsigned int size) +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) { SiFiveUARTState *s = opaque; unsigned char r; @@ -74,7 +74,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); s->rx_fifo_len--; qemu_chr_fe_accept_input(&s->chr); - update_irq(s); + sifive_uart_update_irq(s); return r; } return 0x80000000; @@ -84,7 +84,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: - return uart_ip(s); + return sifive_uart_ip(s); case SIFIVE_UART_TXCTRL: return s->txctrl; case SIFIVE_UART_RXCTRL: @@ -99,8 +99,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) } static void -uart_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) +sifive_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) { SiFiveUARTState *s = opaque; uint32_t value = val64; @@ -109,11 +109,11 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_TXCTRL: s->txctrl = val64; @@ -129,9 +129,9 @@ uart_write(void *opaque, hwaddr addr, __func__, (int)addr, (int)value); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, +static const MemoryRegionOps sifive_uart_ops = { + .read = sifive_uart_read, + .write = sifive_uart_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, @@ -139,7 +139,7 @@ static const MemoryRegionOps uart_ops = { } }; -static void uart_rx(void *opaque, const uint8_t *buf, int size) +static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size) { SiFiveUARTState *s = opaque; @@ -150,26 +150,27 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) } s->rx_fifo[s->rx_fifo_len++] = *buf; - update_irq(s); + sifive_uart_update_irq(s); } -static int uart_can_rx(void *opaque) +static int sifive_uart_can_rx(void *opaque) { SiFiveUARTState *s = opaque; return s->rx_fifo_len < sizeof(s->rx_fifo); } -static void uart_event(void *opaque, QEMUChrEvent event) +static void sifive_uart_event(void *opaque, QEMUChrEvent event) { } -static int uart_be_change(void *opaque) +static int sifive_uart_be_change(void *opaque) { SiFiveUARTState *s = opaque; - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); return 0; } @@ -183,9 +184,10 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); s->irq = irq; qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); - memory_region_init_io(&s->mmio, NULL, &uart_ops, s, + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); + memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s, TYPE_SIFIVE_UART, SIFIVE_UART_MAX); memory_region_add_subregion(address_space, base, &s->mmio); return s; From patchwork Wed Jun 16 09:23:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Lukas_J=C3=BCnger?= X-Patchwork-Id: 1492848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=greensocs.com header.i=@greensocs.com header.a=rsa-sha256 header.s=mail header.b=YWnM2Zlo; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G4g0w01Tbz9sWl for ; Wed, 16 Jun 2021 19:31:11 +1000 (AEST) Received: from localhost ([::1]:54538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRt7-0007EN-CO for incoming@patchwork.ozlabs.org; Wed, 16 Jun 2021 05:31:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRlw-0000kV-7z; Wed, 16 Jun 2021 05:23:44 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:33666) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRlp-0001oV-RO; Wed, 16 Jun 2021 05:23:44 -0400 Received: from fornax.fritz.box (b2b-109-90-5-113.unitymedia.biz [109.90.5.113]) by beetle.greensocs.com (Postfix) with ESMTPSA id A435421C39; Wed, 16 Jun 2021 09:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1623835415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dumAtD2jQ33cfjV7tNOTMaJOWUwYua1Ch5E+iqbW2gk=; b=YWnM2Zlo8ZXzL/EFQ1MRLFuyygH6mdVMaKOZd/XI9fdu7XdLvXZ312nwL3sznVi3cjFExe 2GpM3bhYsl1t9o3Lv8Vqs6ALrUOZ0zD/+VgeISN2qWjGkZni6RSKNgUyJODmTLlOCoF4o6 ysYuQ+6Y6ah6innYGmD4hnoNdlnMLtc= From: =?utf-8?q?Lukas_J=C3=BCnger?= To: qemu-devel@nongnu.org Subject: [PATCH v5 2/2] hw/char: QOMify sifive_uart Date: Wed, 16 Jun 2021 11:23:26 +0200 Message-Id: <20210616092326.59639-3-lukas.juenger@greensocs.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210616092326.59639-1-lukas.juenger@greensocs.com> References: <20210616092326.59639-1-lukas.juenger@greensocs.com> MIME-Version: 1.0 Received-SPF: pass client-ip=5.135.226.135; envelope-from=lukas.juenger@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com, mark.burton@greensocs.com, marcandre.lureau@redhat.com, palmer@dabbelt.com, pbonzini@redhat.com, alistair.francis@wdc.com, Bin Meng , =?utf-8?q?Lukas_J?= =?utf-8?q?=C3=BCnger?= , luc.michel@greensocs.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This QOMifies the SiFive UART model. Migration and reset have been implemented. Signed-off-by: Lukas Jünger Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/char/sifive_uart.h | 11 ++-- hw/char/sifive_uart.c | 114 +++++++++++++++++++++++++++++++--- 2 files changed, 109 insertions(+), 16 deletions(-) diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h index 3e962be659..7f6c79f8bd 100644 --- a/include/hw/char/sifive_uart.h +++ b/include/hw/char/sifive_uart.h @@ -21,6 +21,7 @@ #define HW_SIFIVE_UART_H #include "chardev/char-fe.h" +#include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qom/object.h" @@ -49,12 +50,10 @@ enum { #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) +#define SIFIVE_UART_RX_FIFO_SIZE 8 #define TYPE_SIFIVE_UART "riscv.sifive.uart" - -typedef struct SiFiveUARTState SiFiveUARTState; -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART, - TYPE_SIFIVE_UART) +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) struct SiFiveUARTState { /*< private >*/ @@ -64,8 +63,8 @@ struct SiFiveUARTState { qemu_irq irq; MemoryRegion mmio; CharBackend chr; - uint8_t rx_fifo[8]; - unsigned int rx_fifo_len; + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; + uint8_t rx_fifo_len; uint32_t ie; uint32_t ip; uint32_t txctrl; diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 5df8212961..278e21c434 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -19,10 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" +#include "migration/vmstate.h" #include "chardev/char.h" #include "chardev/char-fe.h" #include "hw/irq.h" #include "hw/char/sifive_uart.h" +#include "hw/qdev-properties-system.h" /* * Not yet implemented: @@ -175,20 +177,112 @@ static int sifive_uart_be_change(void *opaque) return 0; } +static Property sifive_uart_properties[] = { + DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_uart_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + SiFiveUARTState *s = SIFIVE_UART(obj); + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s, + TYPE_SIFIVE_UART, SIFIVE_UART_MAX); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); +} + +static void sifive_uart_realize(DeviceState *dev, Error **errp) +{ + SiFiveUARTState *s = SIFIVE_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); + +} + +static void sifive_uart_reset_enter(Object *obj, ResetType type) +{ + SiFiveUARTState *s = SIFIVE_UART(obj); + s->ie = 0; + s->ip = 0; + s->txctrl = 0; + s->rxctrl = 0; + s->div = 0; + s->rx_fifo_len = 0; +} + +static void sifive_uart_reset_hold(Object *obj) +{ + SiFiveUARTState *s = SIFIVE_UART(obj); + qemu_irq_lower(s->irq); +} + +static const VMStateDescription vmstate_sifive_uart = { + .name = TYPE_SIFIVE_UART, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState, + SIFIVE_UART_RX_FIFO_SIZE), + VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState), + VMSTATE_UINT32(ie, SiFiveUARTState), + VMSTATE_UINT32(ip, SiFiveUARTState), + VMSTATE_UINT32(txctrl, SiFiveUARTState), + VMSTATE_UINT32(rxctrl, SiFiveUARTState), + VMSTATE_UINT32(div, SiFiveUARTState), + VMSTATE_END_OF_LIST() + }, +}; + + +static void sifive_uart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->realize = sifive_uart_realize; + dc->vmsd = &vmstate_sifive_uart; + rc->phases.enter = sifive_uart_reset_enter; + rc->phases.hold = sifive_uart_reset_hold; + device_class_set_props(dc, sifive_uart_properties); +} + +static const TypeInfo sifive_uart_info = { + .name = TYPE_SIFIVE_UART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUARTState), + .instance_init = sifive_uart_init, + .class_init = sifive_uart_class_init, +}; + +static void sifive_uart_register_types(void) +{ + type_register_static(&sifive_uart_info); +} + +type_init(sifive_uart_register_types) + /* * Create UART device. */ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, Chardev *chr, qemu_irq irq) { - SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); - s->irq = irq; - qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, - sifive_uart_event, sifive_uart_be_change, s, - NULL, true); - memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s, - TYPE_SIFIVE_UART, SIFIVE_UART_MAX); - memory_region_add_subregion(address_space, base, &s->mmio); - return s; + DeviceState *dev; + SysBusDevice *s; + SiFiveUARTState *r; + + dev = qdev_new("riscv.sifive.uart"); + s = SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(address_space, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, irq); + + r = SIFIVE_UART(dev); + return r; }