From patchwork Mon Jun 14 10:09:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lara Lazier X-Patchwork-Id: 1491624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ULJSpRtT; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G3S0M4h9hz9sW7 for ; Mon, 14 Jun 2021 20:11:31 +1000 (AEST) Received: from localhost ([::1]:49712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lsjZ3-0000ck-DZ for incoming@patchwork.ozlabs.org; Mon, 14 Jun 2021 06:11:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lsjWt-00059W-Hc for qemu-devel@nongnu.org; Mon, 14 Jun 2021 06:09:15 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:35414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lsjWr-000447-MJ for qemu-devel@nongnu.org; Mon, 14 Jun 2021 06:09:15 -0400 Received: by mail-wm1-x332.google.com with SMTP id k5-20020a05600c1c85b02901affeec3ef8so12663529wms.0 for ; Mon, 14 Jun 2021 03:09:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ObF/ZgQFN9zjCXfOIGIVn098TNV5d0DYaS9kaxO+1to=; b=ULJSpRtTNUwssCXmGNd1POehg/U2jddkGHHwi2fhasQfp/Qye7fAsBZSf69vxI/9bx suEZsYZQ9UwN64/tb1dAH75uCztnWLvOX40gZcW7nDnMTXAuPMmfxINbh14VaAd0easc 8ynayXdbFaZW+CCRYxyiMLFbpO4v5wjOgOrDUJ9T3XRWiFysHazv1Q+xYxg9zfB324rm +D8GRyeALPlhXVgATIGQRqyXRPQau6sc56kL1nwN69DrFfER8WhqCz3q6IsmlKsn6qYB JIdujP0ODEKmeWaxAYp7AAvuvQkKLqHdu4C8dRpgzj8zeuS2qxOZIzt0a9hal3i/46I3 S4Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ObF/ZgQFN9zjCXfOIGIVn098TNV5d0DYaS9kaxO+1to=; b=P806hqR5Ucwfwk8N7y6tWzOf/jaoViQvBppjiUHgWG+f5Ri+ig9s+coujAcR7/Q1gZ Bf0TKo0EiFFnnQ3RCjE1f5VEtJthwQH/cil0WR9K5xHiMA6XIIthKBm8tU3nOPZASMS7 h6ymlsB+eI1mC/6Qq4XdrUsC1WyjmJzsYT1ky7L6ruPqdE90xiaSiYPYbA7bvg3b407c HCvA6GjPLdrRCua0Kj1eKMZL2cXM1zXieXeIZfNNtKSKzcmKBUyCVH9qRcXPkgqoVpDE 3E92xn6ZxbRQUwmadtBXhSQ45hELDcGuRH405WCKHxUpvl5+txbYfdysRE1gRw+13xcA /bqg== X-Gm-Message-State: AOAM533g0U82RPK2GNWEuYrC3pvSu4lUHwT3mvKT+RI8Z9TUgfjrzMs9 ecpl4JwAOsAIDwUkB6+ixHscXba4tfCf5A== X-Google-Smtp-Source: ABdhPJylDOhDCBqwgp5cRayYcD1KVqcKrNtZqBehWALAij0sI+N4/cXiWxFKxyIzQqZlA+m1s3lgmA== X-Received: by 2002:a1c:2142:: with SMTP id h63mr15926613wmh.84.1623665352262; Mon, 14 Jun 2021 03:09:12 -0700 (PDT) Received: from localhost.localdomain ([37.161.140.231]) by smtp.gmail.com with ESMTPSA id o18sm15752254wrx.59.2021.06.14.03.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 03:09:11 -0700 (PDT) From: Lara Lazier To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/i386: Added consistency checks for VMRUN intercept and ASID Date: Mon, 14 Jun 2021 12:09:00 +0200 Message-Id: <20210614100902.15860-2-laramglazier@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100902.15860-1-laramglazier@gmail.com> References: <20210614100902.15860-1-laramglazier@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=laramglazier@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Zero VMRUN intercept and ASID should cause an immediate VMEXIT during the consistency checks performed by VMRUN. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier --- target/i386/svm.h | 2 ++ target/i386/tcg/sysemu/svm_helper.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/i386/svm.h b/target/i386/svm.h index 87965e5bc2..1c55d4f829 100644 --- a/target/i386/svm.h +++ b/target/i386/svm.h @@ -135,6 +135,8 @@ #define SVM_NPTEXIT_GPA (1ULL << 32) #define SVM_NPTEXIT_GPT (1ULL << 33) +#define SVM_VMRUN_INTERCEPT (1ULL << 32) + struct QEMU_PACKED vmcb_control_area { uint16_t intercept_cr_read; uint16_t intercept_cr_write; diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 9d671297cf..ff826fe11a 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -72,6 +72,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) uint64_t nested_ctl; uint32_t event_inj; uint32_t int_ctl; + uint32_t asid; cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0, GETPC()); @@ -154,9 +155,18 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) nested_ctl = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.nested_ctl)); + asid = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, + control.asid)); env->nested_pg_mode = 0; + if (!(env->intercept & SVM_VMRUN_INTERCEPT)) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } + if (asid == 0) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } + if (nested_ctl & SVM_NPT_ENABLED) { env->nested_cr3 = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, From patchwork Mon Jun 14 10:09:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lara Lazier X-Patchwork-Id: 1491625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=vdkhOFgy; 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Mon, 14 Jun 2021 03:09:13 -0700 (PDT) Received: from localhost.localdomain ([37.161.140.231]) by smtp.gmail.com with ESMTPSA id o18sm15752254wrx.59.2021.06.14.03.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 03:09:12 -0700 (PDT) From: Lara Lazier To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/i386: Added consistency checks for CR0 Date: Mon, 14 Jun 2021 12:09:01 +0200 Message-Id: <20210614100902.15860-3-laramglazier@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100902.15860-1-laramglazier@gmail.com> References: <20210614100902.15860-1-laramglazier@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=laramglazier@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The combination of unset CD and set NW bit in CR0 is illegal. CR0[63:32] are also reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier --- target/i386/cpu.h | 2 ++ target/i386/svm.h | 1 + target/i386/tcg/sysemu/svm_helper.c | 12 +++++++++--- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ac3abea97c..46542513cc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -224,6 +224,8 @@ typedef enum X86Seg { #define CR0_NE_MASK (1U << 5) #define CR0_WP_MASK (1U << 16) #define CR0_AM_MASK (1U << 18) +#define CR0_NW_MASK (1U << 29) +#define CR0_CD_MASK (1U << 30) #define CR0_PG_MASK (1U << 31) #define CR4_VME_MASK (1U << 0) diff --git a/target/i386/svm.h b/target/i386/svm.h index 1c55d4f829..7a88906907 100644 --- a/target/i386/svm.h +++ b/target/i386/svm.h @@ -136,6 +136,7 @@ #define SVM_NPTEXIT_GPT (1ULL << 33) #define SVM_VMRUN_INTERCEPT (1ULL << 32) +#define SVM_CR0_RESERVED_MASK 0xffffffff00000000U struct QEMU_PACKED vmcb_control_area { uint16_t intercept_cr_read; diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index ff826fe11a..63aaa53490 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -73,6 +73,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) uint32_t event_inj; uint32_t int_ctl; uint32_t asid; + uint64_t new_cr0; cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0, GETPC()); @@ -192,13 +193,18 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->idt.limit = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit)); + new_cr0 = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr0)); + if (new_cr0 & SVM_CR0_RESERVED_MASK) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } + if ((new_cr0 & CR0_NW_MASK) && !(new_cr0 & CR0_CD_MASK)) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } /* clear exit_info_2 so we behave like the real hardware */ x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0); - cpu_x86_update_cr0(env, x86_ldq_phys(cs, - env->vm_vmcb + offsetof(struct vmcb, - save.cr0))); + cpu_x86_update_cr0(env, new_cr0); cpu_x86_update_cr4(env, x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr4))); From patchwork Mon Jun 14 10:09:02 2021 Content-Type: text/plain; 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Mon, 14 Jun 2021 03:09:13 -0700 (PDT) From: Lara Lazier To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/i386: Added Intercept CR0 writes check Date: Mon, 14 Jun 2021 12:09:02 +0200 Message-Id: <20210614100902.15860-4-laramglazier@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100902.15860-1-laramglazier@gmail.com> References: <20210614100902.15860-1-laramglazier@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=laramglazier@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When the selective CR0 write intercept is set, all writes to bits in CR0 other than CR0.TS or CR0.MP cause a VMEXIT. Signed-off-by: Lara Lazier --- target/i386/cpu.h | 2 ++ target/i386/tcg/sysemu/misc_helper.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 46542513cc..ff0ff97ca9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -228,6 +228,8 @@ typedef enum X86Seg { #define CR0_CD_MASK (1U << 30) #define CR0_PG_MASK (1U << 31) +#define INTERCEPT_SELECTIVE_CR0 (1ULL << 5) + #define CR4_VME_MASK (1U << 0) #define CR4_PVI_MASK (1U << 1) #define CR4_TSD_MASK (1U << 2) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 0cef2f1a4c..53117f47de 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { switch (reg) { case 0: + /* + * If we reach this point, the CR0 write intercept is disabled. + * But we could still exit if the hypervisor has requested the selective + * intercept for bits other than TS and MP + */ + if ((env->intercept & INTERCEPT_SELECTIVE_CR0) && + ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) { + cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC()); + } cpu_x86_update_cr0(env, t0); break; case 3: