From patchwork Wed Jun 9 09:16:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 1489762 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=riJB7v6R; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G0M3d1shCz9sRN for ; Wed, 9 Jun 2021 19:18:36 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7ADB6385E00D for ; Wed, 9 Jun 2021 09:18:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7ADB6385E00D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1623230314; bh=T5AJw+8dTpFH2WAly0GkbnwWbC2wz0YcfN9b07IkYHs=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=riJB7v6R8gEHVhthifCbBY814ab5OSjXHF20NF4+ABgwAn4I9Xh/U3KSyaYyMy1UD huDWLWy2Qo/t9eVTWVtKj4Q3mTkmV7LcdRuxeoGzPlSrGv+kHiwkSJnz1yiktLHlF+ +TElpYSc5XeZ2/ERmcDCsALytOXbK4BQ497gotRM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id D0D85385782B for ; Wed, 9 Jun 2021 09:16:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D0D85385782B Received: by mail-ej1-x634.google.com with SMTP id g20so37401164ejt.0 for ; Wed, 09 Jun 2021 02:16:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T5AJw+8dTpFH2WAly0GkbnwWbC2wz0YcfN9b07IkYHs=; b=Eblhzbd4BoA6oPFcXXk5wZeRp6GokrgWDeOJoSoN1h6aohNV0Ks2b4TFC55RpLWCXb +q5dFarytaQLwnlpYvMRiCs1zbjBheDsHcMXAnZINAtmf0H0v44ffgFjkW5cklaxamRF WZXDI95nUZ/ubJRFdiSPu//i1Ke0xC1B363+nnYsDzAvnwPBPgNScZQUWicRqUkTlvlM AjmzoOHCZ3UwSAY5HWz4JEBfLkdukodSjfn0/rRvOzloJ/rnhj4A4gnb3fPF2nqobPT8 uVOjDpa5LViTnV1OiSXzuGeUffdyLMMjhLh0Le37KjESvql/GiXwyjIn6QNfKdF3G7VF RbEQ== X-Gm-Message-State: AOAM532GglHCh6tjUu9RYL5VEFI3vvBR+Qk5XYQ9YRkzeUQT6BIBH/YP BncwgTLr7KndDMwRSHaTwDxeBQ2PiCLxCA== X-Google-Smtp-Source: ABdhPJwD4SBG0RN6QSgTw4oAzQLlZyy7OaDL9E9uB07ufslNgdWWs5lT04akTFBgrbB4R7o0gXMEyg== X-Received: by 2002:a17:906:3e8d:: with SMTP id a13mr27650278ejj.463.1623230211734; Wed, 09 Jun 2021 02:16:51 -0700 (PDT) Received: from localhost.localdomain ([79.115.44.61]) by smtp.gmail.com with ESMTPSA id t2sm825371ejx.72.2021.06.09.02.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jun 2021 02:16:51 -0700 (PDT) X-Google-Original-From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Subject: [committed] arc: Fix (u)maddhisi patterns Date: Wed, 9 Jun 2021 12:16:43 +0300 Message-Id: <20210609091644.476605-2-claziss@synopsys.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210609091644.476605-1-claziss@synopsys.com> References: <20210609091644.476605-1-claziss@synopsys.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Claudiu Zissulescu via Gcc-patches From: Claudiu Zissulescu Ianculescu Reply-To: Claudiu Zissulescu Cc: fbedard@synopsys.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead of the 64bit MAC(U) instruction. This fixes the next execute.exp failures: arith-rand-ll.c -O2 execution test arith-rand-ll.c -O3 execution test pr78726.c -O2 execution test pr78726.c -O3 execution test Backported to gcc11 too. gcc/ 2021-06-09 Claudiu Zissulescu * config/arc/arc.md (maddhisi4): Use VMAC2H instruction. (machi): New pattern. (umaddhisi4): Use VMAC2HU instruction. (umachi): New pattern. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.md | 66 +++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 6f13b3a01d8..aed0b40728b 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6025,48 +6025,64 @@ (define_insn "stack_irq_dwarf" ;; MAC and DMPY instructions -; Use MAC instruction to emulate 16bit mac. +; Use VMAC2H(U) instruction to emulate scalar 16bit mac. (define_expand "maddhisi4" [(match_operand:SI 0 "register_operand" "") (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "extend_operand" "") (match_operand:SI 3 "register_operand" "")] - "TARGET_PLUS_DMPY" + "TARGET_PLUS_MACD" "{ - rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); - rtx tmp1 = gen_reg_rtx (SImode); - rtx tmp2 = gen_reg_rtx (SImode); - rtx accl = gen_lowpart (SImode, acc_reg); - - emit_move_insn (accl, operands[3]); - emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1]))); - emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode, operands[2]))); - emit_insn (gen_mac (tmp1, tmp2)); - emit_move_insn (operands[0], accl); + rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST); + + emit_move_insn (acc_reg, operands[3]); + emit_insn (gen_machi (operands[1], operands[2])); + emit_move_insn (operands[0], acc_reg); DONE; }") -; The same for the unsigned variant, but using MACU instruction. +(define_insn "machi" + [(set (reg:SI ARCV2_ACC) + (plus:SI + (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r")) + (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))) + (reg:SI ARCV2_ACC)))] + "TARGET_PLUS_MACD" + "vmac2h\\t0,%0,%1" + [(set_attr "length" "4") + (set_attr "type" "multi") + (set_attr "predicable" "no") + (set_attr "cond" "nocond")]) + +; The same for the unsigned variant, but using VMAC2HU instruction. (define_expand "umaddhisi4" [(match_operand:SI 0 "register_operand" "") (match_operand:HI 1 "register_operand" "") - (match_operand:HI 2 "extend_operand" "") + (match_operand:HI 2 "register_operand" "") (match_operand:SI 3 "register_operand" "")] - "TARGET_PLUS_DMPY" + "TARGET_PLUS_MACD" "{ - rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); - rtx tmp1 = gen_reg_rtx (SImode); - rtx tmp2 = gen_reg_rtx (SImode); - rtx accl = gen_lowpart (SImode, acc_reg); - - emit_move_insn (accl, operands[3]); - emit_insn (gen_rtx_SET (tmp1, gen_rtx_ZERO_EXTEND (SImode, operands[1]))); - emit_insn (gen_rtx_SET (tmp2, gen_rtx_ZERO_EXTEND (SImode, operands[2]))); - emit_insn (gen_macu (tmp1, tmp2)); - emit_move_insn (operands[0], accl); + rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST); + + emit_move_insn (acc_reg, operands[3]); + emit_insn (gen_umachi (operands[1], operands[2])); + emit_move_insn (operands[0], acc_reg); DONE; }") +(define_insn "umachi" + [(set (reg:SI ARCV2_ACC) + (plus:SI + (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r")) + (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))) + (reg:SI ARCV2_ACC)))] + "TARGET_PLUS_MACD" + "vmac2hu\\t0,%0,%1" + [(set_attr "length" "4") + (set_attr "type" "multi") + (set_attr "predicable" "no") + (set_attr "cond" "nocond")]) + (define_expand "maddsidi4" [(match_operand:DI 0 "register_operand" "") (match_operand:SI 1 "register_operand" "")