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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id k36sm10100870wms.30.2021.06.08.14.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 14:38:44 -0700 (PDT) To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 1/2] arm: Fix vcond_mask expander for MVE (PR target/100757) Date: Tue, 8 Jun 2021 21:38:43 +0000 Message-Id: <20210608213844.6218-1-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-14.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The problem in this PR is that we call VPSEL with a mask of vector type instead of HImode. This happens because operand 3 in vcond_mask is the pre-computed vector comparison and has vector type. The fix is to transfer this value to VPR.P0 by comparing operand 3 with a vector of constant 1 of the same type as operand 3. The pr100757*.c testcases are derived from gcc.c-torture/compile/20160205-1.c, forcing the use of MVE, and using different types and return values different from 0 and 1 to avoid commonalization with boolean masks. Reducing the number of iterations in pr100757-3.c from 32 to 8, we generate the code below: float a[32]; float fn1(int d) { int c = 4; for (int b = 0; b < 8; b++) if (a[b] != 2.0f) c = 5; return c; } fn1: ldr r3, .L4+80 vpush.64 {d8, d9} vldrw.32 q3, [r3] // q3=a[0..3] vldr.64 d8, .L4 // q4=(2.0,2.0,2.0,2.0) vldr.64 d9, .L4+8 adds r3, r3, #16 vcmp.f32 eq, q3, q4 // cmp a[0..3] == (2.0,2.0,2.0,2.0) vldr.64 d2, .L4+16 // q1=(1,1,1,1) vldr.64 d3, .L4+24 vldrw.32 q3, [r3] // q3=a[4..7] vldr.64 d4, .L4+32 // q2=(0,0,0,0) vldr.64 d5, .L4+40 vpsel q0, q1, q2 // q0=select (a[0..3]) vcmp.f32 eq, q3, q4 // cmp a[4..7] == (2.0,2.0,2.0,2.0) vldm sp!, {d8-d9} vpsel q2, q1, q2 // q2=select (a[4..7]) vand q2, q0, q2 // q2=select (a[0..3]) && select (a[4..7]) vldr.64 d6, .L4+48 // q3=(4.0,4.0,4.0,4.0) vldr.64 d7, .L4+56 vldr.64 d0, .L4+64 // q0=(5.0,5.0,5.0,5.0) vldr.64 d1, .L4+72 vcmp.i32 eq, q2, q1 // cmp mask(a[0..7]) == (1,1,1,1) vpsel q3, q3, q0 // q3= vcond_mask(4.0,5.0) vmov.32 r3, q3[0] // keep the scalar max vmov.32 r1, q3[1] vmov.32 r0, q3[3] vmov.32 r2, q3[2] vmov s14, r1 vmov s15, r3 vmaxnm.f32 s15, s15, s14 vmov s14, r2 vmaxnm.f32 s15, s15, s14 vmov s14, r0 vmaxnm.f32 s15, s15, s14 vmov r0, s15 bx lr .L5: .align 3 .L4: .word 1073741824 .word 1073741824 .word 1073741824 .word 1073741824 .word 1 .word 1 .word 1 .word 1 .word 0 .word 0 .word 0 .word 0 .word 1082130432 .word 1082130432 .word 1082130432 .word 1082130432 .word 1084227584 .word 1084227584 .word 1084227584 .word 1084227584 2021-06-09 Christophe Lyon PR target/100757 gcc/ * config/arm/vec-common.md (vcond_mask_): Fix expansion for MVE. gcc/testsuite/ * gcc.target/arm/simd/pr100757.c: New test. * gcc.target/arm/simd/pr100757-2.c: New test. * gcc.target/arm/simd/pr100757-3.c: New test. --- gcc/config/arm/vec-common.md | 24 +++++++++++++++++-- .../gcc.target/arm/simd/pr100757-2.c | 20 ++++++++++++++++ .../gcc.target/arm/simd/pr100757-3.c | 20 ++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/pr100757.c | 19 +++++++++++++++ 4 files changed, 81 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/pr100757-2.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/pr100757-3.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/pr100757.c diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 0ffc7a9322c..ccdfaa8321f 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -478,8 +478,28 @@ (define_expand "vcond_mask_" } else if (TARGET_HAVE_MVE) { - emit_insn (gen_mve_vpselq (VPSELQ_S, mode, operands[0], - operands[1], operands[2], operands[3])); + /* Convert pre-computed vector comparison into VPR.P0 by comparing + operand 3 with a vector of '1', then use VPSEL. */ + machine_mode cmp_mode = GET_MODE (operands[3]); + rtx vpr_p0 = gen_reg_rtx (HImode); + rtx one = gen_reg_rtx (cmp_mode); + emit_move_insn (one, CONST1_RTX (cmp_mode)); + emit_insn (gen_mve_vcmpq (EQ, cmp_mode, vpr_p0, operands[3], one)); + + switch (GET_MODE_CLASS (mode)) + { + case MODE_VECTOR_INT: + emit_insn (gen_mve_vpselq (VPSELQ_S, mode, operands[0], operands[1], operands[2], vpr_p0)); + break; + case MODE_VECTOR_FLOAT: + if (TARGET_HAVE_MVE_FLOAT) + emit_insn (gen_mve_vpselq_f (mode, operands[0], operands[1], operands[2], vpr_p0)); + else + gcc_unreachable (); + break; + default: + gcc_unreachable (); + } } else gcc_unreachable (); diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c new file mode 100644 index 00000000000..993ce369090 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ +/* Derived from gcc.c-torture/compile/20160205-1.c. */ + +float a[32]; +int fn1(int d) { + int c = 4; + for (int b = 0; b < 32; b++) + if (a[b] != 2.0f) + c = 5; + return c; +} + +/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /* Constant 2.0f. */ +/* { dg-final { scan-assembler-times {\t.word\t1\n} 4 } } */ /* 'true' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t4\n} 4 } } */ /* Initial value for c. */ +/* { dg-final { scan-assembler-times {\t.word\t5\n} 4 } } */ /* Possible value for c. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c new file mode 100644 index 00000000000..b94a73b2d2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ +/* Copied from gcc.c-torture/compile/20160205-1.c. */ + +float a[32]; +float fn1(int d) { + float c = 4; + for (int b = 0; b < 32; b++) + if (a[b] != 2.0f) + c = 5; + return c; +} + +/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /* Constant 2.0f. */ +/* { dg-final { scan-assembler-times {\t.word\t1\n} 4 } } */ /* 'true' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t1084227584\n} 4 } } */ /* Initial value for c. */ +/* { dg-final { scan-assembler-times {\t.word\t1082130432\n} 4 } } */ /* Possible value for c. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757.c b/gcc/testsuite/gcc.target/arm/simd/pr100757.c new file mode 100644 index 00000000000..e51e716b4ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ +/* Derived from gcc.c-torture/compile/20160205-1.c. */ + +int a[32]; +int fn1(int d) { + int c = 2; + for (int b = 0; b < 32; b++) + if (a[b]) + c = 3; + return c; +} + +/* { dg-final { scan-assembler-times {\t.word\t1\n} 4 } } */ /* 'true' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask. */ +/* { dg-final { scan-assembler-times {\t.word\t2\n} 4 } } */ /* Initial value for c. */ +/* { dg-final { scan-assembler-times {\t.word\t3\n} 4 } } */ /* Possible value for c. */ From patchwork Tue Jun 8 21:38:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1489648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id k36sm10100870wms.30.2021.06.08.14.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 14:38:45 -0700 (PDT) To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 2/2] arm: Fix fix arm_expand_vcond for MVE Date: Tue, 8 Jun 2021 21:38:44 +0000 Message-Id: <20210608213844.6218-2-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210608213844.6218-1-christophe.lyon@linaro.org> References: <20210608213844.6218-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-14.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch fixes a problem in arm_expand_vcond() where the result would be a vector of 0 or 1 instead of operand 1 or 2. The mve-vcmp-f32-2.c testcase is an update from mve-vcmp-f32.c using a conditional with 2.0f and 3.0f constants to help scan-assembler-times. 2021-06-09 Christophe Lyon gcc/ * config/arm/arm.c (arm_expand_vcond): Fix select operands. gcc/testsuite/ * gcc.target/arm/simd/mve-vcmp-f32-2.c: New test. --- gcc/config/arm/arm.c | 15 +++++---- .../gcc.target/arm/simd/mve-vcmp-f32-2.c | 32 +++++++++++++++++++ 2 files changed, 40 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9377aaef342..35e22382650 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -31164,7 +31164,7 @@ arm_expand_vcond (rtx *operands, machine_mode cmp_result_mode) if (TARGET_HAVE_MVE) { - vcond_mve=true; + vcond_mve = true; mask = gen_reg_rtx (HImode); } else @@ -31181,18 +31181,19 @@ arm_expand_vcond (rtx *operands, machine_mode cmp_result_mode) { machine_mode cmp_mode = GET_MODE (operands[4]); rtx vpr_p0 = mask; - rtx zero = gen_reg_rtx (cmp_mode); - rtx one = gen_reg_rtx (cmp_mode); - emit_move_insn (zero, CONST0_RTX (cmp_mode)); - emit_move_insn (one, CONST1_RTX (cmp_mode)); + switch (GET_MODE_CLASS (cmp_mode)) { case MODE_VECTOR_INT: - emit_insn (gen_mve_vpselq (VPSELQ_S, cmp_result_mode, operands[0], one, zero, vpr_p0)); + emit_insn (gen_mve_vpselq (VPSELQ_S, cmp_result_mode, operands[0], + operands[1], operands[2], vpr_p0)); break; case MODE_VECTOR_FLOAT: if (TARGET_HAVE_MVE_FLOAT) - emit_insn (gen_mve_vpselq_f (cmp_mode, operands[0], one, zero, vpr_p0)); + emit_insn (gen_mve_vpselq_f (cmp_mode, operands[0], + operands[1], operands[2], vpr_p0)); + else + gcc_unreachable (); break; default: gcc_unreachable (); diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c new file mode 100644 index 00000000000..917a95bf141 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ + +#include + +#define NB 4 + +#define FUNC(OP, NAME) \ + void test_ ## NAME ##_f (float * __restrict__ dest, float *a, float *b) { \ + int i; \ + for (i=0; i, vcmpgt) +FUNC(>=, vcmpge) + +/* { dg-final { scan-assembler-times {\tvcmp.f32\teq, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvcmp.f32\tne, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvcmp.f32\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvcmp.f32\tle, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvcmp.f32\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvcmp.f32\tge, q[0-9]+, q[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 24 } } */ /* Constant 2.0f. */ +/* { dg-final { scan-assembler-times {\t.word\t1077936128\n} 24 } } */ /* Constant 3.0f. */