From patchwork Fri Jun 4 15:10:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487814 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=awImPcFm; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=vKHxm3nD; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FxR7t0jn6z9sRK for ; Sat, 5 Jun 2021 01:12:10 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BwCH/jYEq813rubPhSTyiF9EizTt8u1mV3Pt+i9yFIM=; b=awImPcFmBgBYK4 c4Y0Y97qOt/CmD1V4PqaFMKnijH68opRwi3ko7T/fxkn02TcjjQmQNdEY2BL+lilzvt87eIp9iwcb KpW2pDN+S57gAJaNAR5Nb0Dl+UjUOY7r+xEEyN0cIw8ZX+k9VS/A4XYkYkYnuyxo8OhtUEfDwEwul pRgEsmW2ihZDuqFCGR/1OeTabT0kqcjwdWetsvrrueD2X+UOjwKqNZtAvomrc733Oa775GDFhcqho XyFNb52XsKSFtu9kllDuzKN0BTvwGnmmBvCkyaioJql9WmiNB/taPcl/SOkAfsWAYL2INSuWi+BgN MzebdK8uYgOxNPjvoQBg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lpBTv-00E5GQ-J2; Fri, 04 Jun 2021 15:11:31 +0000 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lpBTb-00E5Bp-VV; Fri, 04 Jun 2021 15:11:16 +0000 Received: by mail-oi1-x22a.google.com with SMTP id w127so10033454oig.12; Fri, 04 Jun 2021 08:11:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fyE+h/cPVeiDZzU3fvDlw6KyVLKd3NiXe8H5PkVg15I=; b=vKHxm3nDA3HVgshFrx1/hhHLEgSBLpZ/a8rMX8R/SMFZ/6mb4BWlAyLaPY+8x13FQH KZN0fJ54yVLWkLiLB279AhZbFpfqGJ3vsYZ6j21GkwcanpYszEy2S5P1cxzTbqad5uhf 37BhcVPJg7h1Gi4kGzaUwGjrlG26Cnkls9QrXL3+8FmtxD7Qv14XtGVsx0ggW0ZEkwuk Mm1oOt+/BPOKPL23O3IPcenLud2AhUI0/ApeGumZx/AYS65p3b55Lzqi9hmkZ1HVqvl6 mjuiUQSr1q1XyKNvaHQeoYYWXY3272HQzpb75zzmt/Og9aKpXsc3AbDz1mdDIY8ha/ap XpAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fyE+h/cPVeiDZzU3fvDlw6KyVLKd3NiXe8H5PkVg15I=; b=nIDvzkzRs/MRY7618HNUiSffkKvdlMueFBJny1qTA4VmRI4EfJYRt/Zk5TAPg27cHt kLJ5lLWKa9G7GRwtH/G7a2doXLcHcRB9KipHc0nNghkx/a0WRVfYonxrs15gCWqupum2 7isyF6cJALWyhgaiKV7LQrpE4ZftB8b+4W7SHD1C/i1oo0R0zx/OZPyOUpXgx11meN6R vITAl4b7qujRoWbNUjV4aHjtFzSNdmzpulZF+bD5gD37jasbgS9EwfON5ch3gy40u+ms qzvlJa74apw4KpUrk5XV7Vbys3IuIEYnhPubku7ecaUwTJAxKw5171zL/pYVQE6RGUsz JyTg== X-Gm-Message-State: AOAM531G+UygFEiRSDE/0LRl+vZ2kdxBqU0xw0uVr7lE025ZTirVKCFi i/sYPWmnfYIZTVtQTEpsAmw= X-Google-Smtp-Source: ABdhPJzZdxeEirRNyoyGsUZEOKwOCHATO6aDYXZqOvnkcmLmlkJEcZJvjrUuZqPb1nDaLCDEQViN5Q== X-Received: by 2002:aca:b443:: with SMTP id d64mr3231279oif.68.1622819469820; Fri, 04 Jun 2021 08:11:09 -0700 (PDT) Received: from wintermute.localdomain (cpe-76-183-134-35.tx.res.rr.com. [76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:09 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 1/8] dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller Date: Fri, 4 Jun 2021 10:10:48 -0500 Message-Id: <20210604151055.28636-2-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081112_041926_711BEE9C X-CRM114-Status: GOOD ( 11.96 ) X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add bindings for the Rockchip serial flash controller. New device specific parameter of rockchip,sfc-no-dma included in documentation. Signed-off-by: Chris Morgan --- .../devicetree/bindings/spi/rockchip-sfc.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/rockc [...] Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:22a listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add bindings for the Rockchip serial flash controller. New device specific parameter of rockchip,sfc-no-dma included in documentation. Signed-off-by: Chris Morgan --- .../devicetree/bindings/spi/rockchip-sfc.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml new file mode 100644 index 000000000000..05728de52921 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Serial Flash Controller (SFC) + +maintainers: + - Heiko Stuebner + - Chris Morgan + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - rockchip,px30-sfc + - rockchip,rk3308-sfc + - rockchip,rv1108-sfc + - const: rockchip,rk3036-sfc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: ahb + - const: sfc + + power-domains: + maxItems: 1 + + rockchip,sfc-no-dma: + description: Disable DMA and utilize FIFO mode only + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc"; + reg = <0xff3a0000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; + pinctrl-names = "default"; + power-domains = <&power PX30_PD_MMC_NAND>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + }; + +... 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:10 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 2/8] spi: rockchip-sfc: add rockchip serial flash controller Date: Fri, 4 Jun 2021 10:10:49 -0500 Message-Id: <20210604151055.28636-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081112_559975_69D32B48 X-CRM114-Status: GOOD ( 27.74 ) X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add the rockchip serial flash controller (SFC) driver. Signed-off-by: Chris Morgan --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-rockchip-sfc.c | 863 +++++++++++++++++++++++++++++++++ 3 files changed, 873 insertions(+) create [...] Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:32a listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add the rockchip serial flash controller (SFC) driver. Signed-off-by: Chris Morgan --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-rockchip-sfc.c | 863 +++++++++++++++++++++++++++++++++ 3 files changed, 873 insertions(+) create mode 100644 drivers/spi/spi-rockchip-sfc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f4481fe48bf0..4d81ba7841e2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -658,6 +658,15 @@ config SPI_ROCKCHIP The main usecase of this controller is to use spi flash as boot device. +config SPI_ROCKCHIP_SFC + tristate "Rockchip Serial Flash Controller (SFC)" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on HAS_IOMEM && HAS_DMA + help + This enables support for Rockchip serial flash controller. This + is a specialized controller used to access SPI flash on some + Rockchip SOCs. + config SPI_RB4XX tristate "Mikrotik RB4XX SPI master" depends on SPI_MASTER && ATH79 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 13e54c45e9df..699db95c8441 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o +obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c new file mode 100644 index 000000000000..ddce87a2f319 --- /dev/null +++ b/drivers/spi/spi-rockchip-sfc.c @@ -0,0 +1,863 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Rockchip Serial Flash Controller Driver +// +// Copyright (c) 2017, Rockchip Inc. +// Author: Shawn Lin +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System control */ +#define SFC_CTRL 0x0 +#define SFC_CTRL_COMMON_BITS_1 0x0 +#define SFC_CTRL_COMMON_BITS_2 0x1 +#define SFC_CTRL_COMMON_BITS_4 0x2 +#define SFC_CTRL_DATA_BITS_SHIFT 12 +#define SFC_CTRL_ADDR_BITS_SHIFT 10 +#define SFC_CTRL_CMD_BITS_SHIFT 8 +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) + +/* Interrupt mask */ +#define SFC_IMR 0x4 +#define SFC_IMR_RX_FULL BIT(0) +#define SFC_IMR_RX_UFLOW BIT(1) +#define SFC_IMR_TX_OFLOW BIT(2) +#define SFC_IMR_TX_EMPTY BIT(3) +#define SFC_IMR_TRAN_FINISH BIT(4) +#define SFC_IMR_BUS_ERR BIT(5) +#define SFC_IMR_NSPI_ERR BIT(6) +#define SFC_IMR_DMA BIT(7) + +/* Interrupt clear */ +#define SFC_ICLR 0x8 +#define SFC_ICLR_RX_FULL BIT(0) +#define SFC_ICLR_RX_UFLOW BIT(1) +#define SFC_ICLR_TX_OFLOW BIT(2) +#define SFC_ICLR_TX_EMPTY BIT(3) +#define SFC_ICLR_TRAN_FINISH BIT(4) +#define SFC_ICLR_BUS_ERR BIT(5) +#define SFC_ICLR_NSPI_ERR BIT(6) +#define SFC_ICLR_DMA BIT(7) + +/* FIFO threshold level */ +#define SFC_FTLR 0xc +#define SFC_FTLR_TX_SHIFT 0 +#define SFC_FTLR_TX_MASK 0x1f +#define SFC_FTLR_RX_SHIFT 8 +#define SFC_FTLR_RX_MASK 0x1f + +/* Reset FSM and FIFO */ +#define SFC_RCVR 0x10 +#define SFC_RCVR_RESET BIT(0) + +/* Enhanced mode */ +#define SFC_AX 0x14 + +/* Address Bit number */ +#define SFC_ABIT 0x18 + +/* Interrupt status */ +#define SFC_ISR 0x1c +#define SFC_ISR_RX_FULL_SHIFT BIT(0) +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) +#define SFC_ISR_TX_FINISH_SHIFT BIT(4) +#define SFC_ISR_BUS_ERR_SHIFT BIT(5) +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) +#define SFC_ISR_DMA_SHIFT BIT(7) + +/* FIFO status */ +#define SFC_FSR 0x20 +#define SFC_FSR_TX_IS_FULL BIT(0) +#define SFC_FSR_TX_IS_EMPTY BIT(1) +#define SFC_FSR_RX_IS_EMPTY BIT(2) +#define SFC_FSR_RX_IS_FULL BIT(3) +#define SFC_FSR_TXLV_MASK GENMASK(12, 8) +#define SFC_FSR_TXLV_SHIFT 8 +#define SFC_FSR_RXLV_MASK GENMASK(20, 16) +#define SFC_FSR_RXLV_SHIFT 16 + +/* FSM status */ +#define SFC_SR 0x24 +#define SFC_SR_IS_IDLE 0x0 +#define SFC_SR_IS_BUSY 0x1 + +/* Raw interrupt status */ +#define SFC_RISR 0x28 +#define SFC_RISR_RX_FULL BIT(0) +#define SFC_RISR_RX_UNDERFLOW BIT(1) +#define SFC_RISR_TX_OVERFLOW BIT(2) +#define SFC_RISR_TX_EMPTY BIT(3) +#define SFC_RISR_TRAN_FINISH BIT(4) +#define SFC_RISR_BUS_ERR BIT(5) +#define SFC_RISR_NSPI_ERR BIT(6) +#define SFC_RISR_DMA BIT(7) + +/* Master trigger */ +#define SFC_DMA_TRIGGER 0x80 + +/* Src or Dst addr for master */ +#define SFC_DMA_ADDR 0x84 + +/* Command */ +#define SFC_CMD 0x100 +#define SFC_CMD_IDX_SHIFT 0 +#define SFC_CMD_DUMMY_SHIFT 8 +#define SFC_CMD_DIR_RD 0 +#define SFC_CMD_DIR_WR 1 +#define SFC_CMD_DIR_SHIFT 12 +#define SFC_CMD_ADDR_ZERO (0x0 << 14) +#define SFC_CMD_ADDR_24BITS (0x1 << 14) +#define SFC_CMD_ADDR_32BITS (0x2 << 14) +#define SFC_CMD_ADDR_FRS (0x3 << 14) +#define SFC_CMD_TRAN_BYTES_SHIFT 16 +#define SFC_CMD_CS_SHIFT 30 + +/* Address */ +#define SFC_ADDR 0x104 + +/* Data */ +#define SFC_DATA 0x108 + +/* The controller and documentation reports that it supports up to 4 CS + * devices (0-3), however I have only been able to test a single CS (CS 0) + * due to the configuration of my device. + */ +#define SFC_MAX_CHIPSELECT_NUM 4 + +/* The SFC can transfer max 16KB - 1 at one time + * we set it to 15.5KB here for alignment. + */ +#define SFC_MAX_TRANS_BYTES (512 * 31) + +/* Maximum clock values from datasheet suggest keeping clock value under + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver + * has a minimum of 10MHz and a default of 80MHz which seems reasonable. + */ +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) + +#define SFC_CMD_DUMMY(x) \ + ((x) << SFC_CMD_DUMMY_SHIFT) + +enum rockchip_sfc_iftype { + IF_TYPE_STD, + IF_TYPE_DUAL, + IF_TYPE_QUAD, +}; + +struct rockchip_sfc; +struct rockchip_sfc_chip_priv { + u8 cs; + u32 clk_rate; + struct rockchip_sfc *sfc; +}; + +struct rockchip_sfc { + struct device *dev; + void __iomem *regbase; + struct clk *hclk; + struct clk *clk; + /* virtual mapped addr for dma_buffer */ + void *buffer; + dma_addr_t dma_buffer; + struct completion cp; + struct rockchip_sfc_chip_priv flash[SFC_MAX_CHIPSELECT_NUM]; + u8 num_chip; + bool use_dma; +}; + +static int rockchip_sfc_get_if_type(const struct spi_mem_op *op, + struct rockchip_sfc *sfc) +{ + switch (op->data.buswidth) { + case 1: + return IF_TYPE_STD; + case 2: + return IF_TYPE_DUAL; + case 4: + return IF_TYPE_QUAD; + default: + dev_err(sfc->dev, "unsupported SPI read mode\n"); + return -EINVAL; + } +} + +static int rockchip_sfc_reset(struct rockchip_sfc *sfc) +{ + int err; + u32 status; + + writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); + + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, + !(status & SFC_RCVR_RESET), 20, + jiffies_to_usecs(HZ)); + if (err) + dev_err(sfc->dev, "SFC reset never finished\n"); + + /* Still need to clear the masked interrupt from RISR */ + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + + dev_dbg(sfc->dev, "reset\n"); + + return err; +} + +static int rockchip_sfc_init(struct rockchip_sfc *sfc) +{ + int err; + + err = clk_set_rate(sfc->clk, SFC_DEFAULT_SPEED_HZ); + if (err) + return err; + + err = rockchip_sfc_reset(sfc); + if (err) + return err; + + /* Mask all eight interrupts */ + writel_relaxed(0xff, sfc->regbase + SFC_IMR); + + writel_relaxed(SFC_CTRL_PHASE_SEL_NEGETIVE, sfc->regbase + SFC_CTRL); + + return 0; +} + +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) +{ + u32 fsr = readl_relaxed(sfc->regbase + SFC_FSR); + int level; + + if (wr) + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; + else + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; + + return level; +} + +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) +{ + unsigned long deadline = jiffies + timeout; + int level; + + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { + if (time_after_eq(jiffies, deadline)) { + dev_warn(sfc->dev, "%s fifo timeout\n", wr ? "write" : "read"); + return -ETIMEDOUT; + } + udelay(1); + } + + return level; +} + +/* The SFC_CTRL register is a global control register, + * when the controller is in busy state(SFC_SR), + * SFC_CTRL cannot be set. + */ +static void rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, u32 timeout_us) +{ + u32 status; + int ret; + + ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, + !(status & SFC_SR_IS_BUSY), + 20, timeout_us); + if (ret) { + dev_err(sfc->dev, "wait sfc idle timeout\n"); + rockchip_sfc_reset(sfc); + } +} + +static void rockchip_sfc_setup_ctrl(struct rockchip_sfc *sfc) +{ + u32 reg; + + reg = IF_TYPE_STD << SFC_CTRL_DATA_BITS_SHIFT; + reg |= IF_TYPE_STD << SFC_CTRL_ADDR_BITS_SHIFT; + reg |= IF_TYPE_STD << SFC_CTRL_CMD_BITS_SHIFT; + reg |= SFC_CTRL_PHASE_SEL_NEGETIVE; + + rockchip_sfc_wait_idle(sfc, 10000); + + writel_relaxed(reg, sfc->regbase + SFC_CTRL); +} + +static int rockchip_sfc_op_reg(struct rockchip_sfc_chip_priv *priv, + u8 opcode, int len, u8 optype) +{ + struct rockchip_sfc *sfc = priv->sfc; + u32 reg; + + rockchip_sfc_setup_ctrl(sfc); + + reg = opcode << SFC_CMD_IDX_SHIFT; + reg |= len << SFC_CMD_TRAN_BYTES_SHIFT; + reg |= priv->cs << SFC_CMD_CS_SHIFT; + reg |= optype << SFC_CMD_DIR_SHIFT; + writel_relaxed(reg, sfc->regbase + SFC_CMD); + + return 0; +} + +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + int tx_level; + u32 write_words; + u32 tmp = 0; + + dwords = len >> 2; + while (dwords) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, HZ); + if (tx_level < 0) + return tx_level; + write_words = min_t(u32, tx_level, dwords); + iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); + buf += write_words << 2; + dwords -= write_words; + } + + /* write the rest of the bytes that are not a multiple of word size */ + if (bytes) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, HZ); + if (tx_level < 0) + return tx_level; + memcpy(&tmp, buf, bytes); + writel_relaxed(tmp, sfc->regbase + SFC_DATA); + } + + return len; +} + +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + u8 read_words; + int rx_level; + int tmp; + + /* word aligned access only */ + dwords = len >> 2; + while (dwords) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, HZ); + if (rx_level < 0) + return rx_level; + read_words = min_t(u32, rx_level, dwords); + ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); + buf += read_words << 2; + dwords -= read_words; + } + + /* read the rest of the bytes that are not a multiple of word size */ + if (bytes) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, HZ); + if (rx_level < 0) + return rx_level; + tmp = readl_relaxed(sfc->regbase + SFC_DATA); + memcpy(buf, &tmp, bytes); + } + + return len; +} + +static int rockchip_sfc_read_reg(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = priv->sfc; + int ret; + int trans; + size_t n_rx = op->data.nbytes; + u8 opcode = op->cmd.opcode; + u8 *rxbuf = op->data.buf.in; + + trans = min_t(int, n_rx, SFC_MAX_TRANS_BYTES); + ret = rockchip_sfc_op_reg(priv, opcode, trans, SFC_CMD_DIR_RD); + if (ret) + return ret; + + ret = rockchip_sfc_read_fifo(sfc, rxbuf, trans); + if (ret < 0) + return ret; + + return 0; +} + +static int rockchip_sfc_write_reg(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = priv->sfc; + int ret; + size_t n_tx = op->data.nbytes; + u8 opcode = op->cmd.opcode; + const u8 *txbuf = op->data.buf.out; + + ret = rockchip_sfc_op_reg(priv, opcode, n_tx, SFC_CMD_DIR_WR); + if (ret) + return ret; + ret = rockchip_sfc_write_fifo(sfc, txbuf, n_tx); + if (ret < 0) + return ret; + + return 0; +} + +static int rockchip_sfc_setup_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, + loff_t from_to, size_t len, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + u8 if_type = IF_TYPE_STD; + u8 addr_width = op->addr.nbytes; + u8 read_dummy_bits = op->dummy.nbytes << 3; + u32 reg; + + if (op_type == SFC_CMD_DIR_RD) + if_type = rockchip_sfc_get_if_type(op, sfc); + + rockchip_sfc_wait_idle(sfc, 10000); + + writel_relaxed((if_type << SFC_CTRL_DATA_BITS_SHIFT) | + (IF_TYPE_STD << SFC_CTRL_ADDR_BITS_SHIFT) | + (IF_TYPE_STD << SFC_CTRL_CMD_BITS_SHIFT) | + SFC_CTRL_PHASE_SEL_NEGETIVE, + sfc->regbase + SFC_CTRL); + + reg = op->cmd.opcode << SFC_CMD_IDX_SHIFT; + + reg |= op_type << SFC_CMD_DIR_SHIFT; + reg |= (addr_width == 4) ? + SFC_CMD_ADDR_32BITS : SFC_CMD_ADDR_24BITS; + + reg |= priv->cs << SFC_CMD_CS_SHIFT; + reg |= len << SFC_CMD_TRAN_BYTES_SHIFT; + + if (op_type == SFC_CMD_DIR_RD) + reg |= SFC_CMD_DUMMY(read_dummy_bits); + + writel_relaxed(reg, sfc->regbase + SFC_CMD); + writel_relaxed(from_to, sfc->regbase + SFC_ADDR); + + return 0; +} + +static int rockchip_sfc_do_dma_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, + dma_addr_t dma_buf, size_t len, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + u32 reg; + int err = 0; + + init_completion(&sfc->cp); + + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + + /* Enable transfer complete interrupt */ + reg = readl_relaxed(sfc->regbase + SFC_IMR); + reg &= ~SFC_IMR_TRAN_FINISH; + writel_relaxed(reg, sfc->regbase + SFC_IMR); + + err = rockchip_sfc_setup_transfer(priv, op, from_to, len, op_type); + if (err < 0) + return err; + + writel_relaxed(dma_buf, sfc->regbase + SFC_DMA_ADDR); + + /* + * Start dma but note that the sfc->dma_buffer is derived from + * dmam_alloc_coherent so we don't actually need any sync operations + * for coherent dma memory. + */ + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); + + /* Wait for the interrupt. */ + if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { + dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); + err = -ETIMEDOUT; + } + + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + /* Disable transfer finish interrupt */ + reg = readl_relaxed(sfc->regbase + SFC_IMR); + reg |= SFC_IMR_TRAN_FINISH; + writel_relaxed(reg, sfc->regbase + SFC_IMR); + + if (err) { + rockchip_sfc_reset(sfc); + return err; + } + + return 0; +} + +static inline int rockchip_sfc_pio_write(struct rockchip_sfc *sfc, u_char *buf, + size_t len) +{ + return rockchip_sfc_write_fifo(sfc, buf, len); +} + +static inline int rockchip_sfc_pio_read(struct rockchip_sfc *sfc, u_char *buf, + size_t len) +{ + return rockchip_sfc_read_fifo(sfc, buf, len); +} + +static int rockchip_sfc_pio_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + size_t trans; + int ret; + + trans = min_t(size_t, SFC_MAX_TRANS_BYTES, len); + ret = rockchip_sfc_setup_transfer(priv, op, from_to, trans, op_type); + if (ret < 0) + return ret; + + if (op_type == SFC_CMD_DIR_WR) + ret = rockchip_sfc_pio_write(sfc, buf, trans); + else + ret = rockchip_sfc_pio_read(sfc, buf, trans); + + return ret; +} + +static int rockchip_sfc_dma_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + size_t trans; + int ret; + + trans = min_t(size_t, SFC_MAX_TRANS_BYTES, len); + + if (op_type == SFC_CMD_DIR_WR) + memcpy(sfc->buffer, buf, trans); + + ret = rockchip_sfc_do_dma_transfer(priv, op, from_to, sfc->dma_buffer, + trans, op_type); + if (ret) { + dev_warn(sfc->dev, "DMA timeout\n"); + return ret; + } + + if (op_type == SFC_CMD_DIR_RD) + memcpy(buf, sfc->buffer, trans); + + return trans; +} + +static ssize_t rockchip_sfc_do_rd_wr(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u32 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + + /* DMA can only handle word aligned transfer chunks */ + if (likely(sfc->use_dma) && !(len & 0x3)) + return rockchip_sfc_dma_transfer(priv, op, from_to, len, buf, op_type); + else + return rockchip_sfc_pio_transfer(priv, op, from_to, len, buf, op_type); +} + +static ssize_t rockchip_sfc_read(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + loff_t from = op->addr.val; + size_t len = op->data.nbytes; + u_char *read_buf = op->data.buf.in; + + return rockchip_sfc_do_rd_wr(priv, op, from, len, read_buf, SFC_CMD_DIR_RD); +} + +static ssize_t rockchip_sfc_write(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + loff_t to = op->addr.val; + size_t len = op->data.nbytes; + const u_char *write_buf = op->data.buf.out; + + return rockchip_sfc_do_rd_wr(priv, op, to, len, (u_char *)write_buf, SFC_CMD_DIR_WR); +} + +static int rockchip_sfc_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct rockchip_sfc_chip_priv *priv = &sfc->flash[mem->spi->chip_select]; + + if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { + if (!op->addr.nbytes) + return rockchip_sfc_read_reg(priv, op); + + return rockchip_sfc_read(priv, op); + } + + if (!op->addr.nbytes || !op->data.buf.out) + return rockchip_sfc_write_reg(priv, op); + + return rockchip_sfc_write(priv, op); +} + +static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct rockchip_sfc_chip_priv *priv = &sfc->flash[mem->spi->chip_select]; + int ret; + + ret = clk_set_rate(sfc->clk, priv->clk_rate); + if (ret) + return ret; + + ret = rockchip_sfc_mem_process(mem, op); + if (ret < 0) { + dev_err(&mem->spi->dev, "operation failed with %d\n", ret); + return ret; + } + + return 0; +} + +static const char *rockchip_sfc_get_name(struct spi_mem *mem) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct device *dev = sfc->dev; + + return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); +} + +static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { + .exec_op = rockchip_sfc_exec_mem_op, + .get_name = rockchip_sfc_get_name, +}; + +static int rockchip_sfc_register(struct device_node *np, + struct rockchip_sfc *sfc) +{ + struct device *dev = sfc->dev; + int ret; + + ret = of_property_read_u8(np, "reg", &sfc->flash[sfc->num_chip].cs); + if (ret) { + dev_err(dev, "No reg property for %s\n", + np->full_name); + return ret; + } + + ret = of_property_read_u32(np, "spi-max-frequency", + &sfc->flash[sfc->num_chip].clk_rate); + if (ret) { + dev_err(dev, "No spi-max-frequency property for %s\n", + np->full_name); + return ret; + } + + sfc->flash[sfc->num_chip].sfc = sfc; + sfc->num_chip++; + return 0; +} + +static int rockchip_sfc_register_all(struct rockchip_sfc *sfc) +{ + struct device *dev = sfc->dev; + struct device_node *np; + int ret; + + for_each_available_child_of_node(dev->of_node, np) { + ret = rockchip_sfc_register(np, sfc); + if (ret) + dev_err(dev, "Failed to register all chips\n"); + return ret; + + if (sfc->num_chip >= SFC_MAX_CHIPSELECT_NUM) { + dev_warn(dev, "Exceeds the max cs limitation\n"); + break; + } + } + + return 0; +} + +static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) +{ + struct rockchip_sfc *sfc = dev_id; + u32 reg; + + reg = readl(sfc->regbase + SFC_RISR); + + /* Clear interrupt if transfer is finished */ + if (reg & SFC_RISR_TRAN_FINISH) { + writel_relaxed(reg, sfc->regbase + SFC_ICLR); + complete(&sfc->cp); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int rockchip_sfc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_master *master; + struct resource *res; + struct rockchip_sfc *sfc; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sfc)); + if (!master) { + dev_err(&pdev->dev, "spi_alloc_master failed\n"); + return -ENOMEM; + } + + master->mem_ops = &rockchip_sfc_mem_ops; + master->dev.of_node = pdev->dev.of_node; + master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; + master->min_speed_hz = SFC_MIN_SPEED_HZ; + master->max_speed_hz = SFC_MAX_SPEED_HZ; + + sfc = spi_master_get_devdata(master); + sfc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sfc->regbase = devm_ioremap_resource(dev, res); + if (IS_ERR(sfc->regbase)) + return PTR_ERR(sfc->regbase); + + sfc->clk = devm_clk_get(&pdev->dev, "sfc"); + if (IS_ERR(sfc->clk)) { + dev_err(&pdev->dev, "Failed to get sfc interface clk\n"); + return PTR_ERR(sfc->clk); + } + + sfc->hclk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(sfc->hclk)) { + dev_err(&pdev->dev, "Failed to get sfc ahb clk\n"); + return PTR_ERR(sfc->hclk); + } + + sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, + "rockchip,sfc-no-dma"); + + if (sfc->use_dma) { + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_warn(dev, "Unable to set dma mask\n"); + return ret; + } + + sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_TRANS_BYTES, + &sfc->dma_buffer, + GFP_KERNEL); + if (!sfc->buffer) + return -ENOMEM; + } + + ret = clk_prepare_enable(sfc->hclk); + if (ret) { + dev_err(&pdev->dev, "Failed to enable ahb clk\n"); + goto err_hclk; + } + + ret = clk_prepare_enable(sfc->clk); + if (ret) { + dev_err(&pdev->dev, "Failed to enable interface clk\n"); + goto err_clk; + } + + /* Find the irq */ + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(dev, "Failed to get the irq\n"); + goto err_irq; + } + + ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, + 0, pdev->name, sfc); + if (ret) { + dev_err(dev, "Failed to request irq\n"); + goto err_irq; + } + + sfc->num_chip = 0; + ret = rockchip_sfc_init(sfc); + if (ret) + goto err_irq; + + ret = rockchip_sfc_register_all(sfc); + if (ret) + goto err_irq; + + ret = devm_spi_register_master(dev, master); + if (ret) + goto err_irq; + + return 0; + +err_irq: + clk_disable_unprepare(sfc->clk); +err_clk: + clk_disable_unprepare(sfc->hclk); +err_hclk: + return ret; +} + +static int rockchip_sfc_remove(struct platform_device *pdev) +{ + struct rockchip_sfc *sfc = platform_get_drvdata(pdev); + + clk_disable_unprepare(sfc->clk); + clk_disable_unprepare(sfc->hclk); + return 0; +} + +static const struct of_device_id rockchip_sfc_dt_ids[] = { + { .compatible = "rockchip,rk3036-sfc"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); + +static struct platform_driver rockchip_sfc_driver = { + .driver = { + .name = "rockchip-sfc", + .of_match_table = rockchip_sfc_dt_ids, + }, + .probe = rockchip_sfc_probe, + .remove = rockchip_sfc_remove, +}; +module_platform_driver(rockchip_sfc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); +MODULE_AUTHOR("Shawn Lin "); From patchwork Fri Jun 4 15:10:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:11 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 3/8] arm64: dts: rockchip: Add SFC to PX30 Date: Fri, 4 Jun 2021 10:10:50 -0500 Message-Id: <20210604151055.28636-4-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081114_308093_C2D50367 X-CRM114-Status: UNSURE ( 9.31 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:334 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce..cc7aced2dde9 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -966,6 +966,18 @@ emmc: mmc@ff390000 { status = "disabled"; }; + sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + nfc: nand-controller@ff3b0000 { compatible = "rockchip,px30-nfc"; reg = <0x0 0xff3b0000 0x0 0x4000>; @@ -1967,6 +1979,32 @@ flash_bus8: flash-bus8 { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>, + <1 RK_PA2 3 &pcfg_pull_none>, + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + }; + lcdc { lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { rockchip,pins = From patchwork Fri Jun 4 15:10:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=kA9LW7bl; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:12 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 4/8] clk: rockchip: Add support for hclk_sfc on rk3036 Date: Fri, 4 Jun 2021 10:10:51 -0500 Message-Id: <20210604151055.28636-5-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081116_561411_90315300 X-CRM114-Status: GOOD ( 12.82 ) X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add support for the bus clock for the serial flash controller on the rk3036. Taken from the Rockchip BSP kernel but not tested on real hardware (as I lack a 3036 based SoC to test). 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Taken from the Rockchip BSP kernel but not tested on real hardware (as I lack a 3036 based SoC to test). Signed-off-by: Chris Morgan --- drivers/clk/rockchip/clk-rk3036.c | 2 +- include/dt-bindings/clock/rk3036-cru.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 91d56ad45817..ebb628733f6d 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -403,7 +403,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), /* pclk_peri gates */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 35a5a01f9697..a96a9870ad59 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -81,6 +81,7 @@ #define HCLK_OTG0 449 #define HCLK_OTG1 450 #define HCLK_NANDC 453 +#define HCLK_SFC 454 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 From patchwork Fri Jun 4 15:10:52 2021 Content-Type: text/plain; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:14 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 5/8] arm: dts: rockchip: Add SFC to RK3036 Date: Fri, 4 Jun 2021 10:10:52 -0500 Message-Id: <20210604151055.28636-6-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081216_497362_999DCEC4 X-CRM114-Status: UNSURE ( 9.49 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RK3036 SOC. Signed-off-by: Chris Morgan --- arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.210.53 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.210.53 listed in wl.mailspike.net] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RK3036 SOC. Signed-off-by: Chris Morgan --- arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e24230d50a78..0dba2956dfb8 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -206,6 +206,17 @@ emac: ethernet@10200000 { status = "disabled"; }; + sfc: spi@10208000 { + compatible = "rockchip,rk3036-sfc"; + reg = <0x10208000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -684,6 +695,37 @@ flash_wrn: flash-wrn { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>, + <1 RK_PD2 3 &pcfg_pull_none>, + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_none>; + }; + }; + emac { emac_xfer: emac-xfer { rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ From patchwork Fri Jun 4 15:10:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:15 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 6/8] arm: dts: rockchip: Add SFC to RV1108 Date: Fri, 4 Jun 2021 10:10:53 -0500 Message-Id: <20210604151055.28636-7-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081216_945732_27143B91 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Chris Morgan --- arch/arm/boot/dts/rv1108.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.167.170 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.167.170 listed in wl.mailspike.net] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RV1108 SOC. Signed-off-by: Chris Morgan --- arch/arm/boot/dts/rv1108.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 884872ca5207..c0d95e13add4 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -536,6 +536,17 @@ usb_otg: usb@30180000 { status = "disabled"; }; + sfc: spi@301c0000 { + compatible = "rockchip,rv1108-sfc", "rockchip,rk3036-sfc"; + reg = <0x301c0000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + gmac: eth@30200000 { compatible = "rockchip,rv1108-gmac"; reg = <0x30200000 0x10000>; @@ -704,6 +715,32 @@ emmc_cmd: emmc-cmd { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>, + <2 RK_PA2 3 &pcfg_pull_none>, + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PB4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; + gmac { rmii_pins: rmii-pins { rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, From patchwork Fri Jun 4 15:10:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487821 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=PbsQuiZc; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:16 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 7/8] arm64: dts: rockchip: Add SFC to RK3308 Date: Fri, 4 Jun 2021 10:10:54 -0500 Message-Id: <20210604151055.28636-8-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081218_164933_C4546539 X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.210.45 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.210.45 listed in wl.mailspike.net] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 0c5fa9801e6f..2d922b1d51d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -637,6 +637,17 @@ nfc: nand-controller@ff4b0000 { status = "disabled"; }; + sfc: spi@ff4c0000 { + compatible = "rockchip,rk3308-sfc", "rockchip,rk3036-sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; @@ -910,6 +921,32 @@ flash_bus8: flash-bus8 { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>, + <3 RK_PA2 3 &pcfg_pull_none>, + <3 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <3 RK_PA5 3 &pcfg_pull_none>; + }; + }; + gmac { rmii_pins: rmii-pins { rockchip,pins = From patchwork Fri Jun 4 15:10:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 1487822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=47f6+Jty; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:17 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 8/8] arm64: dts: rockchip: Enable SFC for Odroid Go Advance Date: Fri, 4 Jun 2021 10:10:55 -0500 Message-Id: <20210604151055.28636-9-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210604_081218_557110_E70FB1A0 X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Chris Morgan This enables the Rockchip Serial Flash Controller for the Odroid Go Advance. Note that while the attached SPI NOR flash and the controller both support quad read mode, only 2 of the required 4 pins ar [...] Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [209.85.210.45 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.210.45 listed in wl.mailspike.net] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [macroalpha82[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [macroalpha82[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Chris Morgan This enables the Rockchip Serial Flash Controller for the Odroid Go Advance. Note that while the attached SPI NOR flash and the controller both support quad read mode, only 2 of the required 4 pins are present. The rx and tx bus width is set to 2 for this reason. Signed-off-by: Chris Morgan --- .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 49c97f76df77..f78e11dd8447 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -484,6 +484,22 @@ &sdmmc { status = "okay"; }; +&sfc { + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &tsadc { status = "okay"; };