From patchwork Wed Jun 2 12:03:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1486637 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=K9P2/iiJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw73r3kLqz9sSs for ; Wed, 2 Jun 2021 22:04:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229626AbhFBMFt (ORCPT ); Wed, 2 Jun 2021 08:05:49 -0400 Received: from mout.gmx.net ([212.227.15.19]:60887 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbhFBMFs (ORCPT ); Wed, 2 Jun 2021 08:05:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635438; bh=ulkox2ATtAdbPPOEglhjZ3k4awk0Qn6kCKCuSyogJsg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=K9P2/iiJ8mYXqb6G1z6NNuVrNUt+HE9psjOZYpmr3urD1/0e0RaNNmAgueu0qsB/Z S3aCO0brAdmcbqKJP458JzShSTehbTDheQmamWMwS49h4WHIGOpEaPqK1RVmO+4GnX UMekteulEDUKahAx5RpVtMaJ36baq9S/dnPK8uIU= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M4JmN-1lo8UB1zbV-000JWu; Wed, 02 Jun 2021 14:03:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Subject: [PATCH 1/8] dt-bindings: arm/npcm: Add binding for global control registers (GCR) Date: Wed, 2 Jun 2021 14:03:22 +0200 Message-Id: <20210602120329.2444672-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:P9ooxxcBWMlue7/aQhsUzie0pEsU417A/bVW+i8qKslDKwe1yoF P0JJK2l+NChG9mUbWE+NUkp8CPJhowOqBbLu2w/eaW939P6xr6+2y6PIp4vGMbzsl/BUcJN rMq74FWAWY9dkqJGs2YCx4c41ickvdnrLbxFpIpY/q8mshEtXf2n4OTzR+tXxZJr7tsvS5A AKeJHK9vJLxE9lAXxDQ3A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:RLLVYPBzafk=:/20tEdy806+Ejjw719ZFcz 0RWaQ1HFc0WDKSSe0h+4TdP9N4RPrdOqkbNoE2k3uDdWC902rmq1iIxlQmg42UGTK1QvhlOZQ U3cVOGv793QjyKN6j4O5iZPmw1kX5yZK6ap1BqzbRLw+FVtQL/k3U1Cmp7DRtoD7K273XpK1k hzK1LZ+LQZBuYMg+wA2t1zBjBIPl9/apzPI9eBTE7kk8MbaaWwSmhPj5xbZG7QypKCsNOkjWx KKQ7j4CVTIV0ZXiwIN080YfDqumtQcX+JTdA22FP15if3vtF4ApDFB1u2SeDF40zio0lU9O9U 1eHi7438pXfh6tbVcxCrnu7hCpyG9d6j/02uBksNZ9eZZ6nqKyCQd+XM1v6yr7w3Y53m9bej6 Q/CTI+GFT3QVyxW+gzcbSmz6Ie4SnSfPqXtZEKmB9AD5aSDbX3iXGThvRk6Fv18qJKxMOFqI5 /cKJbrsYKdSdzgUqZ5a07L1bTOvIZn0nagiTbGA9bXlVj0PJTS5zrchEDRHj8flqcPNSI+u9J keKRkx/JFGOFvBJnOKRfIemRKmlM6hi5r/0e2aaIK38LxbMGEpaUnqryS8uN9pNs0PL6JER6t /dIdK8CESVN0V3SoHH3YMTkSjX4rh/dW6dLPceRVQOp5XwIzqh9ALfvAVwEbK+BRBndHcjbcD sKRjCGEs2iHvcbE5s9Lfbe28jo7S2NJJ5uhbOAZwypoy+mI5SmPU0pDJ9wCbnTYuVutrmBA32 ROYNca/CU9tVdkWYAGBBm08zBqgp/2IHO7tm2fvxM8qaWrT5gHyb2EbXmlldBrZyA2IgtmnlQ mUKi/WQWmFIkCl0XRt3W91kg3OeetOfnuVI8WXcVYdjay2PWr6HTi8cdkU3LMkDQted1qIOCA UURXyVUa14Qt05E/3eFYciteZjmrBzcjztF/42cMhzMnoRzcmmQeAHXPcbi2w/s816hMrwOZO I2KqYlCygdaGUkTDjjNS+SuzPlYuMEKlECDp2ooRj0XBNgAahY6SL19sOxKbx3nvCAz4W1XcJ pViyEalQV50cYxlgpqMyrR5ewKiimluVo8GLJ92bq1WDL8wdcrwUhov75iu6y1Hp0sLcf7ySY aonN8995GNifEwlE/ukzJo8huXbaWjGUXxL+2LvloRnMjf0tf+AXHRW/w== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Linus Walleij --- .../bindings/arm/npcm/nuvoton,gcr.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 0000000000000..3174279f7713a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: | + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + reg: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + }; From patchwork Wed Jun 2 12:03:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1486641 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=XEpTcTJK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74302j5z9sCD for ; Wed, 2 Jun 2021 22:04:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229800AbhFBMF4 (ORCPT ); Wed, 2 Jun 2021 08:05:56 -0400 Received: from mout.gmx.net ([212.227.15.19]:55387 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbhFBMFz (ORCPT ); Wed, 2 Jun 2021 08:05:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635447; bh=2ut7fjvCRXp1vUUCh5jcJNV1bWQfWdPByri+EnaApG4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XEpTcTJKIpUmN+jRuMfsthO1SugHY9sL+kIJZWtp+JUGmd5BVuB9nqyW9WzrGlKzB jiruRmE73d3tzDqcA68xNJ6S2GSuqrzIFzJcArEYPnKV3/CvbNnChW7guzOSLJlciQ pV+nHz+yVNqQqFaEG9QMWLylQNf8BKOfoF0n38ME= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M5fIW-1lleRh0AGI-007Eso; Wed, 02 Jun 2021 14:04:07 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 4/8] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Wed, 2 Jun 2021 14:03:25 +0200 Message-Id: <20210602120329.2444672-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:E6+ZEj70X9yV7fiuKCDzxr1LhJdKjksAzp/xm8VL+BUlNTseNAy okeguoiss3CzSzhZbxUI/g8cehAHeD7BYclX1esdvc/7SzljFeMilw82uESa2irNjwShC6Q +ga7VcY3dY3MetH3iuAhMK8bWENWkzICY+Gglqp5UWPQ1qs5H/lemP4T9TStx+g0Oqy9QPw WhabaSlPxi7wEN+qX+qbw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:l4v+Hockw6I=:sOCxMcqqcQryI1ft9be5w1 JYsHx3jlluDR2PiCP7kBlHApH55MTdTHpTgE/+5RrRTb6JVeSL+Jp4pfRzlc7w8IJ1xj1KqGc RyKzrHax0LTh5qyf5qaM9fmwbjk0J1oO1ZnoZO8BdULLZYnZUte6RkifQtos1+qThbpzLpn7e UIQqUiIFRi+QqRUOeRsNuBqKgmZRtDNleM8P9KriRfsdsOJN+BWA0GFvUjdIASn9EAAWvtmjS FauoUBzK1Wh0Y85GC/4uLg7QonpojwChodBI5wW7XzKwMxhj7j5hV3vIoebP8H+S5BL0PzIcP 4lMJO0Lr+XlUGrAiCkjNl4odHDweti/2B56O9T3WV8klgPuaCfc+Q+HCePVKeIREQy7AA6WyX NeA5iTyVYcBcsZ+yRVtd9ZDVIAf5P4MRrxF+dc2bQwRfUNhtef9eDmH44HNid9jNkFE39XWyM 7aJybtk2rc3y/TceTbOIWUHriypazDKwZKP1zigqsguajAzzTGJyM68luKZ9PNXlXHHzfY2Gl sB37k7bMm6RidcaeqyE5IuGvX30ZRs/visWcYp6djR9Ukc5Nltdgn5ToHsihRXZIWZz0PV+zP GhBvTxpwIoQlM18YczB5ZUNsnKGYVqH231qfT/hEsvAGfeuZWd+nhK3cvK0QVvu7BQbjwXcSs MDfMhPSkDaHUzIip+1q5vk/krtu9j32+0rwjkvrL4IagrzcVf7bBYf396cJxZsi2c26sRdbAK Tl6x33itHEJuwNW4iyfwLxrvTaGWUWnzadcwnW7WIsG5IxWqzBn/rLMzrcPM84Xnicb1ZoTJq pxZJ9+2N/bNjxCT8qOvJJMgREOFfCHE+3mffre+XfPnc33wA0yphDsu0pMgFOtuDZlRDFHL6l B+kTUiwfU2pfIaFRn2CUPx6883svpHQxJKoAXLKC6ggyefvjZKw+2UipuppqASeUW0wtYBMOk d5Z8HPxwh0jTQjD6/VHOxEYvHHy4mAkdqKudExmYssz4JjhPIFYtg/k0+trb34FofblfbQWdx mE9wNCNMa3h37GjVSTh1lKdxr5/9lkciOMcq7PYBRwa/0DFDc4siZAfPr5WEfwWDq8Oo0Sl3Z Yh/OnC9cU5KIiBsTASd8G/0i0cLNXwf0t31bYGp9H1ygXMX+TSaGBFKRw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This binding is heavily based on the one for NPCM7xx, because the hardware is similar. One notable difference is that there are no sub-nodes for GPIO banks, because the GPIO registers are arranged differently. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..0664fe2b90db6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: "nuvoton,wpcm450-pinctrl" + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: true + +patternProperties: + # There are two kinds of subnodes: + # 1. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 2. a pinctrl node configures properties of a single pin + "^.*$": + if: + type: object + then: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + groups: + description: + One or more groups of pins to mux to a certain function + minItems: 1 + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7 ] + + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + minItems: 1 + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, gpio42, + gpio43, gpio44, gpio45, gpio46, gpio47, gpio48, gpio49, + gpio50, gpio51, gpio52, gpio53, gpio54, gpio55, gpio56, + gpio57, gpio58, gpio59, gpio60, gpio61, gpio62, gpio63, + gpio64, gpio65, gpio66, gpio67, gpio68, gpio69, gpio70, + gpio71, gpio72, gpio73, gpio74, gpio75, gpio76, gpio77, + gpio78, gpio79, gpio80, gpio81, gpio82, gpio83, gpio84, + gpio85, gpio86, gpio87, gpio88, gpio89, gpio90, gpio91, + gpio92, gpio93, gpio94, gpio95, gpio96, gpio97, gpio98, + gpio99, gpio100, gpio101, gpio102, gpio103, gpio104, + gpio105, gpio106, gpio107, gpio108, gpio109, gpio110, + gpio111, gpio112, gpio113, gpio114, gpio115, gpio116, + gpio117, gpio118, gpio119, gpio120, gpio121, gpio122, + gpio123, gpio124, gpio125, gpio126, gpio127 ] + + input-debounce: true + phandle: true + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH + 5 IRQ_TYPE_LEVEL_HIGH>; + rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinctrl_uid: uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + }; + };