From patchwork Wed Jun 2 12:03:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=K9P2/iiJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw73r1P7hz9sRN for ; Wed, 2 Jun 2021 22:04:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229629AbhFBMFt (ORCPT ); Wed, 2 Jun 2021 08:05:49 -0400 Received: from mout.gmx.net ([212.227.15.19]:60887 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbhFBMFs (ORCPT ); Wed, 2 Jun 2021 08:05:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635438; bh=ulkox2ATtAdbPPOEglhjZ3k4awk0Qn6kCKCuSyogJsg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=K9P2/iiJ8mYXqb6G1z6NNuVrNUt+HE9psjOZYpmr3urD1/0e0RaNNmAgueu0qsB/Z S3aCO0brAdmcbqKJP458JzShSTehbTDheQmamWMwS49h4WHIGOpEaPqK1RVmO+4GnX UMekteulEDUKahAx5RpVtMaJ36baq9S/dnPK8uIU= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M4JmN-1lo8UB1zbV-000JWu; Wed, 02 Jun 2021 14:03:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Subject: [PATCH 1/8] dt-bindings: arm/npcm: Add binding for global control registers (GCR) Date: Wed, 2 Jun 2021 14:03:22 +0200 Message-Id: <20210602120329.2444672-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:P9ooxxcBWMlue7/aQhsUzie0pEsU417A/bVW+i8qKslDKwe1yoF P0JJK2l+NChG9mUbWE+NUkp8CPJhowOqBbLu2w/eaW939P6xr6+2y6PIp4vGMbzsl/BUcJN rMq74FWAWY9dkqJGs2YCx4c41ickvdnrLbxFpIpY/q8mshEtXf2n4OTzR+tXxZJr7tsvS5A AKeJHK9vJLxE9lAXxDQ3A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:RLLVYPBzafk=:/20tEdy806+Ejjw719ZFcz 0RWaQ1HFc0WDKSSe0h+4TdP9N4RPrdOqkbNoE2k3uDdWC902rmq1iIxlQmg42UGTK1QvhlOZQ U3cVOGv793QjyKN6j4O5iZPmw1kX5yZK6ap1BqzbRLw+FVtQL/k3U1Cmp7DRtoD7K273XpK1k hzK1LZ+LQZBuYMg+wA2t1zBjBIPl9/apzPI9eBTE7kk8MbaaWwSmhPj5xbZG7QypKCsNOkjWx KKQ7j4CVTIV0ZXiwIN080YfDqumtQcX+JTdA22FP15if3vtF4ApDFB1u2SeDF40zio0lU9O9U 1eHi7438pXfh6tbVcxCrnu7hCpyG9d6j/02uBksNZ9eZZ6nqKyCQd+XM1v6yr7w3Y53m9bej6 Q/CTI+GFT3QVyxW+gzcbSmz6Ie4SnSfPqXtZEKmB9AD5aSDbX3iXGThvRk6Fv18qJKxMOFqI5 /cKJbrsYKdSdzgUqZ5a07L1bTOvIZn0nagiTbGA9bXlVj0PJTS5zrchEDRHj8flqcPNSI+u9J keKRkx/JFGOFvBJnOKRfIemRKmlM6hi5r/0e2aaIK38LxbMGEpaUnqryS8uN9pNs0PL6JER6t /dIdK8CESVN0V3SoHH3YMTkSjX4rh/dW6dLPceRVQOp5XwIzqh9ALfvAVwEbK+BRBndHcjbcD sKRjCGEs2iHvcbE5s9Lfbe28jo7S2NJJ5uhbOAZwypoy+mI5SmPU0pDJ9wCbnTYuVutrmBA32 ROYNca/CU9tVdkWYAGBBm08zBqgp/2IHO7tm2fvxM8qaWrT5gHyb2EbXmlldBrZyA2IgtmnlQ mUKi/WQWmFIkCl0XRt3W91kg3OeetOfnuVI8WXcVYdjay2PWr6HTi8cdkU3LMkDQted1qIOCA UURXyVUa14Qt05E/3eFYciteZjmrBzcjztF/42cMhzMnoRzcmmQeAHXPcbi2w/s816hMrwOZO I2KqYlCygdaGUkTDjjNS+SuzPlYuMEKlECDp2ooRj0XBNgAahY6SL19sOxKbx3nvCAz4W1XcJ pViyEalQV50cYxlgpqMyrR5ewKiimluVo8GLJ92bq1WDL8wdcrwUhov75iu6y1Hp0sLcf7ySY aonN8995GNifEwlE/ukzJo8huXbaWjGUXxL+2LvloRnMjf0tf+AXHRW/w== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Linus Walleij --- .../bindings/arm/npcm/nuvoton,gcr.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 0000000000000..3174279f7713a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: | + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + reg: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + }; From patchwork Wed Jun 2 12:03:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486638 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=Vu/c0Q1j; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw73r6RM8z9sRN for ; Wed, 2 Jun 2021 22:04:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229665AbhFBMFu (ORCPT ); Wed, 2 Jun 2021 08:05:50 -0400 Received: from mout.gmx.net ([212.227.17.20]:40551 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229620AbhFBMFt (ORCPT ); Wed, 2 Jun 2021 08:05:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635441; bh=UF4oW0j3C0UfuvEjFkldudNhDCIgYlLwBeW1fCc59U8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Vu/c0Q1jEq9mvmdEVuB62V2tyhqqTqPiKlmAAqFoqUsVPcRgeb0COHeJf7Z/x7wlJ LkysuI2THlyzWOR/wxIZZkwtkjOkOvbaBGFiw2DzGTs2WlpbWkNhyaMxlDkLvGfhfn +/mXK2U2WOam9hcuyzG6Vu41ucq6915sbnqdv5Fo= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MmULx-1l6F0r39px-00iTnv; Wed, 02 Jun 2021 14:04:00 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 2/8] MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM architecture Date: Wed, 2 Jun 2021 14:03:23 +0200 Message-Id: <20210602120329.2444672-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:pj/CAwCpQfjiqJUIRfxtRexDjyawbqBoG1pzwcUmblWyiF1GJF8 VOkUSCbeMuJ3GvXWqH+/U630vfzhMbRvktMv7XAbWeEFTCIdjw+z9+U4/seMg4zyx8j/Sdb ofHNkyR+Wx7ARPFOgix4UPL0vJzKKhCYBmGs+rI2bfAOeAsFnbZgb7GQ98l/ViUodx/rMnm BobamMkegklHiS3ZbSq/Q== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:m5wUD4NWZjU=:wJrbsrF1KVy38/aR2Yf5XW Bmpuw7Y9s3OJPT9BnLE/c08gZDRYLo60hnUPUwFrcPu6gdSwtfrsc8KtqMfAgF3hi0qaG4xQx gl9cRVcVGp8BtnZFaFmdHNpWAb0i+PA0Ix4HBM8qfnFUyyoo+wz1iPErSYP9XgubGBj8uX8qe OJIor/UQrccUrqpWw3GfgPRBj38oCrIvkRVsfhAQ0Oe96Zzw5hqOB6l9xpHVpRVCZsJysRotJ f1ZzEZcHmZraJweGkVpjVqfSOzGrOcQV+mFRGsXtGdQqyB/PaQZxzxceLp/g0mUAUVuxUA84a 2FEFj1a9JRr1UMDzLhO32bONaaxolvPivbZrO8uwa2b/sPkXQUh6iZ8Nk6FPQFLg808Epm1+q rdXoqU/vln8wbz2/cDEn3AvpFWgJv81m6TGcGnnfwH94FZq4dDu4602aQQQo+S6u/40LQEWNY /w5nyNDdA9KzpI9UpiCWvJihGn8cODg3bP6bLBE4r+HAfU9MUaeJUlY+Vo3h8E4CsNfIzluMF FuUXmTs2ygZwlQ0/8Pi/kze9DyunXPN+KyV1+vM/LblDsv0eii8mYtNYD3QapWgALL8kVZoXP Xeggv5Z7wqd0OEY9MUv0G2cJZp1u0+Vo3JdR44bgqBToPwfcspkqEgVJfcNY9aOP0jcrKngeY 53Lavzrh1o8yH3EyVkiJMebTfreED58WMm1ejA5x4Cfw2Ltm95Y17JPHlwRBNBL99j4pzTDLC 5dA5btQWbw/txARQ5rsN/rWgyYPxhkdVkj5Upkp9d6AuNRndi2bz6eNjsnJJRSM6CFYJlXT/R m5+9WoHpy/VdREHx7bRIwZaesEpUbNz/hUNk4KPphll/exb5tDuH2WBnKA1Uaz7iWu2gaeRr4 3QsqgVFktlTVzB0fuUifC2gvJ6NIBHpIGv2y3vxHhiVtHwg7a8ufFCawUOXrpskddhR11TbNL fAXh9WoGHkHvIQ3WcfNasgrLa+6OnNRXASZUP6LL21YszhZU35w34pERYP9tfrkOGxTd6dG/W /neDy5Dd1q2AGGSBoHM9PtrTu3oU7lNaKhJb3z7pNzHEerALsp6i9CgdSlTX89xXcNeQ2yuQi lMCRQMogNJlbHLzRh9pf9AVNiSW9rW8kj5TA6Nn2e4IYorQTyA4LchNuA== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org All files in Documentation/devicetree/bindings/arm/npcm/ belong to the Nuvoton NPCM architecture, even when their names might not spell it out explicitly. Signed-off-by: Jonathan Neuschäfer --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/MAINTAINERS b/MAINTAINERS index 79fb23f576218..288d6a1f2bb1f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2220,6 +2220,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* +F: Documentation/devicetree/bindings/arm/npcm/* F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* From patchwork Wed Jun 2 12:03:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486639 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=GClIPpgJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw73t4T48z9sCD for ; Wed, 2 Jun 2021 22:04:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229697AbhFBMFv (ORCPT ); Wed, 2 Jun 2021 08:05:51 -0400 Received: from mout.gmx.net ([212.227.15.19]:38451 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229647AbhFBMFu (ORCPT ); Wed, 2 Jun 2021 08:05:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635443; bh=ooaky4yb4fR/kpe3fOFHpn9arD6FeYQatJSIhw5he0s=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=GClIPpgJ0ZLEA9aC+vCZiiyrCO5GtyVpu+xXmWOhS9NAtXU7OvKfE0D7YCi1gRZ3N X92fr79GIlF9QKecaqpBZN536OQWO8wwsz2qsHm60LgpCAFrtiboAbHI0u6VyR9zh6 qBU9gd2MrMteLaoBvP0RD4543tt7OvlRpJ6GU8Cw= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MbRfv-1lHHdz3z6v-00br0D; Wed, 02 Jun 2021 14:04:03 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node Date: Wed, 2 Jun 2021 14:03:24 +0200 Message-Id: <20210602120329.2444672-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Av8Q5qyp7UJ+jpsh6te2UQ1HIlwipslvwhbsf5scacg5mpU7ugo GjVhdMGeX5/oKg7lgaQZ58rMJF4KERTu26vyv0BIxA1DANjLu+HtbOt6pT2ZCJ/w+rqes8/ 4I4bKBia4jJNEs3WPo8js8K8rHZlvX5QU+TRsyiGDFfJ73O79WnifVfDu1FxDYvEAo8GEhl lrcuQFljQjozDVB6QI+Ag== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:iDdL61byTUU=:BF2kGh65FVUlT3+OTNuBh+ ofYPsioYmQWuFnCByVavoxtYB/7LXBj8Oe7byeXgg2oCaE+jgJuErwY7VBpwDCYldHdCJjDOT cif4cy50TklukqDNHUBDWdVv8UrC6KMKxUQnE6Sxhtn8NRpoefmj3FJmCudbMJrotvI19G/Pm ApXZ7ysdvzRls7WZYHbejVTC2nCxNI/Jtsjz4KsgUARmolmYlPjaeYk5WwCPvT/1RdtpcTSR2 xGm6MstAYo3+/s8/rqONMERXK4qxG3HRJb+u59CPh7Xml+8AFskpC6u7SuJtF8/sbW4CSVAi2 gTW+Anthk2RBjgcldvRLe0AE6NXONIQCP7s57fB+JPbLMgyp/sv9wlXnR0pDOD/6lpH0PQNgI KLn63SJM9cjBcKKqJCA6QErisCtwrUBzY6Fxh8+gwfY1LlKznVAdZOEZZ7VyYSr8xeHWBJdIx pZRz7V9j7wG8KUZF3FG3Wzi7bw8vsf6baDtVcnxnhjX2RBQz8auUtdAWdNq06vNyeFlBX3vO7 6WzPSD/QmL3x8/yTam788m5rfB2LpJC7vhwEuYAYeRlzu/BMwROsxBC30yVLUtPZzgGcRDs6A 0WsIzneSwjAFr4piCxFyhtLqt0H3rnNwaTSAYWltDOMH39duRg0mkQ1/b7GFAdzra5BJzv/IR xtdPctf86wdPYq8ed7vrflO3Q09rYgOb1BqIaH1zR74zzArRLZX8YCC91F7c5H+/qS+b6G4i8 EQqEeNBpZxonUgQV0WOiP1dIxuPwjc6omQOxw51enRsVs9ufk848PbiWaUWFjqhU5S8A6Ev4G eEtgX3M6XMEUkVnY8CMmEnrg9Qga+sNDL76gYv3PZ+Mu+xNdQstGyAuBpc2i9rVQX4OeJ0iUz wQx+L625eefk/AjYw7HMR2BDm4r4+T7CFtUAxuC31llFUrr6bYxZFGiM0gireKbezyLtg9rRE EQxHGv69Iyrh1UXCvUbsw2DGFebPBsJR8LzusFgHLwoo6tooxU5Yj3O2UaaWNQqTb6zy00PUM 33H33QFDZpynA7g+uOwIEKi+5LKdXEZO3eIH6v4gX6BzYnVy6snRWs1XI0NMQoxFMak6JQeiu D7vQiFvhaGHaJEZcqqf+c2HawC0oXpIVr9K0D2USpUKBqS6d/eZbEfhRw== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs that expose misc functionality such as chip model and version information or pinmux settings. This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for enabling pinctrl on this SoC. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb1874840..8eba4897b41bc 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -33,6 +33,11 @@ soc { interrupt-parent = <&aic>; ranges; + gcr: gcr@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Wed Jun 2 12:03:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=XEpTcTJK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74168Jhz9sCD for ; Wed, 2 Jun 2021 22:04:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229791AbhFBMF4 (ORCPT ); Wed, 2 Jun 2021 08:05:56 -0400 Received: from mout.gmx.net ([212.227.15.19]:55387 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbhFBMFz (ORCPT ); Wed, 2 Jun 2021 08:05:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635447; bh=2ut7fjvCRXp1vUUCh5jcJNV1bWQfWdPByri+EnaApG4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XEpTcTJKIpUmN+jRuMfsthO1SugHY9sL+kIJZWtp+JUGmd5BVuB9nqyW9WzrGlKzB jiruRmE73d3tzDqcA68xNJ6S2GSuqrzIFzJcArEYPnKV3/CvbNnChW7guzOSLJlciQ pV+nHz+yVNqQqFaEG9QMWLylQNf8BKOfoF0n38ME= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M5fIW-1lleRh0AGI-007Eso; Wed, 02 Jun 2021 14:04:07 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 4/8] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Wed, 2 Jun 2021 14:03:25 +0200 Message-Id: <20210602120329.2444672-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:E6+ZEj70X9yV7fiuKCDzxr1LhJdKjksAzp/xm8VL+BUlNTseNAy okeguoiss3CzSzhZbxUI/g8cehAHeD7BYclX1esdvc/7SzljFeMilw82uESa2irNjwShC6Q +ga7VcY3dY3MetH3iuAhMK8bWENWkzICY+Gglqp5UWPQ1qs5H/lemP4T9TStx+g0Oqy9QPw WhabaSlPxi7wEN+qX+qbw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:l4v+Hockw6I=:sOCxMcqqcQryI1ft9be5w1 JYsHx3jlluDR2PiCP7kBlHApH55MTdTHpTgE/+5RrRTb6JVeSL+Jp4pfRzlc7w8IJ1xj1KqGc RyKzrHax0LTh5qyf5qaM9fmwbjk0J1oO1ZnoZO8BdULLZYnZUte6RkifQtos1+qThbpzLpn7e UIQqUiIFRi+QqRUOeRsNuBqKgmZRtDNleM8P9KriRfsdsOJN+BWA0GFvUjdIASn9EAAWvtmjS FauoUBzK1Wh0Y85GC/4uLg7QonpojwChodBI5wW7XzKwMxhj7j5hV3vIoebP8H+S5BL0PzIcP 4lMJO0Lr+XlUGrAiCkjNl4odHDweti/2B56O9T3WV8klgPuaCfc+Q+HCePVKeIREQy7AA6WyX NeA5iTyVYcBcsZ+yRVtd9ZDVIAf5P4MRrxF+dc2bQwRfUNhtef9eDmH44HNid9jNkFE39XWyM 7aJybtk2rc3y/TceTbOIWUHriypazDKwZKP1zigqsguajAzzTGJyM68luKZ9PNXlXHHzfY2Gl sB37k7bMm6RidcaeqyE5IuGvX30ZRs/visWcYp6djR9Ukc5Nltdgn5ToHsihRXZIWZz0PV+zP GhBvTxpwIoQlM18YczB5ZUNsnKGYVqH231qfT/hEsvAGfeuZWd+nhK3cvK0QVvu7BQbjwXcSs MDfMhPSkDaHUzIip+1q5vk/krtu9j32+0rwjkvrL4IagrzcVf7bBYf396cJxZsi2c26sRdbAK Tl6x33itHEJuwNW4iyfwLxrvTaGWUWnzadcwnW7WIsG5IxWqzBn/rLMzrcPM84Xnicb1ZoTJq pxZJ9+2N/bNjxCT8qOvJJMgREOFfCHE+3mffre+XfPnc33wA0yphDsu0pMgFOtuDZlRDFHL6l B+kTUiwfU2pfIaFRn2CUPx6883svpHQxJKoAXLKC6ggyefvjZKw+2UipuppqASeUW0wtYBMOk d5Z8HPxwh0jTQjD6/VHOxEYvHHy4mAkdqKudExmYssz4JjhPIFYtg/k0+trb34FofblfbQWdx mE9wNCNMa3h37GjVSTh1lKdxr5/9lkciOMcq7PYBRwa/0DFDc4siZAfPr5WEfwWDq8Oo0Sl3Z Yh/OnC9cU5KIiBsTASd8G/0i0cLNXwf0t31bYGp9H1ygXMX+TSaGBFKRw== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This binding is heavily based on the one for NPCM7xx, because the hardware is similar. One notable difference is that there are no sub-nodes for GPIO banks, because the GPIO registers are arranged differently. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..0664fe2b90db6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: "nuvoton,wpcm450-pinctrl" + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: true + +patternProperties: + # There are two kinds of subnodes: + # 1. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 2. a pinctrl node configures properties of a single pin + "^.*$": + if: + type: object + then: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + groups: + description: + One or more groups of pins to mux to a certain function + minItems: 1 + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7 ] + + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + minItems: 1 + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, gpio42, + gpio43, gpio44, gpio45, gpio46, gpio47, gpio48, gpio49, + gpio50, gpio51, gpio52, gpio53, gpio54, gpio55, gpio56, + gpio57, gpio58, gpio59, gpio60, gpio61, gpio62, gpio63, + gpio64, gpio65, gpio66, gpio67, gpio68, gpio69, gpio70, + gpio71, gpio72, gpio73, gpio74, gpio75, gpio76, gpio77, + gpio78, gpio79, gpio80, gpio81, gpio82, gpio83, gpio84, + gpio85, gpio86, gpio87, gpio88, gpio89, gpio90, gpio91, + gpio92, gpio93, gpio94, gpio95, gpio96, gpio97, gpio98, + gpio99, gpio100, gpio101, gpio102, gpio103, gpio104, + gpio105, gpio106, gpio107, gpio108, gpio109, gpio110, + gpio111, gpio112, gpio113, gpio114, gpio115, gpio116, + gpio117, gpio118, gpio119, gpio120, gpio121, gpio122, + gpio123, gpio124, gpio125, gpio126, gpio127 ] + + input-debounce: true + phandle: true + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH + 5 IRQ_TYPE_LEVEL_HIGH>; + rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinctrl_uid: uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + }; + }; From patchwork Wed Jun 2 12:03:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=HWfcmdTM; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74M4gnVz9sCD for ; Wed, 2 Jun 2021 22:04:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229864AbhFBMGR (ORCPT ); Wed, 2 Jun 2021 08:06:17 -0400 Received: from mout.gmx.net ([212.227.17.21]:33839 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbhFBMGI (ORCPT ); Wed, 2 Jun 2021 08:06:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635459; bh=TxtfSDMLNFFf8ldarAaJeXA4+LdSNvHs0jsm8fwboYs=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=HWfcmdTMO2lehw1pP5Uu8sSj0KgTE6y+XHWZDxaneooliRsnBGJ8Uy92ziVXTtkau DmaGEYPypDE3O38+GcLjNfA+DyXJhlvZsgMaNqzXi4CJRMxjZ3rXcNgE01U1ow9wi0 8N9Xw6tBkfbJfTKNfTfrCfHeB7MRsonQHJVvfgBc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MJVDM-1m89Nr2JCa-00JowD; Wed, 02 Jun 2021 14:04:19 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 5/8] pinctrl: nuvoton: Add driver for WPCM450 Date: Wed, 2 Jun 2021 14:03:26 +0200 Message-Id: <20210602120329.2444672-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:P2sYVdgQ5rW9AWdZCfzAvOSh3TbzGQARuGJ9rR/itlbTdgpyf8M CQz9HpHc19+oWFDhpCAQ/obp2iYzh7teUaL+Y9TdRJNSBvOvmO2L2A3cjkhD/d03lLKpRjV 4GwjJUtXILLQL7rWn/ohlYvusHSjhFuXCm5AuvZ0TBybovEWUQE0IIyf4zIBldH848PY0Ke dXibSt6LsnmTc9ykhGQ+Q== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:kFuo5m62728=:muCrb77NFwspd1n3NtrzWG tjKoFL4K+WGnejbggk4kZ8wjfl29cT0wHmFYP0veuUz4iFD+LTEjS1x7kpJ6VxdoFiNCEgC/y GWShGQYln9lyPSQZE8LA5SuXcL6qpisk8chmAtykSg/n3Y2D8mE9/Hm9wSTAYam9b+k90RGGE uwynmSgBv/jnat+6NTcsS/wccD4TfeRX0dEsr/mqZmF5eqj0TWvbczvgJGK8amHsAAejPWaT8 5c1cf/Edqu/Dh/9pNFViOXanqxAHXxNmInmoWgRfHER3rPbqww0wJhAUm+lV0vGnQOJoyuPr8 +qC1wJwnci7zmNWXhjj4fDhZK4Bm2NuEfQ2C0rIXwufSAHOJ3sKF1tp6a8BKzE/QaKSI/oXjT I6XiPsxyefPV6XfOW5dK334+O7SYyVoQv6VHLFHxARGZReNp3lO25jtjL1yTmzeAI2Lp9Tro6 CLi62RpGj2dmilGYlpa7PjzodNTy1woV4ECyJ1LNgPulDZfDfvw4HC2+zhe5MIXQ2LkIV3HYV uw5EztXXoTWJ9/JeCElet3wakOt/kUwH6G5r9LMpv8VoZAMYq7/yCAR67wkcQyL1/+x+mcWko SpRvyMuzyJIbpkxcxu4UGMS0UCaYH/xNRFPj4t6foFPgxeV+jxSGkxfLFmq19ULjZgP1ma8Vn IwSEA5dJjHZcYxu/HKFqWqwJxemV2tSi3sFpnh2U/IxwW9NTH/c1nq7m7nufXim4Dm7FszFMz KVywy9T5TxEOy7U41yO31fh0/9cs96eDrlpxjuXZa/Nr8nGj8GN3LnwbtpE79g7bfBZE+4+wI gF+2T+yDn7NqFYqWBXZcIaju4q2w0zAoGww863YwOBx/S622georij83fQaeojw20mZNl+Rwk KvLQADI8Rmkz5Ux2FJ0/NZzUb/r6G2uvu2UZUBsyqzIIXcE7m8mIl1qq5bd3Zh+Epialx5+x+ Q3g+fhsnXnq7C+oI6F9E2h+vVFFiIlagVtl8UkS1AnvljMaCJm9ciRFzpgIYmcDIqpLPz1/SL zXomMo3pXkHyvZKv+vfSwJ4GCQD3VvUyHHxltZ/2qM4sz0cd99+G1BhlWBOddzcopSp2ayGBq r1soBb5gLJuGb4jl9ZCTwW/5SjXYsynaiWrs+hNpT0zz4FYq4wIA1/YDg== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This driver is heavily based on the one for NPCM7xx, because the WPCM450 is a predecessor of those SoCs. The biggest difference is in how the GPIO controller works. In the WPCM450, the GPIO registers are not organized in multiple banks, but rather placed continually into the same register block, and the driver reflects this. Some functionality implemented in the hardware was (for now) left unused in the driver, specifically blinking and pull-up/down. Signed-off-by: Jonathan Neuschäfer Reported-by: kernel test robot Reported-by: kernel test robot --- This patch has a few checkpatch warnings, which are inherited from the pinctrl-npcm7xx driver. I decided to ignore those. Specifically: (1) the Kconfig help text is considered too short; (2) WPCM450_GRPS is an unwrapped list; (3) use of -ENOTSUPP is discouraged. --- MAINTAINERS | 1 + drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/nuvoton/Kconfig | 14 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 1230 +++++++++++++++++++++ 5 files changed, 1247 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c -- 2.30.2 diff --git a/MAINTAINERS b/MAINTAINERS index 288d6a1f2bb1f..ca5cb7f94b115 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2234,6 +2234,7 @@ S: Maintained F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c +F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 5ef5334a797fc..e355c78eecd58 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -56,7 +56,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ -obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_RALINK) += ralink/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig index 48ba0469edda6..f15d345b90083 100644 --- a/drivers/pinctrl/nuvoton/Kconfig +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -1,4 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_WPCM450 + bool "Pinctrl and GPIO driver for Nuvoton WPCM450" + depends on (ARCH_WPCM450 || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for the Nuvoton WPCM450 SoC. + config PINCTRL_NPCM7XX bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile index 886d00784cef5..9e66f5dc74bfc 100644 --- a/drivers/pinctrl/nuvoton/Makefile +++ b/drivers/pinctrl/nuvoton/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 # Nuvoton pinctrl support +obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c new file mode 100644 index 0000000000000..b978b315ffc68 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -0,0 +1,1230 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc +// Copyright (c) 2021 Jonathan Neuschäfer + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define WPCM450_GCR_MFSEL1 0x0C +#define WPCM450_GCR_MFSEL2 0x10 +#define WPCM450_GCR_NONE 0 + +/* GPIO event (interrupt) registers */ +#define WPCM450_GPEVTYPE 0x00 +#define WPCM450_GPEVPOL 0x04 +#define WPCM450_GPEVDBNC 0x08 +#define WPCM450_GPEVEN 0x0c +#define WPCM450_GPEVST 0x10 + +#define WPCM450_NUM_PORTS 8 +#define WPCM450_NUM_GPIOS 128 +#define WPCM450_NUM_GPIO_IRQS 4 + +struct wpcm450_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + struct irq_domain *domain; + struct regmap *gcr_regmap; + + void __iomem *gpio_base; + struct gpio_chip gc; + struct irq_chip irqc; + u32 both_edges; + + /* + * This spinlock protects registers and struct wpcm450_pinctrl fields + * against concurrent access. + */ + spinlock_t lock; +}; + +struct wpcm450_port { + /* Range of GPIOs in this port */ + u8 base; + u8 length; + + /* Register offsets (0 = register doesn't exist in this port) */ + u8 cfg0, cfg1, cfg2; + u8 blink; + u8 dataout, datain; +}; + +static const struct wpcm450_port wpcm450_ports[WPCM450_NUM_PORTS] = { + /* range cfg0 cfg1 cfg2 blink out in */ + { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20 }, + { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38 }, + { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c }, + { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60 }, + { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74 }, + { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88 }, + { 96, 18, 0, 0, 0, 0, 0, 0x8c }, + { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0 }, +}; + +static const struct wpcm450_port *to_port(int offset) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wpcm450_ports); i++) + if (offset >= wpcm450_ports[i].base && + offset - wpcm450_ports[i].base < wpcm450_ports[i].length) + return &wpcm450_ports[i]; + return NULL; +} + +static u32 port_mask(const struct wpcm450_port *port, int offset) +{ + return BIT(offset - port->base); +} + +/* GPIO handling in the pinctrl driver */ + +static int wpcm450_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(chip); + const struct wpcm450_port *port = to_port(offset); + unsigned long flags; + u32 cfg0; + int dir; + + spin_lock_irqsave(&pctrl->lock, flags); + if (port->cfg0) { + cfg0 = ioread32(pctrl->gpio_base + port->cfg0); + dir = !(cfg0 & port_mask(port, offset)); + } else { + /* If cfg0 is unavailable, the GPIO is always an input */ + dir = 1; + } + spin_unlock_irqrestore(&pctrl->lock, flags); + return dir; +} + +static int wpcm450_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(chip); + const struct wpcm450_port *port = to_port(offset); + unsigned long flags; + u32 cfg0; + + spin_lock_irqsave(&pctrl->lock, flags); + if (port->cfg0) { + cfg0 = ioread32(pctrl->gpio_base + port->cfg0); + cfg0 &= ~port_mask(port, offset); + iowrite32(cfg0, pctrl->gpio_base + port->cfg0); + } + spin_unlock_irqrestore(&pctrl->lock, flags); + return 0; +} + +static int wpcm450_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(chip); + const struct wpcm450_port *port = to_port(offset); + unsigned long flags; + u32 dataout, cfg0; + int ret = 0; + + spin_lock_irqsave(&pctrl->lock, flags); + if (port->cfg0) { + /* set output value first, direction second, to avoid glitches */ + dataout = ioread32(pctrl->gpio_base + port->dataout); + if (value) + dataout |= port_mask(port, offset); + else + dataout &= ~port_mask(port, offset); + iowrite32(dataout, pctrl->gpio_base + port->dataout); + + cfg0 = ioread32(pctrl->gpio_base + port->cfg0); + cfg0 |= port_mask(port, offset); + iowrite32(cfg0, pctrl->gpio_base + port->cfg0); + } else { + ret = -EINVAL; + } + spin_unlock_irqrestore(&pctrl->lock, flags); + return ret; +} + +static int wpcm450_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(chip); + const struct wpcm450_port *port = to_port(offset); + unsigned long flags; + u32 datain; + + spin_lock_irqsave(&pctrl->lock, flags); + datain = ioread32(pctrl->gpio_base + port->datain); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return !!(datain & port_mask(port, offset)); +} + +static void wpcm450_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(chip); + const struct wpcm450_port *port = to_port(offset); + unsigned long flags; + u32 dataout; + + spin_lock_irqsave(&pctrl->lock, flags); + if (port->dataout) { + dataout = ioread32(pctrl->gpio_base + port->dataout); + if (value) + dataout |= port_mask(port, offset); + else + dataout &= ~port_mask(port, offset); + iowrite32(dataout, pctrl->gpio_base + port->dataout); + } + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +/* Interrupt support */ + +static int event_bitmask(int gpio) +{ + if (gpio >= 0 && gpio < 16) + return BIT(gpio); + if (gpio == 24 || gpio == 25) + return BIT(gpio - 8); + return -EINVAL; +} + +static int event_bitnum_to_gpio(int num) +{ + if (num >= 0 && num < 16) + return num; + if (num == 16 || num == 17) + return num + 8; + return -EINVAL; +} + +static void wpcm450_gpio_irq_ack(struct irq_data *d) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + int mask = event_bitmask(d->hwirq); + unsigned long flags; + + if (mask < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + iowrite32(mask, pctrl->gpio_base + WPCM450_GPEVST); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_mask(struct irq_data *d) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + int mask = event_bitmask(d->hwirq); + unsigned long flags; + u32 even; + + if (mask < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + even &= ~mask; + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_unmask(struct irq_data *d) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + int mask = event_bitmask(d->hwirq); + unsigned long flags; + u32 even; + + if (mask < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + even |= mask; + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_fix_evpol(struct wpcm450_pinctrl *pctrl, unsigned long all) +{ + int bitnum; + + for_each_set_bit(bitnum, &all, 32) { + int gpio = event_bitnum_to_gpio(bitnum); + u32 mask = BIT(bitnum), evpol; + int level; + + do { + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + level = wpcm450_gpio_get(&pctrl->gc, gpio); + + /* Switch event polarity to the opposite of the current level */ + if (level) + evpol &= ~mask; + else + evpol |= mask; + + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + } while (wpcm450_gpio_get(&pctrl->gc, gpio) != level); + } +} + +static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + int mask = event_bitmask(d->hwirq); + unsigned long flags; + u32 evtype, evpol; + int ret = 0; + + if (mask < 0) + return mask; + + spin_lock_irqsave(&pctrl->lock, flags); + evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + pctrl->both_edges &= ~mask; + switch (flow_type) { + case IRQ_TYPE_LEVEL_LOW: + evtype |= mask; + evpol &= ~mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + evtype |= mask; + evpol |= mask; + break; + case IRQ_TYPE_EDGE_FALLING: + evtype &= ~mask; + evpol &= ~mask; + break; + case IRQ_TYPE_EDGE_RISING: + evtype &= ~mask; + evpol |= mask; + break; + case IRQ_TYPE_EDGE_BOTH: + evtype &= ~mask; + pctrl->both_edges |= mask; + break; + default: + ret = -EINVAL; + } + iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + + /* clear the event status for good measure */ + iowrite32(mask, pctrl->gpio_base + WPCM450_GPEVST); + + /* fix event polarity after clearing event status */ + wpcm450_gpio_fix_evpol(pctrl, mask); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return ret; +} + +static const struct irq_chip wpcm450_gpio_irqchip = { + .name = "WPCM450-GPIO-IRQ", + .irq_ack = wpcm450_gpio_irq_ack, + .irq_unmask = wpcm450_gpio_irq_unmask, + .irq_mask = wpcm450_gpio_irq_mask, + .irq_set_type = wpcm450_gpio_set_irq_type, +}; + +static void wpcm450_gpio_irqhandler(struct irq_desc *desc) +{ + struct wpcm450_pinctrl *pctrl = gpiochip_get_data(irq_desc_get_handler_data(desc)); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned long flags; + int bitnum; + + spin_lock_irqsave(&pctrl->lock, flags); + + pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST); + pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + + if (pending & pctrl->both_edges) + wpcm450_gpio_fix_evpol(pctrl, pending & pctrl->both_edges); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + chained_irq_enter(chip, desc); + for_each_set_bit(bitnum, &pending, 32) { + int gpio = event_bitnum_to_gpio(bitnum); + int irq = irq_find_mapping(pctrl->gc.irq.domain, gpio); + + generic_handle_irq(irq); + } + chained_irq_exit(chip, desc); +} + +/* pinmux handing */ + +static const int smb0_pins[] = { 115, 114 }; +static const int smb1_pins[] = { 117, 116 }; +static const int smb2_pins[] = { 119, 118 }; +static const int smb3_pins[] = { 30, 31 }; +static const int smb4_pins[] = { 28, 29 }; +static const int smb5_pins[] = { 26, 27 }; + +static const int scs1_pins[] = { 32 }; +static const int scs2_pins[] = { 33 }; +static const int scs3_pins[] = { 34 }; + +static const int bsp_pins[] = { 41, 42 }; +static const int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; +static const int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +static const int r1err_pins[] = { 56 }; +static const int r1md_pins[] = { 57, 58 }; +static const int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 }; +static const int r2err_pins[] = { 90 }; +static const int r2md_pins[] = { 91, 92 }; + +static const int kbcc_pins[] = { 94, 93 }; +static const int clko_pins[] = { 96 }; +static const int smi_pins[] = { 97 }; +static const int uinc_pins[] = { 19 }; +static const int mben_pins[] = {}; + +static const int gspi_pins[] = { 12, 13, 14, 15 }; +static const int sspi_pins[] = { 12, 13, 14, 15 }; + +static const int xcs1_pins[] = { 35 }; +static const int xcs2_pins[] = { 36 }; + +static const int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 }; + +static const int fi0_pins[] = { 64 }; +static const int fi1_pins[] = { 65 }; +static const int fi2_pins[] = { 66 }; +static const int fi3_pins[] = { 67 }; +static const int fi4_pins[] = { 68 }; +static const int fi5_pins[] = { 69 }; +static const int fi6_pins[] = { 70 }; +static const int fi7_pins[] = { 71 }; +static const int fi8_pins[] = { 72 }; +static const int fi9_pins[] = { 73 }; +static const int fi10_pins[] = { 74 }; +static const int fi11_pins[] = { 75 }; +static const int fi12_pins[] = { 76 }; +static const int fi13_pins[] = { 77 }; +static const int fi14_pins[] = { 78 }; +static const int fi15_pins[] = { 79 }; + +static const int pwm0_pins[] = { 80 }; +static const int pwm1_pins[] = { 81 }; +static const int pwm2_pins[] = { 82 }; +static const int pwm3_pins[] = { 83 }; +static const int pwm4_pins[] = { 20 }; +static const int pwm5_pins[] = { 21 }; +static const int pwm6_pins[] = { 16 }; +static const int pwm7_pins[] = { 17 }; + +static const int hg0_pins[] = { 20 }; +static const int hg1_pins[] = { 21 }; +static const int hg2_pins[] = { 22 }; +static const int hg3_pins[] = { 23 }; +static const int hg4_pins[] = { 24 }; +static const int hg5_pins[] = { 25 }; +static const int hg6_pins[] = { 59 }; +static const int hg7_pins[] = { 60 }; + +/* + * pin: name, number + * group: name, npins, pins + * function: name, ngroups, groups + */ +struct wpcm450_group { + const char *name; + const unsigned int *pins; + int npins; +}; + +#define WPCM450_GRPS \ + WPCM450_GRP(smb3), \ + WPCM450_GRP(smb4), \ + WPCM450_GRP(smb5), \ + WPCM450_GRP(scs1), \ + WPCM450_GRP(scs2), \ + WPCM450_GRP(scs3), \ + WPCM450_GRP(smb0), \ + WPCM450_GRP(smb1), \ + WPCM450_GRP(smb2), \ + WPCM450_GRP(bsp), \ + WPCM450_GRP(hsp1), \ + WPCM450_GRP(hsp2), \ + WPCM450_GRP(r1err), \ + WPCM450_GRP(r1md), \ + WPCM450_GRP(rmii2), \ + WPCM450_GRP(r2err), \ + WPCM450_GRP(r2md), \ + WPCM450_GRP(kbcc), \ + WPCM450_GRP(clko), \ + WPCM450_GRP(smi), \ + WPCM450_GRP(uinc), \ + WPCM450_GRP(gspi), \ + WPCM450_GRP(mben), \ + WPCM450_GRP(xcs2), \ + WPCM450_GRP(xcs1), \ + WPCM450_GRP(sdio), \ + WPCM450_GRP(sspi), \ + WPCM450_GRP(fi0), \ + WPCM450_GRP(fi1), \ + WPCM450_GRP(fi2), \ + WPCM450_GRP(fi3), \ + WPCM450_GRP(fi4), \ + WPCM450_GRP(fi5), \ + WPCM450_GRP(fi6), \ + WPCM450_GRP(fi7), \ + WPCM450_GRP(fi8), \ + WPCM450_GRP(fi9), \ + WPCM450_GRP(fi10), \ + WPCM450_GRP(fi11), \ + WPCM450_GRP(fi12), \ + WPCM450_GRP(fi13), \ + WPCM450_GRP(fi14), \ + WPCM450_GRP(fi15), \ + WPCM450_GRP(pwm0), \ + WPCM450_GRP(pwm1), \ + WPCM450_GRP(pwm2), \ + WPCM450_GRP(pwm3), \ + WPCM450_GRP(pwm4), \ + WPCM450_GRP(pwm5), \ + WPCM450_GRP(pwm6), \ + WPCM450_GRP(pwm7), \ + WPCM450_GRP(hg0), \ + WPCM450_GRP(hg1), \ + WPCM450_GRP(hg2), \ + WPCM450_GRP(hg3), \ + WPCM450_GRP(hg4), \ + WPCM450_GRP(hg5), \ + WPCM450_GRP(hg6), \ + WPCM450_GRP(hg7), \ + +enum { +#define WPCM450_GRP(x) fn_ ## x + WPCM450_GRPS + /* add placeholder for none/gpio */ + WPCM450_GRP(none), + WPCM450_GRP(gpio), +#undef WPCM450_GRP +}; + +static struct wpcm450_group wpcm450_groups[] = { +#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \ + .npins = ARRAY_SIZE(x ## _pins) } + WPCM450_GRPS +#undef WPCM450_GRP +}; + +#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) +#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct wpcm450_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +WPCM450_SFUNC(smb3); +WPCM450_SFUNC(smb4); +WPCM450_SFUNC(smb5); +WPCM450_SFUNC(scs1); +WPCM450_SFUNC(scs2); +WPCM450_SFUNC(scs3); +WPCM450_SFUNC(smb0); +WPCM450_SFUNC(smb1); +WPCM450_SFUNC(smb2); +WPCM450_SFUNC(bsp); +WPCM450_SFUNC(hsp1); +WPCM450_SFUNC(hsp2); +WPCM450_SFUNC(r1err); +WPCM450_SFUNC(r1md); +WPCM450_SFUNC(rmii2); +WPCM450_SFUNC(r2err); +WPCM450_SFUNC(r2md); +WPCM450_SFUNC(kbcc); +WPCM450_SFUNC(clko); +WPCM450_SFUNC(smi); +WPCM450_SFUNC(uinc); +WPCM450_SFUNC(gspi); +WPCM450_SFUNC(mben); +WPCM450_SFUNC(xcs2); +WPCM450_SFUNC(xcs1); +WPCM450_SFUNC(sdio); +WPCM450_SFUNC(sspi); +WPCM450_SFUNC(fi0); +WPCM450_SFUNC(fi1); +WPCM450_SFUNC(fi2); +WPCM450_SFUNC(fi3); +WPCM450_SFUNC(fi4); +WPCM450_SFUNC(fi5); +WPCM450_SFUNC(fi6); +WPCM450_SFUNC(fi7); +WPCM450_SFUNC(fi8); +WPCM450_SFUNC(fi9); +WPCM450_SFUNC(fi10); +WPCM450_SFUNC(fi11); +WPCM450_SFUNC(fi12); +WPCM450_SFUNC(fi13); +WPCM450_SFUNC(fi14); +WPCM450_SFUNC(fi15); +WPCM450_SFUNC(pwm0); +WPCM450_SFUNC(pwm1); +WPCM450_SFUNC(pwm2); +WPCM450_SFUNC(pwm3); +WPCM450_SFUNC(pwm4); +WPCM450_SFUNC(pwm5); +WPCM450_SFUNC(pwm6); +WPCM450_SFUNC(pwm7); +WPCM450_SFUNC(hg0); +WPCM450_SFUNC(hg1); +WPCM450_SFUNC(hg2); +WPCM450_SFUNC(hg3); +WPCM450_SFUNC(hg4); +WPCM450_SFUNC(hg5); +WPCM450_SFUNC(hg6); +WPCM450_SFUNC(hg7); + +/* Function names */ +static struct wpcm450_func wpcm450_funcs[] = { + WPCM450_MKFUNC(smb3), + WPCM450_MKFUNC(smb4), + WPCM450_MKFUNC(smb5), + WPCM450_MKFUNC(scs1), + WPCM450_MKFUNC(scs2), + WPCM450_MKFUNC(scs3), + WPCM450_MKFUNC(smb0), + WPCM450_MKFUNC(smb1), + WPCM450_MKFUNC(smb2), + WPCM450_MKFUNC(bsp), + WPCM450_MKFUNC(hsp1), + WPCM450_MKFUNC(hsp2), + WPCM450_MKFUNC(r1err), + WPCM450_MKFUNC(r1md), + WPCM450_MKFUNC(rmii2), + WPCM450_MKFUNC(r2err), + WPCM450_MKFUNC(r2md), + WPCM450_MKFUNC(kbcc), + WPCM450_MKFUNC(clko), + WPCM450_MKFUNC(smi), + WPCM450_MKFUNC(uinc), + WPCM450_MKFUNC(gspi), + WPCM450_MKFUNC(mben), + WPCM450_MKFUNC(xcs2), + WPCM450_MKFUNC(xcs1), + WPCM450_MKFUNC(sdio), + WPCM450_MKFUNC(sspi), + WPCM450_MKFUNC(fi0), + WPCM450_MKFUNC(fi1), + WPCM450_MKFUNC(fi2), + WPCM450_MKFUNC(fi3), + WPCM450_MKFUNC(fi4), + WPCM450_MKFUNC(fi5), + WPCM450_MKFUNC(fi6), + WPCM450_MKFUNC(fi7), + WPCM450_MKFUNC(fi8), + WPCM450_MKFUNC(fi9), + WPCM450_MKFUNC(fi10), + WPCM450_MKFUNC(fi11), + WPCM450_MKFUNC(fi12), + WPCM450_MKFUNC(fi13), + WPCM450_MKFUNC(fi14), + WPCM450_MKFUNC(fi15), + WPCM450_MKFUNC(pwm0), + WPCM450_MKFUNC(pwm1), + WPCM450_MKFUNC(pwm2), + WPCM450_MKFUNC(pwm3), + WPCM450_MKFUNC(pwm4), + WPCM450_MKFUNC(pwm5), + WPCM450_MKFUNC(pwm6), + WPCM450_MKFUNC(pwm7), + WPCM450_MKFUNC(hg0), + WPCM450_MKFUNC(hg1), + WPCM450_MKFUNC(hg2), + WPCM450_MKFUNC(hg3), + WPCM450_MKFUNC(hg4), + WPCM450_MKFUNC(hg5), + WPCM450_MKFUNC(hg6), + WPCM450_MKFUNC(hg7), +}; + +#define WPCM450_PINCFG(a, b, c, d, e, f, g) \ + [a] { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g } + +struct wpcm450_pincfg { + int fn0, reg0, bit0; + int fn1, reg1, bit1; +}; + +static const struct wpcm450_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 */ + WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30), + WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22), + WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23), + WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0), + WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20), + WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21), + WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0), + WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0), + WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0), + WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0), + WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0), + WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0), + + WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), + WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), + WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), + WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0), + WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0), + WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30), + WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0), + + WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0), + WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0), + WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0), + WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0), + WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0), + WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0), + WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0), + WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0), + WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0), + WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0), + WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0), + WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0), + WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0), + WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0), + WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0), + WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0), + WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0), + WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0), + WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0), + WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0), + WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), + WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), + + WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */ +}; + +#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n) + +static const struct pinctrl_pin_desc wpcm450_pins[] = { + WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3), + WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7), + WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11), + WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15), + WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19), + WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23), + WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27), + WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31), + WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35), + WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39), + WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43), + WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47), + WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51), + WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55), + WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59), + WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63), + WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67), + WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71), + WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75), + WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79), + WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83), + WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87), + WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91), + WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95), + WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99), + WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103), + WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107), + WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111), + WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115), + WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119), + WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123), + WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), +}; + +/* Enable mode in pin group */ +static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, + int npins, int mode) +{ + const struct wpcm450_pincfg *cfg; + int i; + + for (i = 0; i < npins; i++) { + cfg = &pincfg[pin[i]]; + if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode) { + if (cfg->reg0) + regmap_update_bits(gcr_regmap, cfg->reg0, + BIT(cfg->bit0), + (cfg->fn0 == mode) ? BIT(cfg->bit0) : 0); + if (cfg->reg1) + regmap_update_bits(gcr_regmap, cfg->reg1, + BIT(cfg->bit1), + (cfg->fn1 == mode) ? BIT(cfg->bit1) : 0); + } + } +} + +/* pinctrl_ops */ +static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct wpcm450_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + + dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(wpcm450_groups)); + return ARRAY_SIZE(wpcm450_groups); +} + +static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return wpcm450_groups[selector].name; +} + +static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + *npins = wpcm450_groups[selector].npins; + *pins = wpcm450_groups[selector].pins; + + return 0; +} + +static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + struct wpcm450_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + + dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); + return pinconf_generic_dt_node_to_map(pctldev, np_config, + map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops wpcm450_pinctrl_ops = { + .get_groups_count = wpcm450_get_groups_count, + .get_group_name = wpcm450_get_group_name, + .get_group_pins = wpcm450_get_group_pins, + .dt_node_to_map = wpcm450_dt_node_to_map, + .dt_free_map = wpcm450_dt_free_map, +}; + +/* pinmux_ops */ +static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_funcs); +} + +static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return wpcm450_funcs[function].name; +} + +static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + *ngroups = wpcm450_funcs[function].ngroups; + *groups = wpcm450_funcs[function].groups; + + return 0; +} + +static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct wpcm450_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + + dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, + wpcm450_groups[group].name); + + wpcm450_setfunc(npcm->gcr_regmap, wpcm450_groups[group].pins, + wpcm450_groups[group].npins, group); + + return 0; +} + +static int wpcm450_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct wpcm450_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + + if (!range) { + dev_err(npcm->dev, "invalid range\n"); + return -EINVAL; + } + if (!range->gc) { + dev_err(npcm->dev, "invalid gpiochip\n"); + return -EINVAL; + } + + wpcm450_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); + + return 0; +} + +/* Release GPIO back to pinctrl mode */ +static void wpcm450_gpio_request_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int virq; + + virq = irq_find_mapping(pctrl->domain, offset); + if (virq) + irq_dispose_mapping(virq); +} + +static const struct pinmux_ops wpcm450_pinmux_ops = { + .get_functions_count = wpcm450_get_functions_count, + .get_function_name = wpcm450_get_function_name, + .get_function_groups = wpcm450_get_function_groups, + .set_mux = wpcm450_pinmux_set_mux, + .gpio_request_enable = wpcm450_gpio_request_enable, + .gpio_disable_free = wpcm450_gpio_request_free, +}; + +/* pinconf_ops */ +static int debounce_bitmask(int gpio) +{ + if (gpio >= 0 && gpio < 16) + return BIT(gpio); + return -EINVAL; +} + +static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + int mask; + u32 reg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + mask = debounce_bitmask(pin); + if (mask < 0) + return mask; + + spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + spin_unlock_irqrestore(&pctrl->lock, flags); + + *config = pinconf_to_config_packed(param, !!(reg & mask)); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl, + unsigned int pin, unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + unsigned long flags; + int mask; + u32 reg; + int arg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + mask = event_bitmask(pin); + if (mask < 0) + return mask; + + arg = pinconf_to_config_argument(config); + + spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + if (arg) + reg |= mask; + else + reg &= ~mask; + iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +/* Set multiple configuration settings for a pin */ +static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int rc; + + while (num_configs--) { + rc = wpcm450_config_set_one(pctrl, pin, *configs++); + if (rc) + return rc; + } + + return 0; +} + +static const struct pinconf_ops wpcm450_pinconf_ops = { + .is_generic = true, + .pin_config_get = wpcm450_config_get, + .pin_config_set = wpcm450_config_set, +}; + +static struct pinctrl_desc wpcm450_pinctrl_desc = { + .name = "wpcm450-pinctrl", + .pins = wpcm450_pins, + .npins = ARRAY_SIZE(wpcm450_pins), + .pctlops = &wpcm450_pinctrl_ops, + .pmxops = &wpcm450_pinmux_ops, + .confops = &wpcm450_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int wpcm450_gpio_register(struct wpcm450_pinctrl *pctrl) +{ + struct device_node *np = pctrl->dev->of_node; + struct gpio_irq_chip *girq; + int ret; + int i; + + if (!of_find_property(np, "gpio-controller", NULL)) + return -ENODEV; + + pctrl->gpio_base = of_iomap(np, 0); + if (!pctrl->gpio_base) { + dev_err(pctrl->dev, "Resource fail for GPIO controller\n"); + return -ENOMEM; + } + + pctrl->gc.label = dev_name(pctrl->dev); + pctrl->gc.owner = THIS_MODULE; + pctrl->gc.parent = pctrl->dev; + + pctrl->gc.get_direction = wpcm450_gpio_get_direction; + pctrl->gc.direction_input = wpcm450_gpio_direction_input; + pctrl->gc.direction_output = wpcm450_gpio_direction_output; + pctrl->gc.get = wpcm450_gpio_get; + pctrl->gc.set = wpcm450_gpio_set; + + pctrl->gc.base = -1; + pctrl->gc.ngpio = WPCM450_NUM_GPIOS; + pctrl->gc.can_sleep = false; + + pctrl->irqc = wpcm450_gpio_irqchip; + girq = &pctrl->gc.irq; + girq->chip = &pctrl->irqc; + girq->parent_handler = wpcm450_gpio_irqhandler; + girq->num_parents = WPCM450_NUM_GPIO_IRQS; + girq->parents = devm_kcalloc(pctrl->dev, WPCM450_NUM_GPIO_IRQS, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + + for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) { + int irq = irq_of_parse_and_map(np, i); + + if (irq < 0) { + dev_err(pctrl->dev, "No IRQ for GPIO controller\n"); + return irq; + } + girq->parents[i] = irq; + } + + ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->gc, pctrl); + if (ret) { + dev_err(pctrl->dev, "Failed to add GPIO chip: %d\n", ret); + return ret; + } + + return 0; +} + +static int wpcm450_pinctrl_probe(struct platform_device *pdev) +{ + struct wpcm450_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + spin_lock_init(&pctrl->lock); + dev_set_drvdata(&pdev->dev, pctrl); + + pctrl->gcr_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); + if (IS_ERR(pctrl->gcr_regmap)) { + dev_err(pctrl->dev, "didn't find nuvoton,wpcm450-gcr\n"); + return PTR_ERR(pctrl->gcr_regmap); + } + + pctrl->pctldev = devm_pinctrl_register(&pdev->dev, + &wpcm450_pinctrl_desc, pctrl); + if (IS_ERR(pctrl->pctldev)) { + dev_err(&pdev->dev, "Failed to register pinctrl device\n"); + return PTR_ERR(pctrl->pctldev); + } + + ret = wpcm450_gpio_register(pctrl); + if (ret < 0) + return ret; + + pr_info("WPCM450 pinctrl and GPIO driver probed\n"); + return 0; +} + +static const struct of_device_id wpcm450_pinctrl_match[] = { + { .compatible = "nuvoton,wpcm450-pinctrl" }, + { }, +}; +MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match); + +static struct platform_driver wpcm450_pinctrl_driver = { + .probe = wpcm450_pinctrl_probe, + .driver = { + .name = "wpcm450-pinctrl", + .of_match_table = wpcm450_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init wpcm450_pinctrl_register(void) +{ + return platform_driver_register(&wpcm450_pinctrl_driver); +} +arch_initcall(wpcm450_pinctrl_register); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver"); From patchwork Wed Jun 2 12:03:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486644 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=RkwFpq+9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74N4F6Lz9sSs for ; Wed, 2 Jun 2021 22:04:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229882AbhFBMGS (ORCPT ); Wed, 2 Jun 2021 08:06:18 -0400 Received: from mout.gmx.net ([212.227.17.21]:48733 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229818AbhFBMGK (ORCPT ); Wed, 2 Jun 2021 08:06:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635462; bh=zT2Zl3lhTUhOUnhnYSaHc6rA2XeXARsXVQCo0WrodVs=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=RkwFpq+9B8hoNUe3JRr5pyKy3gBeTC7lbfDcVCkhw991uM0lU5qO7/m4G3gS8T6Ck 64DorLxEwASII+hEYXHsqo/v0edYxgtdWHYpBmV3yMbTqDbYy4n1ZCx4BwKX57R88d CRvTX/cOZnCnElSkrFwWMSC/GT3nBg/r0YcJfl7w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MOiHf-1m1oGP2KsB-00Q7pa; Wed, 02 Jun 2021 14:04:22 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 6/8] ARM: dts: wpcm450: Add pinctrl node Date: Wed, 2 Jun 2021 14:03:27 +0200 Message-Id: <20210602120329.2444672-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:1UGScVg0xqr81vwdwouXKQGzWBRBp3MdBmFKGst0MpYLBkwVMXU 96JQqmvL9cRVL6AAtOZ03z5/vXa+astucPlWv18S2rG2t9avTbU7gWZwpzHbEVJd9T63lyq 0eCfIWnX5M5U8e+kz3WvR913eAOTubj7PRGbraJnB7B4ADf2WMGVsUPKTInMW4qZpQlqK6Z xUiT7J8UTyIljDbNYtdIw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:tBgVAy7xyO4=:tWhbERiSrcXlimCpzEEA3+ O49wbDSYAkS4zoDRbCSBpDVIDmKXyjjW0dDPngd0fN4n2gPyRpa5PY6Mo7sOnSiInDEgrUVHu i5DnCKXzEl6tuAyJnP6FfKfe+AKW+8ceT+/7OHKnW6izgMXpZUpjdjk6SYVK7KFEvp4zb1Ctf feax2wljpSEFFnVBdp80sGGIzAojhKgIpBsqK1+F4MXYFSi/h1RNn92YDBXZQSBdxUvIF2NHf SeCF/Op5T1hwQacochuTkC0y6suNF/brCqkYjsA31X7E5C5aaK2IqsQeWTQoJ9tL8hsUz11a8 HMiGgDLXpqgIpo5CT/6ZszXucCxiDSOlxRXnXEBFB6OIn4HlHrJoekLWf+vDbfI248A8NpA4j JKOstoL40Bo62MoMF/bPaIgzL6E3cCHCqP5jsP+Ydxv5hUAmyuKRObq7Q/AGe7Q9bUgIpFERH qfuOC3DyU5cYyPH6hle8eKsVBSEvBfCIgds+4PA5kOrvV1wihQ/jnB/PiRWwctYeo/VcDNj7N ENn5dvJ2alKIH7eoV9mwSUVWoBVylNUVLsS0hRVXQ13SCdkVsbLvgp7lIz+Dl8V0ruY/+3s+z TQnNCPVVsRMGJxN+5LxnnY60zYBszYXz1DTU0hQ+VwUjZkhusUaSKf7FyUttrKC2oueGwldJP pYCbqN/1VBn/DLh0rQNjmlc1h6ccEgBhOtGddhlgl0e4F9NBWRBuhZt9Aw/PgmpcvQGi5mFSn TdsZ68KVAayX750p9QjZlBl1r1q00l+1CZCnHcriCanh94ffqhtifocryg/319HzZigm2KkK7 1mbqn6OoyLGFMESik/19N0fJrnm9YBBGe7fVIQOOCJVbpIw0EEDdHqYBVP/xpisLSphMm2r3p W5eqjCj/3g63S6Lvt6wwbp/l4qhsUNdoSSwgVcEXNBSPTqpGI1Fz2zolMe0BK5ojxDfpRdDBd NWjwOCCaDPZXwq+mWAs6jxlZAVllj8tsu1M0VS9fMZvFh8iHoFBL05LwcXleN2xObcjFcLDdo nIn7pnuYGLn90ROjE2bOw4Q6/QtmEtj5Cv0LBMcUI2q5QcUaRzrBO+W+VzTMhK+3tsQ2RCzve qq9Rlfu7BXtS2MTAvxo/E7kVyK9Ox+fVRKFqXZZej/1hMi6l/SVvr8ReQ== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds the GPIO and pin controller to the devicetree for the WPCM450 SoC. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 8eba4897b41bc..1b63943b2a42b 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -77,5 +77,16 @@ aic: interrupt-controller@b8002000 { interrupt-controller; #interrupt-cells = <2>; }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH + 5 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; From patchwork Wed Jun 2 12:03:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=G+7z3yjj; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74R5ZWTz9sSs for ; Wed, 2 Jun 2021 22:04:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229896AbhFBMGU (ORCPT ); Wed, 2 Jun 2021 08:06:20 -0400 Received: from mout.gmx.net ([212.227.17.21]:34719 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229653AbhFBMGP (ORCPT ); Wed, 2 Jun 2021 08:06:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635467; bh=RTKzM+J9pqSrUr+vTq6pJh5Z2xpl+EIKfucHJ6Hh99I=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=G+7z3yjj689QsI+iP8aKy5EQJUAKmr8sAyAaC/Wild/lOk8KSOUv97lTksuD+WBJ2 3QUJAftA9Sy58hTi4nHwOROuFcFB+JRw2MnGpegVn3ju47n3L9A4bSXKI+44UX6ciQ HuZXGQfWqtZpQSH7jluDwFfWhZNEjKKtMKAu42Hw= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MNsw4-1m3jXP1PjM-00OCcw; Wed, 02 Jun 2021 14:04:27 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 7/8] ARM: dts: wpcm450: Add pin functions Date: Wed, 2 Jun 2021 14:03:28 +0200 Message-Id: <20210602120329.2444672-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:0cK/YI6AJnCyKI30NY3XUNbqcw/TZvI7OpDmGIulKErhvjg21vO l/ZZlG8okXNSK5BCkBCSLnC0Gv/nx5vChL+jFANXnNd0tz4G2cjVVl/+a7Q0BYeLNBV2iaR bIzjA3fhYtYdPzFLwtDco2GW5Eeu9twvHcjooFyrligtRES7fFeqgQeEP1zay9EWBqWIOgf E2HcaBHN5p67J/nHD+2YA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:66ixAULPhaI=:oQgwzf4z2efBGCfzsGtST1 kiixC4F0MVA8jDyBQDyRyt3eYEASsGP5ayzmWEiis9KqXgXYxkjGlT+UNwchYuP1GQUdgGaS4 K+91mn/jN7iHKN1UcGZ/J+VTIGB3cVepqTL/EQidXbJEIDOQ1fIQ2tjwF9OhwW/jsenK4sCyq TKjt5ic6yi6I8sza8KSMGElT12ugbzP54RsGk81mj1ZdQjSykQAKrDwGbMmVACBAtdxUGUxAG swLLUSeTEj8isDSE8CBWmiVLuG2MDuRxz3PFAJcoxU7UiWmVDBCMO8QtOKqRBW89EX+999RCF nlU1yeiT7YKXK4NImGjvh1n90/peS8YKXn+uJIkD3Wu06ngEVxvjixy64Yhc5pbrj8aDOrr/i dvSENoOPzb6OtfIiX5mabIRKJ9W5ylD4LcPfSzzIwQLl/DASH7yppd5i5dG9xPty2T7NWVBU8 qKKiBIXeQ7vL8EhLQgZqhpOKDrjzjM4hBL708d+CnK/2LBmPKnqzYSno83Hsn/mn/Jd3aD+4v I/9/5ztkHdQ12jfUb3w3fOWir1xgqbhy+iTB0+rIXbY5f9GVmQESOLCqt1G8NPsshgxoGWYvP AJBYuj31gfrgBh5nT/lJ/yRmH0ledWomJ4LnQXABqZetEf7RZWqVubfQg/aezP/lxI4Hj3sbD cZnofj7y4xquQ0pA22yh8LBUj2RuTO7vPJLMHNUZxk+lgZlKZtrnezWb1jlrg49Xv6NDsUbwp 7kwdcHkXLJO4kguChUHFhMb04YlSLDUXBcjpn4aHVlII8hnyFW7QSPOAX38I4PAgR9IVCDxEq yAdr9OCpHgayM+U00qMKojO9x/0dpwv2K1VBwcyOqdKqVhedXGSMJpA2aCsejcgGcMKJVbfJU k/MJdHaiA86ZCjUHUAl96sTE8y9FlsljJH6lDDt6xTNiV/R1igHEoPzg4A65E17+sLwNYBlKP sWJlBzLUfdvtMFlKoRFCP9fKKj4Ulzv/XuSoRx6m8VqAOg5xM/Wxv69akV1ayu8Z05NNMWQ2F rmJNTDFZjKUgF+TYI/mugAnO7dsPsN8kfIN7USmyRWNMIOUQ98K5JPUmUbsQnwhCTiS6EJpK2 Ujx+i5CUbNmEKLdP7nQHtaqLwwkjjGMoJVTCX3EI9xfx2Q3lyXde0ERug== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As done in nuvoton-common-npcm7xx.dtsi, this patch adds pinmux nodes for all pin functions to nuvoton-wpcm450.dtsi. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 305 +++++++++++++++++++++++++ 1 file changed, 305 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 1b63943b2a42b..f1a1b1fdcb3e4 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -87,6 +87,311 @@ pinctrl: pinctrl@b8003000 { 3 IRQ_TYPE_LEVEL_HIGH 4 IRQ_TYPE_LEVEL_HIGH 5 IRQ_TYPE_LEVEL_HIGH>; + + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: scs1-pins { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: scs2-pins { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: scs3-pins { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: bsp-pins { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: hsp1-pins { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: hsp2-pins { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: rmii2-pins { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: kbcc-pins { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: dvo0-pins { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: dvo3-pins { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: clko-pins { + groups = "clko"; + function = "clko"; + }; + + smi_pins: smi-pins { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: uinc-pins { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mben-pins { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: xcs2-pins { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: xcs1-pins { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: sdio-pins { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: sspi-pins { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: fi0-pins { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: fi1-pins { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: fi2-pins { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: fi3-pins { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: fi4-pins { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: fi5-pins { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: fi6-pins { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: fi7-pins { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: fi8-pins { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: fi9-pins { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: fi10-pins { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: fi11-pins { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: fi12-pins { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: fi13-pins { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: fi14-pins { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: fi15-pins { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: hg0-pins { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: hg1-pins { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: hg2-pins { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: hg3-pins { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: hg4-pins { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: hg5-pins { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: hg6-pins { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: hg7-pins { + groups = "hg7"; + function = "hg7"; + }; }; }; }; From patchwork Wed Jun 2 12:03:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 1486647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=lgQKeGjR; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fw74V4wX8z9sSs for ; Wed, 2 Jun 2021 22:04:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbhFBMGX (ORCPT ); Wed, 2 Jun 2021 08:06:23 -0400 Received: from mout.gmx.net ([212.227.15.19]:34647 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229871AbhFBMGS (ORCPT ); Wed, 2 Jun 2021 08:06:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635470; bh=P4/CfhOzE9qRlABqP08JDSxbRq009BHSNhR9z95OX2w=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=lgQKeGjRVV6tsRoM8dHKW++3Uf3CpH6WhKM1AT4f1qaapS9x6dn9fS/sg/wZ4uAGJ uLMVc9flkSrAz0qMZHFH06d1wqMUJTfpB52VIXTii3qg4tAEiDLpINRmLQ4t7RN1br BfDrHqc5auxijmpSZYGz0rA7bgQ5NR3HASU5B/iY= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MFKKh-1ld5st2CCn-00FmqE; Wed, 02 Jun 2021 14:04:30 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 8/8] ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons Date: Wed, 2 Jun 2021 14:03:29 +0200 Message-Id: <20210602120329.2444672-9-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:yAIGTz3cD7aDJ3+2ETP6l+xFmX749yXxCxe42nbjAlS00V6VR85 6vyW3FtqEUrdgJuACoVtyPMbP8wR1VBJCDJVkqP0qa7lv+VasFSyn7CYEUQ0s0kt9YpQw1v 9UPEgaqUuOwvmfl5HpUMHkdFbvMfOxaL6Idqx8PNe9m4Q/wQJblQ2Z5mdqypNAj30FiYW1k oXSMU/CzqHfMiNOum7H/A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:CopH+5nNWnI=:noLlRC8oYJ46PYECr24XOz kZcl4CxGxpi/L6w3Jp39hM5bIoo4rAa94qKCWCehQW23sFQdUKGnlsu1eW4blVOOGOIhinxqY eS7kYrTaVFmG5PJGrTZB3w/hxdTHsOsg3uGTDtvCJv9AfmJm/eROAh8Fi3JNkok1tK78HXBpP 4g5tjIHPyvijXFoO8ncloC2kgd3RD2KMHAYp8jr9KDV/7O5A+S9mcYbJIYMiGnQO9D/h3Wq2X XOLIgBVaVzA4d1gEPQQ400EJ2sUjyr5UMRMRJf2ySiOov3jQe+MbixFhu8a7TiWejLW9qVnIV 5pjmBFy0s1zoCPVoAytvlp/BO4MbRQJVsjKEUSb61aUDEqx1YJr47BrDBsvIlFNybYy7CWlQc 6FDdWIPJNco7PabJODHN/Ls6iJZnVlfbcTrBflVeW34fLcDG+Qav119Yn+L5GL8GTdcq9+fqc uc5nKx8vmV3FYfobJnB0fepFGqpKiGHuj5zX69z1WkfB+dWeQjaYL40t5I1ktjEtABx8BVZPy kC5sG83PgMawaPOsKcRrfzskAUmDM6d/wrKCKrEIyIsKNAVYClVNtnNJxiVG2XZXf1t40+K1G X1oTUJxy77uLUF3Bqf6bGFZBkJuk/5b2007gVPMDJWpJX752n3iEmzB3dgDhZSf/brNZoME0H 1fB9uf2lFIKOdS0uaMBfKAAdfjfbyuzS1g2PTuO9+jozDCIyQiMKITo6/81Ryl3RX5JF95x1B BkFQr4wkv7DGmljY8gNbt+xXZZyUcm/zaZPRTGsxfrk7t2d7h6DncJyJfti9TWY6hTkrRZC2t iRBjzr5RaFlHr5aVqP9FOOyudnvblXQOlxnj3JNGT2Z1evaSdrNLCth23ei7OHLLCc+w+aH5Z 6auUkCihSsL4SawvnbWGwi+Gl8wkfbFWlg+Kf8ZFCOGJp4jFPzJMHc+WVdJwHYI4hqsR1lrP9 GDMtz2ZQthNcUVQ1P2T//KOxAeHrFBqGNLQesFynjYe4Lbi+ioKFv1NUj4NLACm+ejkD8enUC D8W4OPUlxFxprmACq0jb7CnngzyKwbtDENuoIE91ey8LMWtgEIi/tY9jj8BfOIR9GQOkCX9eQ 52kA1jtON+8Prtpo64ppNdK6lF5wadOqHbUZktJe2tDFPgRQpdUhE4Lqw== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Supermicro X9SCi-LN4F server mainboard has a two LEDs and a button under the control of the BMC. This patch makes them accessible under Linux running on the BMC. Signed-off-by: Jonathan Neuschäfer --- .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 83f27fbf4e939..176e22216a75e 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -8,6 +8,9 @@ #include "nuvoton-wpcm450.dtsi" +#include +#include + / { model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; @@ -20,6 +23,30 @@ memory@0 { device_type = "memory"; reg = <0 0x08000000>; /* 128 MiB */ }; + + gpio-keys { + compatible = "gpio-keys"; + + uid { + label = "UID button"; + linux,code = ; + gpios = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + uid { + label = "UID"; + gpios = <&pinctrl 23 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&pinctrl 20 GPIO_ACTIVE_LOW>; + }; + }; }; &serial0 {