From patchwork Fri May 21 07:00:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcvW4TSfz9sWl; Fri, 21 May 2021 17:00:55 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9O-0008Ja-Bm; Fri, 21 May 2021 07:00:50 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9M-0008J5-E7 for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:48 +0000 Received: from mail-qt1-f199.google.com ([209.85.160.199]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9M-0000Zf-6a for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:48 +0000 Received: by mail-qt1-f199.google.com with SMTP id 1-20020aed31010000b029019d1c685840so14621519qtg.3 for ; Fri, 21 May 2021 00:00:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ed2eAtqfPMeIYXDKKDmpjclndAoFxh48IWgtjP7tdeQ=; b=qrQwhql1V3ASoL+eo7qArP0A1uAIW+eUKR8Ls6cxDsRg0YVID1ip6t/a41dKNv5hYM /fqzgWPRLsy8x8+qZCzeRQlEFwvwj+iSfiJwDKuMyl6h4nFHa3NkSn/veLMuKQSqrVHi 0dGqCXHIpNMuBkcGDSisIIJWKo5nLzvR5Tr5zVz3f8clB3TvzjtSmEQwRmkpXSTQRAXU ouNzKLhsR0oTpeFSy7hrIK7sgNgj/Do8lpqdDtJa9ukdj3CJjlAO2KPAGCj6SEa/uHvw iJEChMmsB6RoyOlWaUz2iLIon3XIkTxliNs1LeN55SgBr4GBCxPmvMIMT+L9FTVGALPD iMWA== X-Gm-Message-State: AOAM533d3wiPky+cyRvXUIBVjcvXzS9tS2kWZFfso7asXC7L7CgwmEnO CVdIp5vjjW6qacWJQlVya+p7IniqOoSjX47Dc9OEckhnyH3kwycVcAoLGN+QEfH9apJ5ImhtxxB E/Lhf9Rabzwu54GvTvek8NE/l+Rbq5eB+15Kj8Nlh0Q== X-Received: by 2002:a37:a4b:: with SMTP id 72mr6156499qkk.105.1621580447348; Fri, 21 May 2021 00:00:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzePWWGfsyZrJzjHnrONhgiz5An2vLk6TxPId3O1UyQuRHXvxH6K/zOkDmauf0OUC5Xi9hDkg== X-Received: by 2002:a37:a4b:: with SMTP id 72mr6156475qkk.105.1621580447107; Fri, 21 May 2021 00:00:47 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:46 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-meta-oracle][PATCH 1/1] UBUNTU: [config] oracle: Bring-up for arm64 support Date: Fri, 21 May 2021 03:00:23 -0400 Message-Id: <20210521070042.1445-2-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 Signed-off-by: Khalid Elmously --- debian/control.d/oracle | 10 +++++----- debian/rules | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/debian/control.d/oracle b/debian/control.d/oracle index 906c537a..423fa319 100644 --- a/debian/control.d/oracle +++ b/debian/control.d/oracle @@ -1,5 +1,5 @@ Package: linux-headers-oracle${variant:suffix} -Architecture: amd64 +Architecture: amd64 arm64 Section: kernel Depends: ${misc:Depends}, linux-headers-${kernel-abi-version}-oracle Description: Linux kernel headers for Oracle systems. @@ -7,16 +7,16 @@ Description: Linux kernel headers for Oracle systems. for Oracle systems. Package: linux-image-oracle${variant:suffix} -Architecture: amd64 +Architecture: amd64 arm64 Section: kernel Provides: ${dkms:zfs-modules} ${dkms:virtualbox-guest-modules} ${dkms:wireguard-linux-compat-modules} -Depends: ${misc:Depends}, linux-image-${kernel-abi-version}-oracle, linux-modules-extra-${kernel-abi-version}-oracle [amd64] +Depends: ${misc:Depends}, linux-image-${kernel-abi-version}-oracle, linux-modules-extra-${kernel-abi-version}-oracle Description: Linux kernel image for Oracle systems. This package will always depend on the latest kernel image available for Oracle systems. Package: linux-tools-oracle${variant:suffix} -Architecture: amd64 +Architecture: amd64 arm64 Section: kernel Provides: linux-tools Depends: ${misc:Depends}, linux-tools-${kernel-abi-version}-oracle @@ -25,7 +25,7 @@ Description: Linux kernel versioned tools for Oracle systems. available for Oracle systems. Package: linux-oracle${variant:suffix} -Architecture: amd64 +Architecture: amd64 arm64 Section: kernel Provides: ${test:provides-full-oracle} ${test:provides-full-preferred} Depends: ${misc:Depends}, linux-image-oracle${variant:suffix} (= ${binary:Version}), linux-headers-oracle${variant:suffix} (= ${binary:Version}) diff --git a/debian/rules b/debian/rules index b04275ae..4cb172ae 100755 --- a/debian/rules +++ b/debian/rules @@ -76,7 +76,7 @@ debian/control: $(control_files) gencontrol_flags = -Vkernel-version=$(KERNEL_VERSION) gencontrol_flags += -Vkernel-abi-version=$(KERNEL_ABI_VERSION) gencontrol_flags += -Vdkms:zfs-modules="zfs-modules (= $(dkms_zfs_linux_version))," -gencontrol_flags += -Vdkms:virtualbox-guest-modules="virtualbox-guest-modules (= $(dkms_virtualbox_version))," +gencontrol_flags += -Vdkms:virtualbox-guest-modules="virtualbox-guest-modules (= $(dkms_virtualbox_version)) [amd64]," gencontrol_flags += -Vdkms:wireguard-linux-compat-modules="wireguard-modules (= $(dkms_wireguard_version))," build-%: From patchwork Fri May 21 07:00:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcvq57cmz9sW4; Fri, 21 May 2021 17:01:11 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9e-0008Tl-3o; Fri, 21 May 2021 07:01:06 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9O-0008Jn-U6 for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:50 +0000 Received: from mail-qt1-f199.google.com ([209.85.160.199]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9O-0000aX-J5 for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:50 +0000 Received: by mail-qt1-f199.google.com with SMTP id f17-20020ac87f110000b02901e117339ea7so14551809qtk.16 for ; Fri, 21 May 2021 00:00:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t0duI2SWM4XPLzob/E5UbJiy91RyVn9wvUy8HSTFIoY=; b=X/XDV2I3OTMxGo2B00DF3VdebFR6kijYReRtr85Xxe5YpASJ+oGMY45o8T/znp4098 n9+ByPdPtS2I8voVV13aPV/+F9RwpIXoKJ9ZDRVtb03eAFfEoLuofAeTpwexr9jYjjbo 0ll+HN2p1prgjxBdZaHMPQyfspK+92ownvHEl+TM1gkmUrknqU6dh8vO1eg0zita1Jr/ mXiLG/8v7Wa4nrfjxCJtl8fv5T89/eCQgg8aHTABfPuCCvDB8iQTWRAV2c8urtEPUXr7 liy9T8mDDw/CNlfkG3WeESLQYQPlZqufFKY8EOYj+aN3VESqQMQAUfBvsQ3aSx4DMqhx FNkA== X-Gm-Message-State: AOAM532VGb6IlHyqe5Ay6IGIuTkSnN5B1QuGYvveP+AmuCVzV3IZBlXd pMjWwuZRl29UXSWV1PkH5e+CY5rlx0lBbnA6ygjdTG5Rb6iGGWEwkHyRFXcSGEvjZqxLaZ6n0BH gZtqTG8j6rcwaTConrv0TECaFhfg0qIBQSIHYnGH1sg== X-Received: by 2002:ac8:7f13:: with SMTP id f19mr9543649qtk.202.1621580449708; Fri, 21 May 2021 00:00:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYh+JktFoqK98OgNCXwfkHBjGwcfD2jm7nuaM0PD3JRoqsXzZkC9MBIbgD9ytv+oYpifyhDw== X-Received: by 2002:ac8:7f13:: with SMTP id f19mr9543630qtk.202.1621580449473; Fri, 21 May 2021 00:00:49 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:49 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 02/18] UBUNTU: [packaging] oracle: Update annotations after adding arm64 Date: Fri, 21 May 2021 03:00:26 -0400 Message-Id: <20210521070042.1445-5-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 No effect on amd64 configuration Signed-off-by: Khalid Elmously --- debian.oracle/config/annotations | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/debian.oracle/config/annotations b/debian.oracle/config/annotations index d142a2deae2a..1021d9730b38 100644 --- a/debian.oracle/config/annotations +++ b/debian.oracle/config/annotations @@ -6,19 +6,19 @@ include "../../debian.master/config/annotations" CONFIG_DRM_BOCHS policy<{'amd64': 'n'}> CONFIG_DRM_BOCHS note -CONFIG_FAILOVER policy<{'amd64': 'm'}> +CONFIG_FAILOVER policy<{'amd64': 'm', 'arm64': 'm'}> CONFIG_FAILOVER mark note -CONFIG_MODVERSIONS policy<{'amd64': 'y'}> +CONFIG_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y'}> CONFIG_MODVERSIONS mark note -CONFIG_MTD_DOCG3 policy<{'amd64': 'm'}> +CONFIG_MTD_DOCG3 policy<{'amd64': 'm', 'arm64': 'm'}> CONFIG_MTD_DOCG3 mark note -CONFIG_NET_FAILOVER policy<{'amd64': 'm'}> +CONFIG_NET_FAILOVER policy<{'amd64': 'm', 'arm64': 'm'}> CONFIG_NET_FAILOVER mark note -CONFIG_PAGE_POOL policy<{'amd64': 'y'}> +CONFIG_PAGE_POOL policy<{'amd64': 'y', 'arm64': 'y'}> CONFIG_PAGE_POOL mark note -CONFIG_SOUNDWIRE policy<{'amd64': 'n'}> +CONFIG_SOUNDWIRE policy<{'amd64': 'n', 'arm64': 'n'}> CONFIG_SOUNDWIRE mark note -CONFIG_LATENCYTOP policy<{'amd64': 'n'}> +CONFIG_LATENCYTOP policy<{'amd64': 'n', 'arm64': 'n'}> CONFIG_LATENCYTOP mark note CONFIG_SAMPLE_TRACE_PRINTK policy<{'amd64': '-'}> CONFIG_SAMPLE_TRACE_PRINTK mark note @@ -37,5 +37,7 @@ CONFIG_SND_SOC_INTEL_CNL mark note CONFIG_X86_UV policy<{'amd64': 'n'}> CONFIG_X86_UV mark note -CONFIG_ATARI_PARTITION policy<{'amd64': 'n'}> +CONFIG_ATARI_PARTITION policy<{'amd64': 'n', 'arm64': 'n'}> CONFIG_ATARI_PARTITION mark note +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': '-'}> +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT mark From patchwork Fri May 21 07:00:27 2021 Content-Type: text/plain; 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:50 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 03/18] UBUNTU: [config] generate/split configs for arm64 Date: Fri, 21 May 2021 03:00:27 -0400 Message-Id: <20210521070042.1445-6-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 Updating the configs after the introduction of arm64. No changes for amd64 configuration Signed-off-by: Khalid Elmously --- .../config/amd64/config.common.amd64 | 13 + .../config/arm64/config.common.arm64 | 15 +- debian.oracle/config/config.common.ubuntu | 687 +++++++++++++++++- 3 files changed, 701 insertions(+), 14 deletions(-) diff --git a/debian.oracle/config/amd64/config.common.amd64 b/debian.oracle/config/amd64/config.common.amd64 index 529c49d4daae..3f6ccd2283a0 100644 --- a/debian.oracle/config/amd64/config.common.amd64 +++ b/debian.oracle/config/amd64/config.common.amd64 @@ -1,3 +1,16 @@ # # Config options for config.common.amd64 automatically generated by splitconfig.pl # +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_SPCR_TABLE is not set +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 10.2.0-13ubuntu1) 10.2.0" +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_KVM=m +CONFIG_NR_CPUS=8192 +# CONFIG_OF is not set +CONFIG_PGTABLE_LEVELS=5 diff --git a/debian.oracle/config/arm64/config.common.arm64 b/debian.oracle/config/arm64/config.common.arm64 index 529c49d4daae..a248cdefa5bf 100644 --- a/debian.oracle/config/arm64/config.common.arm64 +++ b/debian.oracle/config/arm64/config.common.arm64 @@ -1,3 +1,16 @@ # -# Config options for config.common.amd64 automatically generated by splitconfig.pl +# Config options for config.common.arm64 automatically generated by splitconfig.pl # +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 10.2.0-8ubuntu1) 10.2.0" +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_KVM is not set +CONFIG_NR_CPUS=256 +CONFIG_OF=y +CONFIG_PGTABLE_LEVELS=3 diff --git a/debian.oracle/config/config.common.ubuntu b/debian.oracle/config/config.common.ubuntu index cfbc637d0288..204a4716d38c 100644 --- a/debian.oracle/config/config.common.ubuntu +++ b/debian.oracle/config/config.common.ubuntu @@ -56,12 +56,15 @@ CONFIG_ACPI_APEI_EINJ=m CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_SEA=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BGRT=y CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CCA_REQUIRED=y CONFIG_ACPI_CMPC=m CONFIG_ACPI_CONFIGFS=m CONFIG_ACPI_CONTAINER=y +# CONFIG_ACPI_CPPC_CPUFREQ is not set CONFIG_ACPI_CPPC_LIB=y CONFIG_ACPI_CPU_FREQ_PSS=y CONFIG_ACPI_CUSTOM_DSDT_FILE="" @@ -73,28 +76,31 @@ CONFIG_ACPI_DOCK=y CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_EXTLOG=m CONFIG_ACPI_FAN=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_GTDT=y CONFIG_ACPI_HED=y CONFIG_ACPI_HMAT=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_HOTPLUG_MEMORY=y CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IORT=y CONFIG_ACPI_IPMI=m CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y CONFIG_ACPI_LPIT=y +CONFIG_ACPI_MCFG=y CONFIG_ACPI_NFIT=m CONFIG_ACPI_NUMA=y CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PPTT=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_PROCESSOR_CSTATE=y CONFIG_ACPI_PROCESSOR_IDLE=y # CONFIG_ACPI_PROCFS_POWER is not set -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_SBS=m CONFIG_ACPI_SLEEP=y -# CONFIG_ACPI_SPCR_TABLE is not set CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TAD=y @@ -216,6 +222,8 @@ CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y CONFIG_AGP_SIS=m CONFIG_AGP_VIA=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_QORIQ is not set CONFIG_AIC79XX_CMDS_PER_DEVICE=32 # CONFIG_AIC79XX_DEBUG_ENABLE is not set CONFIG_AIC79XX_DEBUG_MASK=0 @@ -232,6 +240,7 @@ CONFIG_AIRO=m CONFIG_AIRO_CS=m CONFIG_AIX_PARTITION=y CONFIG_AK09911=m +# CONFIG_AK8974 is not set CONFIG_AK8975=m CONFIG_AL3010=m CONFIG_AL3320A=m @@ -243,10 +252,13 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_ALTERA_MBOX=m CONFIG_ALTERA_MSGDMA=m CONFIG_ALTERA_PR_IP_CORE=m +# CONFIG_ALTERA_PR_IP_CORE_PLAT is not set CONFIG_ALTERA_STAPL=m CONFIG_ALTERA_TSE=m CONFIG_ALX=m +# CONFIG_AL_FIC is not set CONFIG_AM2315=m +# CONFIG_AMBA_PL08X is not set CONFIG_AMD8111_ETH=m CONFIG_AMDTEE=m CONFIG_AMD_IOMMU=y @@ -272,6 +284,15 @@ CONFIG_APPLICOM=m CONFIG_AQTION=m CONFIG_AQUANTIA_PHY=m CONFIG_AR5523=m +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +CONFIG_ARCH_BINFMT_ELF_STATE=y +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_ARCH_CPUIDLE_HALTPOLL=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -280,6 +301,7 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_ARCH_ENABLE_THP_MIGRATION=y +# CONFIG_ARCH_EXYNOS is not set CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ARCH_HAS_ADD_PAGES=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y @@ -289,6 +311,7 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_ARCH_HAS_EARLY_DEBUG=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y @@ -298,6 +321,7 @@ CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_KEXEC_PURGATORY=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y @@ -306,34 +330,80 @@ CONFIG_ARCH_HAS_PKEYS=y CONFIG_ARCH_HAS_PMEM_API=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAVE_ELF_PROT=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_HIBERNATION_HEADER=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_HISI is not set +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +# CONFIG_ARCH_K3 is not set +CONFIG_ARCH_KEEP_MEMBLOCK=y +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set CONFIG_ARCH_MAY_HAVE_PC_FDC=y +# CONFIG_ARCH_MEDIATEK is not set CONFIG_ARCH_MEMORY_PROBE=y +# CONFIG_ARCH_MESON is not set CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set CONFIG_ARCH_PROC_KCORE_TEXT=y +# CONFIG_ARCH_QCOM is not set CONFIG_ARCH_RANDOM=y +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_ARCH_SPRD is not set CONFIG_ARCH_STACKWALK=y +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SUNXI is not set CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y @@ -342,22 +412,34 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_GNU_PROPERTY=y CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_ARCH_VEXPRESS is not set CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set CONFIG_ARCNET=m CONFIG_ARCNET_1051=m CONFIG_ARCNET_1201=m @@ -369,6 +451,90 @@ CONFIG_ARCNET_COM90xx=m CONFIG_ARCNET_COM90xxIO=m CONFIG_ARCNET_RAW=m CONFIG_ARCNET_RIM_I=m +CONFIG_ARM64=y +# CONFIG_ARM64_16K_PAGES is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set +CONFIG_ARM64_AMU_EXTN=y +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_E0PD=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_RAS_EXTN=y +# CONFIG_ARM64_RELOC_TEST is not set +CONFIG_ARM64_SSBD=y +CONFIG_ARM64_SVE=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_UAO=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VHE=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARM_DSU_PMU is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_ARM_PMU=y +CONFIG_ARM_PMU_ACPI=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_ARM_SMC_WATCHDOG is not set +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_ARM_SPE_PMU is not set CONFIG_AS3935=m CONFIG_ASM_MODVERSIONS=y CONFIG_ASN1=y @@ -387,6 +553,8 @@ CONFIG_ASYNC_RAID6_RECOV=m CONFIG_ASYNC_TX_DMA=y CONFIG_ASYNC_XOR=m CONFIG_AS_AVX512=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +CONFIG_AS_HAS_PAC=y CONFIG_AS_SHA1_NI=y CONFIG_AS_SHA256_NI=y CONFIG_AS_TPAUSE=y @@ -404,6 +572,7 @@ CONFIG_ATA_PIIX=y CONFIG_ATA_SFF=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATH10K=m +# CONFIG_ATH10K_AHB is not set CONFIG_ATH10K_CE=y # CONFIG_ATH10K_DEBUG is not set CONFIG_ATH10K_DEBUGFS=y @@ -490,6 +659,9 @@ CONFIG_ATP=m CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_ARCH=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +CONFIG_AUDIT_GENERIC=y CONFIG_AUFS_BDEV_LOOP=y # CONFIG_AUFS_BRANCH_MAX_1023 is not set CONFIG_AUFS_BRANCH_MAX_127=y @@ -575,6 +747,7 @@ CONFIG_BACKLIGHT_DA903X=m CONFIG_BACKLIGHT_DA9052=m CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_LED is not set CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_LM3630A=m CONFIG_BACKLIGHT_LM3639=m @@ -619,6 +792,7 @@ CONFIG_BATTERY_DS2780=m CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m CONFIG_BATTERY_GAUGE_LTC2941=m +# CONFIG_BATTERY_LEGO_EV3 is not set CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m CONFIG_BATTERY_MAX1721X=m @@ -654,6 +828,7 @@ CONFIG_BCMA_SFLASH=y CONFIG_BCMGENET=m CONFIG_BCM_KONA_USB2_PHY=m CONFIG_BCM_NET_PHYLIB=m +# CONFIG_BCM_SBA_RAID is not set CONFIG_BE2ISCSI=m CONFIG_BE2NET=m CONFIG_BE2NET_BE2=y @@ -795,6 +970,7 @@ CONFIG_BRCMFMAC_PROTO_MSGBUF=y CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y CONFIG_BRCMSMAC=m +# CONFIG_BRCMSTB_GISB_ARB is not set CONFIG_BRCMUTIL=m CONFIG_BRCM_TRACING=y CONFIG_BRIDGE=m @@ -929,6 +1105,8 @@ CONFIG_CAN_EMS_PCMCIA=m CONFIG_CAN_EMS_USB=m CONFIG_CAN_ESD_USB2=m CONFIG_CAN_F81601=m +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set CONFIG_CAN_GS_USB=m CONFIG_CAN_GW=m CONFIG_CAN_HI311X=m @@ -959,6 +1137,7 @@ CONFIG_CAN_SOFTING_CS=m # CONFIG_CAN_UCAN is not set CONFIG_CAN_VCAN=m CONFIG_CAN_VXCAN=m +# CONFIG_CAN_XILINXCAN is not set CONFIG_CAPI_TRACE=y CONFIG_CARDBUS=y CONFIG_CARDMAN_4000=m @@ -970,7 +1149,13 @@ CONFIG_CARL9170_LEDS=y CONFIG_CARL9170_WPC=y # CONFIG_CARMINE_DRAM_CUSTOM is not set CONFIG_CASSINI=m +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y CONFIG_CAVIUM_PTP=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y CONFIG_CB710_CORE=m # CONFIG_CB710_DEBUG is not set CONFIG_CB710_DEBUG_ASSUMPTIONS=y @@ -980,16 +1165,19 @@ CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y CONFIG_CC_HAS_INT128=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_CC_HAS_SANE_STACKPROTECTOR=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_CC_IS_GCC=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 10.2.0-13ubuntu1) 10.2.0" # CONFIG_CDNS_I3C_MASTER is not set CONFIG_CDROM=y CONFIG_CDROM_PKTCDVD=m @@ -1045,6 +1233,7 @@ CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_CROS_USBPD=m CONFIG_CHARGER_DA9150=m +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_ISP1704=m CONFIG_CHARGER_LP8727=m @@ -1063,6 +1252,7 @@ CONFIG_CHARGER_SBS=m CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m CONFIG_CHARGER_TWL4030=m +# CONFIG_CHARGER_UCS1002 is not set CONFIG_CHARGER_WILCO=m CONFIG_CHARLCD=m CONFIG_CHARLCD_BL_FLASH=y @@ -1109,18 +1299,23 @@ CONFIG_CLEANCACHE=y CONFIG_CLKBLD_I8253=y CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKEVT_I8253=y +# CONFIG_CLK_HSDK is not set +# CONFIG_CLK_QORIQ is not set CONFIG_CLK_TWL6040=m CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_CLOCKSOURCE_WATCHDOG=y # CONFIG_CLOCK_THERMAL is not set +CONFIG_CLONE_BACKWARDS=y CONFIG_CLS_U32_MARK=y # CONFIG_CLS_U32_PERF is not set CONFIG_CLZ_TAB=y CONFIG_CM32181=m CONFIG_CM3232=m CONFIG_CM3323=m +# CONFIG_CM3605 is not set CONFIG_CM36651=m # CONFIG_CMA is not set +CONFIG_CMDLINE="" # CONFIG_CMDLINE_BOOL is not set CONFIG_CMDLINE_PARTITION=y CONFIG_CNIC=m @@ -1265,15 +1460,22 @@ CONFIG_COMEDI_USB_DRIVERS=m CONFIG_COMEDI_VMK80XX=m CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_CDCE706=m +# CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=m +# CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_MAX9485=y CONFIG_COMMON_CLK_PALMAS=m CONFIG_COMMON_CLK_PWM=m CONFIG_COMMON_CLK_S2MPS11=m +# CONFIG_COMMON_CLK_SI514 is not set CONFIG_COMMON_CLK_SI5341=m CONFIG_COMMON_CLK_SI5351=m CONFIG_COMMON_CLK_SI544=y +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_VC5 is not set CONFIG_COMMON_CLK_WM831X=m +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_COMPACTION=y CONFIG_COMPAL_LAPTOP=m CONFIG_COMPAT=y @@ -1299,13 +1501,16 @@ CONFIG_COPS_DAYNA=y CONFIG_COPS_TANGENT=y CONFIG_CORDIC=m CONFIG_COREDUMP=y +# CONFIG_CORESIGHT is not set CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_CORTINA_PHY=m CONFIG_COUNTER=m # CONFIG_CPA_DEBUG is not set CONFIG_CPU5_WDT=m +# CONFIG_CPUFREQ_DT is not set CONFIG_CPUMASK_OFFSTACK=y CONFIG_CPUSETS=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_FREQ=y # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set @@ -1329,12 +1534,15 @@ CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_CENTAUR=y CONFIG_CPU_SUP_HYGON=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_ZHAOXIN=y +# CONFIG_CPU_THERMAL is not set CONFIG_CRAMFS=m CONFIG_CRAMFS_BLOCKDEV=y CONFIG_CRAMFS_MTD=y @@ -1363,10 +1571,12 @@ CONFIG_CROS_EC_ISHTP=m CONFIG_CROS_EC_LIGHTBAR=m CONFIG_CROS_EC_LPC=m CONFIG_CROS_EC_PROTO=y +# CONFIG_CROS_EC_RPMSG is not set CONFIG_CROS_EC_SENSORHUB=m CONFIG_CROS_EC_SPI=m CONFIG_CROS_EC_SYSFS=m CONFIG_CROS_EC_TYPEC=m +CONFIG_CROS_EC_VBC=m CONFIG_CROS_KBD_LED_BACKLIGHT=m CONFIG_CROS_USBPD_LOGGER=m CONFIG_CROS_USBPD_NOTIFY=m @@ -1378,7 +1588,14 @@ CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_AEGIS128=m CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m +CONFIG_CRYPTO_AEGIS128_SIMD=y CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM64 is not set +# CONFIG_CRYPTO_AES_ARM64_BS is not set +# CONFIG_CRYPTO_AES_ARM64_CE is not set +# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set CONFIG_CRYPTO_AES_NI_INTEL=m CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_AKCIPHER=y @@ -1413,6 +1630,7 @@ CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_CHACHA20_X86_64=m CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_CRC32=m @@ -1420,6 +1638,7 @@ CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32C_INTEL=y CONFIG_CRYPTO_CRC32_PCLMUL=m CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_CTR=y @@ -1434,11 +1653,17 @@ CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set CONFIG_CRYPTO_DEV_CCP=y CONFIG_CRYPTO_DEV_CCP_CRYPTO=m CONFIG_CRYPTO_DEV_CCP_DD=m # CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +# CONFIG_CRYPTO_DEV_CCREE is not set CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_ZIP is not set CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m CONFIG_CRYPTO_DEV_PADLOCK=y @@ -1472,6 +1697,7 @@ CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_GHASH_ARM64_CE is not set CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m CONFIG_CRYPTO_GLUE_HELPER_X86=m CONFIG_CRYPTO_HASH=y @@ -1496,7 +1722,6 @@ CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m CONFIG_CRYPTO_LIB_DES=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_LZ4=m @@ -1510,6 +1735,7 @@ CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_NHPOLY1305=m CONFIG_CRYPTO_NHPOLY1305_AVX2=m +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set CONFIG_CRYPTO_NHPOLY1305_SSE2=m CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y @@ -1517,6 +1743,7 @@ CONFIG_CRYPTO_OFB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_PCRYPT=m CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_POLY1305_NEON=m CONFIG_CRYPTO_POLY1305_X86_64=m CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m @@ -1534,17 +1761,25 @@ CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m CONFIG_CRYPTO_SERPENT_AVX_X86_64=m CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_ARM64_CE is not set CONFIG_CRYPTO_SHA1_SSSE3=m CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA256_ARM64 is not set CONFIG_CRYPTO_SHA256_SSSE3=m +# CONFIG_CRYPTO_SHA2_ARM64_CE is not set CONFIG_CRYPTO_SHA3=m +# CONFIG_CRYPTO_SHA3_ARM64 is not set CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA512_ARM64 is not set +# CONFIG_CRYPTO_SHA512_ARM64_CE is not set CONFIG_CRYPTO_SHA512_SSSE3=m CONFIG_CRYPTO_SIMD=m CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_SM3_ARM64_CE is not set CONFIG_CRYPTO_SM4=m +# CONFIG_CRYPTO_SM4_ARM64_CE is not set CONFIG_CRYPTO_STATS=y CONFIG_CRYPTO_STREEBOG=m CONFIG_CRYPTO_TEA=m @@ -1582,6 +1817,7 @@ CONFIG_DA280=m CONFIG_DA311=m CONFIG_DA9052_WATCHDOG=m CONFIG_DA9055_WATCHDOG=m +# CONFIG_DA9062_THERMAL is not set CONFIG_DA9062_WATCHDOG=m CONFIG_DA9063_WATCHDOG=m CONFIG_DA9150_GPADC=m @@ -1602,6 +1838,7 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_EFI is not set # CONFIG_DEBUG_ENTRY is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set CONFIG_DEBUG_FS=y @@ -1723,6 +1960,7 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMARD06 is not set CONFIG_DMARD09=m CONFIG_DMARD10=m CONFIG_DMAR_TABLE=y @@ -1730,9 +1968,14 @@ CONFIG_DMAR_TABLE=y CONFIG_DMA_ACPI=y # CONFIG_DMA_API_DEBUG is not set CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_ENGINE_RAID=y # CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_VIRTUAL_CHANNELS=m CONFIG_DMA_VIRT_OPS=y @@ -1785,6 +2028,7 @@ CONFIG_DP83867_PHY=m CONFIG_DP83869_PHY=m # CONFIG_DP83TC811_PHY is not set # CONFIG_DPM_WATCHDOG is not set +# CONFIG_DPOT_DAC is not set CONFIG_DPS310=m CONFIG_DPTF_POWER=m CONFIG_DQL=y @@ -1800,14 +2044,19 @@ CONFIG_DRM_AMD_ACP=y CONFIG_DRM_AMD_DC=y CONFIG_DRM_AMD_DC_DCN=y CONFIG_DRM_AMD_DC_HDCP=y +# CONFIG_DRM_ANALOGIX_ANX6345 is not set CONFIG_DRM_ANALOGIX_ANX78XX=m CONFIG_DRM_ANALOGIX_DP=m +# CONFIG_DRM_ARCPGU is not set CONFIG_DRM_AST=m # CONFIG_DRM_BOCHS is not set CONFIG_DRM_BRIDGE=y +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_CIRRUS_QEMU=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_DEBUG_SELFTEST=m +# CONFIG_DRM_DISPLAY_CONNECTOR is not set CONFIG_DRM_DP_AUX_CHARDEV=y # CONFIG_DRM_DP_CEC is not set # CONFIG_DRM_ETNAVIV is not set @@ -1821,6 +2070,10 @@ CONFIG_DRM_GM12U320=m CONFIG_DRM_GMA3600=y CONFIG_DRM_GMA500=m CONFIG_DRM_GMA600=y +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_I2C_ADV7511 is not set CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m @@ -1852,23 +2105,70 @@ CONFIG_DRM_I915_USERPTR=y CONFIG_DRM_KMS_CMA_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_KOMEDA is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_LIB_RANDOM=y +# CONFIG_DRM_LIMA is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set CONFIG_DRM_MGAG200=m CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_MXSFB is not set CONFIG_DRM_NOUVEAU=m CONFIG_DRM_NOUVEAU_BACKLIGHT=y # CONFIG_DRM_NOUVEAU_SVM is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PL111 is not set CONFIG_DRM_QXL=m CONFIG_DRM_RADEON=m # CONFIG_DRM_RADEON_USERPTR is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +CONFIG_DRM_RCAR_WRITEBACK=y CONFIG_DRM_SCHED=m +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set CONFIG_DRM_TTM=m CONFIG_DRM_TTM_DMA_PAGE_POOL=y CONFIG_DRM_TTM_HELPER=m @@ -1886,6 +2186,7 @@ CONFIG_DS1682=m CONFIG_DS1803=m CONFIG_DS4424=m CONFIG_DST_CACHE=y +CONFIG_DTC=y CONFIG_DUMMY=m CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 @@ -2090,8 +2391,10 @@ CONFIG_DVB_ZL10039=m CONFIG_DVB_ZL10353=m CONFIG_DWC_XLGMAC=m CONFIG_DWC_XLGMAC_PCI=m +# CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=m CONFIG_DWMAC_INTEL=m +# CONFIG_DW_AXI_DMAC is not set CONFIG_DW_DMAC=m CONFIG_DW_DMAC_CORE=m CONFIG_DW_DMAC_PCI=m @@ -2123,8 +2426,10 @@ CONFIG_EDAC=y CONFIG_EDAC_AMD64=m # CONFIG_EDAC_AMD64_ERROR_INJECTION is not set CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_BLUEFIELD is not set # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_DECODE_MCE=m +# CONFIG_EDAC_DMC520 is not set CONFIG_EDAC_E752X=m CONFIG_EDAC_GHES=y CONFIG_EDAC_I10NM=m @@ -2142,7 +2447,9 @@ CONFIG_EDAC_PND2=m CONFIG_EDAC_SBRIDGE=m CONFIG_EDAC_SKX=m CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC_THUNDERX is not set CONFIG_EDAC_X38=m +# CONFIG_EDAC_XGENE is not set CONFIG_EDD=y CONFIG_EDD_OFF=y CONFIG_EEEPC_LAPTOP=m @@ -2157,6 +2464,7 @@ CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m CONFIG_EFI=y CONFIG_EFIVAR_FS=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=m CONFIG_EFI_CAPSULE_LOADER=m CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y @@ -2165,8 +2473,10 @@ CONFIG_EFI_DEV_PATH_PARSER=y CONFIG_EFI_EARLYCON=y CONFIG_EFI_ESRT=y # CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_GENERIC_STUB=y CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_MIXED=y +CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_PARTITION=y # CONFIG_EFI_PGT_DUMP is not set CONFIG_EFI_RCI2_TABLE=y @@ -2197,6 +2507,7 @@ CONFIG_ENCRYPTED_KEYS=y CONFIG_ENCX24J600=m CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y CONFIG_EQUALIZER=m @@ -2251,6 +2562,7 @@ CONFIG_EXTCON_SM5502=m CONFIG_EXTCON_USBC_CROS_EC=m CONFIG_EXTCON_USB_GPIO=m CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set CONFIG_EZX_PCAP=y # CONFIG_F2FS_CHECK_FS is not set # CONFIG_F2FS_FAULT_INJECTION is not set @@ -2282,6 +2594,7 @@ CONFIG_FB_3DFX=m # CONFIG_FB_3DFX_I2C is not set CONFIG_FB_ARC=m CONFIG_FB_ARK=m +# CONFIG_FB_ARMCLCD is not set CONFIG_FB_ASILIANT=y CONFIG_FB_ATY=m CONFIG_FB_ATY128=m @@ -2361,6 +2674,7 @@ CONFIG_FB_SM501=m CONFIG_FB_SM712=m CONFIG_FB_SM750=m CONFIG_FB_SMSCUFX=m +# CONFIG_FB_SSD1307 is not set CONFIG_FB_SVGALIB=m CONFIG_FB_SYS_COPYAREA=m CONFIG_FB_SYS_FILLRECT=m @@ -2435,6 +2749,7 @@ CONFIG_FONT_8x16=y CONFIG_FONT_8x8=y CONFIG_FONT_SUPPORT=y CONFIG_FORCEDETH=m +CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_FORTIFY_SOURCE=y CONFIG_FPGA=m CONFIG_FPGA_BRIDGE=m @@ -2447,6 +2762,7 @@ CONFIG_FPGA_DFL_FME_REGION=m CONFIG_FPGA_DFL_PCI=m CONFIG_FPGA_MGR_ALTERA_CVP=m CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +# CONFIG_FPGA_MGR_ICE40_SPI is not set CONFIG_FPGA_MGR_MACHXO2_SPI=m CONFIG_FPGA_MGR_XILINX_SPI=m CONFIG_FPGA_REGION=m @@ -2464,6 +2780,11 @@ CONFIG_FSCACHE=m # CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_FSCACHE_STATS=y +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +CONFIG_FSL_ERRATUM_A008585=y +# CONFIG_FSL_QDMA is not set +# CONFIG_FSL_RCPM is not set CONFIG_FSNOTIFY=y CONFIG_FS_DAX=y CONFIG_FS_DAX_PMD=y @@ -2476,10 +2797,12 @@ CONFIG_FS_VERITY=y CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y # CONFIG_FS_VERITY_DEBUG is not set CONFIG_FTL=m +# CONFIG_FTM_QUADDEC is not set CONFIG_FTRACE=y CONFIG_FTRACE_MCOUNT_RECORD=y # CONFIG_FTRACE_STARTUP_TEST is not set CONFIG_FTRACE_SYSCALLS=y +CONFIG_FUJITSU_ERRATUM_010001=y CONFIG_FUJITSU_ES=m CONFIG_FUJITSU_LAPTOP=m CONFIG_FUJITSU_TABLET=m @@ -2527,9 +2850,11 @@ CONFIG_GART_IOMMU=y CONFIG_GCC_VERSION=100200 # CONFIG_GCOV_KERNEL is not set CONFIG_GDB_SCRIPTS=y +# CONFIG_GEMINI_ETHERNET is not set CONFIG_GENERIC_ADC_BATTERY=m CONFIG_GENERIC_ADC_THERMAL=m CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -2540,18 +2865,23 @@ CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_CPU=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IRQ_CHIP=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y @@ -2561,6 +2891,7 @@ CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_PTDUMP=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y @@ -2590,15 +2921,20 @@ CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_104_DIO_48E=m CONFIG_GPIO_104_IDIO_16=m CONFIG_GPIO_104_IDI_48=m +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set CONFIG_GPIO_ACPI=y +# CONFIG_GPIO_ADNP is not set CONFIG_GPIO_ADP5520=m CONFIG_GPIO_ADP5588=m CONFIG_GPIO_AGGREGATOR=m +# CONFIG_GPIO_ALTERA is not set CONFIG_GPIO_AMD8111=m CONFIG_GPIO_AMDPT=m CONFIG_GPIO_AMD_FCH=m CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_BD9571MWV=m +# CONFIG_GPIO_CADENCE is not set CONFIG_GPIO_CRYSTAL_COVE=y CONFIG_GPIO_DA9052=m CONFIG_GPIO_DA9055=m @@ -2606,13 +2942,18 @@ CONFIG_GPIO_DLN2=m CONFIG_GPIO_DWAPB=m CONFIG_GPIO_EXAR=m CONFIG_GPIO_F7188X=m +# CONFIG_GPIO_FTGPIO010 is not set CONFIG_GPIO_GENERIC=m CONFIG_GPIO_GENERIC_PLATFORM=m CONFIG_GPIO_GPIO_MM=m +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set CONFIG_GPIO_ICH=m CONFIG_GPIO_IT87=m CONFIG_GPIO_JANZ_TTL=m CONFIG_GPIO_KEMPLD=m +# CONFIG_GPIO_LOGICVC is not set CONFIG_GPIO_LP3943=m CONFIG_GPIO_LP873X=m CONFIG_GPIO_MADERA=m @@ -2624,6 +2965,8 @@ CONFIG_GPIO_MAX732X=m CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_MC33880=m CONFIG_GPIO_MENZ127=m +# CONFIG_GPIO_MLXBF is not set +# CONFIG_GPIO_MLXBF2 is not set CONFIG_GPIO_ML_IOH=m # CONFIG_GPIO_MOCKUP is not set CONFIG_GPIO_MSIC=y @@ -2634,11 +2977,15 @@ CONFIG_GPIO_PCF857X=m CONFIG_GPIO_PCIE_IDIO_24=m CONFIG_GPIO_PCI_IDIO_16=m CONFIG_GPIO_PISOSR=m +# CONFIG_GPIO_PL061 is not set CONFIG_GPIO_RC5T583=y CONFIG_GPIO_RDC321X=m +# CONFIG_GPIO_SAMA5D2_PIOBU is not set CONFIG_GPIO_SCH=m CONFIG_GPIO_SCH311X=m +# CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIOX=m +# CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_SYSFS=y CONFIG_GPIO_TPIC2810=m CONFIG_GPIO_TPS65086=m @@ -2652,12 +2999,15 @@ CONFIG_GPIO_TWL6040=m CONFIG_GPIO_UCB1400=m CONFIG_GPIO_VIPERBOARD=m CONFIG_GPIO_VX855=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WCD934X is not set CONFIG_GPIO_WHISKEY_COVE=m CONFIG_GPIO_WINBOND=m CONFIG_GPIO_WM831X=m CONFIG_GPIO_WM8350=m CONFIG_GPIO_WM8994=m CONFIG_GPIO_WS16C48=m +# CONFIG_GPIO_XGENE is not set CONFIG_GPIO_XILINX=m CONFIG_GPIO_XRA1403=m CONFIG_GRACE_PERIOD=m @@ -2691,11 +3041,14 @@ CONFIG_HABANA_AI=m CONFIG_HALTPOLL_CPUIDLE=m CONFIG_HAMACHI=m CONFIG_HAMRADIO=y +CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HANGCHECK_TIMER=m CONFIG_HAPPYMEAL=m CONFIG_HARDENED_USERCOPY=y CONFIG_HARDENED_USERCOPY_FALLBACK=y # CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDEN_EL2_VECTORS=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y CONFIG_HARDLOCKUP_DETECTOR=y @@ -2707,16 +3060,20 @@ CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_ARCH_COMPILER_H=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y @@ -2728,6 +3085,8 @@ CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y CONFIG_HAVE_ARCH_USERFAULTFD_WP=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y CONFIG_HAVE_CLK=y @@ -2737,6 +3096,7 @@ CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_BUGVERBOSE=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y @@ -2753,6 +3113,7 @@ CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y @@ -2790,6 +3151,7 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_NMI=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PATA_PLATFORM=y CONFIG_HAVE_PCI=y CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_HAVE_PERF_EVENTS=y @@ -2807,6 +3169,7 @@ CONFIG_HAVE_UID16=y CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HBMC_AM654 is not set CONFIG_HD44780=m CONFIG_HDC100X=m CONFIG_HDLC=m @@ -2948,13 +3311,25 @@ CONFIG_HID_ZYDACRON=m CONFIG_HIGH_RES_TIMERS=y CONFIG_HINIC=m CONFIG_HIO=m +# CONFIG_HIP04_ETH is not set # CONFIG_HIPPI is not set +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_HISILICON_ERRATUM_161600802=y +# CONFIG_HISI_DMA is not set +# CONFIG_HISI_FEMAC is not set +# CONFIG_HISI_PMU is not set CONFIG_HIST_TRIGGERS=y # CONFIG_HIST_TRIGGERS_DEBUG is not set +# CONFIG_HIX5HD2_GMAC is not set CONFIG_HMC425=m CONFIG_HMC6352=m CONFIG_HMEM_REPORTING=y CONFIG_HMM_MIRROR=y +# CONFIG_HMS_ANYBUSS_BUS is not set +# CONFIG_HNS3 is not set +# CONFIG_HNS_DSAF is not set +# CONFIG_HNS_ENET is not set +CONFIG_HOLES_IN_ZONE=y CONFIG_HOLTEK_FF=y CONFIG_HOSTAP=m CONFIG_HOSTAP_CS=m @@ -2992,6 +3367,7 @@ CONFIG_HSI_BOARDINFO=y CONFIG_HSI_CHAR=m CONFIG_HSR=m CONFIG_HSU_DMA=m +# CONFIG_HT16K33 is not set CONFIG_HTC_I2CPLD=y CONFIG_HTC_PASIC3=m CONFIG_HTS221=m @@ -3001,6 +3377,7 @@ CONFIG_HTU21=m CONFIG_HUAWEI_WMI=m CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y +# CONFIG_HVC_DCC is not set CONFIG_HVC_DRIVER=y CONFIG_HVC_IRQ=y CONFIG_HVC_XEN=y @@ -3012,8 +3389,12 @@ CONFIG_HWMON_VID=m CONFIG_HWPOISON_INJECT=m CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y +CONFIG_HW_PERF_EVENTS=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_AMD=m +CONFIG_HW_RANDOM_CAVIUM=y +# CONFIG_HW_RANDOM_CCTRNG is not set +CONFIG_HW_RANDOM_HISI_V2=y CONFIG_HW_RANDOM_INTEL=m CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_HW_RANDOM_TPM=y @@ -3047,7 +3428,9 @@ CONFIG_I2C_AMD756=m CONFIG_I2C_AMD756_S4882=m CONFIG_I2C_AMD8111=m # CONFIG_I2C_AMD_MP2 is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CADENCE is not set CONFIG_I2C_CBUS_GPIO=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHT_WC=m @@ -3056,6 +3439,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=m # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set CONFIG_I2C_DESIGNWARE_BAYTRAIL=y CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_PCI=m @@ -3076,18 +3460,22 @@ CONFIG_I2C_MLXCPLD=m CONFIG_I2C_MULTI_INSTANTIATE=m CONFIG_I2C_MUX=m CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_GPMUX is not set CONFIG_I2C_MUX_LTC4306=m CONFIG_I2C_MUX_MLXCPLD=m CONFIG_I2C_MUX_PCA9541=m CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set CONFIG_I2C_MUX_REG=m CONFIG_I2C_NFORCE2=m CONFIG_I2C_NFORCE2_S4985=m +# CONFIG_I2C_NOMADIK is not set CONFIG_I2C_NVIDIA_GPU=y CONFIG_I2C_OCORES=m CONFIG_I2C_PARPORT=m CONFIG_I2C_PCA_PLATFORM=m CONFIG_I2C_PIIX4=m +# CONFIG_I2C_RK3X is not set CONFIG_I2C_ROBOTFUZZ_OSIF=m CONFIG_I2C_SCMI=m CONFIG_I2C_SI470X=m @@ -3100,6 +3488,7 @@ CONFIG_I2C_SIS96X=m CONFIG_I2C_SMBUS=m CONFIG_I2C_STUB=m CONFIG_I2C_TAOS_EVM=m +# CONFIG_I2C_THUNDERX is not set CONFIG_I2C_TINY_USB=m CONFIG_I2C_VIA=m CONFIG_I2C_VIAPRO=m @@ -3173,6 +3562,8 @@ CONFIG_IIO_HRTIMER_TRIGGER=m CONFIG_IIO_INTERRUPT_TRIGGER=m CONFIG_IIO_KFIFO_BUF=m CONFIG_IIO_MS_SENSORS_I2C=m +# CONFIG_IIO_MUX is not set +# CONFIG_IIO_RESCALE is not set CONFIG_IIO_SIMPLE_DUMMY=m # CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set # CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set @@ -3234,6 +3625,7 @@ CONFIG_IMA_TRUSTED_KEYRING=y # CONFIG_IMA_WRITE_POLICY is not set CONFIG_IMG_ASCII_LCD=m CONFIG_INA2XX_ADC=m +# CONFIG_INDIRECT_PIO is not set CONFIG_INET=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m @@ -3296,11 +3688,31 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_INIT_STACK_NONE=y +CONFIG_INLINE_READ_LOCK=y +CONFIG_INLINE_READ_LOCK_BH=y +CONFIG_INLINE_READ_LOCK_IRQ=y +CONFIG_INLINE_READ_LOCK_IRQSAVE=y CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_BH=y CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_SPIN_LOCK=y +CONFIG_INLINE_SPIN_LOCK_BH=y +CONFIG_INLINE_SPIN_LOCK_IRQ=y +CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_INLINE_SPIN_TRYLOCK=y +CONFIG_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_BH=y CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_WRITE_LOCK=y +CONFIG_INLINE_WRITE_LOCK_BH=y +CONFIG_INLINE_WRITE_LOCK_IRQ=y +CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_BH=y CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_INOTIFY_USER=y CONFIG_INPUT=y CONFIG_INPUT_88PM80X_ONKEY=m @@ -3315,6 +3727,7 @@ CONFIG_INPUT_APANEL=m CONFIG_INPUT_ARIZONA_HAPTICS=m CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_ATLAS_BTNS=m +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_BMA150=m CONFIG_INPUT_CM109=m @@ -3472,6 +3885,8 @@ CONFIG_IOMMU_API=y CONFIG_IOMMU_DMA=y CONFIG_IOMMU_HELPER=y CONFIG_IOMMU_IOVA=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set CONFIG_IOMMU_SUPPORT=y CONFIG_IONIC=m CONFIG_IOSCHED_BFQ=m @@ -3641,6 +4056,7 @@ CONFIG_IP_VS_WRR=m CONFIG_IQS620AT_TEMP=m CONFIG_IQS621_ALS=m CONFIG_IQS624_POS=m +CONFIG_IRQCHIP=y # CONFIG_IRQSOFF_TRACER is not set CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_IRQ_DOMAIN=y @@ -3654,6 +4070,9 @@ CONFIG_IRQ_REMAP=y CONFIG_IRQ_WORK=y CONFIG_IR_ENE=m CONFIG_IR_FINTEK=m +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_GPIO_TX is not set +# CONFIG_IR_HIX5HD2 is not set CONFIG_IR_IGORPLUGUSB=m CONFIG_IR_IGUANA=m CONFIG_IR_IMON=m @@ -3665,6 +4084,7 @@ CONFIG_IR_MCEUSB=m CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m CONFIG_IR_NUVOTON=m +# CONFIG_IR_PWM_TX is not set CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_RCMM_DECODER=m @@ -3675,6 +4095,7 @@ CONFIG_IR_SERIAL_TRANSMITTER=y CONFIG_IR_SHARP_DECODER=m CONFIG_IR_SIR=m CONFIG_IR_SONY_DECODER=m +# CONFIG_IR_SPI is not set CONFIG_IR_STREAMZAP=m CONFIG_IR_TTUSBIR=m CONFIG_IR_WINBOND_CIR=m @@ -3805,12 +4226,14 @@ CONFIG_KEMPLD_WDT=m CONFIG_KERNEL_LZ4=y # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_MODE_NEON=y # CONFIG_KERNEL_XZ is not set CONFIG_KERNFS=y CONFIG_KEXEC=y CONFIG_KEXEC_BZIMAGE_VERIFY_SIG=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_KEXEC_JUMP=y CONFIG_KEXEC_SIG=y # CONFIG_KEXEC_SIG_FORCE is not set @@ -3820,6 +4243,8 @@ CONFIG_KEYBOARD_ADP5588=m CONFIG_KEYBOARD_ADP5589=m CONFIG_KEYBOARD_APPLESPI=m CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set CONFIG_KEYBOARD_CROS_EC=m CONFIG_KEYBOARD_DLINK_DIR685=m CONFIG_KEYBOARD_GPIO=m @@ -3834,6 +4259,7 @@ CONFIG_KEYBOARD_MCS=m CONFIG_KEYBOARD_MPR121=m # CONFIG_KEYBOARD_MTK_PMIC is not set CONFIG_KEYBOARD_NEWTON=m +# CONFIG_KEYBOARD_OMAP4 is not set CONFIG_KEYBOARD_OPENCORES=m CONFIG_KEYBOARD_QT1050=m CONFIG_KEYBOARD_QT1070=m @@ -3877,7 +4303,7 @@ CONFIG_KS8851_MLL=m CONFIG_KSM=y CONFIG_KSZ884X_PCI=m # CONFIG_KUNIT is not set -CONFIG_KVM=m +CONFIG_KUSER_HELPERS=y CONFIG_KVM_AMD=m # CONFIG_KVM_AMD_SEV is not set CONFIG_KVM_ASYNC_PF=y @@ -3922,20 +4348,30 @@ CONFIG_LDISC_AUTOLOAD=y CONFIG_LDM_PARTITION=y CONFIG_LD_VERSION=235010000 CONFIG_LEDS_88PM860X=m +# CONFIG_LEDS_AAT1290 is not set CONFIG_LEDS_ADP5520=m +# CONFIG_LEDS_AN30259A is not set CONFIG_LEDS_APU=m CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set CONFIG_LEDS_BD2802=m CONFIG_LEDS_BLINKM=m CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=m CONFIG_LEDS_CLEVO_MAIL=m +# CONFIG_LEDS_CR0014114 is not set CONFIG_LEDS_DA903X=m CONFIG_LEDS_DA9052=m CONFIG_LEDS_DAC124S085=m +# CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m CONFIG_LEDS_INTEL_SS4200=m +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_KTD2692 is not set CONFIG_LEDS_LM3530=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_LM3533=m @@ -3943,6 +4379,8 @@ CONFIG_LEDS_LM355x=m CONFIG_LEDS_LM3601X=m CONFIG_LEDS_LM36274=m CONFIG_LEDS_LM3642=m +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3697 is not set CONFIG_LEDS_LP3944=m CONFIG_LEDS_LP3952=m CONFIG_LEDS_LP5521=m @@ -3951,6 +4389,9 @@ CONFIG_LEDS_LP5562=m CONFIG_LEDS_LP55XX_COMMON=m CONFIG_LEDS_LP8501=m CONFIG_LEDS_LP8788=m +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_MAX77693 is not set CONFIG_LEDS_MAX8997=m CONFIG_LEDS_MC13783=m CONFIG_LEDS_MENF21BMC=m @@ -3966,6 +4407,8 @@ CONFIG_LEDS_PCA963X=m CONFIG_LEDS_PWM=m CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_SGM3140=m +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SYSCON is not set CONFIG_LEDS_TCA6507=m CONFIG_LEDS_TI_LMU_COMMON=m CONFIG_LEDS_TLC591XX=m @@ -4015,6 +4458,7 @@ CONFIG_LIBERTAS_THINFIRM_USB=m CONFIG_LIBERTAS_USB=m CONFIG_LIBFC=m CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y CONFIG_LIBIPW=m # CONFIG_LIBIPW_DEBUG is not set CONFIG_LIBNVDIMM=y @@ -4109,6 +4553,7 @@ CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set CONFIG_MANAGER_SBS=m CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_MANTIS_CORE=m @@ -4130,6 +4575,7 @@ CONFIG_MAX517=m CONFIG_MAX5432=m CONFIG_MAX5481=m CONFIG_MAX5487=m +# CONFIG_MAX5821 is not set CONFIG_MAX63XX_WATCHDOG=m CONFIG_MAX8925_POWER=m CONFIG_MAX9611=m @@ -4156,11 +4602,18 @@ CONFIG_MDIO=m CONFIG_MDIO_BCM_UNIMAC=m CONFIG_MDIO_BITBANG=m CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set CONFIG_MDIO_CAVIUM=m CONFIG_MDIO_DEVICE=y CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set CONFIG_MDIO_MSCC_MIIM=y CONFIG_MDIO_MVUSB=m +# CONFIG_MDIO_OCTEON is not set CONFIG_MDIO_THUNDER=m CONFIG_MDIO_XPCS=m CONFIG_MD_AUTODETECT=y @@ -4270,15 +4723,20 @@ CONFIG_MFD_88PM800=m CONFIG_MFD_88PM805=m CONFIG_MFD_88PM860X=y CONFIG_MFD_AAT2870_CORE=y +# CONFIG_MFD_ACT8945A is not set CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=m CONFIG_MFD_ARIZONA_SPI=m CONFIG_MFD_AS3711=y +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set CONFIG_MFD_AXP20X=m CONFIG_MFD_AXP20X_I2C=m CONFIG_MFD_BCM590XX=m CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC=m CONFIG_MFD_CROS_EC_DEV=m CONFIG_MFD_CS47L15=y @@ -4294,6 +4752,8 @@ CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=y CONFIG_MFD_DA9150=m CONFIG_MFD_DLN2=m +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set CONFIG_MFD_INTEL_LPSS=m CONFIG_MFD_INTEL_LPSS_ACPI=m CONFIG_MFD_INTEL_LPSS_PCI=m @@ -4304,12 +4764,16 @@ CONFIG_MFD_IQS62X=m CONFIG_MFD_JANZ_CMODIO=m CONFIG_MFD_KEMPLD=m CONFIG_MFD_LM3533=m +# CONFIG_MFD_LOCHNAGAR is not set CONFIG_MFD_LP3943=m CONFIG_MFD_LP8788=y CONFIG_MFD_MADERA=m CONFIG_MFD_MADERA_I2C=m CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_MAX14577=y +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX77843=y CONFIG_MFD_MAX8907=m @@ -4328,6 +4792,11 @@ CONFIG_MFD_PCF50633=m CONFIG_MFD_RC5T583=y CONFIG_MFD_RDC321X=m CONFIG_MFD_RETU=m +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set CONFIG_MFD_RT5033=m CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SI476X_CORE=m @@ -4335,12 +4804,19 @@ CONFIG_MFD_SKY81452=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SMSC=y +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_TI_LMU=m CONFIG_MFD_TI_LP873X=m +# CONFIG_MFD_TI_LP87565 is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65090=y +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=y @@ -4369,6 +4845,7 @@ CONFIG_MHI_BUS=m CONFIG_MICREL_KS8995MA=m CONFIG_MICREL_PHY=m CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_PIT64B is not set CONFIG_MICROCHIP_T1_PHY=m CONFIG_MICROCODE=y CONFIG_MICROCODE_AMD=y @@ -4425,6 +4902,8 @@ CONFIG_MLX5_SW_STEERING=y CONFIG_MLX5_TC_CT=y CONFIG_MLX90614=m CONFIG_MLX90632=m +# CONFIG_MLXBF_BOOTCTL is not set +# CONFIG_MLXBF_TMFIFO is not set CONFIG_MLXFW=m CONFIG_MLXREG_HOTPLUG=y CONFIG_MLXREG_IO=y @@ -4452,11 +4931,13 @@ CONFIG_MMC=y CONFIG_MMC35240=m CONFIG_MMCONF_FAM10H=y CONFIG_MMC_ALCOR=m +# CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_MINORS=8 CONFIG_MMC_CB710=m CONFIG_MMC_CQHCI=m # CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW is not set # CONFIG_MMC_HSQ is not set CONFIG_MMC_MTK=m CONFIG_MMC_REALTEK_PCI=m @@ -4464,8 +4945,16 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI=m CONFIG_MMC_SDHCI_ACPI=m +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MMC_SDHCI_CADENCE is not set CONFIG_MMC_SDHCI_F_SDH30=m CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_OMAP is not set CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_SDHCI_PLTFM=m CONFIG_MMC_SDHCI_XENON=m @@ -4510,6 +4999,7 @@ CONFIG_MODVERSIONS=y CONFIG_MOST=m CONFIG_MOST_CDEV=m CONFIG_MOST_COMPONENTS=m +# CONFIG_MOST_DIM2 is not set CONFIG_MOST_I2C=m CONFIG_MOST_NET=m CONFIG_MOST_SOUND=m @@ -4544,6 +5034,7 @@ CONFIG_MOUSE_SYNAPTICS_USB=m CONFIG_MOUSE_VSXXXAA=m CONFIG_MOXA_INTELLIO=m CONFIG_MOXA_SMARTIO=m +# CONFIG_MOXTET is not set CONFIG_MP2629_ADC=m CONFIG_MPILIB=y CONFIG_MPL115=m @@ -4567,6 +5058,7 @@ CONFIG_MS5611_I2C=m CONFIG_MS5611_SPI=m CONFIG_MS5637=m CONFIG_MSCC_OCELOT_SWITCH=y +# CONFIG_MSCC_OCELOT_SWITCH_OCELOT is not set CONFIG_MSDOS_FS=m CONFIG_MSDOS_PARTITION=y CONFIG_MSI_LAPTOP=m @@ -4594,6 +5086,7 @@ CONFIG_MTD=m CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTD_ABSENT=m +# CONFIG_MTD_AFS_PARTS is not set CONFIG_MTD_AMD76XROM=m CONFIG_MTD_AR7_PARTS=m CONFIG_MTD_BLKDEVS=m @@ -4629,9 +5122,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MCHP23K256=m CONFIG_MTD_MTDRAM=m CONFIG_MTD_NAND_ARASAN=m +# CONFIG_MTD_NAND_BRCMNAND is not set +# CONFIG_MTD_NAND_CADENCE is not set CONFIG_MTD_NAND_CAFE=m CONFIG_MTD_NAND_CORE=m CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_DT is not set CONFIG_MTD_NAND_DENALI_PCI=m CONFIG_MTD_NAND_DISKONCHIP=m # CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set @@ -4646,6 +5142,7 @@ CONFIG_MTD_NAND_NANDSIM=m CONFIG_MTD_NAND_PLATFORM=m CONFIG_MTD_NAND_RICOH=m CONFIG_MTD_NETtel=m +CONFIG_MTD_OF_PARTS=m CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_ONENAND_GENERIC=m @@ -4660,6 +5157,7 @@ CONFIG_MTD_PHRAM=m CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set +# CONFIG_MTD_PHYSMAP_OF is not set CONFIG_MTD_PLATRAM=m CONFIG_MTD_PMC551=m # CONFIG_MTD_PMC551_BUGFIX is not set @@ -4700,7 +5198,9 @@ CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_MUX_ADG792A=m CONFIG_MUX_ADGS1408=m CONFIG_MUX_GPIO=m +# CONFIG_MUX_MMIO is not set CONFIG_MVMDIO=m +# CONFIG_MV_XOR_V2 is not set CONFIG_MWAVE=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_PCIE=m @@ -5025,6 +5525,7 @@ CONFIG_NET_VENDOR_EMULEX=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_FUJITSU=y CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y @@ -5316,7 +5817,6 @@ CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y # CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=8192 CONFIG_NR_CPUS_DEFAULT=8192 CONFIG_NR_CPUS_RANGE_BEGIN=8192 CONFIG_NR_CPUS_RANGE_END=8192 @@ -5347,6 +5847,7 @@ CONFIG_NVDIMM_KEYS=y CONFIG_NVDIMM_PFN=y CONFIG_NVM=y CONFIG_NVMEM=y +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_NVMEM_SPMI_SDAM=m CONFIG_NVMEM_SYSFS=y CONFIG_NVME_CORE=m @@ -5376,7 +5877,23 @@ CONFIG_OCFS2_FS=m CONFIG_OCFS2_FS_O2CB=m CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -# CONFIG_OF is not set +# CONFIG_OCTEONTX2_AF is not set +# CONFIG_OCTEONTX2_PF is not set +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +# CONFIG_OF_FPGA_REGION is not set +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_NUMA=y +# CONFIG_OF_OVERLAY is not set +CONFIG_OF_PMEM=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_UNITTEST is not set CONFIG_OID_REGISTRY=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OMFS_FS=m @@ -5388,6 +5905,7 @@ CONFIG_OPROFILE=m # CONFIG_OPROFILE_EVENT_MULTIPLEX is not set CONFIG_OPROFILE_NMI_TIMER=y CONFIG_OPT3001=m +# CONFIG_OPTEE is not set CONFIG_OPTPROBES=y CONFIG_ORANGEFS_FS=m CONFIG_ORINOCO_USB=m @@ -5468,6 +5986,7 @@ CONFIG_PARPORT_PC_PCMCIA=m # CONFIG_PARPORT_PC_SUPERIO is not set CONFIG_PARPORT_SERIAL=m CONFIG_PARTITION_ADVANCED=y +CONFIG_PARTITION_PERCPU=y CONFIG_PATA_ACPI=m CONFIG_PATA_ALI=m CONFIG_PATA_AMD=m @@ -5493,6 +6012,7 @@ CONFIG_PATA_NETCELL=m CONFIG_PATA_NINJA32=m CONFIG_PATA_NS87410=m CONFIG_PATA_NS87415=m +# CONFIG_PATA_OF_PLATFORM is not set CONFIG_PATA_OLDPIIX=m CONFIG_PATA_OPTI=m CONFIG_PATA_OPTIDMA=m @@ -5531,7 +6051,11 @@ CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set CONFIG_PCIEPORTBUS=y +# CONFIG_PCIE_AL is not set +# CONFIG_PCIE_ALTERA is not set # CONFIG_PCIE_BW is not set +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set CONFIG_PCIE_DPC=y CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y @@ -5539,8 +6063,11 @@ CONFIG_PCIE_DW_HOST=y # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCIE_ECRC is not set # CONFIG_PCIE_EDR is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set CONFIG_PCIE_PME=y CONFIG_PCIE_PTM=y +# CONFIG_PCIE_XILINX is not set CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_ATMEL=m CONFIG_PCI_ATS=y @@ -5548,10 +6075,17 @@ CONFIG_PCI_ATS=y # CONFIG_PCI_DEBUG is not set CONFIG_PCI_DIRECT=y CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_PCI_EPF_TEST is not set +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set CONFIG_PCI_HYPERV=m CONFIG_PCI_HYPERV_INTERFACE=m CONFIG_PCI_IOV=y @@ -5569,7 +6103,9 @@ CONFIG_PCI_QUIRKS=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=m CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_PCI_SYSCALL=y CONFIG_PCI_XEN=y +# CONFIG_PCI_XGENE is not set CONFIG_PCMCIA=m CONFIG_PCMCIA_3C574=m CONFIG_PCMCIA_3C589=m @@ -5603,7 +6139,6 @@ CONFIG_PERF_EVENTS_INTEL_CSTATE=m CONFIG_PERF_EVENTS_INTEL_RAPL=m CONFIG_PERF_EVENTS_INTEL_UNCORE=y CONFIG_PERSISTENT_KEYRINGS=y -CONFIG_PGTABLE_LEVELS=5 CONFIG_PHANTOM=m CONFIG_PHONET=m CONFIG_PHYLIB=y @@ -5611,19 +6146,30 @@ CONFIG_PHYLINK=m CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_PHYSICAL_START=0x1000000 CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_TORRENT is not set CONFIG_PHY_CPCAP_USB=m +# CONFIG_PHY_FSL_IMX8MQ_USB is not set CONFIG_PHY_INTEL_EMMC=m +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=m CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_QCOM_USB_HSIC=m CONFIG_PHY_SAMSUNG_USB2=m CONFIG_PHY_TUSB1210=m +# CONFIG_PHY_XGENE is not set CONFIG_PI433=m +# CONFIG_PID_IN_CONTEXTIDR is not set CONFIG_PID_NS=y CONFIG_PINCONF=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AMD=y +# CONFIG_PINCTRL_AXP209 is not set CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=y @@ -5645,6 +6191,10 @@ CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MCP23S08_I2C=m CONFIG_PINCTRL_MCP23S08_SPI=m +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_PALMAS is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_SUNRISEPOINT=m CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_TIGERLAKE=m @@ -5653,6 +6203,9 @@ CONFIG_PINMUX=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set CONFIG_PLATFORM_SI4713=m CONFIG_PLIP=m CONFIG_PLX_DMA=m @@ -5672,6 +6225,7 @@ CONFIG_PM_DEBUG=y CONFIG_PM_DEVFREQ=y CONFIG_PM_DEVFREQ_EVENT=y CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_NOTIFIER_ERROR_INJECT=m CONFIG_PM_OPP=y @@ -5697,8 +6251,15 @@ CONFIG_POSIX_TIMERS=y CONFIG_POWERCAP=y CONFIG_POWER_AVS=y CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set CONFIG_POWER_RESET_MT6323=y CONFIG_POWER_RESET_RESTART=y +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -5794,6 +6355,7 @@ CONFIG_PWM=y CONFIG_PWM_CRC=y CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_FSL_FTM is not set CONFIG_PWM_IQS620A=m CONFIG_PWM_LP3943=m CONFIG_PWM_LPSS=m @@ -5803,10 +6365,19 @@ CONFIG_PWM_PCA9685=m CONFIG_PWM_SYSFS=y CONFIG_PWM_TWL=m CONFIG_PWM_TWL_LED=m +CONFIG_PWRSEQ_EMMC=y +# CONFIG_PWRSEQ_SD8787 is not set +CONFIG_PWRSEQ_SIMPLE=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set CONFIG_QCOM_CPR=m CONFIG_QCOM_EMAC=m +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y CONFIG_QCOM_HIDMA=m CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_QDF2400_ERRATUM_0065=y CONFIG_QCOM_SPMI_ADC5=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m @@ -5841,6 +6412,7 @@ CONFIG_QTNFMAC=m CONFIG_QTNFMAC_PCIE=m CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y +# CONFIG_QUICC_ENGINE is not set CONFIG_QUOTA=y CONFIG_QUOTACTL=y CONFIG_QUOTACTL_COMPAT=y @@ -5871,6 +6443,7 @@ CONFIG_RAID_ATTRS=m CONFIG_RANDOMIZE_BASE=y CONFIG_RANDOMIZE_MEMORY=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y CONFIG_RANDOM_TRUST_BOOTLOADER=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RAPIDIO=y @@ -5958,6 +6531,7 @@ CONFIG_REGULATOR_DA903X=m CONFIG_REGULATOR_DA9052=m CONFIG_REGULATOR_DA9055=m CONFIG_REGULATOR_DA9062=m +# CONFIG_REGULATOR_DA9063 is not set CONFIG_REGULATOR_DA9210=m CONFIG_REGULATOR_DA9211=m # CONFIG_REGULATOR_DEBUG is not set @@ -5970,6 +6544,7 @@ CONFIG_REGULATOR_LM363X=m CONFIG_REGULATOR_LP3971=m CONFIG_REGULATOR_LP3972=m CONFIG_REGULATOR_LP872X=m +# CONFIG_REGULATOR_LP873X is not set CONFIG_REGULATOR_LP8755=m CONFIG_REGULATOR_LP8788=m CONFIG_REGULATOR_LTC3589=m @@ -5983,12 +6558,17 @@ CONFIG_REGULATOR_MAX8660=m CONFIG_REGULATOR_MAX8907=m CONFIG_REGULATOR_MAX8925=m CONFIG_REGULATOR_MAX8952=m +# CONFIG_REGULATOR_MAX8973 is not set CONFIG_REGULATOR_MAX8997=m CONFIG_REGULATOR_MAX8998=m CONFIG_REGULATOR_MC13783=m CONFIG_REGULATOR_MC13892=m CONFIG_REGULATOR_MC13XXX_CORE=m +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set CONFIG_REGULATOR_MP8859=m +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set CONFIG_REGULATOR_MT6311=m CONFIG_REGULATOR_MT6323=m CONFIG_REGULATOR_MT6358=m @@ -6009,6 +6589,8 @@ CONFIG_REGULATOR_S2MPS11=m CONFIG_REGULATOR_S5M8767=m CONFIG_REGULATOR_SKY81452=m CONFIG_REGULATOR_SLG51000=m +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set CONFIG_REGULATOR_TPS51632=m CONFIG_REGULATOR_TPS6105X=m CONFIG_REGULATOR_TPS62360=m @@ -6024,6 +6606,7 @@ CONFIG_REGULATOR_TPS65912=m CONFIG_REGULATOR_TPS80031=m CONFIG_REGULATOR_TWL4030=m CONFIG_REGULATOR_USERSPACE_CONSUMER=m +# CONFIG_REGULATOR_VCTRL is not set CONFIG_REGULATOR_VIRTUAL_CONSUMER=m CONFIG_REGULATOR_WM831X=m CONFIG_REGULATOR_WM8350=m @@ -6042,6 +6625,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_BRCMSTB_RESCAL=y CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_TI_SYSCON=m CONFIG_RETPOLINE=y CONFIG_RETU_WATCHDOG=m @@ -6076,6 +6660,7 @@ CONFIG_RMNET=m CONFIG_ROCKCHIP_PHY=m CONFIG_ROCKER=m CONFIG_ROCKETPORT=m +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_ROMFS_BACKED_BY_BLOCK=y # CONFIG_ROMFS_BACKED_BY_BOTH is not set # CONFIG_ROMFS_BACKED_BY_MTD is not set @@ -6135,6 +6720,7 @@ CONFIG_RTC_DRV_ABEOZ9=m CONFIG_RTC_DRV_ABX80X=m CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_BQ4802=m +# CONFIG_RTC_DRV_CADENCE is not set CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_CROS_EC is not set CONFIG_RTC_DRV_DA9052=m @@ -6163,11 +6749,14 @@ CONFIG_RTC_DRV_DS1742=m CONFIG_RTC_DRV_DS2404=m CONFIG_RTC_DRV_DS3232=m CONFIG_RTC_DRV_DS3232_HWMON=y +# CONFIG_RTC_DRV_EFI is not set CONFIG_RTC_DRV_EM3027=m CONFIG_RTC_DRV_FM3130=m CONFIG_RTC_DRV_FTRTC010=m CONFIG_RTC_DRV_HID_SENSOR_TIME=m +# CONFIG_RTC_DRV_HYM8563 is not set CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12026 is not set CONFIG_RTC_DRV_ISL1208=m CONFIG_RTC_DRV_LP8788=m CONFIG_RTC_DRV_M41T80=m @@ -6198,6 +6787,9 @@ CONFIG_RTC_DRV_PCF8523=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_PCF8563=m CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_R7301 is not set CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RC5T583=m CONFIG_RTC_DRV_RP5C01=m @@ -6220,11 +6812,13 @@ CONFIG_RTC_DRV_STK17TA8=m CONFIG_RTC_DRV_TPS6586X=m CONFIG_RTC_DRV_TPS65910=m CONFIG_RTC_DRV_TPS80031=m +# CONFIG_RTC_DRV_TWL4030 is not set CONFIG_RTC_DRV_V3020=m CONFIG_RTC_DRV_WILCO_EC=m CONFIG_RTC_DRV_WM831X=m CONFIG_RTC_DRV_WM8350=m CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_I2C_AND_SPI=y @@ -6369,6 +6963,7 @@ CONFIG_SCSI_FDOMAIN=m CONFIG_SCSI_FDOMAIN_PCI=m CONFIG_SCSI_FLASHPOINT=y CONFIG_SCSI_GDTH=m +# CONFIG_SCSI_HISI_SAS is not set CONFIG_SCSI_HPSA=m CONFIG_SCSI_HPTIOP=m CONFIG_SCSI_IMM=m @@ -6442,6 +7037,7 @@ CONFIG_SDIO_UART=m # CONFIG_SDMA_VERBOSITY is not set CONFIG_SDR_MAX2175=m CONFIG_SDR_PLATFORM_DRIVERS=y +# CONFIG_SD_ADC_MODULATOR is not set CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y CONFIG_SECONDARY_TRUSTED_KEYRING=y @@ -6543,6 +7139,7 @@ CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=m CONFIG_SENSORS_GL518SM=m CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set CONFIG_SENSORS_HDAPS=m CONFIG_SENSORS_HIH6130=m CONFIG_SENSORS_HMC5843=m @@ -6633,11 +7230,13 @@ CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m CONFIG_SENSORS_NTC_THERMISTOR=m +# CONFIG_SENSORS_OCC_P8_I2C is not set CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m CONFIG_SENSORS_PCF8591=m CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PWM_FAN is not set CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m @@ -6692,6 +7291,7 @@ CONFIG_SENSORS_XGENE=m CONFIG_SENSORS_ZL6100=m CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_16550A_VARIANTS=y +# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CS=m # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -6702,6 +7302,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_EXAR=m CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_FINTEK=y +CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_LPSS=m CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_MEN_MCB=m @@ -6717,13 +7318,17 @@ CONFIG_SERIAL_ALTERA_JTAGUART=m CONFIG_SERIAL_ALTERA_UART=m CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set CONFIG_SERIAL_ARC=m CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set CONFIG_SERIAL_FSL_LINFLEXUART=m CONFIG_SERIAL_FSL_LPUART=m # CONFIG_SERIAL_IFX6X60 is not set @@ -6736,6 +7341,7 @@ CONFIG_SERIAL_MAX310X=y CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_MEN_Z135=m CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_SERIAL_RP2=m CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_SC16IS7XX=m @@ -6744,11 +7350,15 @@ CONFIG_SERIAL_SC16IS7XX_I2C=y CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_SERIAL_SCCNXP=y CONFIG_SERIAL_SCCNXP_CONSOLE=y +# CONFIG_SERIAL_SIFIVE is not set CONFIG_SERIAL_SPRD=m CONFIG_SERIAL_UARTLITE=m CONFIG_SERIAL_UARTLITE_NR_UARTS=1 +# CONFIG_SERIAL_XILINX_PS_UART is not set CONFIG_SERIO=y CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set CONFIG_SERIO_ARC_PS2=m CONFIG_SERIO_CT82C710=m CONFIG_SERIO_GPIO_PS2=m @@ -6784,6 +7394,7 @@ CONFIG_SI7020=m CONFIG_SIGNALFD=y CONFIG_SIGNATURE=y CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIMPLE_PM_BUS is not set CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m CONFIG_SIS190=m @@ -6816,6 +7427,7 @@ CONFIG_SLUB_MEMCG_SYSFS_ON=y # CONFIG_SLUB_STATS is not set CONFIG_SMARTJOYPLUS_FF=y CONFIG_SMC=m +# CONFIG_SMC91X is not set CONFIG_SMC_DIAG=m CONFIG_SMP=y CONFIG_SMSC37B787_WDT=m @@ -6845,6 +7457,7 @@ CONFIG_SND_ATMEL_SOC=m CONFIG_SND_AU8810=m CONFIG_SND_AU8820=m CONFIG_SND_AU8830=m +# CONFIG_SND_AUDIO_GRAPH_CARD is not set CONFIG_SND_AW2=m CONFIG_SND_AZT3328=m CONFIG_SND_BCD2000=m @@ -7106,6 +7719,7 @@ CONFIG_SND_SOC_MAX98504=m CONFIG_SND_SOC_MAX9860=m CONFIG_SND_SOC_MAX9867=m CONFIG_SND_SOC_MAX98927=m +# CONFIG_SND_SOC_MIKROE_PROTO is not set CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_MT6351=m @@ -7189,6 +7803,7 @@ CONFIG_SND_SOC_SOF_JASPERLAKE=m CONFIG_SND_SOC_SOF_JASPERLAKE_SUPPORT=y CONFIG_SND_SOC_SOF_MERRIFIELD=m CONFIG_SND_SOC_SOF_MERRIFIELD_SUPPORT=y +# CONFIG_SND_SOC_SOF_OF is not set CONFIG_SND_SOC_SOF_PCI=m CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y CONFIG_SND_SOC_SOF_TIGERLAKE=m @@ -7294,7 +7909,9 @@ CONFIG_SND_VX_LIB=m CONFIG_SND_X86=y CONFIG_SND_XEN_FRONTEND=m CONFIG_SND_YMFPCI=m +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y CONFIG_SOCK_CGROUP_DATA=y +# CONFIG_SOC_BRCMSTB is not set CONFIG_SOC_TI=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_SOFT_WATCHDOG=m @@ -7333,6 +7950,7 @@ CONFIG_SPI_AXI_SPI_ENGINE=m CONFIG_SPI_BITBANG=m CONFIG_SPI_BUTTERFLY=m CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DEBUG is not set CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DLN2=m @@ -7340,7 +7958,9 @@ CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_MMIO=m CONFIG_SPI_DW_PCI=m CONFIG_SPI_DYNAMIC=y +# CONFIG_SPI_FSL_SPI is not set CONFIG_SPI_GPIO=m +# CONFIG_SPI_HISI_SFC_V3XX is not set # CONFIG_SPI_INTEL_SPI_PCI is not set # CONFIG_SPI_INTEL_SPI_PLATFORM is not set CONFIG_SPI_LM70_LLP=m @@ -7351,6 +7971,7 @@ CONFIG_SPI_MUX=m # CONFIG_SPI_MXIC is not set CONFIG_SPI_NXP_FLEXSPI=m CONFIG_SPI_OC_TINY=m +# CONFIG_SPI_PL022 is not set CONFIG_SPI_PXA2XX=m CONFIG_SPI_PXA2XX_PCI=m # CONFIG_SPI_ROCKCHIP is not set @@ -7360,6 +7981,7 @@ CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m CONFIG_SPI_SLAVE_TIME=m CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_THUNDERX is not set CONFIG_SPI_TLE62X0=m CONFIG_SPI_XCOMM=m # CONFIG_SPI_XILINX is not set @@ -7402,6 +8024,7 @@ CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SPROM=y CONFIG_SSFDC=m CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_STACKTRACE=y CONFIG_STACKTRACE_SUPPORT=y @@ -7409,6 +8032,7 @@ CONFIG_STACK_TRACER=y CONFIG_STACK_VALIDATION=y CONFIG_STAGING=y CONFIG_STAGING_APEX_DRIVER=y +# CONFIG_STAGING_BOARD is not set CONFIG_STAGING_GASKET_FRAMEWORK=y CONFIG_STAGING_MEDIA=y # CONFIG_STANDALONE is not set @@ -7476,6 +8100,7 @@ CONFIG_SYNC_FILE=y CONFIG_SYNTH_EVENTS=y # CONFIG_SYNTH_EVENT_GEN_TEST is not set CONFIG_SYN_COOKIES=y +# CONFIG_SYSCON_REBOOT_MODE is not set CONFIG_SYSCTL=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYSFS=y @@ -7496,6 +8121,7 @@ CONFIG_SYSVIPC_COMPAT=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_SYSV_FS=m CONFIG_SYS_HYPERVISOR=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_T5403=m CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_TABLET_USB_ACECAD=m @@ -7584,6 +8210,8 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +CONFIG_THERMAL_OF=y # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THINKPAD_ACPI=m @@ -7607,6 +8235,9 @@ CONFIG_TIFM_CORE=m CONFIG_TIGON3=m CONFIG_TIGON3_HWMON=y CONFIG_TIMERFD=y +CONFIG_TIMER_ACPI=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y CONFIG_TIME_NS=y # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -7629,7 +8260,10 @@ CONFIG_TI_ADC12138=m CONFIG_TI_ADC128S052=m CONFIG_TI_ADC161S626=m CONFIG_TI_ADS1015=m +# CONFIG_TI_ADS124S08 is not set CONFIG_TI_ADS7950=m +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set CONFIG_TI_AM335X_ADC=m # CONFIG_TI_CPSW_PHY_SEL is not set CONFIG_TI_DAC082S085=m @@ -7660,11 +8294,13 @@ CONFIG_TOUCHSCREEN_AD7879_I2C=m CONFIG_TOUCHSCREEN_AD7879_SPI=m CONFIG_TOUCHSCREEN_ADC=m CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y CONFIG_TOUCHSCREEN_AUO_PIXCIR=m CONFIG_TOUCHSCREEN_BU21013=m CONFIG_TOUCHSCREEN_BU21029=y +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m CONFIG_TOUCHSCREEN_CY8CTMA140=m CONFIG_TOUCHSCREEN_CY8CTMG110=m @@ -7680,6 +8316,7 @@ CONFIG_TOUCHSCREEN_DA9052=m CONFIG_TOUCHSCREEN_DYNAPRO=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m CONFIG_TOUCHSCREEN_EKTF2127=m CONFIG_TOUCHSCREEN_ELAN=y @@ -7691,6 +8328,7 @@ CONFIG_TOUCHSCREEN_GUNZE=m CONFIG_TOUCHSCREEN_HAMPSHIRE=m CONFIG_TOUCHSCREEN_HIDEEP=m CONFIG_TOUCHSCREEN_ILI210X=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set CONFIG_TOUCHSCREEN_INEXIO=m CONFIG_TOUCHSCREEN_IQS5XX=m CONFIG_TOUCHSCREEN_MAX11801=m @@ -7838,6 +8476,7 @@ CONFIG_UCSI_CCG=m CONFIG_UDF_FS=m # CONFIG_UDMABUF is not set CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_ARM=y CONFIG_UEFI_CPER_X86=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" @@ -7871,6 +8510,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_UNIX_DIAG=m CONFIG_UNIX_SCM=y +CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_UNUSED_SYMBOLS=y CONFIG_UNWINDER_FRAME_POINTER=y # CONFIG_UNWINDER_GUESS is not set @@ -7916,8 +8556,10 @@ CONFIG_USB_CHAOSKEY=m CONFIG_USB_CHIPIDEA=m CONFIG_USB_CHIPIDEA_GENERIC=m CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_IMX=m CONFIG_USB_CHIPIDEA_MSM=m CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_TEGRA=m CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_COMMON=y CONFIG_USB_CONFIGFS=m @@ -7958,6 +8600,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y # CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_HAPS=m # CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_OF_SIMPLE=m CONFIG_USB_DWC3_PCI=m CONFIG_USB_DWC3_ULPI=y CONFIG_USB_DYNAMIC_MINORS=y @@ -8011,6 +8654,7 @@ CONFIG_USB_GADGETFS=m CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 CONFIG_USB_GADGET_TARGET=m CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set CONFIG_USB_GL860=m CONFIG_USB_GOKU=m CONFIG_USB_GPIO_VBUS=m @@ -8249,6 +8893,7 @@ CONFIG_USB_SL811_CS=m CONFIG_USB_SL811_HCD=m CONFIG_USB_SL811_HCD_ISO=y CONFIG_USB_SNP_CORE=m +# CONFIG_USB_SNP_UDC_PLAT is not set CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_STKWEBCAM=m CONFIG_USB_STORAGE=m @@ -8275,6 +8920,7 @@ CONFIG_USB_U132_HCD=m CONFIG_USB_UAS=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_ULPI is not set CONFIG_USB_ULPI_BUS=m CONFIG_USB_USBNET=m CONFIG_USB_USS720=m @@ -8321,6 +8967,9 @@ CONFIG_VEML6030=m CONFIG_VEML6070=m CONFIG_VERSION_SIGNATURE="" CONFIG_VETH=m +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VF610_DAC is not set CONFIG_VFAT_FS=y CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y @@ -8332,6 +8981,7 @@ CONFIG_VFIO_PCI_IGD=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_VGA=y +# CONFIG_VFIO_PLATFORM is not set CONFIG_VFIO_VIRQFD=y CONFIG_VGASTATE=m CONFIG_VGA_ARB=y @@ -8371,6 +9021,7 @@ CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ADV7183=m CONFIG_VIDEO_ADV7343=m CONFIG_VIDEO_ADV7393=m +# CONFIG_VIDEO_ADV748X is not set CONFIG_VIDEO_ADV7511=m CONFIG_VIDEO_ADV7511_CEC=y CONFIG_VIDEO_ADV7604=m @@ -8478,6 +9129,7 @@ CONFIG_VIDEO_MT9T112=m CONFIG_VIDEO_MT9V011=m CONFIG_VIDEO_MT9V032=m CONFIG_VIDEO_MT9V111=m +# CONFIG_VIDEO_MUX is not set CONFIG_VIDEO_MXB=m CONFIG_VIDEO_NOON010PC30=m CONFIG_VIDEO_OV13858=m @@ -8486,6 +9138,8 @@ CONFIG_VIDEO_OV2659=m CONFIG_VIDEO_OV2680=m CONFIG_VIDEO_OV2685=m CONFIG_VIDEO_OV2740=m +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set CONFIG_VIDEO_OV5647=m CONFIG_VIDEO_OV5670=m CONFIG_VIDEO_OV5675=m @@ -8579,6 +9233,7 @@ CONFIG_VIDEO_VPX3220=m CONFIG_VIDEO_VS6624=m CONFIG_VIDEO_WM8739=m CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_XILINX is not set CONFIG_VIPERBOARD_ADC=m CONFIG_VIRTIO=y CONFIG_VIRTIO_BALLOON=y @@ -8586,6 +9241,7 @@ CONFIG_VIRTIO_BLK=m CONFIG_VIRTIO_CONSOLE=y CONFIG_VIRTIO_FS=m CONFIG_VIRTIO_INPUT=m +# CONFIG_VIRTIO_IOMMU is not set CONFIG_VIRTIO_MEM=m CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_MMIO=y @@ -8749,6 +9405,7 @@ CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLCORE=m CONFIG_WLCORE_SDIO=m +# CONFIG_WLCORE_SPI is not set CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m CONFIG_WM831X_WATCHDOG=m @@ -8906,6 +9563,7 @@ CONFIG_XFS_RT=y # CONFIG_XFS_WARN is not set CONFIG_XIAOMI_WMI=m CONFIG_XILINX_AXI_EMAC=m +# CONFIG_XILINX_DMA is not set CONFIG_XILINX_GMII2RGMII=m CONFIG_XILINX_LL_TEMAC=m CONFIG_XILINX_PR_DECOUPLER=m @@ -8913,8 +9571,11 @@ CONFIG_XILINX_SDFEC=m # CONFIG_XILINX_VCU is not set CONFIG_XILINX_WATCHDOG=m CONFIG_XILINX_XADC=m +# CONFIG_XILINX_ZYNQMP_DMA is not set CONFIG_XILLYBUS=m +# CONFIG_XILLYBUS_OF is not set CONFIG_XILLYBUS_PCIE=m +# CONFIG_XIL_AXIS_FIFO is not set CONFIG_XOR_BLOCKS=m CONFIG_XPOWER_PMIC_OPREGION=y CONFIG_XPS=y From patchwork Fri May 21 07:00:28 2021 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:51 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 04/18] UBUNTU: [config] arm64: Modify configs to make master annotations happy Date: Fri, 21 May 2021 03:00:28 -0400 Message-Id: <20210521070042.1445-7-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 Then run updateconfigs again to split any configs from amd64 No change to amd64 configs Signed-off-by: Khalid Elmously --- .../config/amd64/config.common.amd64 | 12 +++++ .../config/arm64/config.common.arm64 | 16 ++++++- debian.oracle/config/config.common.ubuntu | 45 +++++++++++-------- 3 files changed, 52 insertions(+), 21 deletions(-) diff --git a/debian.oracle/config/amd64/config.common.amd64 b/debian.oracle/config/amd64/config.common.amd64 index 3f6ccd2283a0..707cf3b1ee4d 100644 --- a/debian.oracle/config/amd64/config.common.amd64 +++ b/debian.oracle/config/amd64/config.common.amd64 @@ -8,9 +8,21 @@ CONFIG_ARCH_MMAP_RND_BITS_MAX=32 CONFIG_ARCH_MMAP_RND_BITS_MIN=28 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ATA_PIIX=y CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 10.2.0-13ubuntu1) 10.2.0" +# CONFIG_CMA is not set CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_HIBERNATION=y +CONFIG_HIO=m +CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_KVM=m CONFIG_NR_CPUS=8192 # CONFIG_OF is not set CONFIG_PGTABLE_LEVELS=5 +CONFIG_TOUCHSCREEN_ELAN=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_VFIO=y +CONFIG_VFIO_IOMMU_TYPE1=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_VIRQFD=y diff --git a/debian.oracle/config/arm64/config.common.arm64 b/debian.oracle/config/arm64/config.common.arm64 index a248cdefa5bf..3e125ea48f8b 100644 --- a/debian.oracle/config/arm64/config.common.arm64 +++ b/debian.oracle/config/arm64/config.common.arm64 @@ -4,13 +4,25 @@ CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ATA_PIIX=m CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 10.2.0-8ubuntu1) 10.2.0" +CONFIG_CMA=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +# CONFIG_HIBERNATION is not set +# CONFIG_HIO is not set +CONFIG_IRQ_BYPASS_MANAGER=m # CONFIG_KVM is not set CONFIG_NR_CPUS=256 CONFIG_OF=y -CONFIG_PGTABLE_LEVELS=3 +CONFIG_PGTABLE_LEVELS=4 +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_VFIO=m +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_PCI=m +CONFIG_VFIO_VIRQFD=m diff --git a/debian.oracle/config/config.common.ubuntu b/debian.oracle/config/config.common.ubuntu index 204a4716d38c..442dc5e19149 100644 --- a/debian.oracle/config/config.common.ubuntu +++ b/debian.oracle/config/config.common.ubuntu @@ -497,14 +497,14 @@ CONFIG_ARM64_SVE=y CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_UAO=y CONFIG_ARM64_USE_LSE_ATOMICS=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_VHE=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARMV8_DEPRECATED=y CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y @@ -568,7 +568,6 @@ CONFIG_ATA_BMDMA=y CONFIG_ATA_FORCE=y CONFIG_ATA_GENERIC=y CONFIG_ATA_OVER_ETH=m -CONFIG_ATA_PIIX=y CONFIG_ATA_SFF=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATH10K=m @@ -762,6 +761,7 @@ CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_RAVE_SP=m CONFIG_BACKLIGHT_SAHARA=m CONFIG_BACKLIGHT_SKY81452=m +# CONFIG_BACKLIGHT_TPS65217 is not set CONFIG_BACKLIGHT_WM831X=m CONFIG_BALLOON_COMPACTION=y CONFIG_BAREUDP=m @@ -1251,6 +1251,7 @@ CONFIG_CHARGER_RT9455=m CONFIG_CHARGER_SBS=m CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m +# CONFIG_CHARGER_TPS65217 is not set CONFIG_CHARGER_TWL4030=m # CONFIG_CHARGER_UCS1002 is not set CONFIG_CHARGER_WILCO=m @@ -1314,7 +1315,15 @@ CONFIG_CM3232=m CONFIG_CM3323=m # CONFIG_CM3605 is not set CONFIG_CM36651=m -# CONFIG_CMA is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=32 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set CONFIG_CMDLINE="" # CONFIG_CMDLINE_BOOL is not set CONFIG_CMDLINE_PARTITION=y @@ -1505,6 +1514,7 @@ CONFIG_COREDUMP=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_CORTINA_PHY=m CONFIG_COUNTER=m +CONFIG_CP15_BARRIER_EMULATION=y # CONFIG_CPA_DEBUG is not set CONFIG_CPU5_WDT=m # CONFIG_CPUFREQ_DT is not set @@ -1661,9 +1671,10 @@ CONFIG_CRYPTO_DEV_CCP_DD=m # CONFIG_CRYPTO_DEV_CCREE is not set CONFIG_CRYPTO_DEV_CHELSIO=m # CONFIG_CRYPTO_DEV_HISI_HPRE is not set +CONFIG_CRYPTO_DEV_HISI_QM=m # CONFIG_CRYPTO_DEV_HISI_SEC is not set # CONFIG_CRYPTO_DEV_HISI_SEC2 is not set -# CONFIG_CRYPTO_DEV_HISI_ZIP is not set +CONFIG_CRYPTO_DEV_HISI_ZIP=m CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m CONFIG_CRYPTO_DEV_PADLOCK=y @@ -1900,7 +1911,6 @@ CONFIG_DEFAULT_CUBIC=y CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_SECURITY_APPARMOR=y # CONFIG_DEFAULT_SECURITY_DAC is not set @@ -1955,6 +1965,7 @@ CONFIG_DLM=m CONFIG_DLN2_ADC=m CONFIG_DM9102=m CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_HEAPS_CMA is not set CONFIG_DMABUF_HEAPS_SYSTEM=y # CONFIG_DMABUF_MOVE_NOTIFY is not set # CONFIG_DMABUF_SELFTESTS is not set @@ -1967,6 +1978,7 @@ CONFIG_DMAR_TABLE=y # CONFIG_DMATEST is not set CONFIG_DMA_ACPI=y # CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_CMA=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_DMA_DIRECT_REMAP=y @@ -2071,7 +2083,7 @@ CONFIG_DRM_GMA3600=y CONFIG_DRM_GMA500=m CONFIG_DRM_GMA600=y # CONFIG_DRM_HDLCD is not set -# CONFIG_DRM_HISI_HIBMC is not set +CONFIG_DRM_HISI_HIBMC=m # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_I2C_ADV7511 is not set CONFIG_DRM_I2C_CH7006=m @@ -3190,7 +3202,6 @@ CONFIG_HFSPLUS_FS=m CONFIG_HFS_FS=m CONFIG_HI8435=m CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_HID=m CONFIG_HIDRAW=y @@ -3310,7 +3321,6 @@ CONFIG_HID_ZEROPLUS=m CONFIG_HID_ZYDACRON=m CONFIG_HIGH_RES_TIMERS=y CONFIG_HINIC=m -CONFIG_HIO=m # CONFIG_HIP04_ETH is not set # CONFIG_HIPPI is not set CONFIG_HISILICON_ERRATUM_161010101=y @@ -3784,6 +3794,7 @@ CONFIG_INPUT_SOC_BUTTON_ARRAY=m CONFIG_INPUT_SPARSEKMAP=m CONFIG_INPUT_TABLET=y CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_INPUT_TPS65218_PWRBUTTON is not set CONFIG_INPUT_TWL4030_PWRBUTTON=m CONFIG_INPUT_TWL4030_VIBRA=m CONFIG_INPUT_TWL6040_VIBRA=m @@ -4058,7 +4069,6 @@ CONFIG_IQS621_ALS=m CONFIG_IQS624_POS=m CONFIG_IRQCHIP=y # CONFIG_IRQSOFF_TRACER is not set -CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y @@ -4815,7 +4825,7 @@ CONFIG_MFD_TI_LP873X=m # CONFIG_MFD_TI_LP87565 is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65090=y -# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TPS65217=m # CONFIG_MFD_TPS65218 is not set CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y @@ -6599,6 +6609,7 @@ CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65086=m CONFIG_REGULATOR_TPS65090=m CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65217=m CONFIG_REGULATOR_TPS6524X=m CONFIG_REGULATOR_TPS6586X=m CONFIG_REGULATOR_TPS65910=m @@ -7369,6 +7380,7 @@ CONFIG_SERIO_PCIPS2=m CONFIG_SERIO_PS2MULT=m CONFIG_SERIO_RAW=m CONFIG_SERIO_SERPORT=m +CONFIG_SETEND_EMULATION=y CONFIG_SFC=m CONFIG_SFC_FALCON=m CONFIG_SFC_FALCON_MTD=y @@ -8087,6 +8099,7 @@ CONFIG_SWAP=y CONFIG_SWIOTLB=y CONFIG_SWIOTLB_XEN=y CONFIG_SWPHY=y +CONFIG_SWP_EMULATION=y CONFIG_SW_SYNC=y CONFIG_SX9310=m CONFIG_SX9500=m @@ -8319,7 +8332,6 @@ CONFIG_TOUCHSCREEN_EETI=m # CONFIG_TOUCHSCREEN_EGALAX is not set CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m CONFIG_TOUCHSCREEN_EKTF2127=m -CONFIG_TOUCHSCREEN_ELAN=y CONFIG_TOUCHSCREEN_ELO=m CONFIG_TOUCHSCREEN_EXC3000=m CONFIG_TOUCHSCREEN_FUJITSU=m @@ -8607,7 +8619,6 @@ CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_EG20T=m CONFIG_USB_EHCI_FSL=m CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y @@ -8971,18 +8982,14 @@ CONFIG_VETH=m # CONFIG_VF610_ADC is not set # CONFIG_VF610_DAC is not set CONFIG_VFAT_FS=y -CONFIG_VFIO=y -CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_MDEV=m CONFIG_VFIO_MDEV_DEVICE=m CONFIG_VFIO_NOIOMMU=y -CONFIG_VFIO_PCI=y CONFIG_VFIO_PCI_IGD=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_VGA=y # CONFIG_VFIO_PLATFORM is not set -CONFIG_VFIO_VIRQFD=y CONFIG_VGASTATE=m CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 From patchwork Fri May 21 07:00:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcw05m0Zz9sRf; Fri, 21 May 2021 17:01:20 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9l-000073-Lr; Fri, 21 May 2021 07:01:13 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9S-0008Le-OF for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:54 +0000 Received: from mail-qk1-f199.google.com ([209.85.222.199]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9S-0000bY-9P for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:54 +0000 Received: by mail-qk1-f199.google.com with SMTP id o14-20020a05620a130eb02902ea53a6ef80so15306945qkj.6 for ; Fri, 21 May 2021 00:00:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LZCmcizg0JDvRSGXqF+Il8EZsadKR6xAjBNfbToh/b0=; b=l+7rbuRIGqs+TgorRRGeZnB1SoyxynAU4q911h0L8Cnu3L2jaj+ikbmUia1pK8QVWB JXyO4K+0En7hvgWWCtBQZMSSKmlw55vX7gaOLyuySQZsGQhXJeJ+fRxufaZYI9zGraFd fRwRQ5DmL8XVLy3laLn93Hc/u/oi8FlIxz6+7Sp4y7dtvM3o5lTXpgL1FC7m1TTqdV1f cmomPAHzEHOAv0hUDwWPT9KCQ+QXjhZg9Oy5XrYz0rJseLI/jsJ5p/1kX6TtJDn6C+Tb znsmF1Zfw4MI2ZEH3r8tPkwqCRomo212Pf+YuQGMV9DVFDEnTMBDQ1uK3a4S90s7fCNS P2NA== X-Gm-Message-State: AOAM533TsUdIyokrjqmscNoom8aFqdwVW4xVXiwWn0zivBP1MKHfAHAu y6fEFcHfkzdxSe/QtLsAYee/5rTW9+EVqCl7d0vqJfq/YssVb67fqEz6/6P5ugram+6xV+9ld0q 3OxjIQeFtNDeni834VCre/Y9FqUYzNnzkDeSvMfiI9A== X-Received: by 2002:a05:620a:1359:: with SMTP id c25mr9959472qkl.228.1621580453028; Fri, 21 May 2021 00:00:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJweFm+YZoPP1HefEhEzYmpnd9OEVE0Eg4242vvCgAfKgwUb1dL/gq9jcClDZc3LUOa+UxnczQ== X-Received: by 2002:a05:620a:1359:: with SMTP id c25mr9959411qkl.228.1621580452419; Fri, 21 May 2021 00:00:52 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:52 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 05/18] perf: Add Arm CMN-600 PMU driver Date: Fri, 21 May 2021 03:00:29 -0400 Message-Id: <20210521070042.1445-8-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Robin Murphy BugLink: https://bugs.launchpad.net/bugs/1925421 Initial driver for PMU event counting on the Arm CMN-600 interconnect. CMN sports an obnoxiously complex distributed PMU system as part of its debug and trace features, which can do all manner of things like sampling, cross-triggering and generating CoreSight trace. This driver covers the PMU functionality, plus the relevant aspects of watchpoints for simply counting matching flits. Tested-by: Tsahi Zidenberg Tested-by: Tuan Phan Signed-off-by: Robin Murphy Signed-off-by: Will Deacon (cherry picked from commit 0ba64770a2f2e5a104bf835e133d78d3f82287ad) Signed-off-by: Khalid Elmously --- Documentation/admin-guide/perf/arm-cmn.rst | 65 + Documentation/admin-guide/perf/index.rst | 1 + drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/arm-cmn.c | 1641 ++++++++++++++++++++ 5 files changed, 1715 insertions(+) create mode 100644 Documentation/admin-guide/perf/arm-cmn.rst create mode 100644 drivers/perf/arm-cmn.c diff --git a/Documentation/admin-guide/perf/arm-cmn.rst b/Documentation/admin-guide/perf/arm-cmn.rst new file mode 100644 index 000000000000..0e4809346014 --- /dev/null +++ b/Documentation/admin-guide/perf/arm-cmn.rst @@ -0,0 +1,65 @@ +============================= +Arm Coherent Mesh Network PMU +============================= + +CMN-600 is a configurable mesh interconnect consisting of a rectangular +grid of crosspoints (XPs), with each crosspoint supporting up to two +device ports to which various AMBA CHI agents are attached. + +CMN implements a distributed PMU design as part of its debug and trace +functionality. This consists of a local monitor (DTM) at every XP, which +counts up to 4 event signals from the connected device nodes and/or the +XP itself. Overflow from these local counters is accumulated in up to 8 +global counters implemented by the main controller (DTC), which provides +overall PMU control and interrupts for global counter overflow. + +PMU events +---------- + +The PMU driver registers a single PMU device for the whole interconnect, +see /sys/bus/event_source/devices/arm_cmn. Multi-chip systems may link +more than one CMN together via external CCIX links - in this situation, +each mesh counts its own events entirely independently, and additional +PMU devices will be named arm_cmn_{1..n}. + +Most events are specified in a format based directly on the TRM +definitions - "type" selects the respective node type, and "eventid" the +event number. Some events require an additional occupancy ID, which is +specified by "occupid". + +* Since RN-D nodes do not have any distinct events from RN-I nodes, they + are treated as the same type (0xa), and the common event templates are + named "rnid_*". + +* The cycle counter is treated as a synthetic event belonging to the DTC + node ("type" == 0x3, "eventid" is ignored). + +* XP events also encode the port and channel in the "eventid" field, to + match the underlying pmu_event0_id encoding for the pmu_event_sel + register. The event templates are named with prefixes to cover all + permutations. + +By default each event provides an aggregate count over all nodes of the +given type. To target a specific node, "bynodeid" must be set to 1 and +"nodeid" to the appropriate value derived from the CMN configuration +(as defined in the "Node ID Mapping" section of the TRM). + +Watchpoints +----------- + +The PMU can also count watchpoint events to monitor specific flit +traffic. Watchpoints are treated as a synthetic event type, and like PMU +events can be global or targeted with a particular XP's "nodeid" value. +Since the watchpoint direction is otherwise implicit in the underlying +register selection, separate events are provided for flit uploads and +downloads. + +The flit match value and mask are passed in config1 and config2 ("val" +and "mask" respectively). "wp_dev_sel", "wp_chn_sel", "wp_grp" and +"wp_exclusive" are specified per the TRM definitions for dtm_wp_config0. +Where a watchpoint needs to match fields from both match groups on the +REQ or SNP channel, it can be specified as two events - one for each +group - with the same nonzero "combine" value. The count for such a +pair of combined events will be attributed to the primary match. +Watchpoint events with a "combine" value of 0 are considered independent +and will count individually. diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst index 47c99f40cc16..5a8f2529a033 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -12,6 +12,7 @@ Performance monitor support qcom_l2_pmu qcom_l3_pmu arm-ccn + arm-cmn xgene-pmu arm_dsu_pmu thunderx2-pmu diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index a9261cf48293..c49c3e1042c2 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -41,6 +41,13 @@ config ARM_CCN PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) interconnect. +config ARM_CMN + tristate "Arm CMN-600 PMU support" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh + Network interconnect. + config ARM_PMU depends on ARM || ARM64 bool "ARM PMU framework" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 2ebb4de17815..5365fd56f88f 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o obj-$(CONFIG_ARM_CCN) += arm-ccn.o +obj-$(CONFIG_ARM_CMN) += arm-cmn.o obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c new file mode 100644 index 000000000000..e824b5b83ea2 --- /dev/null +++ b/drivers/perf/arm-cmn.c @@ -0,0 +1,1641 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2016-2020 Arm Limited +// CMN-600 Coherent Mesh Network PMU driver + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Common register stuff */ +#define CMN_NODE_INFO 0x0000 +#define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) +#define CMN_NI_NODE_ID GENMASK_ULL(31, 16) +#define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) + +#define CMN_NODEID_DEVID(reg) ((reg) & 3) +#define CMN_NODEID_PID(reg) (((reg) >> 2) & 1) +#define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits))) +#define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1)) + +#define CMN_CHILD_INFO 0x0080 +#define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) +#define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) + +#define CMN_CHILD_NODE_ADDR GENMASK(27,0) +#define CMN_CHILD_NODE_EXTERNAL BIT(31) + +#define CMN_ADDR_NODE_PTR GENMASK(27, 14) + +#define CMN_NODE_PTR_DEVID(ptr) (((ptr) >> 2) & 3) +#define CMN_NODE_PTR_PID(ptr) ((ptr) & 1) +#define CMN_NODE_PTR_X(ptr, bits) ((ptr) >> (6 + (bits))) +#define CMN_NODE_PTR_Y(ptr, bits) (((ptr) >> 6) & ((1U << (bits)) - 1)) + +#define CMN_MAX_XPS (8 * 8) + +/* The CFG node has one other useful purpose */ +#define CMN_CFGM_PERIPH_ID_2 0x0010 +#define CMN_CFGM_PID2_REVISION GENMASK(7, 4) + +/* PMU registers occupy the 3rd 4KB page of each node's 16KB space */ +#define CMN_PMU_OFFSET 0x2000 + +/* For most nodes, this is all there is */ +#define CMN_PMU_EVENT_SEL 0x000 +#define CMN_PMU_EVENTn_ID_SHIFT(n) ((n) * 8) + +/* DTMs live in the PMU space of XP registers */ +#define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) +#define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) +#define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(6) +#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(5) +#define CMN_DTM_WPn_CONFIG_WP_GRP BIT(4) +#define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) +#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) +#define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) +#define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) + +#define CMN_DTM_PMU_CONFIG 0x210 +#define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) +#define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 +#define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 +#define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 +#define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) +#define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) +#define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) +#define CMN__PMEVCNT23_COMBINED BIT(2) +#define CMN__PMEVCNT01_COMBINED BIT(1) +#define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) + +#define CMN_DTM_PMEVCNT 0x220 + +#define CMN_DTM_PMEVCNTSR 0x240 + +#define CMN_DTM_NUM_COUNTERS 4 + +/* The DTC node is where the magic happens */ +#define CMN_DT_DTC_CTL 0x0a00 +#define CMN_DT_DTC_CTL_DT_EN BIT(0) + +/* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ +#define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) +#define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n)) +#define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40) + +#define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n)) +#define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90) + +#define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100) +#define CMN_DT_PMCR_PMU_EN BIT(0) +#define CMN_DT_PMCR_CNTR_RST BIT(5) +#define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) + +#define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118) +#define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120) + +#define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128) +#define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) + +#define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130) +#define CMN_DT_PMSRR_SS_REQ BIT(0) + +#define CMN_DT_NUM_COUNTERS 8 +#define CMN_MAX_DTCS 4 + +/* + * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, + * so throwing away one bit to make overflow handling easy is no big deal. + */ +#define CMN_COUNTER_INIT 0x80000000 +/* Similarly for the 40-bit cycle counter */ +#define CMN_CC_INIT 0x8000000000ULL + + +/* Event attributes */ +#define CMN_CONFIG_TYPE GENMASK(15, 0) +#define CMN_CONFIG_EVENTID GENMASK(23, 16) +#define CMN_CONFIG_OCCUPID GENMASK(27, 24) +#define CMN_CONFIG_BYNODEID BIT(31) +#define CMN_CONFIG_NODEID GENMASK(47, 32) + +#define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) +#define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) +#define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config) +#define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) +#define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) + +#define CMN_CONFIG_WP_COMBINE GENMASK(27, 24) +#define CMN_CONFIG_WP_DEV_SEL BIT(48) +#define CMN_CONFIG_WP_CHN_SEL GENMASK(50, 49) +#define CMN_CONFIG_WP_GRP BIT(52) +#define CMN_CONFIG_WP_EXCLUSIVE BIT(53) +#define CMN_CONFIG1_WP_VAL GENMASK(63, 0) +#define CMN_CONFIG2_WP_MASK GENMASK(63, 0) + +#define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) +#define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) +#define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) +#define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) +#define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) +#define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) +#define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) + +/* Made-up event IDs for watchpoint direction */ +#define CMN_WP_UP 0 +#define CMN_WP_DOWN 2 + + +/* r0px probably don't exist in silicon, thankfully */ +enum cmn_revision { + CMN600_R1P0, + CMN600_R1P1, + CMN600_R1P2, + CMN600_R1P3, + CMN600_R2P0, + CMN600_R3P0, +}; + +enum cmn_node_type { + CMN_TYPE_INVALID, + CMN_TYPE_DVM, + CMN_TYPE_CFG, + CMN_TYPE_DTC, + CMN_TYPE_HNI, + CMN_TYPE_HNF, + CMN_TYPE_XP, + CMN_TYPE_SBSX, + CMN_TYPE_RNI = 0xa, + CMN_TYPE_RND = 0xd, + CMN_TYPE_RNSAM = 0xf, + CMN_TYPE_CXRA = 0x100, + CMN_TYPE_CXHA = 0x101, + CMN_TYPE_CXLA = 0x102, + /* Not a real node type */ + CMN_TYPE_WP = 0x7770 +}; + +struct arm_cmn_node { + void __iomem *pmu_base; + u16 id, logid; + enum cmn_node_type type; + + union { + /* Device node */ + struct { + int to_xp; + /* DN/HN-F/CXHA */ + unsigned int occupid_val; + unsigned int occupid_count; + }; + /* XP */ + struct { + int dtc; + u32 pmu_config_low; + union { + u8 input_sel[4]; + __le32 pmu_config_high; + }; + s8 wp_event[4]; + }; + }; + + union { + u8 event[4]; + __le32 event_sel; + }; +}; + +struct arm_cmn_dtc { + void __iomem *base; + unsigned int irq; + int irq_friend; + bool cc_active; + + struct perf_event *counters[CMN_DT_NUM_COUNTERS]; + struct perf_event *cycles; +}; + +#define CMN_STATE_DISABLED BIT(0) +#define CMN_STATE_TXN BIT(1) + +struct arm_cmn { + struct device *dev; + void __iomem *base; + + enum cmn_revision rev; + u8 mesh_x; + u8 mesh_y; + u16 num_xps; + u16 num_dns; + struct arm_cmn_node *xps; + struct arm_cmn_node *dns; + + struct arm_cmn_dtc *dtc; + unsigned int num_dtcs; + + int cpu; + struct hlist_node cpuhp_node; + + unsigned int state; + struct pmu pmu; +}; + +#define to_cmn(p) container_of(p, struct arm_cmn, pmu) + +static int arm_cmn_hp_state; + +struct arm_cmn_hw_event { + struct arm_cmn_node *dn; + u64 dtm_idx[2]; + unsigned int dtc_idx; + u8 dtcs_used; + u8 num_dns; +}; + +#define for_each_hw_dn(hw, dn, i) \ + for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) + +static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) +{ + BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target)); + return (struct arm_cmn_hw_event *)&event->hw; +} + +static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) +{ + x[pos / 32] |= (u64)val << ((pos % 32) * 2); +} + +static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) +{ + return (x[pos / 32] >> ((pos % 32) * 2)) & 3; +} + +struct arm_cmn_event_attr { + struct device_attribute attr; + enum cmn_node_type type; + u8 eventid; + u8 occupid; +}; + +struct arm_cmn_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static int arm_cmn_xyidbits(const struct arm_cmn *cmn) +{ + return cmn->mesh_x > 4 || cmn->mesh_y > 4 ? 3 : 2; +} + +static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn, + struct arm_cmn_node *dn) +{ + int bits = arm_cmn_xyidbits(cmn); + int x = CMN_NODEID_X(dn->id, bits); + int y = CMN_NODEID_Y(dn->id, bits); + int xp_idx = cmn->mesh_x * y + x; + + dn->to_xp = (cmn->xps + xp_idx) - dn; +} + +static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn) +{ + return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp; +} + +static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, + enum cmn_node_type type) +{ + int i; + + for (i = 0; i < cmn->num_dns; i++) + if (cmn->dns[i].type == type) + return &cmn->dns[i]; + return NULL; +} + +#define CMN_EVENT_ATTR(_name, _type, _eventid, _occupid) \ + (&((struct arm_cmn_event_attr[]) {{ \ + .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ + .type = _type, \ + .eventid = _eventid, \ + .occupid = _occupid, \ + }})[0].attr.attr) + +static bool arm_cmn_is_occup_event(enum cmn_node_type type, unsigned int id) +{ + return (type == CMN_TYPE_DVM && id == 0x05) || + (type == CMN_TYPE_HNF && id == 0x0f); +} + +static ssize_t arm_cmn_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_cmn_event_attr *eattr; + + eattr = container_of(attr, typeof(*eattr), attr); + + if (eattr->type == CMN_TYPE_DTC) + return snprintf(buf, PAGE_SIZE, "type=0x%x\n", eattr->type); + + if (eattr->type == CMN_TYPE_WP) + return snprintf(buf, PAGE_SIZE, + "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", + eattr->type, eattr->eventid); + + if (arm_cmn_is_occup_event(eattr->type, eattr->eventid)) + return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x,occupid=0x%x\n", + eattr->type, eattr->eventid, eattr->occupid); + + return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x\n", + eattr->type, eattr->eventid); +} + +static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) +{ + struct device *dev = kobj_to_dev(kobj); + struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); + struct arm_cmn_event_attr *eattr; + enum cmn_node_type type; + + eattr = container_of(attr, typeof(*eattr), attr.attr); + type = eattr->type; + + /* Watchpoints aren't nodes */ + if (type == CMN_TYPE_WP) + type = CMN_TYPE_XP; + + /* Revision-specific differences */ + if (cmn->rev < CMN600_R1P2) { + if (type == CMN_TYPE_HNF && eattr->eventid == 0x1b) + return 0; + } + + if (!arm_cmn_node(cmn, type)) + return 0; + + return attr->mode; +} + +#define _CMN_EVENT_DVM(_name, _event, _occup) \ + CMN_EVENT_ATTR(dn_##_name, CMN_TYPE_DVM, _event, _occup) +#define CMN_EVENT_DTC(_name) \ + CMN_EVENT_ATTR(dtc_##_name, CMN_TYPE_DTC, 0, 0) +#define _CMN_EVENT_HNF(_name, _event, _occup) \ + CMN_EVENT_ATTR(hnf_##_name, CMN_TYPE_HNF, _event, _occup) +#define CMN_EVENT_HNI(_name, _event) \ + CMN_EVENT_ATTR(hni_##_name, CMN_TYPE_HNI, _event, 0) +#define __CMN_EVENT_XP(_name, _event) \ + CMN_EVENT_ATTR(mxp_##_name, CMN_TYPE_XP, _event, 0) +#define CMN_EVENT_SBSX(_name, _event) \ + CMN_EVENT_ATTR(sbsx_##_name, CMN_TYPE_SBSX, _event, 0) +#define CMN_EVENT_RNID(_name, _event) \ + CMN_EVENT_ATTR(rnid_##_name, CMN_TYPE_RNI, _event, 0) + +#define CMN_EVENT_DVM(_name, _event) \ + _CMN_EVENT_DVM(_name, _event, 0) +#define CMN_EVENT_HNF(_name, _event) \ + _CMN_EVENT_HNF(_name, _event, 0) +#define _CMN_EVENT_XP(_name, _event) \ + __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ + __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ + __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ + __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \ + __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ + __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)) + +/* Good thing there are only 3 fundamental XP events... */ +#define CMN_EVENT_XP(_name, _event) \ + _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ + _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ + _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ + _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)) + + +static struct attribute *arm_cmn_event_attrs[] = { + CMN_EVENT_DTC(cycles), + + /* + * DVM node events conflict with HN-I events in the equivalent PMU + * slot, but our lazy short-cut of using the DTM counter index for + * the PMU index as well happens to avoid that by construction. + */ + CMN_EVENT_DVM(rxreq_dvmop, 0x01), + CMN_EVENT_DVM(rxreq_dvmsync, 0x02), + CMN_EVENT_DVM(rxreq_dvmop_vmid_filtered, 0x03), + CMN_EVENT_DVM(rxreq_retried, 0x04), + _CMN_EVENT_DVM(rxreq_trk_occupancy_all, 0x05, 0), + _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmop, 0x05, 1), + _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmsync, 0x05, 2), + + CMN_EVENT_HNF(cache_miss, 0x01), + CMN_EVENT_HNF(slc_sf_cache_access, 0x02), + CMN_EVENT_HNF(cache_fill, 0x03), + CMN_EVENT_HNF(pocq_retry, 0x04), + CMN_EVENT_HNF(pocq_reqs_recvd, 0x05), + CMN_EVENT_HNF(sf_hit, 0x06), + CMN_EVENT_HNF(sf_evictions, 0x07), + CMN_EVENT_HNF(dir_snoops_sent, 0x08), + CMN_EVENT_HNF(brd_snoops_sent, 0x09), + CMN_EVENT_HNF(slc_eviction, 0x0a), + CMN_EVENT_HNF(slc_fill_invalid_way, 0x0b), + CMN_EVENT_HNF(mc_retries, 0x0c), + CMN_EVENT_HNF(mc_reqs, 0x0d), + CMN_EVENT_HNF(qos_hh_retry, 0x0e), + _CMN_EVENT_HNF(qos_pocq_occupancy_all, 0x0f, 0), + _CMN_EVENT_HNF(qos_pocq_occupancy_read, 0x0f, 1), + _CMN_EVENT_HNF(qos_pocq_occupancy_write, 0x0f, 2), + _CMN_EVENT_HNF(qos_pocq_occupancy_atomic, 0x0f, 3), + _CMN_EVENT_HNF(qos_pocq_occupancy_stash, 0x0f, 4), + CMN_EVENT_HNF(pocq_addrhaz, 0x10), + CMN_EVENT_HNF(pocq_atomic_addrhaz, 0x11), + CMN_EVENT_HNF(ld_st_swp_adq_full, 0x12), + CMN_EVENT_HNF(cmp_adq_full, 0x13), + CMN_EVENT_HNF(txdat_stall, 0x14), + CMN_EVENT_HNF(txrsp_stall, 0x15), + CMN_EVENT_HNF(seq_full, 0x16), + CMN_EVENT_HNF(seq_hit, 0x17), + CMN_EVENT_HNF(snp_sent, 0x18), + CMN_EVENT_HNF(sfbi_dir_snp_sent, 0x19), + CMN_EVENT_HNF(sfbi_brd_snp_sent, 0x1a), + CMN_EVENT_HNF(snp_sent_untrk, 0x1b), + CMN_EVENT_HNF(intv_dirty, 0x1c), + CMN_EVENT_HNF(stash_snp_sent, 0x1d), + CMN_EVENT_HNF(stash_data_pull, 0x1e), + CMN_EVENT_HNF(snp_fwded, 0x1f), + + CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), + CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), + CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), + CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), + CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), + CMN_EVENT_HNI(rrt_rd_alloc, 0x25), + CMN_EVENT_HNI(rrt_wr_alloc, 0x26), + CMN_EVENT_HNI(rdt_rd_alloc, 0x27), + CMN_EVENT_HNI(rdt_wr_alloc, 0x28), + CMN_EVENT_HNI(wdb_alloc, 0x29), + CMN_EVENT_HNI(txrsp_retryack, 0x2a), + CMN_EVENT_HNI(arvalid_no_arready, 0x2b), + CMN_EVENT_HNI(arready_no_arvalid, 0x2c), + CMN_EVENT_HNI(awvalid_no_awready, 0x2d), + CMN_EVENT_HNI(awready_no_awvalid, 0x2e), + CMN_EVENT_HNI(wvalid_no_wready, 0x2f), + CMN_EVENT_HNI(txdat_stall, 0x30), + CMN_EVENT_HNI(nonpcie_serialization, 0x31), + CMN_EVENT_HNI(pcie_serialization, 0x32), + + CMN_EVENT_XP(txflit_valid, 0x01), + CMN_EVENT_XP(txflit_stall, 0x02), + CMN_EVENT_XP(partial_dat_flit, 0x03), + /* We treat watchpoints as a special made-up class of XP events */ + CMN_EVENT_ATTR(watchpoint_up, CMN_TYPE_WP, 0, 0), + CMN_EVENT_ATTR(watchpoint_down, CMN_TYPE_WP, 2, 0), + + CMN_EVENT_SBSX(rd_req, 0x01), + CMN_EVENT_SBSX(wr_req, 0x02), + CMN_EVENT_SBSX(cmo_req, 0x03), + CMN_EVENT_SBSX(txrsp_retryack, 0x04), + CMN_EVENT_SBSX(txdat_flitv, 0x05), + CMN_EVENT_SBSX(txrsp_flitv, 0x06), + CMN_EVENT_SBSX(rd_req_trkr_occ_cnt_ovfl, 0x11), + CMN_EVENT_SBSX(wr_req_trkr_occ_cnt_ovfl, 0x12), + CMN_EVENT_SBSX(cmo_req_trkr_occ_cnt_ovfl, 0x13), + CMN_EVENT_SBSX(wdb_occ_cnt_ovfl, 0x14), + CMN_EVENT_SBSX(rd_axi_trkr_occ_cnt_ovfl, 0x15), + CMN_EVENT_SBSX(cmo_axi_trkr_occ_cnt_ovfl, 0x16), + CMN_EVENT_SBSX(arvalid_no_arready, 0x21), + CMN_EVENT_SBSX(awvalid_no_awready, 0x22), + CMN_EVENT_SBSX(wvalid_no_wready, 0x23), + CMN_EVENT_SBSX(txdat_stall, 0x24), + CMN_EVENT_SBSX(txrsp_stall, 0x25), + + CMN_EVENT_RNID(s0_rdata_beats, 0x01), + CMN_EVENT_RNID(s1_rdata_beats, 0x02), + CMN_EVENT_RNID(s2_rdata_beats, 0x03), + CMN_EVENT_RNID(rxdat_flits, 0x04), + CMN_EVENT_RNID(txdat_flits, 0x05), + CMN_EVENT_RNID(txreq_flits_total, 0x06), + CMN_EVENT_RNID(txreq_flits_retried, 0x07), + CMN_EVENT_RNID(rrt_occ_ovfl, 0x08), + CMN_EVENT_RNID(wrt_occ_ovfl, 0x09), + CMN_EVENT_RNID(txreq_flits_replayed, 0x0a), + CMN_EVENT_RNID(wrcancel_sent, 0x0b), + CMN_EVENT_RNID(s0_wdata_beats, 0x0c), + CMN_EVENT_RNID(s1_wdata_beats, 0x0d), + CMN_EVENT_RNID(s2_wdata_beats, 0x0e), + CMN_EVENT_RNID(rrt_alloc, 0x0f), + CMN_EVENT_RNID(wrt_alloc, 0x10), + CMN_EVENT_RNID(rdb_unord, 0x11), + CMN_EVENT_RNID(rdb_replay, 0x12), + CMN_EVENT_RNID(rdb_hybrid, 0x13), + CMN_EVENT_RNID(rdb_ord, 0x14), + + NULL +}; + +static const struct attribute_group arm_cmn_event_attrs_group = { + .name = "events", + .attrs = arm_cmn_event_attrs, + .is_visible = arm_cmn_event_attr_is_visible, +}; + +static ssize_t arm_cmn_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); + int lo = __ffs(fmt->field), hi = __fls(fmt->field); + + if (lo == hi) + return snprintf(buf, PAGE_SIZE, "config:%d\n", lo); + + if (!fmt->config) + return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi); + + return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, hi); +} + +#define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ + (&((struct arm_cmn_format_attr[]) {{ \ + .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ + .config = _cfg, \ + .field = _fld, \ + }})[0].attr.attr) +#define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) + +static struct attribute *arm_cmn_format_attrs[] = { + CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), + CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), + CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID), + CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), + CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), + + CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), + CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), + CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), + CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), + CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), + + _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), + _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), + + NULL +}; + +static const struct attribute_group arm_cmn_format_attrs_group = { + .name = "format", + .attrs = arm_cmn_format_attrs, +}; + +static ssize_t arm_cmn_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); +} + +static struct device_attribute arm_cmn_cpumask_attr = + __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); + +static struct attribute *arm_cmn_cpumask_attrs[] = { + &arm_cmn_cpumask_attr.attr, + NULL, +}; + +static struct attribute_group arm_cmn_cpumask_attr_group = { + .attrs = arm_cmn_cpumask_attrs, +}; + +static const struct attribute_group *arm_cmn_attr_groups[] = { + &arm_cmn_event_attrs_group, + &arm_cmn_format_attrs_group, + &arm_cmn_cpumask_attr_group, + NULL +}; + +static int arm_cmn_wp_idx(struct perf_event *event) +{ + return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event); +} + +static u32 arm_cmn_wp_config(struct perf_event *event) +{ + u32 config; + u32 dev = CMN_EVENT_WP_DEV_SEL(event); + u32 chn = CMN_EVENT_WP_CHN_SEL(event); + u32 grp = CMN_EVENT_WP_GRP(event); + u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); + u32 combine = CMN_EVENT_WP_COMBINE(event); + + config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | + FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | + FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | + FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc); + if (combine && !grp) + config |= CMN_DTM_WPn_CONFIG_WP_COMBINE; + + return config; +} + +static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) +{ + if (!cmn->state) + writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); + cmn->state |= state; +} + +static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) +{ + cmn->state &= ~state; + if (!cmn->state) + writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, + cmn->dtc[0].base + CMN_DT_PMCR); +} + +static void arm_cmn_pmu_enable(struct pmu *pmu) +{ + arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); +} + +static void arm_cmn_pmu_disable(struct pmu *pmu) +{ + arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); +} + +static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, + bool snapshot) +{ + struct arm_cmn_node *dn; + unsigned int i, offset; + u64 count = 0; + + offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; + for_each_hw_dn(hw, dn, i) { + struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn); + int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); + u64 reg = readq_relaxed(xp->pmu_base + offset); + u16 dtm_count = reg >> (dtm_idx * 16); + + count += dtm_count; + } + return count; +} + +static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) +{ + u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR); + + writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); + return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); +} + +static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) +{ + u32 val, pmevcnt = CMN_DT_PMEVCNT(idx); + + val = readl_relaxed(dtc->base + pmevcnt); + writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt); + return val - CMN_COUNTER_INIT; +} + +static void arm_cmn_init_counter(struct perf_event *event) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx); + u64 count; + + for (i = 0; hw->dtcs_used & (1U << i); i++) { + writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt); + cmn->dtc[i].counters[hw->dtc_idx] = event; + } + + count = arm_cmn_read_dtm(cmn, hw, false); + local64_set(&event->hw.prev_count, count); +} + +static void arm_cmn_event_read(struct perf_event *event) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + u64 delta, new, prev; + unsigned long flags; + unsigned int i; + + if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) { + i = __ffs(hw->dtcs_used); + delta = arm_cmn_read_cc(cmn->dtc + i); + local64_add(delta, &event->count); + return; + } + new = arm_cmn_read_dtm(cmn, hw, false); + prev = local64_xchg(&event->hw.prev_count, new); + + delta = new - prev; + + local_irq_save(flags); + for (i = 0; hw->dtcs_used & (1U << i); i++) { + new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx); + delta += new << 16; + } + local_irq_restore(flags); + local64_add(delta, &event->count); +} + +static void arm_cmn_event_start(struct perf_event *event, int flags) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_node *dn; + enum cmn_node_type type = CMN_EVENT_TYPE(event); + int i; + + if (type == CMN_TYPE_DTC) { + i = __ffs(hw->dtcs_used); + writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR); + cmn->dtc[i].cc_active = true; + } else if (type == CMN_TYPE_WP) { + int wp_idx = arm_cmn_wp_idx(event); + u64 val = CMN_EVENT_WP_VAL(event); + u64 mask = CMN_EVENT_WP_MASK(event); + + for_each_hw_dn(hw, dn, i) { + writeq_relaxed(val, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); + writeq_relaxed(mask, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); + } + } else for_each_hw_dn(hw, dn, i) { + int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); + + dn->event[dtm_idx] = CMN_EVENT_EVENTID(event); + writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); + } +} + +static void arm_cmn_event_stop(struct perf_event *event, int flags) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_node *dn; + enum cmn_node_type type = CMN_EVENT_TYPE(event); + int i; + + if (type == CMN_TYPE_DTC) { + i = __ffs(hw->dtcs_used); + cmn->dtc[i].cc_active = false; + } else if (type == CMN_TYPE_WP) { + int wp_idx = arm_cmn_wp_idx(event); + + for_each_hw_dn(hw, dn, i) { + writeq_relaxed(0, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); + writeq_relaxed(~0ULL, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); + } + } else for_each_hw_dn(hw, dn, i) { + int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); + + dn->event[dtm_idx] = 0; + writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); + } + + arm_cmn_event_read(event); +} + +struct arm_cmn_val { + u8 dtm_count[CMN_MAX_XPS]; + u8 occupid[CMN_MAX_XPS]; + u8 wp[CMN_MAX_XPS][4]; + int dtc_count; + bool cycles; +}; + +static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *event) +{ + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_node *dn; + enum cmn_node_type type; + int i; + u8 occupid; + + if (is_software_event(event)) + return; + + type = CMN_EVENT_TYPE(event); + if (type == CMN_TYPE_DTC) { + val->cycles = true; + return; + } + + val->dtc_count++; + if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + occupid = CMN_EVENT_OCCUPID(event) + 1; + else + occupid = 0; + + for_each_hw_dn(hw, dn, i) { + int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid; + + val->dtm_count[xp]++; + val->occupid[xp] = occupid; + + if (type != CMN_TYPE_WP) + continue; + + wp_idx = arm_cmn_wp_idx(event); + val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; + } +} + +static int arm_cmn_validate_group(struct perf_event *event) +{ + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_node *dn; + struct perf_event *sibling, *leader = event->group_leader; + enum cmn_node_type type; + struct arm_cmn_val val; + int i; + u8 occupid; + + if (leader == event) + return 0; + + if (event->pmu != leader->pmu && !is_software_event(leader)) + return -EINVAL; + + memset(&val, 0, sizeof(val)); + + arm_cmn_val_add_event(&val, leader); + for_each_sibling_event(sibling, leader) + arm_cmn_val_add_event(&val, sibling); + + type = CMN_EVENT_TYPE(event); + if (type == CMN_TYPE_DTC) + return val.cycles ? -EINVAL : 0; + + if (val.dtc_count == CMN_DT_NUM_COUNTERS) + return -EINVAL; + + if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + occupid = CMN_EVENT_OCCUPID(event) + 1; + else + occupid = 0; + + for_each_hw_dn(hw, dn, i) { + int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid; + + if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS) + return -EINVAL; + + if (occupid && val.occupid[xp] && occupid != val.occupid[xp]) + return -EINVAL; + + if (type != CMN_TYPE_WP) + continue; + + wp_idx = arm_cmn_wp_idx(event); + if (val.wp[xp][wp_idx]) + return -EINVAL; + + wp_cmb = val.wp[xp][wp_idx ^ 1]; + if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) + return -EINVAL; + } + + return 0; +} + +static int arm_cmn_event_init(struct perf_event *event) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + enum cmn_node_type type; + unsigned int i; + bool bynodeid; + u16 nodeid, eventid; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + event->cpu = cmn->cpu; + if (event->cpu < 0) + return -EINVAL; + + type = CMN_EVENT_TYPE(event); + /* DTC events (i.e. cycles) already have everything they need */ + if (type == CMN_TYPE_DTC) + return 0; + + /* For watchpoints we need the actual XP node here */ + if (type == CMN_TYPE_WP) { + type = CMN_TYPE_XP; + /* ...and we need a "real" direction */ + eventid = CMN_EVENT_EVENTID(event); + if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) + return -EINVAL; + } + + bynodeid = CMN_EVENT_BYNODEID(event); + nodeid = CMN_EVENT_NODEID(event); + + hw->dn = arm_cmn_node(cmn, type); + for (i = hw->dn - cmn->dns; i < cmn->num_dns && cmn->dns[i].type == type; i++) { + if (!bynodeid) { + hw->num_dns++; + } else if (cmn->dns[i].id != nodeid) { + hw->dn++; + } else { + hw->num_dns = 1; + break; + } + } + + if (!hw->num_dns) { + int bits = arm_cmn_xyidbits(cmn); + + dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n", + nodeid, CMN_NODEID_X(nodeid, bits), CMN_NODEID_Y(nodeid, bits), + CMN_NODEID_PID(nodeid), CMN_NODEID_DEVID(nodeid), type); + return -EINVAL; + } + /* + * By assuming events count in all DTC domains, we cunningly avoid + * needing to know anything about how XPs are assigned to domains. + */ + hw->dtcs_used = (1U << cmn->num_dtcs) - 1; + + return arm_cmn_validate_group(event); +} + +static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, + int i) +{ + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + enum cmn_node_type type = CMN_EVENT_TYPE(event); + + while (i--) { + struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i); + unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); + + if (type == CMN_TYPE_WP) + hw->dn[i].wp_event[arm_cmn_wp_idx(event)] = -1; + + if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) + hw->dn[i].occupid_count--; + + xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); + writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG); + } + memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); + + for (i = 0; hw->dtcs_used & (1U << i); i++) + cmn->dtc[i].counters[hw->dtc_idx] = NULL; +} + +static int arm_cmn_event_add(struct perf_event *event, int flags) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + struct arm_cmn_dtc *dtc = &cmn->dtc[0]; + struct arm_cmn_node *dn; + enum cmn_node_type type = CMN_EVENT_TYPE(event); + unsigned int i, dtc_idx, input_sel; + + if (type == CMN_TYPE_DTC) { + i = 0; + while (cmn->dtc[i].cycles) + if (++i == cmn->num_dtcs) + return -ENOSPC; + + cmn->dtc[i].cycles = event; + hw->dtc_idx = CMN_DT_NUM_COUNTERS; + hw->dtcs_used = 1U << i; + + if (flags & PERF_EF_START) + arm_cmn_event_start(event, 0); + return 0; + } + + /* Grab a free global counter first... */ + dtc_idx = 0; + while (dtc->counters[dtc_idx]) + if (++dtc_idx == CMN_DT_NUM_COUNTERS) + return -ENOSPC; + + hw->dtc_idx = dtc_idx; + + /* ...then the local counters to feed it. */ + for_each_hw_dn(hw, dn, i) { + struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn); + unsigned int dtm_idx, shift; + u64 reg; + + dtm_idx = 0; + while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) + if (++dtm_idx == CMN_DTM_NUM_COUNTERS) + goto free_dtms; + + if (type == CMN_TYPE_XP) { + input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; + } else if (type == CMN_TYPE_WP) { + int tmp, wp_idx = arm_cmn_wp_idx(event); + u32 cfg = arm_cmn_wp_config(event); + + if (dn->wp_event[wp_idx] >= 0) + goto free_dtms; + + tmp = dn->wp_event[wp_idx ^ 1]; + if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != + CMN_EVENT_WP_COMBINE(dtc->counters[tmp])) + goto free_dtms; + + input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; + dn->wp_event[wp_idx] = dtc_idx; + writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx)); + } else { + unsigned int port = CMN_NODEID_PID(dn->id); + unsigned int dev = CMN_NODEID_DEVID(dn->id); + + input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + + (port << 4) + (dev << 2); + + if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) { + int occupid = CMN_EVENT_OCCUPID(event); + + if (dn->occupid_count == 0) { + dn->occupid_val = occupid; + writel_relaxed(occupid, + dn->pmu_base + CMN_PMU_EVENT_SEL + 4); + } else if (dn->occupid_val != occupid) { + goto free_dtms; + } + dn->occupid_count++; + } + } + + arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); + + xp->input_sel[dtm_idx] = input_sel; + shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); + xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); + xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift; + xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); + reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low; + writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG); + } + + /* Go go go! */ + arm_cmn_init_counter(event); + + if (flags & PERF_EF_START) + arm_cmn_event_start(event, 0); + + return 0; + +free_dtms: + arm_cmn_event_clear(cmn, event, i); + return -ENOSPC; +} + +static void arm_cmn_event_del(struct perf_event *event, int flags) +{ + struct arm_cmn *cmn = to_cmn(event->pmu); + struct arm_cmn_hw_event *hw = to_cmn_hw(event); + enum cmn_node_type type = CMN_EVENT_TYPE(event); + + arm_cmn_event_stop(event, PERF_EF_UPDATE); + + if (type == CMN_TYPE_DTC) + cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL; + else + arm_cmn_event_clear(cmn, event, hw->num_dns); +} + +/* + * We stop the PMU for both add and read, to avoid skew across DTM counters. + * In theory we could use snapshots to read without stopping, but then it + * becomes a lot trickier to deal with overlow and racing against interrupts, + * plus it seems they don't work properly on some hardware anyway :( + */ +static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) +{ + arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); +} + +static void arm_cmn_end_txn(struct pmu *pmu) +{ + arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); +} + +static int arm_cmn_commit_txn(struct pmu *pmu) +{ + arm_cmn_end_txn(pmu); + return 0; +} + +static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct arm_cmn *cmn; + unsigned int target; + + cmn = hlist_entry_safe(node, struct arm_cmn, cpuhp_node); + if (cpu != cmn->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&cmn->pmu, cpu, target); + cmn->cpu = target; + return 0; +} + +static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) +{ + struct arm_cmn_dtc *dtc = dev_id; + irqreturn_t ret = IRQ_NONE; + + for (;;) { + u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR); + u64 delta; + int i; + + for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) { + if (status & (1U << i)) { + ret = IRQ_HANDLED; + if (WARN_ON(!dtc->counters[i])) + continue; + delta = (u64)arm_cmn_read_counter(dtc, i) << 16; + local64_add(delta, &dtc->counters[i]->count); + } + } + + if (status & (1U << CMN_DT_NUM_COUNTERS)) { + ret = IRQ_HANDLED; + if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { + delta = arm_cmn_read_cc(dtc); + local64_add(delta, &dtc->cycles->count); + } + } + + writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR); + + if (!dtc->irq_friend) + return ret; + dtc += dtc->irq_friend; + } +} + +/* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ +static int arm_cmn_init_irqs(struct arm_cmn *cmn) +{ + int i, j, irq, err; + + for (i = 0; i < cmn->num_dtcs; i++) { + irq = cmn->dtc[i].irq; + for (j = i; j--; ) { + if (cmn->dtc[j].irq == irq) { + cmn->dtc[j].irq_friend = j - i; + goto next; + } + } + err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, + IRQF_NOBALANCING | IRQF_NO_THREAD, + dev_name(cmn->dev), &cmn->dtc[i]); + if (err) + return err; + + err = irq_set_affinity_hint(irq, cpumask_of(cmn->cpu)); + if (err) + return err; + next: + ; /* isn't C great? */ + } + return 0; +} + +static void arm_cmn_init_dtm(struct arm_cmn_node *xp) +{ + int i; + + for (i = 0; i < 4; i++) { + xp->wp_event[i] = -1; + writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i)); + writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i)); + } + xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; + xp->dtc = -1; +} + +static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) +{ + struct arm_cmn_dtc *dtc = cmn->dtc + idx; + struct arm_cmn_node *xp; + + dtc->base = dn->pmu_base - CMN_PMU_OFFSET; + dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); + if (dtc->irq < 0) + return dtc->irq; + + writel_relaxed(0, dtc->base + CMN_DT_PMCR); + writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); + writel_relaxed(CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR); + + /* We do at least know that a DTC's XP must be in that DTC's domain */ + xp = arm_cmn_node_to_xp(dn); + xp->dtc = idx; + + return 0; +} + +static int arm_cmn_node_cmp(const void *a, const void *b) +{ + const struct arm_cmn_node *dna = a, *dnb = b; + int cmp; + + cmp = dna->type - dnb->type; + if (!cmp) + cmp = dna->logid - dnb->logid; + return cmp; +} + +static int arm_cmn_init_dtcs(struct arm_cmn *cmn) +{ + struct arm_cmn_node *dn; + int dtc_idx = 0; + + cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); + if (!cmn->dtc) + return -ENOMEM; + + sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); + + cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); + + for (dn = cmn->dns; dn < cmn->dns + cmn->num_dns; dn++) { + if (dn->type != CMN_TYPE_XP) + arm_cmn_init_node_to_xp(cmn, dn); + else if (cmn->num_dtcs == 1) + dn->dtc = 0; + + if (dn->type == CMN_TYPE_DTC) + arm_cmn_init_dtc(cmn, dn, dtc_idx++); + + /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ + if (dn->type == CMN_TYPE_RND) + dn->type = CMN_TYPE_RNI; + } + + writel_relaxed(CMN_DT_DTC_CTL_DT_EN, cmn->dtc[0].base + CMN_DT_DTC_CTL); + + return 0; +} + +static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) +{ + int level; + u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); + + node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); + node->id = FIELD_GET(CMN_NI_NODE_ID, reg); + node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); + + node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET; + + if (node->type == CMN_TYPE_CFG) + level = 0; + else if (node->type == CMN_TYPE_XP) + level = 1; + else + level = 2; + + dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6hx id:%-4hd off:%#x\n", + (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', + node->type, node->logid, offset); +} + +static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) +{ + void __iomem *cfg_region; + struct arm_cmn_node cfg, *dn; + u16 child_count, child_poff; + u32 xp_offset[CMN_MAX_XPS]; + u64 reg; + int i, j; + + cfg_region = cmn->base + rgn_offset; + reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2); + cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); + dev_dbg(cmn->dev, "periph_id_2 revision: %d\n", cmn->rev); + + arm_cmn_init_node_info(cmn, rgn_offset, &cfg); + if (cfg.type != CMN_TYPE_CFG) + return -ENODEV; + + reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); + child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); + child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); + + cmn->num_xps = child_count; + cmn->num_dns = cmn->num_xps; + + /* Pass 1: visit the XPs, enumerate their children */ + for (i = 0; i < cmn->num_xps; i++) { + reg = readq_relaxed(cfg_region + child_poff + i * 8); + xp_offset[i] = reg & CMN_CHILD_NODE_ADDR; + + reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO); + cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); + } + + /* Cheeky +1 to help terminate pointer-based iteration */ + cmn->dns = devm_kcalloc(cmn->dev, cmn->num_dns + 1, + sizeof(*cmn->dns), GFP_KERNEL); + if (!cmn->dns) + return -ENOMEM; + + /* Pass 2: now we can actually populate the nodes */ + dn = cmn->dns; + for (i = 0; i < cmn->num_xps; i++) { + void __iomem *xp_region = cmn->base + xp_offset[i]; + struct arm_cmn_node *xp = dn++; + + arm_cmn_init_node_info(cmn, xp_offset[i], xp); + arm_cmn_init_dtm(xp); + /* + * Thanks to the order in which XP logical IDs seem to be + * assigned, we can handily infer the mesh X dimension by + * looking out for the XP at (0,1) without needing to know + * the exact node ID format, which we can later derive. + */ + if (xp->id == (1 << 3)) + cmn->mesh_x = xp->logid; + + reg = readq_relaxed(xp_region + CMN_CHILD_INFO); + child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); + child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); + + for (j = 0; j < child_count; j++) { + reg = readq_relaxed(xp_region + child_poff + j * 8); + /* + * Don't even try to touch anything external, since in general + * we haven't a clue how to power up arbitrary CHI requesters. + * As of CMN-600r1 these could only be RN-SAMs or CXLAs, + * neither of which have any PMU events anyway. + * (Actually, CXLAs do seem to have grown some events in r1p2, + * but they don't go to regular XP DTMs, and they depend on + * secure configuration which we can't easily deal with) + */ + if (reg & CMN_CHILD_NODE_EXTERNAL) { + dev_dbg(cmn->dev, "ignoring external node %llx\n", reg); + continue; + } + + arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); + + switch (dn->type) { + case CMN_TYPE_DTC: + cmn->num_dtcs++; + dn++; + break; + /* These guys have PMU events */ + case CMN_TYPE_DVM: + case CMN_TYPE_HNI: + case CMN_TYPE_HNF: + case CMN_TYPE_SBSX: + case CMN_TYPE_RNI: + case CMN_TYPE_RND: + case CMN_TYPE_CXRA: + case CMN_TYPE_CXHA: + dn++; + break; + /* Nothing to see here */ + case CMN_TYPE_RNSAM: + case CMN_TYPE_CXLA: + break; + /* Something has gone horribly wrong */ + default: + dev_err(cmn->dev, "invalid device node type: 0x%hx\n", dn->type); + return -ENODEV; + } + } + } + + /* Correct for any nodes we skipped */ + cmn->num_dns = dn - cmn->dns; + + /* + * If mesh_x wasn't set during discovery then we never saw + * an XP at (0,1), thus we must have an Nx1 configuration. + */ + if (!cmn->mesh_x) + cmn->mesh_x = cmn->num_xps; + cmn->mesh_y = cmn->num_xps / cmn->mesh_x; + + dev_dbg(cmn->dev, "mesh %dx%d, ID width %d\n", + cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn)); + + return 0; +} + +static int arm_cmn_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) +{ + struct resource *cfg, *root; + + cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!cfg) + return -EINVAL; + + root = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!root) + return -EINVAL; + + if (!resource_contains(cfg, root)) + swap(cfg, root); + /* + * Note that devm_ioremap_resource() is dumb and won't let the platform + * device claim cfg when the ACPI companion device has already claimed + * root within it. But since they *are* already both claimed in the + * appropriate name, we don't really need to do it again here anyway. + */ + cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); + if (!cmn->base) + return -ENOMEM; + + return root->start - cfg->start; +} + +static int arm_cmn_of_probe(struct platform_device *pdev, struct arm_cmn *cmn) +{ + struct device_node *np = pdev->dev.of_node; + u32 rootnode; + int ret; + + cmn->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cmn->base)) + return PTR_ERR(cmn->base); + + ret = of_property_read_u32(np, "arm,root-node", &rootnode); + if (ret) + return ret; + + return rootnode; +} + +static int arm_cmn_probe(struct platform_device *pdev) +{ + struct arm_cmn *cmn; + const char *name; + static atomic_t id; + int err, rootnode, this_id; + + cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); + if (!cmn) + return -ENOMEM; + + cmn->dev = &pdev->dev; + platform_set_drvdata(pdev, cmn); + + if (has_acpi_companion(cmn->dev)) + rootnode = arm_cmn_acpi_probe(pdev, cmn); + else + rootnode = arm_cmn_of_probe(pdev, cmn); + if (rootnode < 0) + return rootnode; + + err = arm_cmn_discover(cmn, rootnode); + if (err) + return err; + + err = arm_cmn_init_dtcs(cmn); + if (err) + return err; + + err = arm_cmn_init_irqs(cmn); + if (err) + return err; + + cmn->cpu = raw_smp_processor_id(); + cmn->pmu = (struct pmu) { + .module = THIS_MODULE, + .attr_groups = arm_cmn_attr_groups, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr = perf_invalid_context, + .pmu_enable = arm_cmn_pmu_enable, + .pmu_disable = arm_cmn_pmu_disable, + .event_init = arm_cmn_event_init, + .add = arm_cmn_event_add, + .del = arm_cmn_event_del, + .start = arm_cmn_event_start, + .stop = arm_cmn_event_stop, + .read = arm_cmn_event_read, + .start_txn = arm_cmn_start_txn, + .commit_txn = arm_cmn_commit_txn, + .cancel_txn = arm_cmn_end_txn, + }; + + this_id = atomic_fetch_inc(&id); + if (this_id == 0) { + name = "arm_cmn"; + } else { + name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); + if (!name) + return -ENOMEM; + } + + err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); + if (err) + return err; + + err = perf_pmu_register(&cmn->pmu, name, -1); + if (err) + cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node); + return err; +} + +static int arm_cmn_remove(struct platform_device *pdev) +{ + struct arm_cmn *cmn = platform_get_drvdata(pdev); + int i; + + writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); + + perf_pmu_unregister(&cmn->pmu); + cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node); + + for (i = 0; i < cmn->num_dtcs; i++) + irq_set_affinity_hint(cmn->dtc[i].irq, NULL); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id arm_cmn_of_match[] = { + { .compatible = "arm,cmn-600", }, + {} +}; +MODULE_DEVICE_TABLE(of, arm_cmn_of_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id arm_cmn_acpi_match[] = { + { "ARMHC600", }, + {} +}; +MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); +#endif + +static struct platform_driver arm_cmn_driver = { + .driver = { + .name = "arm-cmn", + .of_match_table = of_match_ptr(arm_cmn_of_match), + .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), + }, + .probe = arm_cmn_probe, + .remove = arm_cmn_remove, +}; + +static int __init arm_cmn_init(void) +{ + int ret; + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/arm/cmn:online", NULL, + arm_cmn_pmu_offline_cpu); + if (ret < 0) + return ret; + + arm_cmn_hp_state = ret; + ret = platform_driver_register(&arm_cmn_driver); + if (ret) + cpuhp_remove_multi_state(arm_cmn_hp_state); + return ret; +} + +static void __exit arm_cmn_exit(void) +{ + platform_driver_unregister(&arm_cmn_driver); + cpuhp_remove_multi_state(arm_cmn_hp_state); +} + +module_init(arm_cmn_init); +module_exit(arm_cmn_exit); + +MODULE_AUTHOR("Robin Murphy "); +MODULE_DESCRIPTION("Arm CMN-600 PMU driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri May 21 07:00:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:52 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 06/18] perf: Add Arm CMN-600 DT binding Date: Fri, 21 May 2021 03:00:30 -0400 Message-Id: <20210521070042.1445-9-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Robin Murphy BugLink: https://bugs.launchpad.net/bugs/1925421 Document the requirements for the CMN-600 DT binding. The internal topology is almost entirely discoverable by walking a tree of ID registers, but sadly both the starting point for that walk and the exact format of those registers are configuration-dependent and not discoverable from some sane fixed location. Oh well. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon (cherry picked from commit c8fdbbfa981a7bc64acec234620788c97d1f6a88) Signed-off-by: Khalid Elmously --- .../devicetree/bindings/perf/arm,cmn.yaml | 57 +++++++++++++++++++ debian.oracle/config/config.common.ubuntu | 1 + 2 files changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/arm,cmn.yaml diff --git a/Documentation/devicetree/bindings/perf/arm,cmn.yaml b/Documentation/devicetree/bindings/perf/arm,cmn.yaml new file mode 100644 index 000000000000..e4fcc0de25e2 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,cmn.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2020 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,cmn.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CMN (Coherent Mesh Network) Performance Monitors + +maintainers: + - Robin Murphy + +properties: + compatible: + const: arm,cmn-600 + + reg: + items: + - description: Physical address of the base (PERIPHBASE) and + size (up to 64MB) of the configuration address space. + + interrupts: + minItems: 1 + maxItems: 4 + items: + - description: Overflow interrupt for DTC0 + - description: Overflow interrupt for DTC1 + - description: Overflow interrupt for DTC2 + - description: Overflow interrupt for DTC3 + description: One interrupt for each DTC domain implemented must + be specified, in order. DTC0 is always present. + + arm,root-node: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset from PERIPHBASE of the configuration + discovery node (see TRM definition of ROOTNODEBASE). + +required: + - compatible + - reg + - interrupts + - arm,root-node + +additionalProperties: false + +examples: + - | + #include + #include + pmu@50000000 { + compatible = "arm,cmn-600"; + reg = <0x50000000 0x4000000>; + /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */ + interrupts = ; + arm,root-node = <0x104000>; + }; +... diff --git a/debian.oracle/config/config.common.ubuntu b/debian.oracle/config/config.common.ubuntu index 442dc5e19149..377cb3c4ed52 100644 --- a/debian.oracle/config/config.common.ubuntu +++ b/debian.oracle/config/config.common.ubuntu @@ -511,6 +511,7 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set +CONFIG_ARM_CMN=m # CONFIG_ARM_CPUIDLE is not set # CONFIG_ARM_DSU_PMU is not set CONFIG_ARM_GIC=y From patchwork Fri May 21 07:00:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwC5n6nz9sW1; Fri, 21 May 2021 17:01:31 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9x-0000GO-4T; Fri, 21 May 2021 07:01:25 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9T-0008M5-ON for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:55 +0000 Received: from mail-qk1-f197.google.com ([209.85.222.197]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9T-0000bt-9w for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:55 +0000 Received: by mail-qk1-f197.google.com with SMTP id b19-20020a05620a0893b02902e956b29f5dso15284880qka.16 for ; Fri, 21 May 2021 00:00:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5eGVmAw6UXyNgpqdULBeNYVXCaTCtDDmI3aXkHciU/Y=; b=B0dagbtAhOBRPrVDFi0PHjh2IxTxV3XB6GpNoq7wmvbsaxej5E4tCY4JcIdrqfKCvn Z3Rzvt9CtD91h8UTZXaJkB28vhxPyzE+wuCgedn4WvLUCN0yc2Gtn4Ze0drBCTSgujWn y9bHyMbjhttLzqe6XBKK73JyX3sUymOXCSHix8eNckq9WNnRIkVosA4wxduliriCYNm9 2wfPk6SwA+yN9FupLpy1O8Uc4N5X9tClfDKmKpkXSh5ihyjfT8Luwt2vz0fJudfMlHWO HAeKYiHQjnZ+xebWbkNP044/Q2qu+/iHDxgdKwPPcRCe6k7Owwskji4rHD7exrrPXcVY rj4w== X-Gm-Message-State: AOAM533tjGJILAeAqb0YQ0Dmufj7FJBZI7Hq4C1ovVWvM8he9dKUxR/U +ZcpxEZOtVSaGVwLhbo5mUSS4cY6crb3p4G6jgDjTiDnN1Rd5TrtURC4Cpt2eqMzCr+tLSJOqOn 17cilF6xV3vt6QMeW4V0A1ipTu/k1Njheua+ZCo4Ojw== X-Received: by 2002:a05:620a:951:: with SMTP id w17mr9928199qkw.50.1621580454331; Fri, 21 May 2021 00:00:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZfXf2p5mnTbkSdhTDZgD5xdlgN8Vl89MS5kL02xz1MhU8gTgZN4ukb9SkYd7ii8zKcfn6Rw== X-Received: by 2002:a05:620a:951:: with SMTP id w17mr9928177qkw.50.1621580453965; Fri, 21 May 2021 00:00:53 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:53 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 07/18] UBUNTU: SAUCE: hwmon: Add Ampere Altra HW monitor driver Date: Fri, 21 May 2021 03:00:31 -0400 Message-Id: <20210521070042.1445-10-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: lho BugLink: https://bugs.launchpad.net/bugs/1925421 Add Ampere Altra HW monitor driver to support per core energy and SoC temperature reporting. Signed-off-by: lho Signed-off-by: lho (backported from commit f2e6dee522cc4be9dd094c30dc88273f44d5ffe2 https://github.com/AmpereComputing/ampere-centos-kernel) [ kmously: context adjustment in drivers/hwmon/Makefile ] Signed-off-by: Khalid Elmously --- drivers/hwmon/Kconfig | 10 + drivers/hwmon/Makefile | 1 + drivers/hwmon/altra-hwmon.c | 435 ++++++++++++++++++++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 drivers/hwmon/altra-hwmon.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 288ae9f63588..e94d68d1dcc3 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -334,6 +334,16 @@ config SENSORS_AMD_ENERGY This driver can also be built as a module. If so, the module will be called as amd_energy. +config SENSORS_ALTRA + tristate "Altra sensors driver" + depends on ARM64 + help + If you say yes here you get support for Ampere SoC core and package + sensors for Ampere Altra CPUs. + + This driver can also be built as a module. If so, the module + will be called as altra-hwmon. + config SENSORS_APPLESMC tristate "Apple SMC (Motion sensor, light sensor, keyboard backlight)" depends on INPUT && X86 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 3e32c21f5efe..f4b8367cde40 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SENSORS_ADT7462) += adt7462.o obj-$(CONFIG_SENSORS_ADT7470) += adt7470.o obj-$(CONFIG_SENSORS_ADT7475) += adt7475.o obj-$(CONFIG_SENSORS_AMD_ENERGY) += amd_energy.o +obj-$(CONFIG_SENSORS_ALTRA) += altra-hwmon.o obj-$(CONFIG_SENSORS_APPLESMC) += applesmc.o obj-$(CONFIG_SENSORS_ARM_SCMI) += scmi-hwmon.o obj-$(CONFIG_SENSORS_ARM_SCPI) += scpi-hwmon.o diff --git a/drivers/hwmon/altra-hwmon.c b/drivers/hwmon/altra-hwmon.c new file mode 100644 index 000000000000..12460edd5f18 --- /dev/null +++ b/drivers/hwmon/altra-hwmon.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Ampere Altra SoC Hardware Monitoring Driver + * + * Copyright (C) 2020 Ampere Computing LLC + * Author: Loc Ho + * Hoan Tran + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "altra_hwmon" +#define ALTRA_HWMON_VER1 1 +#define ALTRA_HWMON_VER2 2 + +#define HW_SUPPORTED_VER 1 + +#define UNIT_DEGREE_CELSIUS 0x0001 +#define UNIT_JOULE 0x0010 +#define UNIT_MILLI_JOULE 0x0011 +#define UNIT_MICRO_JOULE 0x0012 + +#define HW_METRIC_LABEL_REG 0x0000 +#define HW_METRIC_LABEL_SIZE 16 +#define HW_METRIC_INFO_REG 0x0010 +#define HW_METRIC_INFO_UNIT_RD(x) ((x) & 0xFF) +#define HW_METRIC_INFO_DATASIZE_RD(x) (((x) >> 8) & 0xFF) +#define HW_METRIC_INFO_DATACNT_RD(x) (((x) >> 16) & 0xFFFF) +#define HW_METRIC_DATA_REG 0x0018 +#define HW_METRIC_HDRSIZE 24 + +#define HW_METRICS_ID_REG 0x0000 +#define HW_METRICS_ID 0x304D5748 /* HWM0 */ +#define HW_METRICS_INFO_REG 0x0004 +#define HW_METRICS_INFO_VER_RD(x) ((x) & 0xFFFF) +#define HW_METRICS_INFO_CNT_RD(x) (((x) >> 16) & 0xFFFF) +#define HW_METRICS_DATA_REG 0x0008 +#define HW_METRICS_HDRSIZE 8 + +#define SENSOR_ITEM_LABEL_SIZE (HW_METRIC_LABEL_SIZE + 3 + 1) + +struct sensor_item { + char label[SENSOR_ITEM_LABEL_SIZE]; /* NULL terminator label */ + u32 scale_factor; /* Convert HW unit to HWmon unnt */ + u8 data_size; /* 4 or 8 bytes */ + u32 hw_reg; /* Registor offset to data */ +}; + +struct altra_hwmon_context { + struct hwmon_channel_info *channel_info; + const struct hwmon_channel_info **info; + struct hwmon_chip_info chip; + struct sensor_item *sensor_list[hwmon_max]; + u32 sensor_list_cnt[hwmon_max]; + struct device *dev; + struct device *hwmon_dev; + void __iomem *base; + u32 base_size; +}; + +static u32 altra_hwmon_read32(struct altra_hwmon_context *ctx, u32 reg) +{ + return readl_relaxed(ctx->base + reg); +} + +static u64 altra_hwmon_read64(struct altra_hwmon_context *ctx, u32 reg) +{ + return readq_relaxed(ctx->base + reg); +} + +static int altra_hwmon_read_labels(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, const char **str) +{ + struct altra_hwmon_context *ctx = dev_get_drvdata(dev); + struct sensor_item *item; + + if (type >= hwmon_max) + return -EINVAL; + if (channel >= ctx->sensor_list_cnt[type]) + return -EINVAL; + + item = ctx->sensor_list[type]; + *str = item[channel].label; + return 0; +} + +static int altra_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct altra_hwmon_context *ctx = dev_get_drvdata(dev); + struct sensor_item *item; + + if (type >= hwmon_max) + return -EINVAL; + if (channel >= ctx->sensor_list_cnt[type]) + return -EINVAL; + + item = ctx->sensor_list[type]; + if (item[channel].data_size == 4) + *val = altra_hwmon_read32(ctx, item[channel].hw_reg); + else + *val = altra_hwmon_read64(ctx, item[channel].hw_reg); + *val *= item[channel].scale_factor; + + return 0; +} + +static umode_t altra_hwmon_is_visible(const void *_data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + return 0444; +} + +static const struct hwmon_ops altra_hwmon_ops = { + .is_visible = altra_hwmon_is_visible, + .read = altra_hwmon_read, + .read_string = altra_hwmon_read_labels, +}; + +static enum hwmon_sensor_types altra_hwmon_unit2type(u8 unit) +{ + switch (unit) { + case UNIT_DEGREE_CELSIUS: + return hwmon_temp; + case UNIT_JOULE: + case UNIT_MILLI_JOULE: + case UNIT_MICRO_JOULE: + return hwmon_energy; + } + return hwmon_max; +} + +static u32 altra_hwmon_scale_factor(u8 unit) +{ + switch (unit) { + case UNIT_DEGREE_CELSIUS: + return 1000; + case UNIT_JOULE: + return 1000000; + case UNIT_MILLI_JOULE: + return 1000; + case UNIT_MICRO_JOULE: + return 1; + } + return 1; +} + +static u32 altra_hwmon_type2flag(enum hwmon_sensor_types type) +{ + switch (type) { + case hwmon_energy: + return HWMON_E_INPUT | HWMON_E_LABEL; + case hwmon_temp: + return HWMON_T_LABEL | HWMON_T_INPUT; + default: + return 0; + } +} + +static int altra_sensor_is_valid(struct altra_hwmon_context *ctx, u32 reg, u32 data_size) +{ + int val; + + if (data_size == 4) + val = altra_hwmon_read32(ctx, reg); + else + val = altra_hwmon_read64(ctx, reg); + + return val ? 1 : 0; +} + +static int altra_create_sensor(struct altra_hwmon_context *ctx, + u32 metric_info, + struct hwmon_channel_info *info) +{ + enum hwmon_sensor_types type; + char label[SENSOR_ITEM_LABEL_SIZE]; + struct sensor_item *item_list; + struct sensor_item *item; + int data_size; + u32 *s_config; + u32 hw_info; + u32 total; + int i, j; + + /* Check for supported type */ + hw_info = altra_hwmon_read32(ctx, metric_info + HW_METRIC_INFO_REG); + type = altra_hwmon_unit2type(HW_METRIC_INFO_UNIT_RD(hw_info)); + if (type == hwmon_max) { + dev_err(ctx->dev, + "malform info header @ 0x%x value 0x%x. Ignore remaining\n", + metric_info + HW_METRIC_INFO_REG, hw_info); + return -ENODEV; + } + + /* Label */ + for (i = 0; i < HW_METRIC_LABEL_SIZE; i += 4) + *(u32 *)&label[i] = altra_hwmon_read32(ctx, + metric_info + HW_METRIC_LABEL_REG + i); + label[sizeof(label) - 1] = '\0'; + if (strlen(label) <= 0) { + dev_err(ctx->dev, + "malform label header 0x%x. Ignore remaining\n", + metric_info + HW_METRIC_LABEL_REG); + return -ENODEV; + } + + total = HW_METRIC_INFO_DATACNT_RD(hw_info); + data_size = HW_METRIC_INFO_DATASIZE_RD(hw_info); + /* Get the total valid sensors */ + j = 0; + for (i = 0; i < total; i++) { + if (altra_sensor_is_valid(ctx, metric_info + HW_METRIC_DATA_REG + + i * data_size, data_size)) + j++; + } + total = j; + + if (!ctx->sensor_list[type]) { + ctx->sensor_list[type] = devm_kzalloc(ctx->dev, + sizeof(struct sensor_item) * total, + GFP_KERNEL); + } else { + item_list = devm_kzalloc(ctx->dev, + sizeof(*item) * (ctx->sensor_list_cnt[type] + total), + GFP_KERNEL); + if (!item_list) + return -ENOMEM; + memcpy(item_list, ctx->sensor_list[type], + sizeof(*item) * ctx->sensor_list_cnt[type]); + devm_kfree(ctx->dev, ctx->sensor_list[type]); + ctx->sensor_list[type] = item_list; + } + + s_config = devm_kcalloc(ctx->dev, total, sizeof(u32), GFP_KERNEL); + if (!s_config) + return -ENOMEM; + info->type = type; + info->config = s_config; + + /* Set up sensor entry */ + item_list = ctx->sensor_list[type]; + j = 0; + for (i = 0; i < HW_METRIC_INFO_DATACNT_RD(hw_info); i++) { + /* Check if sensor is valid */ + if (!altra_sensor_is_valid(ctx, metric_info + HW_METRIC_DATA_REG + + i * data_size, data_size)) + continue; + + item = &item_list[ctx->sensor_list_cnt[type]]; + item->hw_reg = metric_info + HW_METRIC_DATA_REG + i * data_size; + scnprintf(item->label, SENSOR_ITEM_LABEL_SIZE, "%s %03u", label, j); + item->scale_factor = altra_hwmon_scale_factor(HW_METRIC_INFO_UNIT_RD(hw_info)); + item->data_size = data_size; + s_config[j] = altra_hwmon_type2flag(type); + ctx->sensor_list_cnt[type]++; + j++; + } + + return 0; +} + +static int altra_hwmon_create_sensors(struct altra_hwmon_context *ctx) +{ + u32 metrics_info; + u32 total_metric; + u32 hw_reg; + u32 hw_end_reg; + int ret; + u32 val; + int i; + int used; + + if (altra_hwmon_read32(ctx, HW_METRICS_ID_REG) != HW_METRICS_ID) + return -ENODEV; + + metrics_info = altra_hwmon_read32(ctx, HW_METRICS_INFO_REG); + if (HW_METRICS_INFO_VER_RD(metrics_info) != HW_SUPPORTED_VER) + return -ENODEV; + + total_metric = HW_METRICS_INFO_CNT_RD(metrics_info); + ctx->channel_info = devm_kzalloc(ctx->dev, + sizeof(struct hwmon_channel_info) * total_metric, + GFP_KERNEL); + if (!ctx->channel_info) + return -ENOMEM; + ctx->info = devm_kzalloc(ctx->dev, + sizeof(struct hwmon_channel_info *) * (total_metric + 1), + GFP_KERNEL); + if (!ctx->info) + return -ENOMEM; + + hw_reg = HW_METRICS_HDRSIZE; + for (used = 0, i = 0; i < total_metric; i++) { + /* Check for out of bound */ + if ((hw_reg + HW_METRIC_HDRSIZE) > ctx->base_size) { + dev_err(ctx->dev, + "malform metric header 0x%x (exceeded range). Ignore remaining\n", + hw_reg); + break; + } + + /* + * At least a metric header. Check with data. + */ + val = altra_hwmon_read32(ctx, hw_reg + HW_METRIC_INFO_REG); + hw_end_reg = hw_reg + HW_METRIC_HDRSIZE + + HW_METRIC_INFO_DATASIZE_RD(val) * + HW_METRIC_INFO_DATACNT_RD(val); + if (hw_end_reg > ctx->base_size) { + dev_err(ctx->dev, + "malform metric data 0x%x (exceeded range). Ignore remaining\n", + hw_reg); + break; + } + ret = altra_create_sensor(ctx, hw_reg, &ctx->channel_info[used]); + + /* 64-bit alignment */ + hw_reg = hw_end_reg; + hw_reg = ((hw_reg + 7) / 8) * 8; + if (ret == -ENODEV) + continue; + if (ret < 0) + return ret; + ctx->info[used] = &ctx->channel_info[used]; + used++; + } + ctx->info[used] = NULL; + return 0; +} + +static int altra_hwmon_probe(struct platform_device *pdev) +{ + const struct acpi_device_id *acpi_id; + struct altra_hwmon_context *ctx; + struct device *dev = &pdev->dev; + struct resource *res; + int version; + int err; + + ctx = devm_kzalloc(dev, sizeof(struct altra_hwmon_context), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + dev_set_drvdata(dev, ctx); + ctx->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); + if (!acpi_id) + return -EINVAL; + + version = (int)acpi_id->driver_data; + + ctx->base_size = resource_size(res); + if (version == ALTRA_HWMON_VER1) + ctx->base = devm_ioremap_resource(dev, res); + else + ctx->base = memremap(res->start, ctx->base_size, MEMREMAP_WB); + if (IS_ERR(ctx->base)) + return PTR_ERR(ctx->base); + + /* Create sensors */ + err = altra_hwmon_create_sensors(ctx); + if (err != 0) { + if (err == -ENODEV) + dev_err(dev, "No sensor\n"); + else + dev_err(dev, "Failed to create sensors error %d\n", err); + return err; + } + + ctx->chip.ops = &altra_hwmon_ops; + ctx->chip.info = ctx->info; + ctx->hwmon_dev = devm_hwmon_device_register_with_info(dev, DRVNAME, ctx, + &ctx->chip, NULL); + if (IS_ERR(ctx->hwmon_dev)) { + dev_err(dev, "Fail to register with HWmon\n"); + err = PTR_ERR(ctx->hwmon_dev); + return err; + } + + return 0; +} + +static int altra_hwmon_remove(struct platform_device *pdev) +{ + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id altra_hwmon_acpi_match[] = { + {"AMPC0005", ALTRA_HWMON_VER1}, + {"AMPC0006", ALTRA_HWMON_VER2}, + { }, +}; +MODULE_DEVICE_TABLE(acpi, altra_hwmon_acpi_match); +#endif + +static struct platform_driver altra_hwmon_driver = { + .probe = altra_hwmon_probe, + .remove = altra_hwmon_remove, + .driver = { + .name = "altra-hwmon", + .acpi_match_table = ACPI_PTR(altra_hwmon_acpi_match), + }, +}; +module_platform_driver(altra_hwmon_driver); + +MODULE_DESCRIPTION("Altra SoC hardware sensor monitor"); +MODULE_LICENSE("GPL v2"); From patchwork Fri May 21 07:00:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwJ1lGgz9sW4; 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:54 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 08/18] arm64: NUMA: Kconfig: Increase NODES_SHIFT to 4 Date: Fri, 21 May 2021 03:00:32 -0400 Message-Id: <20210521070042.1445-11-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Vanshidhar Konda BugLink: https://bugs.launchpad.net/bugs/1925421 The current arm64 default config limits max NUMA nodes available on system to 4 (NODES_SHIFT = 2). Today's arm64 systems can reach or exceed 16 NUMA nodes. To accomodate current hardware and to fit NODES_SHIFT within page flags on arm64, increase NODES_SHIFT to 4. Signed-off-by: Vanshidhar Konda Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20201020173409.1266576-1-vanshikonda@os.amperecomputing.com/ Link: https://lore.kernel.org/r/20201030173050.1182876-1-vanshikonda@os.amperecomputing.com Signed-off-by: Will Deacon (cherry picked from commit 2a13c13b39a8aea4c69a31549e4cb0094f30103b) Signed-off-by: Khalid Elmously --- arch/arm64/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 587b2a429892..19631f22c547 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -972,7 +972,7 @@ config NUMA config NODES_SHIFT int "Maximum NUMA Nodes (as a power of 2)" range 1 10 - default "2" + default "4" depends on NEED_MULTIPLE_NODES help Specify the maximum number of NUMA Nodes available on the target From patchwork Fri May 21 07:00:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwQ1W8Cz9sRf; Fri, 21 May 2021 17:01:42 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzA7-0000NI-6t; Fri, 21 May 2021 07:01:35 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9V-0008N8-Ev for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:57 +0000 Received: from mail-qk1-f198.google.com ([209.85.222.198]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9V-0000cI-1X for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:57 +0000 Received: by mail-qk1-f198.google.com with SMTP id o14-20020a05620a0d4eb02903a5eee61155so4869873qkl.9 for ; Fri, 21 May 2021 00:00:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DqZhe4SVvesQpcP+HL6rA8xTTIGHLhx7gSqFfXSxRQo=; b=L02X2q7ZPaQODRz/gGtdjjfgZIvsfCIHJHfartyQl2+B/KO3l0Mio8aI2LDQry4O8F Se+fYN+EABCAUrB1sVP774ozcMJUF3CKvd3Y4cqJoQUC+VkptyNpwGKOkpVBbVH/LCrB kMmKuwhObUOiY6/GKg4WTZXsgRNoBkqC2O8e5iBfq1Kc05CZBvZVZXMDEgk7awHbb4Xq m8CHkihYMscZb3ao2Bzg/DOoh0QOvI35F+Kjc4zMMxBOHbLEeeiOC2pT2m1dfiSn5Ztp sXw4dDIBiJB3GFsra39EichRDB4dGoUFFDjf9Dvb2MunJtwfikXlcDDrqMT0SDLGbP3Q GtMQ== X-Gm-Message-State: AOAM530+TfdhCUonMMoJCOcexGTgIRMVILHqxY9FSOjmeJYzzkzJruCp YtNP1/I3OlAcPwN4B/afNYHItJpPPsuwxG+rdfVuDc+C9PXIS89hg/f0msgnXqgAYCqbO1aYAEz CXTGNOKEEzDdfScRIv/deKa69hPGUimBl7AJF69vwCw== X-Received: by 2002:ac8:758e:: with SMTP id s14mr9925578qtq.341.1621580456036; Fri, 21 May 2021 00:00:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjC3jT6OlUwxHxKtGp95osbRkom3jz+7AbTTIeahFlJNDXhK3mNhgXHkXssO/gQ8Xg8gt8IQ== X-Received: by 2002:ac8:758e:: with SMTP id s14mr9925547qtq.341.1621580455615; Fri, 21 May 2021 00:00:55 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:55 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 09/18] driver/perf: Add PMU driver for the ARM DMC-620 memory controller Date: Fri, 21 May 2021 03:00:33 -0400 Message-Id: <20210521070042.1445-12-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Tuan Phan BugLink: https://bugs.launchpad.net/bugs/1925421 DMC-620 PMU supports total 10 counters which each is independently programmable to different events and can be started and stopped individually. Currently, it only supports ACPI. Other platforms feel free to test and add support for device tree. Usage example: #perf stat -e arm_dmc620_10008c000/clk_cycle_count/ -C 0 Get perf event for clk_cycle_count counter. #perf stat -e arm_dmc620_10008c000/clkdiv2_allocate,mask=0x1f,match=0x2f, incr=2,invert=1/ -C 0 The above example shows how to specify mask, match, incr, invert parameters for clkdiv2_allocate event. Reviewed-by: Robin Murphy Signed-off-by: Tuan Phan Link: https://lore.kernel.org/r/1604518246-6198-1-git-send-email-tuanphan@os.amperecomputing.com Signed-off-by: Will Deacon (backported from commit 53c218da220c3619b5befec4674ffa35d590092a) [ kmously: Minor context adjustment in drivers/perf/Kconfig ] Signed-off-by: Khalid Elmously --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/arm_dmc620_pmu.c | 748 ++++++++++++++++++++++++++++++++++ 3 files changed, 756 insertions(+) create mode 100644 drivers/perf/arm_dmc620_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index c49c3e1042c2..32774b9f3845 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -129,6 +129,13 @@ config ARM_SPE_PMU Extension, which provides periodic sampling of operations in the CPU pipeline and reports this via the perf AUX interface. +config ARM_DMC620_PMU + tristate "Enable PMU support for the ARM DMC-620 memory controller" + depends on (ARM64 && ACPI) || COMPILE_TEST + help + Support for PMU events monitoring on the ARM DMC-620 memory + controller. + source "drivers/perf/hisilicon/Kconfig" endmenu diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 5365fd56f88f..5260b116c7da 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o +obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o diff --git a/drivers/perf/arm_dmc620_pmu.c b/drivers/perf/arm_dmc620_pmu.c new file mode 100644 index 000000000000..004930eb4bbb --- /dev/null +++ b/drivers/perf/arm_dmc620_pmu.c @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ARM DMC-620 memory controller PMU driver + * + * Copyright (C) 2020 Ampere Computing LLC. + */ + +#define DMC620_PMUNAME "arm_dmc620" +#define DMC620_DRVNAME DMC620_PMUNAME "_pmu" +#define pr_fmt(fmt) DMC620_DRVNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DMC620_PA_SHIFT 12 +#define DMC620_CNT_INIT 0x80000000 +#define DMC620_CNT_MAX_PERIOD 0xffffffff +#define DMC620_PMU_CLKDIV2_MAX_COUNTERS 8 +#define DMC620_PMU_CLK_MAX_COUNTERS 2 +#define DMC620_PMU_MAX_COUNTERS \ + (DMC620_PMU_CLKDIV2_MAX_COUNTERS + DMC620_PMU_CLK_MAX_COUNTERS) + +/* + * The PMU registers start at 0xA00 in the DMC-620 memory map, and these + * offsets are relative to that base. + * + * Each counter has a group of control/value registers, and the + * DMC620_PMU_COUNTERn offsets are within a counter group. + * + * The counter registers groups start at 0xA10. + */ +#define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2 0x8 +#define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2_MASK \ + (DMC620_PMU_CLKDIV2_MAX_COUNTERS - 1) +#define DMC620_PMU_OVERFLOW_STATUS_CLK 0xC +#define DMC620_PMU_OVERFLOW_STATUS_CLK_MASK \ + (DMC620_PMU_CLK_MAX_COUNTERS - 1) +#define DMC620_PMU_COUNTERS_BASE 0x10 +#define DMC620_PMU_COUNTERn_MASK_31_00 0x0 +#define DMC620_PMU_COUNTERn_MASK_63_32 0x4 +#define DMC620_PMU_COUNTERn_MATCH_31_00 0x8 +#define DMC620_PMU_COUNTERn_MATCH_63_32 0xC +#define DMC620_PMU_COUNTERn_CONTROL 0x10 +#define DMC620_PMU_COUNTERn_CONTROL_ENABLE BIT(0) +#define DMC620_PMU_COUNTERn_CONTROL_INVERT BIT(1) +#define DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX GENMASK(6, 2) +#define DMC620_PMU_COUNTERn_CONTROL_INCR_MUX GENMASK(8, 7) +#define DMC620_PMU_COUNTERn_VALUE 0x20 +/* Offset of the registers for a given counter, relative to 0xA00 */ +#define DMC620_PMU_COUNTERn_OFFSET(n) \ + (DMC620_PMU_COUNTERS_BASE + 0x28 * (n)) + +static LIST_HEAD(dmc620_pmu_irqs); +static DEFINE_MUTEX(dmc620_pmu_irqs_lock); + +struct dmc620_pmu_irq { + struct hlist_node node; + struct list_head pmus_node; + struct list_head irqs_node; + refcount_t refcount; + unsigned int irq_num; + unsigned int cpu; +}; + +struct dmc620_pmu { + struct pmu pmu; + + void __iomem *base; + struct dmc620_pmu_irq *irq; + struct list_head pmus_node; + + /* + * We put all clkdiv2 and clk counters to a same array. + * The first DMC620_PMU_CLKDIV2_MAX_COUNTERS bits belong to + * clkdiv2 counters, the last DMC620_PMU_CLK_MAX_COUNTERS + * belong to clk counters. + */ + DECLARE_BITMAP(used_mask, DMC620_PMU_MAX_COUNTERS); + struct perf_event *events[DMC620_PMU_MAX_COUNTERS]; +}; + +#define to_dmc620_pmu(p) (container_of(p, struct dmc620_pmu, pmu)) + +static int cpuhp_state_num; + +struct dmc620_pmu_event_attr { + struct device_attribute attr; + u8 clkdiv2; + u8 eventid; +}; + +static ssize_t +dmc620_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct dmc620_pmu_event_attr *eattr; + + eattr = container_of(attr, typeof(*eattr), attr); + + return sprintf(page, "event=0x%x,clkdiv2=0x%x\n", eattr->eventid, eattr->clkdiv2); +} + +#define DMC620_PMU_EVENT_ATTR(_name, _eventid, _clkdiv2) \ + (&((struct dmc620_pmu_event_attr[]) {{ \ + .attr = __ATTR(_name, 0444, dmc620_pmu_event_show, NULL), \ + .clkdiv2 = _clkdiv2, \ + .eventid = _eventid, \ + }})[0].attr.attr) + +static struct attribute *dmc620_pmu_events_attrs[] = { + /* clkdiv2 events list */ + DMC620_PMU_EVENT_ATTR(clkdiv2_cycle_count, 0x0, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_allocate, 0x1, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_queue_depth, 0x2, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_waiting_for_wr_data, 0x3, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_read_backlog, 0x4, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_waiting_for_mi, 0x5, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_hazard_resolution, 0x6, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_enqueue, 0x7, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_arbitrate, 0x8, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_lrank_turnaround_activate, 0x9, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_prank_turnaround_activate, 0xa, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_read_depth, 0xb, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_write_depth, 0xc, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_highigh_qos_depth, 0xd, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_high_qos_depth, 0xe, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_medium_qos_depth, 0xf, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_low_qos_depth, 0x10, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_activate, 0x11, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_rdwr, 0x12, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_refresh, 0x13, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_training_request, 0x14, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_t_mac_tracker, 0x15, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_bk_fsm_tracker, 0x16, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_bk_open_tracker, 0x17, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_ranks_in_pwr_down, 0x18, 1), + DMC620_PMU_EVENT_ATTR(clkdiv2_ranks_in_sref, 0x19, 1), + + /* clk events list */ + DMC620_PMU_EVENT_ATTR(clk_cycle_count, 0x0, 0), + DMC620_PMU_EVENT_ATTR(clk_request, 0x1, 0), + DMC620_PMU_EVENT_ATTR(clk_upload_stall, 0x2, 0), + NULL, +}; + +static struct attribute_group dmc620_pmu_events_attr_group = { + .name = "events", + .attrs = dmc620_pmu_events_attrs, +}; + +/* User ABI */ +#define ATTR_CFG_FLD_mask_CFG config +#define ATTR_CFG_FLD_mask_LO 0 +#define ATTR_CFG_FLD_mask_HI 44 +#define ATTR_CFG_FLD_match_CFG config1 +#define ATTR_CFG_FLD_match_LO 0 +#define ATTR_CFG_FLD_match_HI 44 +#define ATTR_CFG_FLD_invert_CFG config2 +#define ATTR_CFG_FLD_invert_LO 0 +#define ATTR_CFG_FLD_invert_HI 0 +#define ATTR_CFG_FLD_incr_CFG config2 +#define ATTR_CFG_FLD_incr_LO 1 +#define ATTR_CFG_FLD_incr_HI 2 +#define ATTR_CFG_FLD_event_CFG config2 +#define ATTR_CFG_FLD_event_LO 3 +#define ATTR_CFG_FLD_event_HI 8 +#define ATTR_CFG_FLD_clkdiv2_CFG config2 +#define ATTR_CFG_FLD_clkdiv2_LO 9 +#define ATTR_CFG_FLD_clkdiv2_HI 9 + +#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ + (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi + +#define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ + __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) + +#define GEN_PMU_FORMAT_ATTR(name) \ + PMU_FORMAT_ATTR(name, \ + _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \ + ATTR_CFG_FLD_##name##_LO, \ + ATTR_CFG_FLD_##name##_HI)) + +#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \ + ((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0)) + +#define ATTR_CFG_GET_FLD(attr, name) \ + _ATTR_CFG_GET_FLD(attr, \ + ATTR_CFG_FLD_##name##_CFG, \ + ATTR_CFG_FLD_##name##_LO, \ + ATTR_CFG_FLD_##name##_HI) + +GEN_PMU_FORMAT_ATTR(mask); +GEN_PMU_FORMAT_ATTR(match); +GEN_PMU_FORMAT_ATTR(invert); +GEN_PMU_FORMAT_ATTR(incr); +GEN_PMU_FORMAT_ATTR(event); +GEN_PMU_FORMAT_ATTR(clkdiv2); + +static struct attribute *dmc620_pmu_formats_attrs[] = { + &format_attr_mask.attr, + &format_attr_match.attr, + &format_attr_invert.attr, + &format_attr_incr.attr, + &format_attr_event.attr, + &format_attr_clkdiv2.attr, + NULL, +}; + +static struct attribute_group dmc620_pmu_format_attr_group = { + .name = "format", + .attrs = dmc620_pmu_formats_attrs, +}; + +static const struct attribute_group *dmc620_pmu_attr_groups[] = { + &dmc620_pmu_events_attr_group, + &dmc620_pmu_format_attr_group, + NULL, +}; + +static inline +u32 dmc620_pmu_creg_read(struct dmc620_pmu *dmc620_pmu, + unsigned int idx, unsigned int reg) +{ + return readl(dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg); +} + +static inline +void dmc620_pmu_creg_write(struct dmc620_pmu *dmc620_pmu, + unsigned int idx, unsigned int reg, u32 val) +{ + writel(val, dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg); +} + +static +unsigned int dmc620_event_to_counter_control(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + unsigned int reg = 0; + + reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_INVERT, + ATTR_CFG_GET_FLD(attr, invert)); + reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX, + ATTR_CFG_GET_FLD(attr, event)); + reg |= FIELD_PREP(DMC620_PMU_COUNTERn_CONTROL_INCR_MUX, + ATTR_CFG_GET_FLD(attr, incr)); + + return reg; +} + +static int dmc620_get_event_idx(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + int idx, start_idx, end_idx; + + if (ATTR_CFG_GET_FLD(&event->attr, clkdiv2)) { + start_idx = 0; + end_idx = DMC620_PMU_CLKDIV2_MAX_COUNTERS; + } else { + start_idx = DMC620_PMU_CLKDIV2_MAX_COUNTERS; + end_idx = DMC620_PMU_MAX_COUNTERS; + } + + for (idx = start_idx; idx < end_idx; ++idx) { + if (!test_and_set_bit(idx, dmc620_pmu->used_mask)) + return idx; + } + + /* The counters are all in use. */ + return -EAGAIN; +} + +static inline +u64 dmc620_pmu_read_counter(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + + return dmc620_pmu_creg_read(dmc620_pmu, + event->hw.idx, DMC620_PMU_COUNTERn_VALUE); +} + +static void dmc620_pmu_event_update(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + u64 delta, prev_count, new_count; + + do { + /* We may also be called from the irq handler */ + prev_count = local64_read(&hwc->prev_count); + new_count = dmc620_pmu_read_counter(event); + } while (local64_cmpxchg(&hwc->prev_count, + prev_count, new_count) != prev_count); + delta = (new_count - prev_count) & DMC620_CNT_MAX_PERIOD; + local64_add(delta, &event->count); +} + +static void dmc620_pmu_event_set_period(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + + local64_set(&event->hw.prev_count, DMC620_CNT_INIT); + dmc620_pmu_creg_write(dmc620_pmu, + event->hw.idx, DMC620_PMU_COUNTERn_VALUE, DMC620_CNT_INIT); +} + +static void dmc620_pmu_enable_counter(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + u32 reg; + + reg = dmc620_event_to_counter_control(event) | DMC620_PMU_COUNTERn_CONTROL_ENABLE; + dmc620_pmu_creg_write(dmc620_pmu, + event->hw.idx, DMC620_PMU_COUNTERn_CONTROL, reg); +} + +static void dmc620_pmu_disable_counter(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + + dmc620_pmu_creg_write(dmc620_pmu, + event->hw.idx, DMC620_PMU_COUNTERn_CONTROL, 0); +} + +static irqreturn_t dmc620_pmu_handle_irq(int irq_num, void *data) +{ + struct dmc620_pmu_irq *irq = data; + struct dmc620_pmu *dmc620_pmu; + irqreturn_t ret = IRQ_NONE; + + rcu_read_lock(); + list_for_each_entry_rcu(dmc620_pmu, &irq->pmus_node, pmus_node) { + unsigned long status; + struct perf_event *event; + unsigned int idx; + + /* + * HW doesn't provide a control to atomically disable all counters. + * To prevent race condition (overflow happens while clearing status register), + * disable all events before continuing + */ + for (idx = 0; idx < DMC620_PMU_MAX_COUNTERS; idx++) { + event = dmc620_pmu->events[idx]; + if (!event) + continue; + dmc620_pmu_disable_counter(event); + } + + status = readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); + status |= (readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK) << + DMC620_PMU_CLKDIV2_MAX_COUNTERS); + if (status) { + for_each_set_bit(idx, &status, + DMC620_PMU_MAX_COUNTERS) { + event = dmc620_pmu->events[idx]; + if (WARN_ON_ONCE(!event)) + continue; + dmc620_pmu_event_update(event); + dmc620_pmu_event_set_period(event); + } + + if (status & DMC620_PMU_OVERFLOW_STATUS_CLKDIV2_MASK) + writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); + + if ((status >> DMC620_PMU_CLKDIV2_MAX_COUNTERS) & + DMC620_PMU_OVERFLOW_STATUS_CLK_MASK) + writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK); + } + + for (idx = 0; idx < DMC620_PMU_MAX_COUNTERS; idx++) { + event = dmc620_pmu->events[idx]; + if (!event) + continue; + if (!(event->hw.state & PERF_HES_STOPPED)) + dmc620_pmu_enable_counter(event); + } + + ret = IRQ_HANDLED; + } + rcu_read_unlock(); + + return ret; +} + +static struct dmc620_pmu_irq *__dmc620_pmu_get_irq(int irq_num) +{ + struct dmc620_pmu_irq *irq; + int ret; + + list_for_each_entry(irq, &dmc620_pmu_irqs, irqs_node) + if (irq->irq_num == irq_num && refcount_inc_not_zero(&irq->refcount)) + return irq; + + irq = kzalloc(sizeof(*irq), GFP_KERNEL); + if (!irq) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&irq->pmus_node); + + /* Pick one CPU to be the preferred one to use */ + irq->cpu = raw_smp_processor_id(); + refcount_set(&irq->refcount, 1); + + ret = request_irq(irq_num, dmc620_pmu_handle_irq, + IRQF_NOBALANCING | IRQF_NO_THREAD, + "dmc620-pmu", irq); + if (ret) + goto out_free_aff; + + ret = irq_set_affinity_hint(irq_num, cpumask_of(irq->cpu)); + if (ret) + goto out_free_irq; + + ret = cpuhp_state_add_instance_nocalls(cpuhp_state_num, &irq->node); + if (ret) + goto out_free_irq; + + irq->irq_num = irq_num; + list_add(&irq->irqs_node, &dmc620_pmu_irqs); + + return irq; + +out_free_irq: + free_irq(irq_num, irq); +out_free_aff: + kfree(irq); + return ERR_PTR(ret); +} + +static int dmc620_pmu_get_irq(struct dmc620_pmu *dmc620_pmu, int irq_num) +{ + struct dmc620_pmu_irq *irq; + + mutex_lock(&dmc620_pmu_irqs_lock); + irq = __dmc620_pmu_get_irq(irq_num); + mutex_unlock(&dmc620_pmu_irqs_lock); + + if (IS_ERR(irq)) + return PTR_ERR(irq); + + dmc620_pmu->irq = irq; + mutex_lock(&dmc620_pmu_irqs_lock); + list_add_rcu(&dmc620_pmu->pmus_node, &irq->pmus_node); + mutex_unlock(&dmc620_pmu_irqs_lock); + + return 0; +} + +static void dmc620_pmu_put_irq(struct dmc620_pmu *dmc620_pmu) +{ + struct dmc620_pmu_irq *irq = dmc620_pmu->irq; + + mutex_lock(&dmc620_pmu_irqs_lock); + list_del_rcu(&dmc620_pmu->pmus_node); + + if (!refcount_dec_and_test(&irq->refcount)) { + mutex_unlock(&dmc620_pmu_irqs_lock); + return; + } + + list_del(&irq->irqs_node); + mutex_unlock(&dmc620_pmu_irqs_lock); + + WARN_ON(irq_set_affinity_hint(irq->irq_num, NULL)); + free_irq(irq->irq_num, irq); + cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &irq->node); + kfree(irq); +} + +static int dmc620_pmu_event_init(struct perf_event *event) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + struct perf_event *sibling; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* + * DMC 620 PMUs are shared across all cpus and cannot + * support task bound and sampling events. + */ + if (is_sampling_event(event) || + event->attach_state & PERF_ATTACH_TASK) { + dev_dbg(dmc620_pmu->pmu.dev, + "Can't support per-task counters\n"); + return -EOPNOTSUPP; + } + + /* + * Many perf core operations (eg. events rotation) operate on a + * single CPU context. This is obvious for CPU PMUs, where one + * expects the same sets of events being observed on all CPUs, + * but can lead to issues for off-core PMUs, where each + * event could be theoretically assigned to a different CPU. To + * mitigate this, we enforce CPU assignment to one, selected + * processor. + */ + event->cpu = dmc620_pmu->irq->cpu; + if (event->cpu < 0) + return -EINVAL; + + /* + * We can't atomically disable all HW counters so only one event allowed, + * although software events are acceptable. + */ + if (event->group_leader != event && + !is_software_event(event->group_leader)) + return -EINVAL; + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling != event && + !is_software_event(sibling)) + return -EINVAL; + } + + hwc->idx = -1; + return 0; +} + +static void dmc620_pmu_read(struct perf_event *event) +{ + dmc620_pmu_event_update(event); +} + +static void dmc620_pmu_start(struct perf_event *event, int flags) +{ + event->hw.state = 0; + dmc620_pmu_event_set_period(event); + dmc620_pmu_enable_counter(event); +} + +static void dmc620_pmu_stop(struct perf_event *event, int flags) +{ + if (event->hw.state & PERF_HES_STOPPED) + return; + + dmc620_pmu_disable_counter(event); + dmc620_pmu_event_update(event); + event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static int dmc620_pmu_add(struct perf_event *event, int flags) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + struct perf_event_attr *attr = &event->attr; + struct hw_perf_event *hwc = &event->hw; + int idx; + u64 reg; + + idx = dmc620_get_event_idx(event); + if (idx < 0) + return idx; + + hwc->idx = idx; + dmc620_pmu->events[idx] = event; + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + + reg = ATTR_CFG_GET_FLD(attr, mask); + dmc620_pmu_creg_write(dmc620_pmu, + idx, DMC620_PMU_COUNTERn_MASK_31_00, lower_32_bits(reg)); + dmc620_pmu_creg_write(dmc620_pmu, + idx, DMC620_PMU_COUNTERn_MASK_63_32, upper_32_bits(reg)); + + reg = ATTR_CFG_GET_FLD(attr, match); + dmc620_pmu_creg_write(dmc620_pmu, + idx, DMC620_PMU_COUNTERn_MATCH_31_00, lower_32_bits(reg)); + dmc620_pmu_creg_write(dmc620_pmu, + idx, DMC620_PMU_COUNTERn_MATCH_63_32, upper_32_bits(reg)); + + if (flags & PERF_EF_START) + dmc620_pmu_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + return 0; +} + +static void dmc620_pmu_del(struct perf_event *event, int flags) +{ + struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + dmc620_pmu_stop(event, PERF_EF_UPDATE); + dmc620_pmu->events[idx] = NULL; + clear_bit(idx, dmc620_pmu->used_mask); + perf_event_update_userpage(event); +} + +static int dmc620_pmu_cpu_teardown(unsigned int cpu, + struct hlist_node *node) +{ + struct dmc620_pmu_irq *irq; + struct dmc620_pmu *dmc620_pmu; + unsigned int target; + + irq = hlist_entry_safe(node, struct dmc620_pmu_irq, node); + if (cpu != irq->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + /* We're only reading, but this isn't the place to be involving RCU */ + mutex_lock(&dmc620_pmu_irqs_lock); + list_for_each_entry(dmc620_pmu, &irq->pmus_node, pmus_node) + perf_pmu_migrate_context(&dmc620_pmu->pmu, irq->cpu, target); + mutex_unlock(&dmc620_pmu_irqs_lock); + + WARN_ON(irq_set_affinity_hint(irq->irq_num, cpumask_of(target))); + irq->cpu = target; + + return 0; +} + +static int dmc620_pmu_device_probe(struct platform_device *pdev) +{ + struct dmc620_pmu *dmc620_pmu; + struct resource *res; + char *name; + int irq_num; + int i, ret; + + dmc620_pmu = devm_kzalloc(&pdev->dev, + sizeof(struct dmc620_pmu), GFP_KERNEL); + if (!dmc620_pmu) + return -ENOMEM; + + platform_set_drvdata(pdev, dmc620_pmu); + + dmc620_pmu->pmu = (struct pmu) { + .module = THIS_MODULE, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr = perf_invalid_context, + .event_init = dmc620_pmu_event_init, + .add = dmc620_pmu_add, + .del = dmc620_pmu_del, + .start = dmc620_pmu_start, + .stop = dmc620_pmu_stop, + .read = dmc620_pmu_read, + .attr_groups = dmc620_pmu_attr_groups, + }; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc620_pmu->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dmc620_pmu->base)) + return PTR_ERR(dmc620_pmu->base); + + /* Make sure device is reset before enabling interrupt */ + for (i = 0; i < DMC620_PMU_MAX_COUNTERS; i++) + dmc620_pmu_creg_write(dmc620_pmu, i, DMC620_PMU_COUNTERn_CONTROL, 0); + writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2); + writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK); + + irq_num = platform_get_irq(pdev, 0); + if (irq_num < 0) + return irq_num; + + ret = dmc620_pmu_get_irq(dmc620_pmu, irq_num); + if (ret) + return ret; + + name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%s_%llx", DMC620_PMUNAME, + (u64)(res->start >> DMC620_PA_SHIFT)); + if (!name) { + dev_err(&pdev->dev, + "Create name failed, PMU @%pa\n", &res->start); + goto out_teardown_dev; + } + + ret = perf_pmu_register(&dmc620_pmu->pmu, name, -1); + if (ret) + goto out_teardown_dev; + + return 0; + +out_teardown_dev: + dmc620_pmu_put_irq(dmc620_pmu); + synchronize_rcu(); + return ret; +} + +static int dmc620_pmu_device_remove(struct platform_device *pdev) +{ + struct dmc620_pmu *dmc620_pmu = platform_get_drvdata(pdev); + + dmc620_pmu_put_irq(dmc620_pmu); + + /* perf will synchronise RCU before devres can free dmc620_pmu */ + perf_pmu_unregister(&dmc620_pmu->pmu); + + return 0; +} + +static const struct acpi_device_id dmc620_acpi_match[] = { + { "ARMHD620", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, dmc620_acpi_match); +static struct platform_driver dmc620_pmu_driver = { + .driver = { + .name = DMC620_DRVNAME, + .acpi_match_table = dmc620_acpi_match, + }, + .probe = dmc620_pmu_device_probe, + .remove = dmc620_pmu_device_remove, +}; + +static int __init dmc620_pmu_init(void) +{ + cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + DMC620_DRVNAME, + NULL, + dmc620_pmu_cpu_teardown); + if (cpuhp_state_num < 0) + return cpuhp_state_num; + + return platform_driver_register(&dmc620_pmu_driver); +} + +static void __exit dmc620_pmu_exit(void) +{ + platform_driver_unregister(&dmc620_pmu_driver); + cpuhp_remove_multi_state(cpuhp_state_num); +} + +module_init(dmc620_pmu_init); +module_exit(dmc620_pmu_exit); + +MODULE_DESCRIPTION("Perf driver for the ARM DMC-620 memory controller"); +MODULE_AUTHOR("Tuan Phan X-Patchwork-Id: 1482045 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcvj6VcNz9sW4; Fri, 21 May 2021 17:01:05 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9Z-0008PS-Fp; Fri, 21 May 2021 07:01:01 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9V-0008NL-R5 for kernel-team@lists.ubuntu.com; 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:56 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 10/18] perf/arm_dmc620_pmu: Fix error return code in dmc620_pmu_device_probe() Date: Fri, 21 May 2021 03:00:34 -0400 Message-Id: <20210521070042.1445-13-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Wei Yongjun BugLink: https://bugs.launchpad.net/bugs/1925421 Fix to return negative error code -ENOMEM from the error handling case instead of 0, as done elsewhere in this function. Fixes: 53c218da220c ("driver/perf: Add PMU driver for the ARM DMC-620 memory controller") Reported-by: Hulk Robot Signed-off-by: Wei Yongjun Link: https://lore.kernel.org/r/20210312080421.277562-1-weiyongjun1@huawei.com Signed-off-by: Will Deacon (cherry picked from commit c8e3866836528a4ba3b0535834f03768d74f7d8e) Signed-off-by: Khalid Elmously --- drivers/perf/arm_dmc620_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/perf/arm_dmc620_pmu.c b/drivers/perf/arm_dmc620_pmu.c index 004930eb4bbb..b50b47f1a0d9 100644 --- a/drivers/perf/arm_dmc620_pmu.c +++ b/drivers/perf/arm_dmc620_pmu.c @@ -681,6 +681,7 @@ static int dmc620_pmu_device_probe(struct platform_device *pdev) if (!name) { dev_err(&pdev->dev, "Create name failed, PMU @%pa\n", &res->start); + ret = -ENOMEM; goto out_teardown_dev; } From patchwork Fri May 21 07:00:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcw3608kz9sW4; Fri, 21 May 2021 17:01:23 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljz9o-00009I-FH; Fri, 21 May 2021 07:01:16 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9W-0008O5-Pc for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:58 +0000 Received: from mail-qk1-f198.google.com ([209.85.222.198]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9W-0000ce-BY for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:00:58 +0000 Received: by mail-qk1-f198.google.com with SMTP id b3-20020a05620a0cc3b02902e9d5ca06f2so6370174qkj.19 for ; Fri, 21 May 2021 00:00:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a2Y7B3Khhb65ln3eFCHZk0nYFAMO7x/fdfE61i0H7AA=; b=h6eng06y3eOq8Sbc4BJ1f9yuWbORFIBEMlRsvBktGeVA5aq8NaCibGIBznjSH1Cy+0 rwqr3P1BXcR977ACVihiFTHEuW6PAOOZPwQvpm79ztYU7vxvjGjOwr8FGipVgoG9PVDH 6iptEiHkaKLSCEuj1cWagIlmFEtMDNupZojThtjjAPDicfcTZpOm7nIXV1UI/q4PKYlr QADHxKBkHU2AcXSZjf6VZ5lgtlfT1w/1241p4dS4eFFM38mAzB/aPqv5VWKMy8OyA/6B KVhpjHMYPQNUY5bJBnbkSs3iUOnXN2oteQ6ZzMFZ4f0xDkv/rfYMCGEyJm2rVm9g4q17 7hrA== X-Gm-Message-State: AOAM532us5F5+Ik1unkbNI5nAM99hrYn+HtTajkBbJB7WsX7UpSUjtkF 5nehIIE90WPDUtu3kpQgdDepwcXhAMeOmzUQDBcJrKbjHhw+jUYa/TfQQN+/WPOtfpinMJUFz68 NFRUulldhNDYpaHyzrgGgaNGBCeqDG1jQiWxZVyHYxw== X-Received: by 2002:a37:9dd3:: with SMTP id g202mr10584555qke.177.1621580457439; Fri, 21 May 2021 00:00:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHiIDGGwzDoBQw0Dji6D2RogAtFiHGZzI/svKRDZFPUGXhkIhMnHvydh+qWrAm7TUGYDao8w== X-Received: by 2002:a37:9dd3:: with SMTP id g202mr10584527qke.177.1621580457200; Fri, 21 May 2021 00:00:57 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:56 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 12/18] perf: arm_dsu: Support DSU ACPI devices Date: Fri, 21 May 2021 03:00:35 -0400 Message-Id: <20210521070042.1445-14-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Tuan Phan BugLink: https://bugs.launchpad.net/bugs/1925421 Add support for probing device from ACPI node. Each DSU ACPI node and its associated cpus are inside a cluster node. Signed-off-by: Tuan Phan Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1600106656-9542-1-git-send-email-tuanphan@os.amperecomputing.com Signed-off-by: Will Deacon (cherry picked from commit 2b694fc92a34e8c8b774a17266656d72b8cd4429) Signed-off-by: Khalid Elmously --- drivers/perf/arm_dsu_pmu.c | 63 ++++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c index 96ed93cc78e6..98e68ed7db85 100644 --- a/drivers/perf/arm_dsu_pmu.c +++ b/drivers/perf/arm_dsu_pmu.c @@ -11,6 +11,7 @@ #define DRVNAME PMUNAME "_pmu" #define pr_fmt(fmt) DRVNAME ": " fmt +#include #include #include #include @@ -603,18 +604,19 @@ static struct dsu_pmu *dsu_pmu_alloc(struct platform_device *pdev) } /** - * dsu_pmu_dt_get_cpus: Get the list of CPUs in the cluster. + * dsu_pmu_dt_get_cpus: Get the list of CPUs in the cluster + * from device tree. */ -static int dsu_pmu_dt_get_cpus(struct device_node *dev, cpumask_t *mask) +static int dsu_pmu_dt_get_cpus(struct device *dev, cpumask_t *mask) { int i = 0, n, cpu; struct device_node *cpu_node; - n = of_count_phandle_with_args(dev, "cpus", NULL); + n = of_count_phandle_with_args(dev->of_node, "cpus", NULL); if (n <= 0) return -ENODEV; for (; i < n; i++) { - cpu_node = of_parse_phandle(dev, "cpus", i); + cpu_node = of_parse_phandle(dev->of_node, "cpus", i); if (!cpu_node) break; cpu = of_cpu_node_to_id(cpu_node); @@ -631,6 +633,36 @@ static int dsu_pmu_dt_get_cpus(struct device_node *dev, cpumask_t *mask) return 0; } +/** + * dsu_pmu_acpi_get_cpus: Get the list of CPUs in the cluster + * from ACPI. + */ +static int dsu_pmu_acpi_get_cpus(struct device *dev, cpumask_t *mask) +{ +#ifdef CONFIG_ACPI + int cpu; + + /* + * A dsu pmu node is inside a cluster parent node along with cpu nodes. + * We need to find out all cpus that have the same parent with this pmu. + */ + for_each_possible_cpu(cpu) { + struct acpi_device *acpi_dev; + struct device *cpu_dev = get_cpu_device(cpu); + + if (!cpu_dev) + continue; + + acpi_dev = ACPI_COMPANION(cpu_dev); + if (acpi_dev && + acpi_dev->parent == ACPI_COMPANION(dev)->parent) + cpumask_set_cpu(cpu, mask); + } +#endif + + return 0; +} + /* * dsu_pmu_probe_pmu: Probe the PMU details on a CPU in the cluster. */ @@ -676,6 +708,7 @@ static int dsu_pmu_device_probe(struct platform_device *pdev) { int irq, rc; struct dsu_pmu *dsu_pmu; + struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); char *name; static atomic_t pmu_idx = ATOMIC_INIT(-1); @@ -683,7 +716,16 @@ static int dsu_pmu_device_probe(struct platform_device *pdev) if (IS_ERR(dsu_pmu)) return PTR_ERR(dsu_pmu); - rc = dsu_pmu_dt_get_cpus(pdev->dev.of_node, &dsu_pmu->associated_cpus); + if (IS_ERR_OR_NULL(fwnode)) + return -ENOENT; + + if (is_of_node(fwnode)) + rc = dsu_pmu_dt_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus); + else if (is_acpi_device_node(fwnode)) + rc = dsu_pmu_acpi_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus); + else + return -ENOENT; + if (rc) { dev_warn(&pdev->dev, "Failed to parse the CPUs\n"); return rc; @@ -752,11 +794,21 @@ static const struct of_device_id dsu_pmu_of_match[] = { { .compatible = "arm,dsu-pmu", }, {}, }; +MODULE_DEVICE_TABLE(of, dsu_pmu_of_match); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id dsu_pmu_acpi_match[] = { + { "ARMHD500", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, dsu_pmu_acpi_match); +#endif static struct platform_driver dsu_pmu_driver = { .driver = { .name = DRVNAME, .of_match_table = of_match_ptr(dsu_pmu_of_match), + .acpi_match_table = ACPI_PTR(dsu_pmu_acpi_match), .suppress_bind_attrs = true, }, .probe = dsu_pmu_device_probe, @@ -826,7 +878,6 @@ static void __exit dsu_pmu_exit(void) module_init(dsu_pmu_init); module_exit(dsu_pmu_exit); -MODULE_DEVICE_TABLE(of, dsu_pmu_of_match); MODULE_DESCRIPTION("Perf driver for ARM DynamIQ Shared Unit"); MODULE_AUTHOR("Suzuki K Poulose "); MODULE_LICENSE("GPL v2"); From patchwork Fri May 21 07:00:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:58 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 13/18] Perf: arm-cmn: Allow irq to be shared. Date: Fri, 21 May 2021 03:00:37 -0400 Message-Id: <20210521070042.1445-16-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Tuan Phan BugLink: https://bugs.launchpad.net/bugs/1925421 Multiple sockets can share a same pmu interrupts. Signed-off-by: Tuan Phan (backported from commit 19a1b3868b040d9c444719eccc6ede39e5bd0857 https://github.com/AmpereComputing/ampere-centos-kernel) [ kmously: The code we're looking for moved from arm_cmn_init_pmu() to arm_cmn_init_irqs() ] Signed-off-by: Khalid Elmously --- drivers/perf/arm-cmn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index e824b5b83ea2..92dbea6633bc 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1215,7 +1215,7 @@ static int arm_cmn_init_irqs(struct arm_cmn *cmn) } } err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, - IRQF_NOBALANCING | IRQF_NO_THREAD, + IRQF_NOBALANCING | IRQF_NO_THREAD | IRQF_SHARED, dev_name(cmn->dev), &cmn->dtc[i]); if (err) return err; From patchwork Fri May 21 07:00:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwY6qnYz9sRf; Fri, 21 May 2021 17:01:49 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzAH-0000Us-0A; Fri, 21 May 2021 07:01:45 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9Y-0008Ou-Qm for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:00 +0000 Received: from mail-qv1-f72.google.com ([209.85.219.72]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9Y-0000dH-H7 for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:00 +0000 Received: by mail-qv1-f72.google.com with SMTP id f17-20020a0cf3d10000b02901eda24e6b92so15869941qvm.1 for ; Fri, 21 May 2021 00:01:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qjrcU8HfvJMno9dimsUZOHNLPhiJNMIAJVhewkQSlTY=; b=uanmasAieznp6hAcbORrdirHdzfznoE2wrfrDjjX5PW1hU36oAZH5cj8bXdIGIVLXk NcKd6UfeN21m6k9h12+XJdVfdrys2spiJVCgSDI3A/hw5O6mBLTTBtTMG3rlsfKxlC3A k8sxVqisEfQVB/rzVnz9G0FWnVa5QDr6aebEZzGfxA6nQac6rJFFANDkuZpTezwmWwPb 8ctb+5r1YMzKZTG+xfVZAhSiD88Th+75Kq+AtAeOODdmmdv9jgnV/8aL3eOT1a6rk0Jl CojUhW3wezJRoMDcdhkTfvZQHM/eMFHnJUS4C0573VMvDhtZOgfze7S2W4/km5rYpQ0K qzrA== X-Gm-Message-State: AOAM533azg4V/sTDubGlxk1jOSBWVi+cQdHlcBldIhm+DRAhKZ5nAiXf Gd+xZuSxgYvoF0XsVDCRqAfJhRyeuyqtZQDuyiNO4wuIqGqYG9YNy7/TwlBOuW8bwqZvjDE3yt9 hG8uKrDpNzTMjWBRIW71TWpCJJhGRj8xDgb8XJmvh6w== X-Received: by 2002:a0c:9e4f:: with SMTP id z15mr10879731qve.52.1621580459711; Fri, 21 May 2021 00:00:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOBuJOJpjcWiT6VXRuIPsxnHgJYbJ+Z5mJ1zH9o4gJP3km1IR0/hZ43NZoccg5fqF57MfCww== X-Received: by 2002:a0c:9e4f:: with SMTP id z15mr10879703qve.52.1621580459521; Fri, 21 May 2021 00:00:59 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:00:59 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 14/18] perf: arm-cmn: Fix unsigned comparison to less than zero Date: Fri, 21 May 2021 03:00:38 -0400 Message-Id: <20210521070042.1445-17-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Will Deacon BugLink: https://bugs.launchpad.net/bugs/1925421 Ensure that the 'irq' field of 'struct arm_cmn_dtc' is a signed int so that it can be compared '< 0'. Link: https://lore.kernel.org/r/20200929170835.GA15956@embeddedor Addresses-Coverity-ID: 1497488 ("Unsigned compared against 0") Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver") Reported-by: Gustavo A. R. Silva Reviewed-by: Gustavo A. R. Silva Signed-off-by: Will Deacon (cherry picked from commit d9ef632fab9ba81b708763bcbcfdbea9a55c95d2) Signed-off-by: Khalid Elmously --- drivers/perf/arm-cmn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 92dbea6633bc..cf85596f55ea 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -217,7 +217,7 @@ struct arm_cmn_node { struct arm_cmn_dtc { void __iomem *base; - unsigned int irq; + int irq; int irq_friend; bool cc_active; From patchwork Fri May 21 07:00:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwZ3jWfz9sWl; Fri, 21 May 2021 17:01:50 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzAH-0000W1-Vm; Fri, 21 May 2021 07:01:46 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9a-0008Pb-JF for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:02 +0000 Received: from mail-qk1-f199.google.com ([209.85.222.199]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9Z-0000dT-Fl for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:01 +0000 Received: by mail-qk1-f199.google.com with SMTP id l6-20020a3770060000b02902fa5329f2b4so15337396qkc.18 for ; Fri, 21 May 2021 00:01:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tOJo/7pTBvy/1zzHT+WqpAqoOg0pWQpTxmIzuGp5l6M=; b=LE61UCCy0MSRJ7FAC0Ym9F8UDy5QLDLKO5v4WqzSLgJnsNFO3x0yCqsozJUOIjpnEN BSCYGKiSqVUBZjFRXAPf95Iq4aJCdVPkrPKrJ9Q6oY3M3dvtWAe2pqcOnpR1J4Xh+9pO zInbIzmDRt62dA7BxEXvyGO7rcarJ00IUtMIRv+nxQ87AvfWDJ+sOl78w9xZWmxriAXn P0DRn0z1BT6TfqsCPcE4Hr90FBF9q27cnN1xDE6Ehcj72sdsotBPwOEfgXCMGbqoakmz ZVPhJreKAZwnpVft2L3RiQLs0ibPi4tYFnjQhlikt2hH5dIAM6TwFysAWrGxWPbK7qFR ClCA== X-Gm-Message-State: AOAM532W9KZ25+Aw4Qll88h8tQpiKJsP7ncDMVVUgx1ytEJRL+BVS2x0 zXpcXmOlcRSkBfOxpmOmbHh8O2KhO1e3KjNEUsyr5WcJaH7aJ27D4wGrBb6MyGxJ8s9l9/WH1UB L97GTxI+FlfbrNSsOsTwhjFbFhbb3Kp4uVFj9h/gaVw== X-Received: by 2002:a05:6214:6f1:: with SMTP id bk17mr11063307qvb.37.1621580460626; Fri, 21 May 2021 00:01:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2s7gtFmYGgLJP/gWI4PdsMsJz5lwvE0RbEL2Hy6hdVL/f8vT+CGmn1ETWzhYu6xOg58fwBw== X-Received: by 2002:a05:6214:6f1:: with SMTP id bk17mr11063286qvb.37.1621580460405; Fri, 21 May 2021 00:01:00 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:01:00 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 15/18] perf/arm-cmn: Fix PMU instance naming Date: Fri, 21 May 2021 03:00:39 -0400 Message-Id: <20210521070042.1445-18-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Robin Murphy BugLink: https://bugs.launchpad.net/bugs/1925421 Although it's neat to avoid the suffix for the typical case of a single PMU, it means systems with multiple CMN instances end up with inconsistent naming. I think it also breaks perf tool's "uncore alias" logic if the common instance prefix is also the full name of one. Avoid any surprises by not trying to be clever and simply numbering every instance, even when it might technically prove redundant. Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver") Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/649a2281233f193d59240b13ed91b57337c77b32.1611839564.git.robin.murphy@arm.com Signed-off-by: Will Deacon (cherry picked from commit 79d7c3dca99fa96033695ddf5d495b775a3a137b) Signed-off-by: Khalid Elmously --- Documentation/admin-guide/perf/arm-cmn.rst | 2 +- drivers/perf/arm-cmn.c | 13 ++++--------- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/perf/arm-cmn.rst b/Documentation/admin-guide/perf/arm-cmn.rst index 0e4809346014..796e25b7027b 100644 --- a/Documentation/admin-guide/perf/arm-cmn.rst +++ b/Documentation/admin-guide/perf/arm-cmn.rst @@ -17,7 +17,7 @@ PMU events ---------- The PMU driver registers a single PMU device for the whole interconnect, -see /sys/bus/event_source/devices/arm_cmn. Multi-chip systems may link +see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link more than one CMN together via external CCIX links - in this situation, each mesh counts its own events entirely independently, and additional PMU devices will be named arm_cmn_{1..n}. diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index cf85596f55ea..25f3a5a0d3a0 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1502,7 +1502,7 @@ static int arm_cmn_probe(struct platform_device *pdev) struct arm_cmn *cmn; const char *name; static atomic_t id; - int err, rootnode, this_id; + int err, rootnode; cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); if (!cmn) @@ -1549,14 +1549,9 @@ static int arm_cmn_probe(struct platform_device *pdev) .cancel_txn = arm_cmn_end_txn, }; - this_id = atomic_fetch_inc(&id); - if (this_id == 0) { - name = "arm_cmn"; - } else { - name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); - if (!name) - return -ENOMEM; - } + name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", atomic_fetch_inc(&id)); + if (!name) + return -ENOMEM; err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); if (err) From patchwork Fri May 21 07:00:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FmcwT0hs8z9sW1; Fri, 21 May 2021 17:01:45 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzAB-0000QG-7f; Fri, 21 May 2021 07:01:39 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9b-0008Qb-4N for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:03 +0000 Received: from mail-qv1-f70.google.com ([209.85.219.70]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9a-0000e3-7G for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:02 +0000 Received: by mail-qv1-f70.google.com with SMTP id b24-20020a0cb3d80000b02901e78b82d74aso15807499qvf.20 for ; Fri, 21 May 2021 00:01:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f+VC0vbK0p/LuDV6dOz3W2PPRRHGBpCrRicOd6Yq5u8=; b=BkNVbOcFou0Z4VdVrc13MQrr9q1PG1mlqpWs9Jf8ZibRRMLOgjxZWnBdB2WN55yOtf 9/9M2WPJkRNevb5ZfLgGlpakk+ofSU6fwma2eo40bEQUK87Yz2ZwBDECtg7BngAa0N0K iLZ4nfSWJ/k7yQvPrW+wwtTyGgN6n9/AA5x5L3Zk0yJ3O7oigdZxxjp/WJgbTE6D2uDe 6gCW/6mQkoEb4+9ETS8ySTL5hiCK0zbSZCFdiO4PST+OreB8RgZ5RndGGAl4sRZ0reqe neCuNo+orhbfDkUNnLajXfBcZdVht5Eb+CXow04Gov/NO622QapxoPF9PLSnSSSQ3yeg uNEQ== X-Gm-Message-State: AOAM531kp3ElshBJs5tqiKxHLiL27xHzAqPSgaU5rVnkZ+2Awf2pEFcB hxEunHr3UhU6lXuCaiQfJYwhitxTeh79JJ3WYJC37jMj+OlJ+jnqe6TtF6ap+3tOSOHsOAYU5hT +6En4wpceTJETYOtVE0TtPh4rrRtJ8o9pobRw2RptuQ== X-Received: by 2002:a37:9a47:: with SMTP id c68mr9013502qke.376.1621580461382; Fri, 21 May 2021 00:01:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOBs4KioA1AxB6aeBlLM93Ew0COohPZLm2ORV609gbPna54teEU43xwpNhFyekXFTD4mJ5vA== X-Received: by 2002:a37:9a47:: with SMTP id c68mr9013471qke.376.1621580461163; Fri, 21 May 2021 00:01:01 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:01:00 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 16/18] perf/arm-cmn: Move IRQs when migrating context Date: Fri, 21 May 2021 03:00:40 -0400 Message-Id: <20210521070042.1445-19-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Robin Murphy BugLink: https://bugs.launchpad.net/bugs/1925421 If we migrate the PMU context to another CPU, we need to remember to retarget the IRQs as well. Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver") Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/e080640aea4ed8dfa870b8549dfb31221803eb6b.1611839564.git.robin.murphy@arm.com Signed-off-by: Will Deacon (cherry picked from commit 1c8147ea89c883d1f4e20f1b1d9c879291430102) Signed-off-by: Khalid Elmously --- drivers/perf/arm-cmn.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 25f3a5a0d3a0..211ee3f4473f 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1150,7 +1150,7 @@ static int arm_cmn_commit_txn(struct pmu *pmu) static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) { struct arm_cmn *cmn; - unsigned int target; + unsigned int i, target; cmn = hlist_entry_safe(node, struct arm_cmn, cpuhp_node); if (cpu != cmn->cpu) @@ -1161,6 +1161,8 @@ static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) return 0; perf_pmu_migrate_context(&cmn->pmu, cpu, target); + for (i = 0; i < cmn->num_dtcs; i++) + irq_set_affinity_hint(cmn->dtc[i].irq, cpumask_of(target)); cmn->cpu = target; return 0; } From patchwork Fri May 21 07:00:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcwb3HgRz9sX1; Fri, 21 May 2021 17:01:51 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzAJ-0000Xa-9G; Fri, 21 May 2021 07:01:47 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9b-0008Rc-Qs for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:03 +0000 Received: from mail-qk1-f198.google.com ([209.85.222.198]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9b-0000eB-1c for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:03 +0000 Received: by mail-qk1-f198.google.com with SMTP id l6-20020a3770060000b02902fa5329f2b4so15337501qkc.18 for ; Fri, 21 May 2021 00:01:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hd1y2/un38FoLECUVa0tFky/hjilfgzwhOOTOh6ZlGY=; b=Wv6Sj634l5MNYLtAulBJxYko224j0dtDpM9Ti5i7cvcoVG+KJyx0gAKqPs7UsI/gkB qYrQmJI8OEkLBGP1jP16Gsu1BUgwqHZ33czn8dVpLEtk3ZFsOwvuL1tcyCWWM40Q0wOW dz3TD9Z+wYStvfbx2+6z8cTF/XK3LqL9ZXTRGuMC5guvNwvmZ3FPKsyXgcqitP7f8CxD Qys5G28i1WoHTl6+ERlmYjhWoU0uGXSFtiAxy5s+QNnziFSOH2VvQKo5TDYjP8HZfzwy 1Q5JXDWADrdoGQ9QiM4MhLupnsXSVmtsUP4DmSbKFFqHcO8EJngGQ9d4EgviF6S0o6Oc fSTw== X-Gm-Message-State: AOAM532phPnlUGZTA6UsMSSEZl+v2S1hq1zB5DSXtEiJTrfiEw3gB203 nAxGZ2/JujuD83lA9q3PFQILNKxfzUEKK46G5kG79+K7OMpJ9qZ0BJ2wC08Cn/lYJvv59o+pl3M cocm0ZIqinWmDcIumeLXk+/dD6huo7uFT+5q61wTKng== X-Received: by 2002:a37:a0c9:: with SMTP id j192mr10619888qke.19.1621580462207; Fri, 21 May 2021 00:01:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPmoCVonaREZ4iz9jts4UT1YfuLDIXaHVqi9A5f7EekCEIzklac9P2hqUuf4JCcz2yESGAow== X-Received: by 2002:a37:a0c9:: with SMTP id j192mr10619863qke.19.1621580461986; Fri, 21 May 2021 00:01:01 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:01:01 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 17/18] UBUNTU: [config] oracle: Ampere Altra modules =m Date: Fri, 21 May 2021 03:00:41 -0400 Message-Id: <20210521070042.1445-20-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 Signed-off-by: Khalid Elmously --- debian.oracle/config/config.common.ubuntu | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debian.oracle/config/config.common.ubuntu b/debian.oracle/config/config.common.ubuntu index 377cb3c4ed52..3024af392657 100644 --- a/debian.oracle/config/config.common.ubuntu +++ b/debian.oracle/config/config.common.ubuntu @@ -513,6 +513,7 @@ CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y # CONFIG_ARM_CCN is not set CONFIG_ARM_CMN=m # CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_DMC620_PMU=m # CONFIG_ARM_DSU_PMU is not set CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 @@ -7117,6 +7118,7 @@ CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m CONFIG_SENSORS_ADT7475=m CONFIG_SENSORS_ADT7X10=m +CONFIG_SENSORS_ALTRA=m CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_AMD_ENERGY=m CONFIG_SENSORS_APDS990X=m From patchwork Fri May 21 07:00:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalid Elmously X-Patchwork-Id: 1482062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fmcwd6Wnyz9sWp; Fri, 21 May 2021 17:01:53 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ljzAL-0000aS-9G; Fri, 21 May 2021 07:01:49 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1ljz9d-0008Sb-EG for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:05 +0000 Received: from mail-qv1-f72.google.com ([209.85.219.72]) by youngberry.canonical.com with esmtps (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1ljz9b-0000eQ-S3 for kernel-team@lists.ubuntu.com; Fri, 21 May 2021 07:01:03 +0000 Received: by mail-qv1-f72.google.com with SMTP id r11-20020a0cb28b0000b02901c87a178503so15781301qve.22 for ; Fri, 21 May 2021 00:01:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XCn56kVaOY7kdvkBu70m5CledPW7WxbbWH9GRJDlNic=; b=KLKnh0EOoyv/qaff/JLQw/8GTtEcSKfwQ97Q/2Zy6z++zjNjVSLNeGqtHjk1JuMyXk iQTF8HgEZXWh4Zox4SjWYBB6/QoC8OJ4sMioLm62e/pPH9NRKjGKY4fkcd9K/oXuBCsu Duex4RX0L+0EmruA5czrmsitVKIFchYJU+iBAia5GVFRV14rLv3sf2njKgEowNGwz3Xr PrOBRoGHPh5RnyhwICSMYZFL07zVPjtPf9RG2oS38rbavO0jMMB+jJZ2NE3H/prBNShy V/M92KdkhRLItufgPTrpbGFG2qh7vVOOyh/+KUZbiysM8udS9eGro2faacyra+ojp33J uYVg== X-Gm-Message-State: AOAM53095SrV1gnH/QnvMyOpx2ssK/a+wjiuNc01Ec7VQdrzk1fH6Xif M2htcpkq8oACH6nwK2IFFJrksr8eEoBdA+Ei+5U4HGncvqN1xkn2UC5+iB8Kz1DogaGmeLHTwte 8IZ4lVJwcf7k9RUvw4oAJg+FU5HeXdSqz/LqhWyUaTg== X-Received: by 2002:a37:ef05:: with SMTP id j5mr10730160qkk.203.1621580463039; Fri, 21 May 2021 00:01:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdYiErKCJu2kIe+vU+Dbb2FgNESr+zgSFf/nI21pLJp3oMxM2i07tNqX9bjGLpGeK0PaIGMQ== X-Received: by 2002:a37:ef05:: with SMTP id j5mr10730139qkk.203.1621580462833; Fri, 21 May 2021 00:01:02 -0700 (PDT) Received: from kbuntu2.fuzzbuzz.org (dhcp-24-53-240-22.cable.user.start.ca. [24.53.240.22]) by smtp.gmail.com with ESMTPSA id t128sm4138951qkh.50.2021.05.21.00.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 00:01:02 -0700 (PDT) From: Khalid Elmously To: kernel-team@lists.ubuntu.com Subject: [SRU][G/linux-oracle][PATCH 18/18] UBUNTU: [config] oracle: enable CONFIG_SERIAL_AMBA_PL011=y Date: Fri, 21 May 2021 03:00:42 -0400 Message-Id: <20210521070042.1445-21-khalid.elmously@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210521070042.1445-1-khalid.elmously@canonical.com> References: <20210521070042.1445-1-khalid.elmously@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1925421 Signed-off-by: Khalid Elmously --- debian.oracle/config/annotations | 6 ++++-- debian.oracle/config/config.common.ubuntu | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/debian.oracle/config/annotations b/debian.oracle/config/annotations index 1021d9730b38..2d65682261c1 100644 --- a/debian.oracle/config/annotations +++ b/debian.oracle/config/annotations @@ -37,7 +37,9 @@ CONFIG_SND_SOC_INTEL_CNL mark note CONFIG_X86_UV policy<{'amd64': 'n'}> CONFIG_X86_UV mark note -CONFIG_ATARI_PARTITION policy<{'amd64': 'n', 'arm64': 'n'}> -CONFIG_ATARI_PARTITION mark note +CONFIG_ATARI_PARTITION policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_ATARI_PARTITION mark note CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': '-'}> CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT mark +CONFIG_SERIAL_AMBA_PL011 policy<{'amd64': '-', 'arm64': 'y'}> +CONFIG_SERIAL_AMBA_PL011 mark note diff --git a/debian.oracle/config/config.common.ubuntu b/debian.oracle/config/config.common.ubuntu index 3024af392657..118d131bea68 100644 --- a/debian.oracle/config/config.common.ubuntu +++ b/debian.oracle/config/config.common.ubuntu @@ -7333,7 +7333,8 @@ CONFIG_SERIAL_ALTERA_UART=m CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 # CONFIG_SERIAL_AMBA_PL010 is not set -# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_ARC=m CONFIG_SERIAL_ARC_NR_PORTS=1 # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set