From patchwork Thu May 20 09:14:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1481459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=pjE1MhH/; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fm3wH1SYpz9sV5 for ; Thu, 20 May 2021 19:14:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 82347395185D; Thu, 20 May 2021 09:14:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 82347395185D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621502075; bh=HHWQrKKJ3M6PeZIL0begW7Q7dc0iNHSQcsgjYVNy3xo=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=pjE1MhH/NYBeuV/0PS5mXDag1rT4worKQdlS27gUwyGA9FfgDpbe0wFXG1JFRofiD ub/zgtHzkl+xi+D/4XbRx+veNvlIopTeFswU0ndsJKEedDU+jJFU8qBg+VjxD/1hJ/ d1iGTDqvAHIVh0uBEB8mgzhD3a0/GUpWOBDiYd+4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by sourceware.org (Postfix) with ESMTPS id 242D8394FC27 for ; Thu, 20 May 2021 09:14:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 242D8394FC27 Received: by mail-qv1-xf2e.google.com with SMTP id u33so8256062qvf.9 for ; Thu, 20 May 2021 02:14:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=HHWQrKKJ3M6PeZIL0begW7Q7dc0iNHSQcsgjYVNy3xo=; b=ro8C6WFuY+so8LlJjPa/uaoT/XCN+yu7hTjgaOJ2B1z0pzJZ5VT7nJLlG2OjQeN/Fz DOZ89JMAW47138nLjgEtzm+gE2seq/xIk29yMqhkreLBUoo4bd2njADp1p7O9y+s8Zpm un5IjiY53l+9MzkyONQkbY5eMyDadoV9tE1sMlSnJgdNtRWvGV1JXY/qNK79ZJ6c7bYr QCO53rlOI/yrl2/Rr4khsYNRYv7/SiX/0lYc9I6jVUuchxNtusbxfmStkTh6Hx9Fie0a VYofGj2C8ZUuP12uoKmDtEOifIDi4C1tFCuRzBV7xHlwmxi8TN88+GYz8NPupztcj//n 5Y8w== X-Gm-Message-State: AOAM533LK67MVvY2oLgiUwvn4WmunEuySbpru+ybcUTccROhVThfaPXC 81m67FiizRQ8k+I7KNBCg2vOA9hHWE6SDKljmsGbdn09YbwNiQ== X-Google-Smtp-Source: ABdhPJzQG5iIwjy79vzoFS2OufhlqQS9R5JQX5arbF4iGTwAuWjmKGwK7k1jJJJ2heBS24gFz6UUmelJo3Mu171DIm8= X-Received: by 2002:a05:6214:142d:: with SMTP id o13mr4553997qvx.30.1621502071454; Thu, 20 May 2021 02:14:31 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 20 May 2021 11:14:20 +0200 Message-ID: Subject: [PATCH] i386: Add mult-high and shift patterns for 4-byte vectors [PR100637] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" 2021-05-20 Uroš Bizjak gcc/ PR target/100637 * config/i386/mmx.md (Yv_Yw): Revert adding V4QI and V2HI modes. (*3): Use Yw instad of constrint. (mulv4hi3_highpart): New expander. (*mulv2hi3_highpart): New insn pattern. (mulv2hi3_higpart): New expander. (*v2hi3): New insn pattern. (v2hi3): New expander. * config/i386/sse.md (smulhrsv2hi3): New expander. (*smulhrsv2hi3): New insn pattern. gcc/testsuite/ PR target/100637 * gcc.target/i386/pr100637-1w.c (shl, ashr, lshr): New tests. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d8479782e90..948ba479c32 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -78,8 +78,7 @@ (define_mode_attr mmxintvecmodelower [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")]) (define_mode_attr Yv_Yw - [(V8QI "Yw") (V4QI "Yw") (V4HI "Yw") (V2HI "Yw") - (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")]) + [(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; @@ -1367,10 +1366,10 @@ (define_expand "3" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*3" - [(set (match_operand:VI_32 0 "register_operand" "=x,") + [(set (match_operand:VI_32 0 "register_operand" "=x,Yw") (plusminus:VI_32 - (match_operand:VI_32 1 "register_operand" "0,") - (match_operand:VI_32 2 "register_operand" "x,")))] + (match_operand:VI_32 1 "register_operand" "0,Yw") + (match_operand:VI_32 2 "register_operand" "x,Yw")))] "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" "@ @@ -1523,6 +1522,51 @@ (define_insn "*mmx_umulv4hi3_highpart" (set_attr "type" "mmxmul,ssemul,ssemul") (set_attr "mode" "DI,TI,TI")]) +(define_expand "mulv4hi3_highpart" + [(set (match_operand:V4HI 0 "register_operand") + (truncate:V4HI + (lshiftrt:V4SI + (mult:V4SI + (any_extend:V4SI + (match_operand:V4HI 1 "register_operand")) + (any_extend:V4SI + (match_operand:V4HI 2 "register_operand"))) + (const_int 16))))] + "TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") + +(define_insn "*mulv2hi3_highpart" + [(set (match_operand:V2HI 0 "register_operand" "=x,Yw") + (truncate:V2HI + (lshiftrt:V2SI + (mult:V2SI + (any_extend:V2SI + (match_operand:V2HI 1 "register_operand" "%0,Yw")) + (any_extend:V2SI + (match_operand:V2HI 2 "register_operand" "x,Yw"))) + (const_int 16))))] + "TARGET_SSE2 + && ix86_binary_operator_ok (MULT, V2HImode, operands)" + "@ + pmulhw\t{%2, %0|%0, %2} + vpmulhw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssemul") + (set_attr "mode" "TI")]) + +(define_expand "mulv2hi3_highpart" + [(set (match_operand:V2HI 0 "register_operand") + (truncate:V2HI + (lshiftrt:V2SI + (mult:V2SI + (any_extend:V2SI + (match_operand:V2HI 1 "register_operand")) + (any_extend:V2SI + (match_operand:V2HI 2 "register_operand"))) + (const_int 16))))] + "TARGET_SSE2" + "ix86_fixup_binary_operands_no_copy (MULT, V2HImode, operands);") + (define_expand "mmx_pmaddwd" [(set (match_operand:V2SI 0 "register_operand") (plus:V2SI @@ -1817,6 +1861,30 @@ (define_expand "3" (match_operand:DI 2 "nonmemory_operand")))] "TARGET_MMX_WITH_SSE") +(define_insn "*v2hi3" + [(set (match_operand:V2HI 0 "register_operand" "=x,Yw") + (any_shift:V2HI + (match_operand:V2HI 1 "register_operand" "0,Yw") + (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))] + "TARGET_SSE2" + "@ + pw\t{%2, %0|%0, %2} + vpw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseishft") + (set (attr "length_immediate") + (if_then_else (match_operand 2 "const_int_operand") + (const_string "1") + (const_string "0"))) + (set_attr "mode" "TI")]) + +(define_expand "v2hi3" + [(set (match_operand:V2HI 0 "register_operand") + (any_shift:V2HI + (match_operand:V2HI 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_SSE2") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral comparisons diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a4503ddcb73..0f1108f0db1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17239,6 +17239,51 @@ (define_insn "*ssse3_pmulhrswv4hi3" (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI,TI,TI")]) +(define_expand "smulhrsv2hi3" + [(set (match_operand:V2HI 0 "register_operand") + (truncate:V2HI + (lshiftrt:V2SI + (plus:V2SI + (lshiftrt:V2SI + (mult:V2SI + (sign_extend:V2SI + (match_operand:V2HI 1 "register_operand")) + (sign_extend:V2SI + (match_operand:V2HI 2 "register_operand"))) + (const_int 14)) + (match_dup 3)) + (const_int 1))))] + "TARGET_SSSE3" +{ + operands[3] = CONST1_RTX(V2HImode); + ix86_fixup_binary_operands_no_copy (MULT, V2HImode, operands); +}) + +(define_insn "*smulhrsv2hi3" + [(set (match_operand:V2HI 0 "register_operand" "=x,Yv") + (truncate:V2HI + (lshiftrt:V2SI + (plus:V2SI + (lshiftrt:V2SI + (mult:V2SI + (sign_extend:V2SI + (match_operand:V2HI 1 "register_operand" "%0,Yv")) + (sign_extend:V2SI + (match_operand:V2HI 2 "register_operand" "x,Yv"))) + (const_int 14)) + (match_operand:V2HI 3 "const1_operand")) + (const_int 1))))] + "TARGET_SSSE3 + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" + "@ + pmulhrsw\t{%2, %0|%0, %2} + vpmulhrsw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseimul") + (set_attr "prefix_extra" "1") + (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) + (set_attr "mode" "TI")]) + (define_insn "_pshufb3" [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,") (unspec:VI1_AVX512 diff --git a/gcc/testsuite/gcc.target/i386/pr100637-1w.c b/gcc/testsuite/gcc.target/i386/pr100637-1w.c index ed1baeb3acd..fe6964044b6 100644 --- a/gcc/testsuite/gcc.target/i386/pr100637-1w.c +++ b/gcc/testsuite/gcc.target/i386/pr100637-1w.c @@ -3,6 +3,7 @@ /* { dg-options "-O2 -msse2 -dp" } */ typedef short __v2hi __attribute__ ((__vector_size__ (4))); +typedef unsigned short __v2hu __attribute__ ((__vector_size__ (4))); __v2hi and (__v2hi a, __v2hi b) { return a & b; }; /* { dg-final { scan-assembler "andv2hi3" } } */ @@ -26,3 +27,12 @@ __v2hi neg (__v2hi a) { return -a; }; __v2hi mul (__v2hi a, __v2hi b) { return a * b; }; /* { dg-final { scan-assembler "mulv2hi3" } } */ + +__v2hi shl (__v2hi a, int b) { return a << b; }; +/* { dg-final { scan-assembler "ashlv2hi3" } } */ + +__v2hi ashr (__v2hi a, int b) { return a >> b; }; +/* { dg-final { scan-assembler "ashrv2hi3" } } */ + +__v2hu lshr (__v2hu a, int b) { return a >> b; }; +/* { dg-final { scan-assembler "lshrv2hi3" } } */