From patchwork Wed May 19 23:54:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=AuJP2W4s; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqVB1BMKz9sWc for ; Thu, 20 May 2021 09:54:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230053AbhESX4B (ORCPT ); Wed, 19 May 2021 19:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229498AbhESX4B (ORCPT ); Wed, 19 May 2021 19:56:01 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 046FEC061574; Wed, 19 May 2021 16:54:41 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id 10so11052294pfl.1; Wed, 19 May 2021 16:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=saGJ8MOGoMsUyv5kls1YdVGYFyRu0m+lWIn5KG+KbKE=; b=AuJP2W4sui0Jz23E73840AgKtN5T4+Ui1HltUsoW6gcogkb5i4/wgaiHvFNu19xHzg +KgRxMPWNUUYuAndR8X4SGFjPiwWUuMcvZaI61aQnjb3FU5WbqavR/N2hmF/Ao8nO+oW XkUi4Cik7zckY+9XizE6WCLhvvhnQLd4ID1rBz/VuSsnVndH37VBcFF7tFWVno+Tyu64 zNYnulegzNkTk30DGC1Ca+4iui/Gyo+pbDTz5rBhzPKZ9rjNmDdQDPavpmN13Y+ILu3z 1Bn5FEbKl0zQCPCFnI3HOEczQbTrlQYiZbWp4RaKS/t+9fnJ9AOmPfEKCLkN3GBhuC3x pLaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saGJ8MOGoMsUyv5kls1YdVGYFyRu0m+lWIn5KG+KbKE=; b=tfbUeK6kuFGO/vv+3Pnr7E9iAgBU0Ixys5gfmg9or+qoakwYIB1/Nq0zwWTW045IhQ 6/Xkwdb7VHWySk3S6RwtkXWN7liiAA65xsOauF/uJ4bG8nNUbl0JE09bEqoRgJv8j1WE ULLkO+bYJpRPEEsh5s4+Kgw9KOsEvnNdkX1lQUv8Mzg9s63PSCJNnf2h7w54amCd+/8V 9b4UUyHmBzo7XI6Wfpf1OtzydIC/8HCtIc30BIIloM7NpEa/qubJD1NfY/5fgny/73eZ eEC8v69cNAhe/B/NDmujKUl6mEn2MQKiG40BrV4KuN6hw925+Lw467exS422t89vfLSm Cl+A== X-Gm-Message-State: AOAM530L4QONb66dFeCYpJCoex2l7xv6w9ZSWae6qeKL88GYujUiqNMH Tr7UVldOD5lxBhZdBSCF/0U= X-Google-Smtp-Source: ABdhPJxXfQSxitBWipKKPmKnPeu94pbmbr+c/34GKq1ITLPe4jMUtzYHuy2lCcaUrX7xWD8UX6Cmsw== X-Received: by 2002:a65:53c8:: with SMTP id z8mr1692570pgr.192.1621468480580; Wed, 19 May 2021 16:54:40 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.54.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:54:40 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Amey Narkhede Subject: [PATCH RESEND v2 1/7] PCI: merge slot and bus reset implementations Date: Thu, 20 May 2021 05:24:20 +0530 Message-Id: <20210519235426.99728-2-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Raphael Norwitz Slot resets are bus resets with additional logic to prevent a device from being removed during the reset. Currently slot and bus resets have separate implementations in pci.c, complicating higher level logic. As discussed on the mailing list, they should be combined into a generic function which performs an SBR. This change adds a function, pci_reset_bus_function(), which first attempts a slot reset and then attempts a bus reset if -ENOTTY is returned, such that there is now a single device agnostic function to perform an SBR. This new function is also needed to add SBR reset quirks and therefore is exposed in pci.h. Link: https://lkml.org/lkml/2021/3/23/911 Suggested-by: Alex Williamson Signed-off-by: Amey Narkhede Signed-off-by: Raphael Norwitz --- drivers/pci/pci.c | 19 +++++++++++-------- include/linux/pci.h | 1 + 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16a17215f..a8f8dd588 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4982,6 +4982,15 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) return pci_reset_hotplug_slot(dev->slot->hotplug, probe); } +int pci_reset_bus_function(struct pci_dev *dev, int probe) +{ + int rc = pci_dev_reset_slot_function(dev, probe); + + if (rc != -ENOTTY) + return rc; + return pci_parent_bus_reset(dev, probe); +} + static void pci_dev_lock(struct pci_dev *dev) { pci_cfg_access_lock(dev); @@ -5102,10 +5111,7 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_pm_reset(dev, 0); if (rc != -ENOTTY) return rc; - rc = pci_dev_reset_slot_function(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_parent_bus_reset(dev, 0); + return pci_reset_bus_function(dev, 0); } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); @@ -5135,13 +5141,10 @@ int pci_probe_reset_function(struct pci_dev *dev) if (rc != -ENOTTY) return rc; rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_dev_reset_slot_function(dev, 1); if (rc != -ENOTTY) return rc; - return pci_parent_bus_reset(dev, 1); + return pci_reset_bus_function(dev, 1); } /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 86c799c97..979d54335 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1228,6 +1228,7 @@ int pci_probe_reset_bus(struct pci_bus *bus); int pci_reset_bus(struct pci_dev *dev); void pci_reset_secondary_bus(struct pci_dev *dev); void pcibios_reset_secondary_bus(struct pci_dev *dev); +int pci_reset_bus_function(struct pci_dev *dev, int probe); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); From patchwork Wed May 19 23:54:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=nP8ENpfq; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqVG3jpGz9sWc for ; Thu, 20 May 2021 09:54:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230114AbhESX4F (ORCPT ); Wed, 19 May 2021 19:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229498AbhESX4F (ORCPT ); Wed, 19 May 2021 19:56:05 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C48EDC061574; Wed, 19 May 2021 16:54:44 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id gb21-20020a17090b0615b029015d1a863a91so4431431pjb.2; Wed, 19 May 2021 16:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E2K31zv9B7ffj6B6TFciOEn0r2d2kzsg0XNwIGTDF7c=; b=nP8ENpfqIFpEx7M0xeCQNVEa+5CfObnfAMYCn8GGHvFPOd2BttV4dEjAiarMIDFWnC u/1gApsyElPI0OkpbDCMj6HSg0Yt89KKCBUakGE7+BcmW/cvoiE/A1Y1EMg63szFwtKc SbxBmdNc+U754OEjYdNy7jFWydtNMNUdzKu4oyYE45lCS/R32+boIQGIUhYeJaCnkUOn uVeVQauDX+OHL5VZTtUnHYbf+/9rbSrW89KmdtrstVjRgLyOfP+WsKMhoZcYV+PUjqhe PwEp6QDjjWOUsWj4T3mMeRjHZihwz9vrFTKWaxtgA/XjaZc274bpmIWEAUlFuhtSxx1X beRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E2K31zv9B7ffj6B6TFciOEn0r2d2kzsg0XNwIGTDF7c=; b=hFn/Ww7KsV56kYvIHIcQNzMmf+F22L2a+a4ge8cc9sz14MKD+ZNkjnnlBtXRkiuISD K+Dvn043rNdUCMg5vAVFFCoiFqHh4ZtIyrEyQJBuWtZPEFL3qb9/V6vOdC9goTL/3oMo vf1HYpzLX+0a33yd8ipC9n4j5zF5cIFfY9G3o1LSWUk0FSvlnvt20P6JCMM0ZOr6aO+1 Aneo/nu8QDqJsWdZgH8334c1q6YSSj6AL6BpOGZnWlB4uEoMkNrMdzdKXVkCjnquGJUU q+yJdA1TD2UOp0SkbTxsuKGTIYPLmLPnN6oKFYA4fyRZf9K4yPz495mZRDA4/4Db2B48 VrIQ== X-Gm-Message-State: AOAM530JXYqoDKxeyWUWXDNlo4/coAUACqidqP70l2bZ72ZJ3faqzCO8 ulRMcFbyb179qCZTqXekro0= X-Google-Smtp-Source: ABdhPJw5VMKw5kRFakreLS1ifTncYWXVE7BRVskxggZCR47GoILaoStU1VKzMO7YrxSfPe/JtVPWbw== X-Received: by 2002:a17:90a:fa91:: with SMTP id cu17mr1676202pjb.214.1621468484370; Wed, 19 May 2021 16:54:44 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:54:44 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Amey Narkhede Subject: [PATCH RESEND v2 2/7] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Date: Thu, 20 May 2021 05:24:21 +0530 Message-Id: <20210519235426.99728-3-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently there is separate function pcie_has_flr to probe if pcie flr is supported by the device which does not match the calling convention followed by reset methods which use second function argument to decide whether to probe or not. Add new function pcie_reset_flr that follows the calling convention of reset methods. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +- drivers/pci/pci.c | 62 ++++++++++++---------- drivers/pci/pcie/aer.c | 12 ++--- drivers/pci/quirks.c | 9 ++-- include/linux/pci.h | 2 +- 5 files changed, 43 insertions(+), 46 deletions(-) -- 2.31.1 diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index facc8e6bc..15d6c8452 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - /* check flr support */ - if (pcie_has_flr(pdev)) - pcie_flr(pdev); + pcie_reset_flr(pdev, 0); pci_restore_state(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index a8f8dd588..b998d6ad3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4573,32 +4573,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -/** - * pcie_has_flr - check if a device supports function level resets - * @dev: device to check - * - * Returns true if the device advertises support for PCIe function level - * resets. - */ -bool pcie_has_flr(struct pci_dev *dev) -{ - u32 cap; - - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) - return false; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; -} -EXPORT_SYMBOL_GPL(pcie_has_flr); - /** * pcie_flr - initiate a PCIe function level reset * @dev: device to reset * - * Initiate a function level reset on @dev. The caller should ensure the - * device supports FLR before calling this function, e.g. by using the - * pcie_has_flr() helper. + * Initiate a function level reset unconditionally on @dev without + * checking any flags and DEVCAP */ int pcie_flr(struct pci_dev *dev) { @@ -4621,6 +4601,31 @@ int pcie_flr(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pcie_flr); +/** + * pcie_reset_flr - initiate a PCIe function level reset + * @dev: device to reset + * @probe: If set, only check if the device can be reset this way. + * + * Initiate a function level reset on @dev. + */ +int pcie_reset_flr(struct pci_dev *dev, int probe) +{ + u32 cap; + + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) + return -ENOTTY; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (!(cap & PCI_EXP_DEVCAP_FLR)) + return -ENOTTY; + + if (probe) + return 0; + + return pcie_flr(dev); +} +EXPORT_SYMBOL_GPL(pcie_reset_flr); + static int pci_af_flr(struct pci_dev *dev, int probe) { int pos; @@ -5100,11 +5105,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 0); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - if (rc != -ENOTTY) - return rc; - } + rc = pcie_reset_flr(dev, 0); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) return rc; @@ -5135,8 +5138,9 @@ int pci_probe_reset_function(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 1); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) - return 0; + rc = pcie_reset_flr(dev, 1); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 1); if (rc != -ENOTTY) return rc; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ba2238834..f4e891bd5 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,13 +1405,11 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - pci_info(dev, "has been reset (%d)\n", rc); - } else { - pci_info(dev, "not reset (no FLR support)\n"); - rc = -ENOTTY; - } + rc = pcie_reset_flr(dev, 0); + if (!rc) + pci_info(dev, "has been reset\n"); + else + pci_info(dev, "not reset (no FLR support: %d)\n", rc); } else { rc = pci_bus_error_reset(dev); pci_info(dev, "%s Port link has been reset (%d)\n", diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3b..5318833f3 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3831,7 +3831,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) return -ENOTTY; if (probe) @@ -3900,13 +3900,10 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) */ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) { - if (!pcie_has_flr(dev)) - return -ENOTTY; + int ret = pcie_reset_flr(dev, probe); if (probe) - return 0; - - pcie_flr(dev); + return ret; msleep(250); diff --git a/include/linux/pci.h b/include/linux/pci.h index 979d54335..8d20e51ab 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1217,7 +1217,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -bool pcie_has_flr(struct pci_dev *dev); +int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Wed May 19 23:54:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GDIItr/Q; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqVQ0GXpz9sWc for ; Thu, 20 May 2021 09:54:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbhESX4M (ORCPT ); Wed, 19 May 2021 19:56:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230149AbhESX4J (ORCPT ); Wed, 19 May 2021 19:56:09 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4832C061761; Wed, 19 May 2021 16:54:48 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id k15so10568425pgb.10; Wed, 19 May 2021 16:54:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HuduY+gK1o4V1a+1CvxRCByt7bwGjlQdRi4ZrjqyKHg=; b=GDIItr/Qv96Lw83u9w2pWnPoSy1QnVhn5dqKhftoWYXlGOgmgHwYsnJoFO518e6LyB r/e/08Ri2+iTVa4CCGYq9ZfDjCFfVZfRo9HPqXsDfvT8GTNM85MCIGe08sMIU3Huucth +jqZGo+dZsdA00foj2Omh6/3wIc7jbKT9VltAaP2GGFjOBMXMC27kXMJRTCWjNJ2FIcS 2Qjf61qpqipy9XuVswlwqJBQePJ7PrWc00VNjMet3JdVGdWVc+SkEJ2cwQC0q+HF64Cc LTz192EF5gphqPOeBm3tSwxggk7ISZnEkJgBf0RfWSFt7cjbfOnExpCdPKALCeN9SOFG ftqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HuduY+gK1o4V1a+1CvxRCByt7bwGjlQdRi4ZrjqyKHg=; b=Yg/Qwkee72OEcmSfwLDT1LFLS9romW/DkdHhYTSgnpEUBRcdwZpkkmxkl+xe7w4efB EkyBfPM+pgXMPbNtNes52axh2Gs/ConESKI21abrKyooekzizb+npuAdX3ReLKaPY2Bb rdSQIOn0BTnSYGYzTqf1xSVyOtTN19wpG7woE0XYe1PoPCJY///arDHoD1Bj7Vy7953y dqPkqc0kd/MjKFTY/ZS43nTyZeeLoQ3kK1+hG3BT6SRtruISXqvE1HVQnGSvZyo5O2Iz 5lBDPvbHPGPB4r9pDw1Ng7ttsqrTdFipMQqje+GCLEre6jcv1Mr3TnSMrJCrmEDbKV2y HiHQ== X-Gm-Message-State: AOAM531cmIdMnb2iKSqxfEkFTtHvA7ZKBiMKxDSFVL1oz84Qkn9Sx4PQ tIVu+Le94eID9TE5DQUXGcs= X-Google-Smtp-Source: ABdhPJwqHpj5T83lnY1JFMIFxazt1Gj8txFuNNSQTsa7MlpxYOrKGzRDbPQl9qyB1HvxJzF4mRVC5w== X-Received: by 2002:a05:6a00:a:b029:2e0:d1b:59d6 with SMTP id h10-20020a056a00000ab02902e00d1b59d6mr1857914pfk.27.1621468488185; Wed, 19 May 2021 16:54:48 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:54:47 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Amey Narkhede Subject: [PATCH RESEND v2 3/7] PCI: Add new array for keeping track of ordering of reset methods Date: Thu, 20 May 2021 05:24:22 +0530 Message-Id: <20210519235426.99728-4-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new array reset_methods in struct pci_dev to keep track of reset mechanisms supported by the device and their ordering. Also refactor probing and reset functions to take advantage of calling convention of reset functions. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/pci/pci.c | 107 ++++++++++++++++++++++++++------------------ drivers/pci/pci.h | 10 ++++- drivers/pci/probe.c | 5 +-- include/linux/pci.h | 7 +++ 4 files changed, 82 insertions(+), 47 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b998d6ad3..ca46a55c7 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -72,6 +72,14 @@ static void pci_dev_d3_sleep(struct pci_dev *dev) msleep(delay); } +bool pci_reset_supported(struct pci_dev *dev) +{ + u8 null_reset_methods[PCI_RESET_FN_METHODS] = { 0 }; + + return memcmp(null_reset_methods, + dev->reset_methods, PCI_RESET_FN_METHODS); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -5068,6 +5076,19 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/* + * The ordering for functions in pci_reset_fn_methods + * is required for reset_methods byte array defined + * in struct pci_dev + */ +const struct pci_reset_fn_method pci_reset_fn_methods[] = { + { .reset_fn = &pci_dev_specific_reset, .name = "device_specific" }, + { .reset_fn = &pcie_reset_flr, .name = "flr" }, + { .reset_fn = &pci_af_flr, .name = "af_flr" }, + { .reset_fn = &pci_pm_reset, .name = "pm" }, + { .reset_fn = &pci_reset_bus_function, .name = "bus" }, +}; + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5090,65 +5111,65 @@ static void pci_dev_restore(struct pci_dev *dev) */ int __pci_reset_function_locked(struct pci_dev *dev) { - int rc; + int i, rc = -ENOTTY; + u8 prio; might_sleep(); - /* - * A reset method returns -ENOTTY if it doesn't support this device - * and we should try the next method. - * - * If it returns 0 (success), we're finished. If it returns any - * other error, we're also finished: this indicates that further - * reset mechanisms might be broken on the device. - */ - rc = pci_dev_specific_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_reset_bus_function(dev, 0); + for (prio = PCI_RESET_FN_METHODS; prio; prio--) { + for (i = 0; i < PCI_RESET_FN_METHODS; i++) { + if (dev->reset_methods[i] == prio) { + /* + * A reset method returns -ENOTTY if it doesn't support this device + * and we should try the next method. + * + * If it returns 0 (success), we're finished. If it returns any + * other error, we're also finished: this indicates that further + * reset mechanisms might be broken on the device. + */ + rc = pci_reset_fn_methods[i].reset_fn(dev, 0); + if (rc != -ENOTTY) + return rc; + break; + } + } + if (i == PCI_RESET_FN_METHODS) + break; + } + return rc; } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); /** - * pci_probe_reset_function - check whether the device can be safely reset - * @dev: PCI device to reset + * pci_init_reset_methods - check whether device can be safely reset + * and store supported reset mechanisms. + * @dev: PCI device to check for reset mechanisms * * Some devices allow an individual function to be reset without affecting * other functions in the same device. The PCI device must be responsive - * to PCI config space in order to use this function. + * to reads and writes to its PCI config space in order to use this function. * - * Returns 0 if the device function can be reset or negative if the - * device doesn't support resetting a single function. + * Stores reset mechanisms supported by device in reset_methods byte array + * which is a member of struct pci_dev */ -int pci_probe_reset_function(struct pci_dev *dev) +void pci_init_reset_methods(struct pci_dev *dev) { - int rc; + int i, rc; + u8 prio = PCI_RESET_FN_METHODS; + u8 reset_methods[PCI_RESET_FN_METHODS] = { 0 }; - might_sleep(); + BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_RESET_FN_METHODS); - rc = pci_dev_specific_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; + might_sleep(); - return pci_reset_bus_function(dev, 1); + for (i = 0; i < PCI_RESET_FN_METHODS; i++) { + rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + if (!rc) + reset_methods[i] = prio--; + else if (rc != -ENOTTY) + break; + } + memcpy(dev->reset_methods, reset_methods, sizeof(reset_methods)); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ef7c46613..61d09e4dd 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -39,7 +39,7 @@ enum pci_mmap_api { int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, enum pci_mmap_api mmap_api); -int pci_probe_reset_function(struct pci_dev *dev); +void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); @@ -612,6 +612,14 @@ struct pci_dev_reset_methods { int (*reset)(struct pci_dev *dev, int probe); }; +typedef int (*pci_reset_fn_t)(struct pci_dev *, int); + +struct pci_reset_fn_method { + pci_reset_fn_t reset_fn; + char *name; +}; + +extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_reset(struct pci_dev *dev, int probe); #else diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 953f15abc..c5cfdd239 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2403,9 +2403,8 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - - if (pci_probe_reset_function(dev) == 0) - dev->reset_fn = 1; + pci_init_reset_methods(dev); + dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 8d20e51ab..5c5925ecf 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,6 +49,8 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) +#define PCI_RESET_FN_METHODS 5 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -506,6 +508,10 @@ struct pci_dev { char *driver_override; /* Driver name to force a match */ unsigned long priv_flags; /* Private flags for the PCI driver */ + /* + * See pci_reset_fn_methods array in pci.c for ordering + */ + u8 reset_methods[PCI_RESET_FN_METHODS]; /* Array for storing ordering of reset methods */ }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) @@ -1219,6 +1225,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, void pcie_print_link_status(struct pci_dev *dev); int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); +bool pci_reset_supported(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); int pci_reset_function_locked(struct pci_dev *dev); From patchwork Wed May 19 23:54:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KRzjISu0; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqVR2w3Tz9sWc for ; Thu, 20 May 2021 09:54:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbhESX4O (ORCPT ); Wed, 19 May 2021 19:56:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230157AbhESX4M (ORCPT ); Wed, 19 May 2021 19:56:12 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F9DCC061574; Wed, 19 May 2021 16:54:52 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id l70so10595056pga.1; Wed, 19 May 2021 16:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j3+Y0zXhw6oRbh1m+BJ3zWP7Qr31tk01wHFVmcRZ4wE=; b=KRzjISu0Nz5xgIhnyRtdixkLfZx2emIynOYwQ8r8BpC5RIbbZNSVRAw3ia7789u6G8 Yd8Wv9VJX/lXXQk8f381qURyRUk0WNyftGO4sRQl+x0uVEMsjOjAtLwjAt9FJmEfzT8S bIGFuvrkuT6JVmoFAL+ozCmFhQJqYGM6JvPrv55f78Zr7bbzCBWEoKRxDUpmNRT7gNY3 hgpcgB6UVxcICX3jWYx5eV2gjAsYETJBWHSvvVt/CiXDduAjKnIJcgjrrKVIawgJ0ZoL pJNf0ZUVHrbhsEHLzc81TxhHOotLMpJhTuy3et8nBW8V8F/2TGwxVNDvGK+wvXz2x5AY eVAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j3+Y0zXhw6oRbh1m+BJ3zWP7Qr31tk01wHFVmcRZ4wE=; b=aHBvhu1Ut381d+bCfS8qSDvMg5eXlMEQvTySX2rkBih9rLmMbGtv0iuNYoag8OlQLP /1gMvfAiSA9MtqAFYxopTbVjuUeqmWZ3ImeF1dA0GYPVsbA6aHj8pLFNS3dAtS8leqfN /wuLjJMU7F+etHNpRttR/M3YiqZ2rZnIO4FPpW63Vk0dMxXKJUZ+FB2wMtc2rvtcMjpi zue/6y6ywcR4fSuGxz6wYy5A/FIWXjo7v4g7NZ58mWvyy/ritekxTVvwASnCKDJttaZ6 e3Zg9Z7akqoszEg2m+WtwXdBouoX0eHDwl8CBwmV0NOwlqBQlt+Ndb2T6p1C0qe1wkLu /pHw== X-Gm-Message-State: AOAM531WDXIFq8jMWw/fVRmZe85qgiAYBp+UnXZqDYmLNlIkEclPkRV3 nAyR/DYIeU3bp/9Zu880JZI= X-Google-Smtp-Source: ABdhPJyLdXRtmhxMAFQnHk7I+ShuC5vbdeyKNFDpnb9jFXefDAscxVobX8fksgxqxan/FEOUoyYPlg== X-Received: by 2002:a63:f248:: with SMTP id d8mr1630436pgk.219.1621468491967; Wed, 19 May 2021 16:54:51 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:54:51 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Amey Narkhede Subject: [PATCH RESEND v2 4/7] PCI: Remove reset_fn field from pci_dev Date: Thu, 20 May 2021 05:24:23 +0530 Message-Id: <20210519235426.99728-5-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org reset_fn field is used to indicate whether the device supports any reset mechanism or not. Deprecate use of reset_fn in favor of new reset_methods array which can be used to keep track of all supported reset mechanisms of a device and their ordering. The octeon driver is incorrectly using reset_fn field to detect if the device supports FLR or not. Use pcie_reset_flr to probe whether it supports FLR or not. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/net/ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/pci-sysfs.c | 6 ++---- drivers/pci/pci.c | 6 +++--- drivers/pci/probe.c | 1 - drivers/pci/quirks.c | 2 +- include/linux/pci.h | 1 - 6 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 516f166ce..336d149ee 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (oct->pci_dev->reset_fn) + if (!pcie_reset_flr(oct->pci_dev, 1)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index f8afd54ca..388895099 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1334,7 +1334,7 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev) pcie_vpd_create_sysfs_dev_files(dev); - if (dev->reset_fn) { + if (pci_reset_supported(dev)) { retval = device_create_file(&dev->dev, &dev_attr_reset); if (retval) goto error; @@ -1417,10 +1417,8 @@ int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) static void pci_remove_capabilities_sysfs(struct pci_dev *dev) { pcie_vpd_remove_sysfs_dev_files(dev); - if (dev->reset_fn) { + if (pci_reset_supported(dev)) device_remove_file(&dev->dev, &dev_attr_reset); - dev->reset_fn = 0; - } } /** diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ca46a55c7..664cf2d35 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5192,7 +5192,7 @@ int pci_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_lock(dev); @@ -5228,7 +5228,7 @@ int pci_reset_function_locked(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_save_and_disable(dev); @@ -5251,7 +5251,7 @@ int pci_try_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; if (!pci_dev_trylock(dev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index c5cfdd239..4764e031a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2404,7 +2404,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pcie_report_downtraining(dev); pci_init_reset_methods(dev); - dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 5318833f3..8f47d139c 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5535,7 +5535,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || pdev->subsystem_device != 0x222e || - !pdev->reset_fn) + !pci_reset_supported(pdev)) return; if (pci_enable_device_mem(pdev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 5c5925ecf..9f8347799 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -429,7 +429,6 @@ struct pci_dev { unsigned int state_saved:1; unsigned int is_physfn:1; unsigned int is_virtfn:1; - unsigned int reset_fn:1; unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ From patchwork Wed May 19 23:54:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=shlelyBt; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqVW2Pqnz9sWF for ; Thu, 20 May 2021 09:54:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbhESX4S (ORCPT ); Wed, 19 May 2021 19:56:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230149AbhESX4Q (ORCPT ); Wed, 19 May 2021 19:56:16 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585B8C061574; Wed, 19 May 2021 16:54:56 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id e19so11047765pfv.3; Wed, 19 May 2021 16:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lJOBwH8PLMV6va8nHZHAu/lGBTZiJMwsNPKzTsCadho=; b=shlelyBt1qer5wpAW1LO1ffaKwlZNc+NTVk/TDOT5Veelln89KUemjua0v5IN+I8Pw xCJMCWCPYNDdV5YtaCNkkuDKOPBWvdeQwBUfWoBmoOXoqmNfSFMvqcck/wnG+CiklpPa 2qpUxmNrLT6UqQkG20zR0hhAer7qvJPUKGbQe5zPZyuxLsXASkifoaeXz+qXtWWnpmdx Kq6+Vrht1mT6Wij6555fgo659jwoRcJAh70yeO1grR+BBDsp+GmroNpVVFFdRawyStdr ABfNXZJDYXwZE38wxiPkr48YWMQLU7NcV8ILOi7RF72IhTAIJOxA4jldzaDmdrf/Vyvm O2UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lJOBwH8PLMV6va8nHZHAu/lGBTZiJMwsNPKzTsCadho=; b=hKaGiJA7EaWs0Ao6+LADli4/aSaqXLFih3EiHwXSJiB2YN/VtL6tzO0Gg1HqVfIDbY yY5pebyM3Vpj3MRZuQ8aLcBW5TKpe4BpUNSBrlZPxMVCsjjMFP5VwerMkkAj2II4lCDK iaxvfEPl0mbHqEiNTWUI4bobb6K5LlsPWfdvy9zNJie7ugq9SPycxhIaDT9kVLMlKjxP IFkcUBVPdepQf6a8pPTEXXZyP19/HErIWO5YA1DPFsbGfSQbaOWuXNNi9x0W96FxFIpW aMgSiX5HJ2JdkdxtzO29dPDjLY+D04RMhbRkqSnW2LThyQJwLp74PkQ3c+KGXj1vuf8H jRCg== X-Gm-Message-State: AOAM531HNZziPGq3TjwZMciqkcFsgSXJl6qakCAvTWcYyGCTkPA7zwJq rZWP4z9zlSRS0ZZUSeWd8No= X-Google-Smtp-Source: ABdhPJwBR5UiqxPKh5orhB46cc6OgROEopUdOd9YV2XyQc/FczqPS0T5Ng4oOE16A/l+SwLuucDAKQ== X-Received: by 2002:aa7:8d5a:0:b029:227:7b07:7d8b with SMTP id s26-20020aa78d5a0000b02902277b077d8bmr1594306pfe.26.1621468495847; Wed, 19 May 2021 16:54:55 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:54:55 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Amey Narkhede Subject: [PATCH RESEND v2 5/7] PCI/sysfs: Allow userspace to query and set device reset mechanism Date: Thu, 20 May 2021 05:24:24 +0530 Message-Id: <20210519235426.99728-6-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add reset_method sysfs attribute to enable user to query and set user preferred device reset methods and their ordering. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- Documentation/ABI/testing/sysfs-bus-pci | 16 +++++ drivers/pci/pci-sysfs.c | 91 ++++++++++++++++++++++++- 2 files changed, 104 insertions(+), 3 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 25c9c3977..36fba7ebf 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -121,6 +121,22 @@ Description: child buses, and re-discover devices removed earlier from this part of the device tree. +What: /sys/bus/pci/devices/.../reset_method +Date: March 2021 +Contact: Amey Narkhede +Description: + Some devices allow an individual function to be reset + without affecting other functions in the same slot. + For devices that have this support, a file named reset_method + will be present in sysfs. Reading this file will give names + of the device supported reset methods and their ordering. + Writing the name or comma separated list of names of any of + the device supported reset methods to this file will set the + reset methods and their ordering to be used when resetting + the device. Writing empty string to this file will disable + ability to reset the device and writing "default" will return + to the original value. + What: /sys/bus/pci/devices/.../reset Date: July 2009 Contact: Michael S. Tsirkin diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 388895099..cf2f66270 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1304,6 +1304,84 @@ static const struct bin_attribute pcie_config_attr = { .write = pci_write_config, }; +static ssize_t reset_method_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + ssize_t len = 0; + int i, prio; + + for (prio = PCI_RESET_FN_METHODS; prio; prio--) { + for (i = 0; i < PCI_RESET_FN_METHODS; i++) { + if (prio == pdev->reset_methods[i]) { + len += sysfs_emit_at(buf, len, "%s%s", + len ? "," : "", + pci_reset_fn_methods[i].name); + break; + } + } + + if (i == PCI_RESET_FN_METHODS) + break; + } + + return len; +} + +static ssize_t reset_method_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 reset_methods[PCI_RESET_FN_METHODS]; + struct pci_dev *pdev = to_pci_dev(dev); + u8 prio = PCI_RESET_FN_METHODS; + char *name; + int i; + + /* + * Initialize reset_method such that 0xff indicates + * supported but not currently enabled reset methods + * as we only use priority values which are within + * the range of PCI_RESET_FN_METHODS array size + */ + for (i = 0; i < PCI_RESET_FN_METHODS; i++) + reset_methods[i] = pdev->reset_methods[i] ? 0xff : 0; + + if (sysfs_streq(buf, "")) { + pci_warn(pdev, "All device reset methods disabled by user"); + goto set_reset_methods; + } + + if (sysfs_streq(buf, "default")) { + for (i = 0; i < PCI_RESET_FN_METHODS; i++) + reset_methods[i] = reset_methods[i] ? prio-- : 0; + goto set_reset_methods; + } + + while ((name = strsep((char **)&buf, ",")) != NULL) { + for (i = 0; i < PCI_RESET_FN_METHODS; i++) { + if (reset_methods[i] && + sysfs_streq(name, pci_reset_fn_methods[i].name)) { + reset_methods[i] = prio--; + break; + } + } + if (i == PCI_RESET_FN_METHODS) + return -EINVAL; + } + + if (reset_methods[0] && + reset_methods[0] != PCI_RESET_FN_METHODS) + pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); + +set_reset_methods: + memcpy(pdev->reset_methods, reset_methods, sizeof(reset_methods)); + return count; +} + +static DEVICE_ATTR_RW(reset_method); + static ssize_t reset_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1337,11 +1415,16 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev) if (pci_reset_supported(dev)) { retval = device_create_file(&dev->dev, &dev_attr_reset); if (retval) - goto error; + goto err_reset; + retval = device_create_file(&dev->dev, &dev_attr_reset_method); + if (retval) + goto err_method; } return 0; -error: +err_method: + device_remove_file(&dev->dev, &dev_attr_reset); +err_reset: pcie_vpd_remove_sysfs_dev_files(dev); return retval; } @@ -1417,8 +1500,10 @@ int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) static void pci_remove_capabilities_sysfs(struct pci_dev *dev) { pcie_vpd_remove_sysfs_dev_files(dev); - if (pci_reset_supported(dev)) + if (pci_reset_supported(dev)) { device_remove_file(&dev->dev, &dev_attr_reset); + device_remove_file(&dev->dev, &dev_attr_reset_method); + } } /** From patchwork Wed May 19 23:54:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KIgRdEc9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqWm0Wzmz9sWX for ; Thu, 20 May 2021 09:56:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229952AbhESX5W (ORCPT ); Wed, 19 May 2021 19:57:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229808AbhESX5V (ORCPT ); Wed, 19 May 2021 19:57:21 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47EDDC061574; Wed, 19 May 2021 16:56:00 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id t193so10597490pgb.4; Wed, 19 May 2021 16:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JID/D/KXtWMVZbJD63Qy/P1niv6pTy4RV0ayNkwMylI=; b=KIgRdEc9tBygnG0si+aZz6QPnCZLqGoi8r/tiKBxljEqXvl8h3I9TG19Midl7WkSsB GRHNI++c7Bp2cfFPwHF+eZn3mLy+3+oLAqQDnfOgtBTtmRC06PVP1VQGrncSG2J5Fzzo /kpLrO0Prgb021SKwGWygj0tt/2+IxqwKzFKAWghG2L3pVv9brDOCMkkeGosheGsepkT EeecSwvansL7np+p8Rjw5NOCmteSAIgNnGT7eQGHEOgcL4s8urgoIJgDBeAUilLpCH9N bm22ljDnSzpEe9liRgCoPKV0VmhpmP+L9fcM39KGeqO8Qshgtg3BRz4JicIEjA7aLrfW yQQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JID/D/KXtWMVZbJD63Qy/P1niv6pTy4RV0ayNkwMylI=; b=Y26fUsEOO36BN6kO5Wzlt4HBcL1E+gyKHI5vF2izm2BLOGJlYsCIS9vyqb//v52+gp OpI/0dQw495J1brIdM4uJArx8J3SzAxkWOTqqFhy945lVM8uWl6CPW6DsO2NdcXGXzG8 vMejZHMZqbkL3hbVT9fILvxSg6ANR0rMPPj9dPbL5Ow7+UWluAS/a+DlOB9lavHEJSJh 5cv9eHob/WR4jdhddjPeWmF54Hawov8iZ85Jvp7wFEWdg2tKpkIrfhWJUKOthNVv4MlI O1zUTqT1+n8hA49Hu8z8UwemeKysQ2vBcHgbKpueyrl6b35UG9FjXq1SSkvInz30I8sE uueA== X-Gm-Message-State: AOAM530kqiWFtfQE5gO0g3lnQzPwVmRLwvEK+0f22lQ3pNCjokg5l6rr Dx9UssQ/xkmJNoCT1OP3Ly8= X-Google-Smtp-Source: ABdhPJwHNVfl28T31yW0FsTl7GDa+cG/GiO/x0XEtnesypMpVIAw0M0UfS62XDUKa+bwCzQSqpGdWg== X-Received: by 2002:a65:640c:: with SMTP id a12mr1667768pgv.229.1621468559857; Wed, 19 May 2021 16:55:59 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:55:59 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, sdonthineni@nvidia.com Subject: [PATCH RESEND v2 6/7] PCI: Add support for a function level reset based on _RST method Date: Thu, 20 May 2021 05:24:25 +0530 Message-Id: <20210519235426.99728-7-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The ACPI binding information is available only after calling device_add(), so move pci_init_reset_methods() to end of the pci_device_add(). The default priority of the acpi reset is set to below device-specific and above hardware resets. Signed-off-by: Shanker Donthineni --- drivers/pci/pci.c | 30 ++++++++++++++++++++++++++++++ drivers/pci/probe.c | 2 +- include/linux/pci.h | 2 +- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 664cf2d35..d39dba590 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5076,6 +5076,35 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ +#ifdef CONFIG_ACPI + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + /* Return -ENOTTY if _RST method is not included in the dev context */ + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + /* Return 0 for probe phase indicating that we can reset this device */ + if (probe) + return 0; + + /* Invoke _RST() method to perform a function level reset */ + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "Failed to reset the device\n"); + return -EINVAL; + } + return 0; +#else + return -ENOTTY; +#endif +} + /* * The ordering for functions in pci_reset_fn_methods * is required for reset_methods byte array defined @@ -5083,6 +5112,7 @@ static void pci_dev_restore(struct pci_dev *dev) */ const struct pci_reset_fn_method pci_reset_fn_methods[] = { { .reset_fn = &pci_dev_specific_reset, .name = "device_specific" }, + { .reset_fn = &pci_dev_acpi_reset, .name = "acpi" }, { .reset_fn = &pcie_reset_flr, .name = "flr" }, { .reset_fn = &pci_af_flr, .name = "af_flr" }, { .reset_fn = &pci_pm_reset, .name = "pm" }, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4764e031a..d4becd6ff 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2403,7 +2403,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - pci_init_reset_methods(dev); } /* @@ -2494,6 +2493,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev->match_driver = false; ret = device_add(&dev->dev); WARN_ON(ret < 0); + pci_init_reset_methods(dev); } struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) diff --git a/include/linux/pci.h b/include/linux/pci.h index 9f8347799..b4a5d2146 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,7 +49,7 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) -#define PCI_RESET_FN_METHODS 5 +#define PCI_RESET_FN_METHODS 6 /* * The PCI interface treats multi-function devices as independent From patchwork Wed May 19 23:54:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amey Narkhede X-Patchwork-Id: 1481327 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=DqHxukMa; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FlqX06X5jz9sWF for ; Thu, 20 May 2021 09:56:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229808AbhESX5f (ORCPT ); Wed, 19 May 2021 19:57:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbhESX5e (ORCPT ); Wed, 19 May 2021 19:57:34 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FE41C061574; Wed, 19 May 2021 16:56:12 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id q15so10569909pgg.12; Wed, 19 May 2021 16:56:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JNMQiBUZJXJ3UxQ2xkL0KPsN3/Hv3HAfTP43B6QlmJU=; b=DqHxukMa5VU3tYERMgbbJuvKGXE07lSus/5TqPuBWlszSptPZs13grMg70c47berPu 7Fl0s/OMldkxDA0bRdymTTAA+npmKYYIGCRfSfPAjvfKtKW2Sl2hii41oep87ZU/Up/S ZQKqcjwxDFOYXda+UprCLyyfv7IVT95/IBDIDRxc0174nF7MAvUc/oYfNaXeW3QGeknN ACYTO3wqBhympTZ8ygIHDpzk6kFfAeaGhh6cpaVdAXp0OmGiKHx1oIRdXr+NXrqifJJ/ x4EQ9VT1z4+hXehnx82w4zxqi1a7Bzj4ztjbENar+5ObIBJWrl3h7Ofiq/xPaWgzmCWI U+Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JNMQiBUZJXJ3UxQ2xkL0KPsN3/Hv3HAfTP43B6QlmJU=; b=sAOAjgvupJtBkGLoa+bF2iOIaXQzrIuuN7zBZAxove07VA2aqZDsoUPN/uwb2FyKvA HLXpihRXctbbMKF6JqA6MGE8I/heXa8vw7IsqAhlXIcCpxIJdmt6OKzucgdEU2uoYsWP i0FoYo4irPOIbAmHhuEr+Uwu4vte9KmAtrviu1f+pQ5OtYx5ARbuFr3ljW2BDiQ+Q9ms wWuhpcmTJHL7nn/YIQS+CRIJrm4KuBdOik6poiUzttToNkBB6MO8nGJxrw4CM6ZFJV8t paMnaFMwHvBaujVlxw67kbcxO5duslaucpye0JaVRsKQtuVCSMv9TBWrDriv3AOr4lHW tYYA== X-Gm-Message-State: AOAM531/9RDKqY8ZnRMiZUyl9+Gi6U7pv89b1vRfdOF/xm2jcyFqobo0 QyDyn5ec4u0m7d35R9yt4Gw= X-Google-Smtp-Source: ABdhPJwN0cRMlSFzgP6WkzbRtqX6a6E7f8eUcAFNhAfjm5HJfya2n6REMjACn4roKy9Ne+kBxShXng== X-Received: by 2002:a63:36c1:: with SMTP id d184mr1672616pga.47.1621468572051; Wed, 19 May 2021 16:56:12 -0700 (PDT) Received: from localhost.localdomain ([94.140.8.39]) by smtp.googlemail.com with ESMTPSA id z12sm397670pfk.45.2021.05.19.16.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 16:56:11 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, raphael.norwitz@nutanix.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, sdonthineni@nvidia.com Subject: [PATCH RESEND v2 7/7] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Date: Thu, 20 May 2021 05:24:26 +0530 Message-Id: <20210519235426.99728-8-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519235426.99728-1-ameynarkhede03@gmail.com> References: <20210519235426.99728-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni On select platforms, some Nvidia GPU devices do not work with SBR. Triggering SBR would leave the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to fix the issue. This issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni --- drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 8f47d139c..ceec67342 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3558,6 +3558,18 @@ static void quirk_no_bus_reset(struct pci_dev *dev) dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + quirk_no_bus_reset(dev); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + /* * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. * The device will throw a Link Down error on AER-capable systems and