From patchwork Fri Jan 19 23:17:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcFR65y9z9t1t for ; Sat, 20 Jan 2018 10:18:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932444AbeASXSS (ORCPT ); Fri, 19 Jan 2018 18:18:18 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48305 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932382AbeASXSJ (ORCPT ); Fri, 19 Jan 2018 18:18:09 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 23CF754CFE; Fri, 19 Jan 2018 23:18:03 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 1/9] ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs Date: Sat, 20 Jan 2018 07:17:27 +0800 Message-Id: <20180119231735.61504-2-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Allwinner also has some ARMv5 SoCs. In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 option that is selectable when ARMv7 is selceted, and make CONFIG_ARCH_SUNXI a common bool config which is selected by both V7 and V5 sunxi option. The ARMv7 defconfigs are modified to have the new CONFIG_ARCH_SUNXI_V7 option. Signed-off-by: Icenowy Zheng --- arch/arm/configs/multi_v7_defconfig | 2 +- arch/arm/configs/sunxi_defconfig | 2 +- arch/arm/mach-sunxi/Kconfig | 14 ++++++++++++-- arch/arm/mach-sunxi/Makefile | 2 +- 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 61509c4b769f..9b4267b2ad49 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -98,7 +98,7 @@ CONFIG_ARCH_R8A7792=y CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y CONFIG_ARCH_SH73A0=y -CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI_V7=y CONFIG_ARCH_SIRF=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA_2x_SOC=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 5caaf971fb50..9e9be989a4bd 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -5,7 +5,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI_V7=y CONFIG_SMP=y CONFIG_NR_CPUS=8 CONFIG_AEABI=y diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 58153cdf025b..65509a35935f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,6 +1,16 @@ -menuconfig ARCH_SUNXI +config ARCH_SUNXI + bool + select ARCH_HAS_RESET_CONTROLLER + select CLKSRC_MMIO + select GENERIC_IRQ_CHIP + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + +menuconfig ARCH_SUNXI_V7 bool "Allwinner SoCs" depends on ARCH_MULTI_V7 + select ARCH_SUNXI select ARCH_HAS_RESET_CONTROLLER select CLKSRC_MMIO select GENERIC_IRQ_CHIP @@ -10,7 +20,7 @@ menuconfig ARCH_SUNXI select SUN4I_TIMER select RESET_CONTROLLER -if ARCH_SUNXI +if ARCH_SUNXI_V7 config MACH_SUN4I bool "Allwinner A10 (sun4i) SoCs support" diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 27b168f121a1..6d874f6c9d3a 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_ARCH_SUNXI) += sunxi.o +obj-$(CONFIG_ARCH_SUNXI_V7) += sunxi.o obj-$(CONFIG_SMP) += platsmp.o From patchwork Fri Jan 19 23:17:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863854 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcFn2qlXz9sPk for ; Sat, 20 Jan 2018 10:18:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932616AbeASXSe (ORCPT ); Fri, 19 Jan 2018 18:18:34 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48330 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932314AbeASXSR (ORCPT ); Fri, 19 Jan 2018 18:18:17 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id D6C2C56065; Fri, 19 Jan 2018 23:18:11 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 2/9] ARM: sunxi: add Allwinner ARMv5 SoCs Date: Sat, 20 Jan 2018 07:17:28 +0800 Message-Id: <20180119231735.61504-3-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/Kconfig | 13 +++++++++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/sunxi_v5.c | 22 ++++++++++++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 arch/arm/mach-sunxi/sunxi_v5.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 65509a35935f..78ac9ce70641 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -59,3 +59,16 @@ config MACH_SUN9I select ARM_GIC endif + +menuconfig ARCH_SUNXI_V5 + bool "Allwinner SoCs" + depends on ARCH_MULTI_V5 + select ARCH_SUNXI + select SUN4I_TIMER + +if ARCH_SUNXI_V5 + +config MACH_SUNIV + bool "Allwinner new F-series (suniv) SoCs support" + default ARCH_SUNXI +endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 6d874f6c9d3a..e43e1557842d 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ARCH_SUNXI_V7) += sunxi.o +obj-$(CONFIG_ARCH_SUNXI_V5) += sunxi_v5.o obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-sunxi/sunxi_v5.c b/arch/arm/mach-sunxi/sunxi_v5.c new file mode 100644 index 000000000000..1777c5b0db4b --- /dev/null +++ b/arch/arm/mach-sunxi/sunxi_v5.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for Allwinner F series SoCs + * + * Copyright (C) 2017 Icenowy Zheng + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +static const char * const suniv_board_dt_compat[] = { + "allwinner,suniv", + "allwinner,suniv-f1c100s", + NULL, +}; + +DT_MACHINE_START(SUNXI_DT, "Allwinner suniv Family") + .dt_compat = suniv_board_dt_compat, +MACHINE_END From patchwork Fri Jan 19 23:17:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcFk3p89z9sRW for ; Sat, 20 Jan 2018 10:18:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932574AbeASXSb (ORCPT ); Fri, 19 Jan 2018 18:18:31 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48350 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932527AbeASXSY (ORCPT ); Fri, 19 Jan 2018 18:18:24 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id EBF0B56068; Fri, 19 Jan 2018 23:18:18 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 3/9] irqchip/sun4i: add support for suniv interrupt controller Date: Sat, 20 Jan 2018 07:17:29 +0800 Message-Id: <20180119231735.61504-4-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13. Add support for it in irq-sun4i driver. Signed-off-by: Icenowy Zheng --- drivers/irqchip/irq-sun4i.c | 43 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index e3e5b9132b75..64ae41379802 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -23,13 +23,26 @@ #include +enum sun4i_irq_type { + sun4i_ic, + suniv_ic +}; + +static enum sun4i_irq_type sun4i_irq_type; +static int sun4i_irq_enable_reg_offset; +static int sun4i_irq_mask_reg_offset; + #define SUN4I_IRQ_VECTOR_REG 0x00 #define SUN4I_IRQ_PROTECTION_REG 0x08 #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 +#define SUN4I_IRQ_ENABLE_REG(x) (sun4i_irq_enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(x) (sun4i_irq_mask_reg_offset + 0x4 * x) static void __iomem *sun4i_irq_base; static struct irq_domain *sun4i_irq_domain; @@ -115,8 +128,9 @@ static int __init sun4i_of_init(struct device_node *node, writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); - /* Enable protection mode */ - writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); + /* Enable protection mode (not available in suniv) */ + if (sun4i_irq_type == sun4i_ic) + writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); /* Configure the external interrupt source type */ writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); @@ -130,7 +144,26 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = sun4i_ic; + sun4i_irq_enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); +} +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = suniv_ic; + sun4i_irq_enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); +} +IRQCHIP_DECLARE(allwinner_suniv_ic, "allwinner,suniv-ic", suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) { From patchwork Fri Jan 19 23:17:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcHn2MMnz9t1t for ; Sat, 20 Jan 2018 10:20:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756422AbeASXUS (ORCPT ); Fri, 19 Jan 2018 18:20:18 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48366 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932382AbeASXSb (ORCPT ); Fri, 19 Jan 2018 18:18:31 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 3D9765606A; Fri, 19 Jan 2018 23:18:26 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 4/9] clocksource: sun4i: add a compatible for suniv Date: Sat, 20 Jan 2018 07:17:30 +0800 Message-Id: <20180119231735.61504-5-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. Signed-off-by: Icenowy Zheng --- drivers/clocksource/sun4i_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 6e0180aaf784..88e09554ce7a 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -218,3 +218,5 @@ static int __init sun4i_timer_init(struct device_node *node) } TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", sun4i_timer_init); +TIMER_OF_DECLARE(suniv, "allwinner,suniv-timer", + sun4i_timer_init); From patchwork Fri Jan 19 23:17:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcG00ML7z9sRm for ; Sat, 20 Jan 2018 10:18:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756019AbeASXSl (ORCPT ); Fri, 19 Jan 2018 18:18:41 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48387 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932644AbeASXSj (ORCPT ); Fri, 19 Jan 2018 18:18:39 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id D71F35606B; Fri, 19 Jan 2018 23:18:34 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 5/9] clocksource/drivers/sun4i: register as sched_clock on suniv Date: Sat, 20 Jan 2018 07:17:31 +0800 Message-Id: <20180119231735.61504-6-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Icenowy Zheng --- drivers/clocksource/sun4i_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 88e09554ce7a..16dedf5ff0ca 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) + of_machine_is_compatible("allwinner,sun5i-a10s") || + of_machine_is_compatible("allwinner,suniv")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); From patchwork Fri Jan 19 23:17:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863860 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcHS40Vmz9t20 for ; Sat, 20 Jan 2018 10:20:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756317AbeASXUA (ORCPT ); Fri, 19 Jan 2018 18:20:00 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48408 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932527AbeASXSq (ORCPT ); Fri, 19 Jan 2018 18:18:46 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 904135606D; Fri, 19 Jan 2018 23:18:39 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 6/9] pinctrl: sunxi: add support for suniv (newer F-series SoCs) Date: Sat, 20 Jan 2018 07:17:32 +0800 Message-Id: <20180119231735.61504-7-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-suniv.c | 417 ++++++++++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index bfce99d86dfc..206770d14b20 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -6,6 +6,10 @@ config PINCTRL_SUNXI select GENERIC_PINCONF select GPIOLIB +config PINCTRL_SUNIV + def_bool MACH_SUNIV + select PINCTRL_SUNXI + config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 12a752e836ef..3c31c5a41ed5 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -3,6 +3,7 @@ obj-y += pinctrl-sunxi.o # SoC Drivers +obj-$(CONFIG_PINCTRL_SUNIV) += pinctrl-suniv.o obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv.c b/drivers/pinctrl/sunxi/pinctrl-suniv.c new file mode 100644 index 000000000000..57c914dfe063 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-suniv.c @@ -0,0 +1,417 @@ +/* + * Allwinner new F-series SoC (suniv) pinctrl driver. + * + * Copyright (C) 2018 Icenowy Zheng + * + * Icenowy Zheng + * + * Copyright (C) 2014 Jackie Hwang + * + * Jackie Hwang + * + * Copyright (C) 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" +static const struct sunxi_desc_pin suniv_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X2 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* CKE */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4*/ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x3, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x3, "i2s"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi0"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D0 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION(0x5, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D1 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION(0x5, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "lcd"), /* D8 */ + SUNXI_FUNCTION(0x4, "clk"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D9 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D16 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D17 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "clk0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION(0x4, "ir0"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "dgb0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), +}; + +static const struct sunxi_pinctrl_desc suniv_pinctrl_data = { + .pins = suniv_pins, + .npins = ARRAY_SIZE(suniv_pins), + .irq_banks = 3, + .disable_strict_mode = true, +}; + +static int suniv_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &suniv_pinctrl_data); +} + +static const struct of_device_id suniv_pinctrl_match[] = { + { .compatible = "allwinner,suniv-pinctrl", }, + {} +}; + +static struct platform_driver suniv_pinctrl_driver = { + .probe = suniv_pinctrl_probe, + .driver = { + .name = "suniv-pinctrl", + .of_match_table = suniv_pinctrl_match, + }, +}; +builtin_platform_driver(suniv_pinctrl_driver); From patchwork Fri Jan 19 23:17:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcH52wL4z9sPk for ; Sat, 20 Jan 2018 10:19:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756230AbeASXTn (ORCPT ); Fri, 19 Jan 2018 18:19:43 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48434 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932730AbeASXSx (ORCPT ); Fri, 19 Jan 2018 18:18:53 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id EC6E156073; Fri, 19 Jan 2018 23:18:47 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 7/9] clk: sunxi-ng: add support for suniv SoC Date: Sat, 20 Jan 2018 07:17:33 +0800 Message-Id: <20180119231735.61504-8-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-suniv.c | 536 ++++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-suniv.h | 34 +++ include/dt-bindings/clock/suniv-ccu.h | 69 +++++ include/dt-bindings/reset/suniv-ccu.h | 37 +++ 6 files changed, 682 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-suniv.c create mode 100644 drivers/clk/sunxi-ng/ccu-suniv.h create mode 100644 include/dt-bindings/clock/suniv-ccu.h create mode 100644 include/dt-bindings/reset/suniv-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6427d0ebe2de..138fe1ce763b 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -6,6 +6,11 @@ config SUNXI_CCU if SUNXI_CCU +config SUNIV_CCU + bool "Support for the Allwinner newer F-series SoC CCU" + default MACH_SUNIV + depends on MACH_SUNIV || COMPILE_TEST + config SUN50I_A64_CCU bool "Support for the Allwinner A64 CCU" default ARM64 && ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 4141c3fe08ae..c667b60c7f61 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_nm.o lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o # SoC support +obj-$(CONFIG_SUNIV_CCU) += ccu-suniv.o obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-suniv.c b/drivers/clk/sunxi-ng/ccu-suniv.c new file mode 100644 index 000000000000..d6040b2b147c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-suniv.h" + +static struct ccu_nkmp pll_cpu_clk = { + .enable = BIT(31), + .lock = BIT(28), + + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + /* MAX is guessed by the BSP table */ + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpu", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUNIV_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_IS_CRITICAL); + +static struct ccu_nk pll_periph_clk = { + .enable = BIT(31), + .lock = BIT(28), + .k = _SUNXI_CCU_MULT(4, 2), + .n = _SUNXI_CCU_MULT(8, 5), + .common = { + .reg = 0x028, + .hw.init = CLK_HW_INIT("pll-periph", "osc24M", + &ccu_nk_ops, 0), + }, +}; + +static const char * const cpu_parents[] = { "osc32k", "osc24M", + "pll-cpu" , "pll-cpu" }; +static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); + +static const char * const ahb_parents[] = { "osc32k", "osc24M", + "cpu" , "pll-periph" }; +static const struct ccu_mux_var_prediv ahb_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; +static struct ccu_div ahb_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .var_predivs = ahb_predivs, + .n_var_predivs = ARRAY_SIZE(ahb_predivs), + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb", + 0x054, 8, 2, apb_div_table, 0); + +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb", + 0x060, BIT(24), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb", + 0x064, BIT(9), 0); +static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb", + 0x064, BIT(10), 0); +static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb", + 0x064, BIT(14), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb", + 0x068, BIT(2), 0); +static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb", + 0x068, BIT(3), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb", + 0x068, BIT(16), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb", + 0x068, BIT(17), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb", + 0x068, BIT(18), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb", + 0x068, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb", + 0x068, BIT(20), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb", + 0x068, BIT(21), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb", + 0x068, BIT(22), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static const char * const i2s_spdif_parents[] = { "pll-audio-8x", + "pll-audio-4x", + "pll-audio-2x", + "pll-audio" }; + +static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, + 0x0b4, 16, 2, BIT(31), 0); + +/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", + "pll-ddr", 0x100, BIT(2), 0); +static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr", + 0x100, BIT(3), 0); +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", + 0x100, BIT(26), 0); + +static const char * const de_parents[] = { "pll-video", "pll-periph" }; +static const u8 de_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", + de_parents, de_table, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", + de_parents, de_table, + 0x10c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 tcon_table[] = { 0, 2, }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon", + tcon_parents, tcon_table, + 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + +static const char * const deinterlace_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 deinterlace_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace", + deinterlace_parents, deinterlace_table, + 0x11c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tve_clk2_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 tve_clk2_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", + tve_clk2_parents, tve_clk2_table, + 0x120, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2", + 0x120, 8, 1, BIT(15), 0); + +static const char * const tvd_parents[] = { "pll-video", "osc24M", + "pll-video-2x" }; +static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, + 0x124, 0, 4, 24, 3, BIT(31), 0); + +static const char * const csi_parents[] = { "pll-video", "osc24M" }; +static const u8 csi_table[] = { 0, 5, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, + 0x120, 0, 4, 8, 3, BIT(15), 0); + +/* + * TODO: BSP says the parent is pll-audio, however common sense and experience + * told us it should be pll-ve. pll-ve is totally not used in BSP code. + */ +static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); + +static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); + +static struct ccu_common *suniv_ccu_clks[] = { + &pll_cpu_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph_clk.common, + &cpu_clk.common, + &ahb_clk.common, + &apb_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_dram_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ve_clk.common, + &bus_lcd_clk.common, + &bus_deinterlace_clk.common, + &bus_csi_clk.common, + &bus_tve_clk.common, + &bus_tvd_clk.common, + &bus_de_be_clk.common, + &bus_de_fe_clk.common, + &bus_codec_clk.common, + &bus_spdif_clk.common, + &bus_ir_clk.common, + &bus_rsb_clk.common, + &bus_i2s0_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_pio_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &i2s_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_deinterlace_clk.common, + &dram_tvd_clk.common, + &dram_de_fe_clk.common, + &dram_de_be_clk.common, + &de_be_clk.common, + &de_fe_clk.common, + &tcon_clk.common, + &deinterlace_clk.common, + &tve_clk2_clk.common, + &tve_clk1_clk.common, + &tvd_clk.common, + &csi_clk.common, + &ve_clk.common, + &codec_clk.common, + &avs_clk.common, +}; + +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", + "pll-video", 1, 2, 0); + +static struct clk_hw_onecell_data suniv_hw_clks = { + .hws = { + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_CPU] = &cpu_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB] = &apb_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_TVD] = &bus_tvd_clk.common.hw, + [CLK_BUS_TVE] = &bus_tve_clk.common.hw, + [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, + [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_IR] = &bus_ir_clk.common.hw, + [CLK_BUS_RSB] = &bus_rsb_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_I2S] = &i2s_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, + [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, + [CLK_DE_BE] = &de_be_clk.common.hw, + [CLK_DE_FE] = &de_fe_clk.common.hw, + [CLK_TCON] = &tcon_clk.common.hw, + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, + [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw, + [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw, + [CLK_TVD] = &tvd_clk.common.hw, + [CLK_CSI] = &csi_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_CODEC] = &codec_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map suniv_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_LCD] = { 0x2c4, BIT(4) }, + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_TVD] = { 0x2c4, BIT(9) }, + [RST_BUS_TVE] = { 0x2c4, BIT(10) }, + [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, + [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_IR] = { 0x2d0, BIT(2) }, + [RST_BUS_RSB] = { 0x2d0, BIT(3) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2C0] = { 0x2d0, BIT(16) }, + [RST_BUS_I2C1] = { 0x2d0, BIT(17) }, + [RST_BUS_I2C2] = { 0x2d0, BIT(18) }, + [RST_BUS_UART0] = { 0x2d0, BIT(20) }, + [RST_BUS_UART1] = { 0x2d0, BIT(21) }, + [RST_BUS_UART2] = { 0x2d0, BIT(22) }, +}; + +static const struct sunxi_ccu_desc suniv_ccu_desc = { + .ccu_clks = suniv_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks), + + .hw_clks = &suniv_hw_clks, + + .resets = suniv_ccu_resets, + .num_resets = ARRAY_SIZE(suniv_ccu_resets), +}; + +static struct ccu_pll_nb suniv_pll_cpu_nb = { + .common = &pll_cpu_clk.common, + /* copy from pll_cpu_clk */ + .enable = BIT(31), + .lock = BIT(28), +}; + +static struct ccu_mux_nb suniv_cpu_nb = { + .common = &cpu_clk.common, + .cm = &cpu_clk.mux, + .delay_us = 1, /* > 8 clock cycles at 24 MHz */ + .bypass_index = 1, /* index of 24 MHz oscillator */ +}; + +static void __init suniv_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%pOF: Could not map the clock registers\n", node); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUNIV_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); + + sunxi_ccu_probe(node, reg, &suniv_ccu_desc); + + /* Gate then ungate PLL CPU after any rate changes */ + ccu_pll_notifier_register(&suniv_pll_cpu_nb); + + /* Reparent CPU during PLL CPU rate changes */ + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, + &suniv_cpu_nb); +} +CLK_OF_DECLARE(suniv_ccu, "allwinner,suniv-ccu", + suniv_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-suniv.h b/drivers/clk/sunxi-ng/ccu-suniv.h new file mode 100644 index 000000000000..9b9cd19ea5ee --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv.h @@ -0,0 +1,34 @@ +/* + * Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CCU_SUNIV_H_ +#define _CCU_SUNIV_H_ + +#include +#include + +#define CLK_PLL_CPU 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO 6 +#define CLK_PLL_VIDEO_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR0 9 +#define CLK_PLL_PERIPH 10 + +/* CPU clock is exported */ + +#define CLK_AHB 12 +#define CLK_APB 13 + +/* All bus gates, DRAM gates and mod clocks are exported */ + +#define CLK_NUMBER (CLK_AVS + 1) + +#endif /* _CCU_SUNIV_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu.h b/include/dt-bindings/clock/suniv-ccu.h new file mode 100644 index 000000000000..9c22d70b2cff --- /dev/null +++ b/include/dt-bindings/clock/suniv-ccu.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2018 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_CLK_SUNIV_H_ +#define _DT_BINDINGS_CLK_SUNIV_H_ + +#define CLK_CPU 11 + +#define CLK_BUS_MMC0 14 +#define CLK_BUS_MMC1 15 +#define CLK_BUS_DRAM 16 +#define CLK_BUS_SPI0 17 +#define CLK_BUS_SPI1 18 +#define CLK_BUS_OTG 19 +#define CLK_BUS_VE 20 +#define CLK_BUS_LCD 21 +#define CLK_BUS_DEINTERLACE 22 +#define CLK_BUS_CSI 23 +#define CLK_BUS_TVD 24 +#define CLK_BUS_TVE 25 +#define CLK_BUS_DE_BE 26 +#define CLK_BUS_DE_FE 27 +#define CLK_BUS_CODEC 28 +#define CLK_BUS_SPDIF 29 +#define CLK_BUS_IR 30 +#define CLK_BUS_RSB 31 +#define CLK_BUS_I2S0 32 +#define CLK_BUS_I2C0 33 +#define CLK_BUS_I2C1 34 +#define CLK_BUS_I2C2 35 +#define CLK_BUS_PIO 36 +#define CLK_BUS_UART0 37 +#define CLK_BUS_UART1 38 +#define CLK_BUS_UART2 39 + +#define CLK_MMC0 40 +#define CLK_MMC0_SAMPLE 41 +#define CLK_MMC0_OUTPUT 42 +#define CLK_MMC1 43 +#define CLK_MMC1_SAMPLE 44 +#define CLK_MMC1_OUTPUT 45 +#define CLK_I2S 46 +#define CLK_SPDIF 47 + +#define CLK_USB_PHY0 48 + +#define CLK_DRAM_VE 49 +#define CLK_DRAM_CSI 50 +#define CLK_DRAM_DEINTERLACE 51 +#define CLK_DRAM_TVD 52 +#define CLK_DRAM_DE_FE 53 +#define CLK_DRAM_DE_BE 54 + +#define CLK_DE_BE 55 +#define CLK_DE_FE 56 +#define CLK_TCON 57 +#define CLK_DEINTERLACE 58 +#define CLK_TVE2_CLK 59 +#define CLK_TVE1_CLK 60 +#define CLK_TVD 61 +#define CLK_CSI 62 +#define CLK_VE 63 +#define CLK_CODEC 64 +#define CLK_AVS 65 + +#endif diff --git a/include/dt-bindings/reset/suniv-ccu.h b/include/dt-bindings/reset/suniv-ccu.h new file mode 100644 index 000000000000..993f6b5381df --- /dev/null +++ b/include/dt-bindings/reset/suniv-ccu.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_RST_SUNIV_H_ +#define _DT_BINDINGS_RST_SUNIV_H_ + +#define RST_USB_PHY0 0 +#define RST_BUS_MMC0 1 +#define RST_BUS_MMC1 2 +#define RST_BUS_DRAM 3 +#define RST_BUS_SPI0 4 +#define RST_BUS_SPI1 5 +#define RST_BUS_OTG 6 +#define RST_BUS_VE 7 +#define RST_BUS_LCD 8 +#define RST_BUS_DEINTERLACE 9 +#define RST_BUS_CSI 10 +#define RST_BUS_TVD 11 +#define RST_BUS_TVE 12 +#define RST_BUS_DE_BE 13 +#define RST_BUS_DE_FE 14 +#define RST_BUS_CODEC 15 +#define RST_BUS_SPDIF 16 +#define RST_BUS_IR 17 +#define RST_BUS_RSB 18 +#define RST_BUS_I2S0 19 +#define RST_BUS_I2C0 20 +#define RST_BUS_I2C1 21 +#define RST_BUS_I2C2 22 +#define RST_BUS_UART0 23 +#define RST_BUS_UART1 24 +#define RST_BUS_UART2 25 + +#endif /* _DT_BINDINGS_RST_SUNIV_H_ */ From patchwork Fri Jan 19 23:17:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863856 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcGv4q4pz9sPk for ; Sat, 20 Jan 2018 10:19:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932836AbeASXTN (ORCPT ); Fri, 19 Jan 2018 18:19:13 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48447 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932749AbeASXS6 (ORCPT ); Fri, 19 Jan 2018 18:18:58 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 46A145606D; Fri, 19 Jan 2018 23:18:54 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 8/9] ARM: dts: suniv: add initial DTSI file for suniv and F1C100s Date: Sat, 20 Jan 2018 07:17:34 +0800 Message-Id: <20180119231735.61504-9-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As there's nothing special for it, add a dummy DTSI file for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 ++ arch/arm/boot/dts/suniv.dtsi | 157 +++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi create mode 100644 arch/arm/boot/dts/suniv.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..b877e0bf1823 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -972,6 +972,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 000000000000..f084bc8dd19b --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +#include "suniv.dtsi" diff --git a/arch/arm/boot/dts/suniv.dtsi b/arch/arm/boot/dts/suniv.dtsi new file mode 100644 index 000000000000..af1903237514 --- /dev/null +++ b/arch/arm/boot/dts/suniv.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + fake100M: clk-100M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "fake-100M"; + }; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pins_a: uart-pins-pe { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + }; +}; From patchwork Fri Jan 19 23:17:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 863857 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zNcH13048z9t1t for ; Sat, 20 Jan 2018 10:19:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932801AbeASXTK (ORCPT ); Fri, 19 Jan 2018 18:19:10 -0500 Received: from hermes.aosc.io ([199.195.250.187]:48477 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932780AbeASXTE (ORCPT ); Fri, 19 Jan 2018 18:19:04 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 4881156077; Fri, 19 Jan 2018 23:18:59 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 9/9] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Date: Sat, 20 Jan 2018 07:17:35 +0800 Message-Id: <20180119231735.61504-10-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts new file mode 100644 index 000000000000..11c891716acc --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +/ { + model = "Lichee Pi Nano"; + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s", + "allwinner,suniv"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +};