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[88.207.99.66]) by smtp.googlemail.com with ESMTPSA id y2sm12222717ejg.123.2021.05.19.04.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 04:03:20 -0700 (PDT) From: Robert Marko To: openwrt-devel@lists.openwrt.org Cc: Robert Marko Subject: [PATCH v2] mvebu: 5.10 fix DVFS caused random boot crashes Date: Wed, 19 May 2021 13:02:31 +0200 Message-Id: <20210519110230.1914575-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_120322_765353_289BDEAB X-CRM114-Status: GOOD ( 22.16 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: 5.10.37 and 5.4.119 introduced a lot of DVFS changes for Armada 37xx from 5.13 kernel. Unfortunately commit: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/cpufreq/armada-37xx-cpufreq.c?h=v5.10.37&id=a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:62f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org 5.10.37 and 5.4.119 introduced a lot of DVFS changes for Armada 37xx from 5.13 kernel. Unfortunately commit: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/cpufreq/armada-37xx-cpufreq.c?h=v5.10.37&id=a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc This patch actually corrects the things so that 1 or 1.2GHz models would actually get scaled to their native frequency. However, due to a AVS setting voltages too low this will cause random crashes on 1.2GHz models. So, until a new safe for everybody voltage is agreed on lets revert the patch. Fixes: d337731 ("kernel: bump 5.10 to 5.10.37") Signed-off-by: Robert Marko --- Changes in v2: * Update the commit message to make the reason clear ...rmada-37xx-Fix-setting-TBG-parent-fo.patch | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 target/linux/mvebu/patches-5.10/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch diff --git a/target/linux/mvebu/patches-5.10/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch b/target/linux/mvebu/patches-5.10/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch new file mode 100644 index 0000000000..65184df584 --- /dev/null +++ b/target/linux/mvebu/patches-5.10/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch @@ -0,0 +1,107 @@ +From 35639bac13927d1476398b740b11cbed0ee3ddb2 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 18 May 2021 13:24:30 +0200 +Subject: [PATCH] Revert "cpufreq: armada-37xx: Fix setting TBG parent for load + levels" + +This reverts commit a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc. + +This patch actually corrects the things so that 1 or 1.2GHz models would +actually get scaled to their native frequency. + +However, due to a AVS setting voltages too low this will cause random +crashes on 1.2GHz models. + +So, until a new safe for everybody voltage is agreed on +lets revert the patch. + +Signed-off-by: Robert Marko +--- + drivers/cpufreq/armada-37xx-cpufreq.c | 35 +++++++++------------------ + 1 file changed, 12 insertions(+), 23 deletions(-) + +--- a/drivers/cpufreq/armada-37xx-cpufreq.c ++++ b/drivers/cpufreq/armada-37xx-cpufreq.c +@@ -25,10 +25,6 @@ + + #include "cpufreq-dt.h" + +-/* Clk register set */ +-#define ARMADA_37XX_CLK_TBG_SEL 0 +-#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22 +- + /* Power management in North Bridge register set */ + #define ARMADA_37XX_NB_L0L1 0x18 + #define ARMADA_37XX_NB_L2L3 0x1C +@@ -126,15 +122,10 @@ static struct armada_37xx_dvfs *armada_3 + * will be configured then the DVFS will be enabled. + */ + static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, +- struct regmap *clk_base, u8 *divider) ++ struct clk *clk, u8 *divider) + { +- u32 cpu_tbg_sel; + int load_lvl; +- +- /* Determine to which TBG clock is CPU connected */ +- regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel); +- cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF; +- cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK; ++ struct clk *parent; + + for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) { + unsigned int reg, mask, val, offset = 0; +@@ -153,11 +144,6 @@ static void __init armada37xx_cpufreq_dv + mask = (ARMADA_37XX_NB_CLK_SEL_MASK + << ARMADA_37XX_NB_CLK_SEL_OFF); + +- /* Set TBG index, for all levels we use the same TBG */ +- val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF; +- mask = (ARMADA_37XX_NB_TBG_SEL_MASK +- << ARMADA_37XX_NB_TBG_SEL_OFF); +- + /* + * Set cpu divider based on the pre-computed array in + * order to have balanced step. +@@ -176,6 +162,14 @@ static void __init armada37xx_cpufreq_dv + + regmap_update_bits(base, reg, mask, val); + } ++ ++ /* ++ * Set cpu clock source, for all the level we keep the same ++ * clock source that the one already configured. For this one ++ * we need to use the clock framework ++ */ ++ parent = clk_get_parent(clk); ++ clk_set_parent(clk, parent); + } + + /* +@@ -401,16 +395,11 @@ static int __init armada37xx_cpufreq_dri + struct platform_device *pdev; + unsigned long freq; + unsigned int cur_frequency, base_frequency; +- struct regmap *nb_clk_base, *nb_pm_base, *avs_base; ++ struct regmap *nb_pm_base, *avs_base; + struct device *cpu_dev; + int load_lvl, ret; + struct clk *clk, *parent; + +- nb_clk_base = +- syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb"); +- if (IS_ERR(nb_clk_base)) +- return -ENODEV; +- + nb_pm_base = + syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); + +@@ -487,7 +476,7 @@ static int __init armada37xx_cpufreq_dri + armada37xx_cpufreq_avs_configure(avs_base, dvfs); + armada37xx_cpufreq_avs_setup(avs_base, dvfs); + +- armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider); ++ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); + clk_put(clk); + + for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;