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(localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 3260AC0412; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE Date: Mon, 17 May 2021 06:15:16 -0700 Message-Id: <20210517131527.3053833-2-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Add TARGET_READ_MEMSET_VALUE and TARGET_GEN_MEMSET_VALUE to support target instructions to duplicate QImode value to TImode/OImode/XImode value for memmset. PR middle-end/90773 * builtins.c (builtin_memset_read_str): Call targetm.read_memset_value. (builtin_memset_gen_str): Call targetm.gen_memset_value. * target.def (read_memset_value): New hook. (gen_memset_value): Likewise. * targhooks.c: Inclue "builtins.h". (default_read_memset_value): New function. (default_gen_memset_value): Likewise. * targhooks.h (default_read_memset_value): New prototype. (default_gen_memset_value): Likewise. * doc/tm.texi.in: Add TARGET_READ_MEMSET_VALUE and TARGET_GEN_MEMSET_VALUE hooks. * doc/tm.texi: Regenerated. --- gcc/builtins.c | 47 ++++---------------------------------- gcc/doc/tm.texi | 16 +++++++++++++ gcc/doc/tm.texi.in | 4 ++++ gcc/target.def | 20 +++++++++++++++++ gcc/targhooks.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ gcc/targhooks.h | 4 ++++ 6 files changed, 104 insertions(+), 43 deletions(-) diff --git a/gcc/builtins.c b/gcc/builtins.c index e1b284846b1..f78a36478ef 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -6584,24 +6584,11 @@ expand_builtin_strncpy (tree exp, rtx target) previous iteration. */ rtx -builtin_memset_read_str (void *data, void *prevp, +builtin_memset_read_str (void *data, void *prev, HOST_WIDE_INT offset ATTRIBUTE_UNUSED, scalar_int_mode mode) { - by_pieces_prev *prev = (by_pieces_prev *) prevp; - if (prev != nullptr && prev->data != nullptr) - { - /* Use the previous data in the same mode. */ - if (prev->mode == mode) - return prev->data; - } - - const char *c = (const char *) data; - char *p = XALLOCAVEC (char, GET_MODE_SIZE (mode)); - - memset (p, *c, GET_MODE_SIZE (mode)); - - return c_readstr (p, mode); + return targetm.read_memset_value ((const char *) data, prev, mode); } /* Callback routine for store_by_pieces. Return the RTL of a register @@ -6611,37 +6598,11 @@ builtin_memset_read_str (void *data, void *prevp, nullptr, it has the RTL info from the previous iteration. */ static rtx -builtin_memset_gen_str (void *data, void *prevp, +builtin_memset_gen_str (void *data, void *prev, HOST_WIDE_INT offset ATTRIBUTE_UNUSED, scalar_int_mode mode) { - rtx target, coeff; - size_t size; - char *p; - - by_pieces_prev *prev = (by_pieces_prev *) prevp; - if (prev != nullptr && prev->data != nullptr) - { - /* Use the previous data in the same mode. */ - if (prev->mode == mode) - return prev->data; - - target = simplify_gen_subreg (mode, prev->data, prev->mode, 0); - if (target != nullptr) - return target; - } - - size = GET_MODE_SIZE (mode); - if (size == 1) - return (rtx) data; - - p = XALLOCAVEC (char, size); - memset (p, 1, size); - coeff = c_readstr (p, mode); - - target = convert_to_mode (mode, (rtx) data, 1); - target = expand_mult (mode, target, coeff, NULL_RTX, 1); - return force_reg (mode, target); + return targetm.gen_memset_value ((rtx) data, prev, mode); } /* Expand expression EXP, which is a call to the memset builtin. Return diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 85ea9395560..51385044e76 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11868,6 +11868,22 @@ This function prepares to emit a conditional comparison within a sequence @var{bit_code} is @code{AND} or @code{IOR}, which is the op on the compares. @end deftypefn +@deftypefn {Target Hook} rtx TARGET_READ_MEMSET_VALUE (const char *@var{c}, void *@var{prev}, scalar_int_mode @var{mode}) +This function returns the RTL of a constant integer corresponding to +target reading @code{GET_MODE_SIZE (@var{mode})} bytes from the stringn +constant @var{str}. If @var{prev} is not @samp{nullptr}, it contains +the RTL information from the previous interation. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_MEMSET_VALUE (rtx @var{data}, void *@var{prev}, scalar_int_mode @var{mode}) +This function returns the RTL of a register containing +@code{GET_MODE_SIZE (@var{mode})} consecutive copies of the unsigned +char value given in the RTL register @var{data}. For example, if +@var{mode} is 4 bytes wide, return the RTL for 0x01010101*@var{data}. +If @var{PREV} is not @samp{nullptr}, it is the RTL information from +the previous iteration. +@end deftypefn + @deftypefn {Target Hook} unsigned TARGET_LOOP_UNROLL_ADJUST (unsigned @var{nunroll}, class loop *@var{loop}) This target hook returns a new value for the number of times @var{loop} should be unrolled. The parameter @var{nunroll} is the number of times diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index d8e3de14af1..8d4c3949fbf 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -7956,6 +7956,10 @@ lists. @hook TARGET_GEN_CCMP_NEXT +@hook TARGET_READ_MEMSET_VALUE + +@hook TARGET_GEN_MEMSET_VALUE + @hook TARGET_LOOP_UNROLL_ADJUST @defmac POWI_MAX_MULTS diff --git a/gcc/target.def b/gcc/target.def index bbaf6b4f3a0..c9aca40fa88 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -2694,6 +2694,26 @@ DEFHOOK rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code), NULL) +DEFHOOK +(read_memset_value, + "This function returns the RTL of a constant integer corresponding to\n\ +target reading @code{GET_MODE_SIZE (@var{mode})} bytes from the stringn\n\ +constant @var{str}. If @var{prev} is not @samp{nullptr}, it contains\n\ +the RTL information from the previous interation.", + rtx, (const char *c, void *prev, scalar_int_mode mode), + default_read_memset_value) + +DEFHOOK +(gen_memset_value, + "This function returns the RTL of a register containing\n\ +@code{GET_MODE_SIZE (@var{mode})} consecutive copies of the unsigned\n\ +char value given in the RTL register @var{data}. For example, if\n\ +@var{mode} is 4 bytes wide, return the RTL for 0x01010101*@var{data}.\n\ +If @var{PREV} is not @samp{nullptr}, it is the RTL information from\n\ +the previous iteration.", + rtx, (rtx data, void *prev, scalar_int_mode mode), + default_gen_memset_value) + /* Return a new value for loop unroll size. */ DEFHOOK (loop_unroll_adjust, diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 1947ef26fd6..b55e6ec6756 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -90,6 +90,7 @@ along with GCC; see the file COPYING3. If not see #include "attribs.h" #include "asan.h" #include "emit-rtl.h" +#include "builtins.h" bool default_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, @@ -2627,4 +2628,59 @@ default_memtag_untagged_pointer (rtx tagged_pointer, rtx target) return untagged_base; } +/* Default implementation of TARGET_READ_MEMSET_VALUE. */ + +rtx +default_read_memset_value (const char *c, void *prevp, + scalar_int_mode mode) +{ + by_pieces_prev *prev = (by_pieces_prev *) prevp; + if (prev != nullptr && prev->data != nullptr) + { + /* Use the previous data in the same mode. */ + if (prev->mode == mode) + return prev->data; + } + + char *p = XALLOCAVEC (char, GET_MODE_SIZE (mode)); + + memset (p, *c, GET_MODE_SIZE (mode)); + + return c_readstr (p, mode); +} + +/* Default implementation of TARGET_GEN_MEMSET_VALUE. */ + +rtx +default_gen_memset_value (rtx data, void *prevp, scalar_int_mode mode) +{ + rtx target, coeff; + size_t size; + char *p; + + by_pieces_prev *prev = (by_pieces_prev *) prevp; + if (prev != nullptr && prev->data != nullptr) + { + /* Use the previous data in the same mode. */ + if (prev->mode == mode) + return prev->data; + + target = simplify_gen_subreg (mode, prev->data, prev->mode, 0); + if (target != nullptr) + return target; + } + + size = GET_MODE_SIZE (mode); + if (size == 1) + return data; + + p = XALLOCAVEC (char, size); + memset (p, 1, size); + coeff = c_readstr (p, mode); + + target = convert_to_mode (mode, data, 1); + target = expand_mult (mode, target, coeff, NULL_RTX, 1); + return force_reg (mode, target); +} + #include "gt-targhooks.h" diff --git a/gcc/targhooks.h b/gcc/targhooks.h index b537038c0aa..3c00927e196 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -300,4 +300,8 @@ extern rtx default_memtag_set_tag (rtx, rtx, rtx); extern rtx default_memtag_extract_tag (rtx, rtx); extern rtx default_memtag_untagged_pointer (rtx, rtx); +extern rtx default_read_memset_value (const char *, void *, + scalar_int_mode); +extern rtx default_gen_memset_value (rtx, void *, scalar_int_mode); + #endif /* GCC_TARGHOOKS_H */ From patchwork Mon May 17 13:15:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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(localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 3D74AC0445; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 02/12] x86: Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE Date: Mon, 17 May 2021 06:15:17 -0700 Message-Id: <20210517131527.3053833-3-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3034.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, LOTS_OF_MONEY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" 1. Make ix86_expand_vector_init_duplicate global to duplicate QImode value to TImode/OImode/XImode. 2. Make ix86_minimum_incoming_stack_boundary global and add an argument to ignore stack_alignment_estimated. 3. Define SCRATCH_SSE_REG as a scratch register for ix86_gen_memset_value. 4. Add TARGET_READ_MEMSET_VALUE and TARGET_GEN_MEMSET_VALUE to support target instructions to duplicate QImode value to TImode/OImode/XImode value for memmset. gcc/ PR middle-end/90773 * config/i386/i386-expand.c (ix86_expand_vector_init_duplicate): Make it global. * config/i386/i386-protos.h (ix86_minimum_incoming_stack_boundary): New. (ix86_expand_vector_init_duplicate): Likewise. * config/i386/i386.c (ix86_minimum_incoming_stack_boundary): Add an argument to ignore stack_alignment_estimated. It is passed as false by default. Make it global. (ix86_gen_memset_value_from_prev): New function. (ix86_gen_memset_value): Likewise. (ix86_read_memset_value): Likewise. (TARGET_GEN_MEMSET_VALUE): New. (TARGET_READ_MEMSET_VALUE): Likewise. * config/i386/i386.h (SCRATCH_SSE_REG): New. gcc/testsuite/ PR middle-end/90773 * gcc.target/i386/pr90773-15.c: New test. * gcc.target/i386/pr90773-16.c: Likewise. * gcc.target/i386/pr90773-17.c: Likewise. * gcc.target/i386/pr90773-18.c: Likewise. * gcc.target/i386/pr90773-19.c: Likewise. --- gcc/config/i386/i386-expand.c | 2 +- gcc/config/i386/i386-protos.h | 5 + gcc/config/i386/i386.c | 268 ++++++++++++++++++++- gcc/config/i386/i386.h | 4 + gcc/testsuite/gcc.target/i386/pr90773-15.c | 14 ++ gcc/testsuite/gcc.target/i386/pr90773-16.c | 14 ++ gcc/testsuite/gcc.target/i386/pr90773-17.c | 14 ++ gcc/testsuite/gcc.target/i386/pr90773-18.c | 15 ++ gcc/testsuite/gcc.target/i386/pr90773-19.c | 14 ++ 9 files changed, 345 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-15.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-16.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-17.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-18.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-19.c diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 0fa8d45a684..485825b3c15 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -13648,7 +13648,7 @@ static bool expand_vec_perm_1 (struct expand_vec_perm_d *d); /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector with all elements equal to VAR. Return true if successful. */ -static bool +bool ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, rtx target, rtx val) { diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 7782cf1163f..c4896c2da74 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -50,6 +50,9 @@ extern void ix86_reset_previous_fndecl (void); extern bool ix86_using_red_zone (void); +extern unsigned int ix86_minimum_incoming_stack_boundary (bool, + bool = false); + extern unsigned int ix86_regmode_natural_size (machine_mode); #ifdef RTX_CODE extern int standard_80387_constant_p (rtx); @@ -257,6 +260,8 @@ extern void ix86_expand_mul_widen_hilo (rtx, rtx, rtx, bool, bool); extern void ix86_expand_sse2_mulv4si3 (rtx, rtx, rtx); extern void ix86_expand_sse2_mulvxdi3 (rtx, rtx, rtx); extern void ix86_expand_sse2_abs (rtx, rtx); +extern bool ix86_expand_vector_init_duplicate (bool, machine_mode, rtx, + rtx); /* In i386-c.c */ extern void ix86_target_macros (void); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 6a1f5746089..8b9b2346478 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -415,7 +415,6 @@ static unsigned int split_stack_prologue_scratch_regno (void); static bool i386_asm_output_addr_const_extra (FILE *, rtx); static bool ix86_can_inline_p (tree, tree); -static unsigned int ix86_minimum_incoming_stack_boundary (bool); /* Whether -mtune= or -march= were specified */ @@ -7232,8 +7231,9 @@ find_drap_reg (void) /* Return minimum incoming stack alignment. */ -static unsigned int -ix86_minimum_incoming_stack_boundary (bool sibcall) +unsigned int +ix86_minimum_incoming_stack_boundary (bool sibcall, + bool ignore_estimated) { unsigned int incoming_stack_boundary; @@ -7248,7 +7248,8 @@ ix86_minimum_incoming_stack_boundary (bool sibcall) estimated stack alignment is 128bit. */ else if (!sibcall && ix86_force_align_arg_pointer - && crtl->stack_alignment_estimated == 128) + && (ignore_estimated + || crtl->stack_alignment_estimated == 128)) incoming_stack_boundary = MIN_STACK_BOUNDARY; else incoming_stack_boundary = ix86_default_incoming_stack_boundary; @@ -23052,6 +23053,259 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode, } } +/* Return the RTL for memset in MODE from PREV. */ + +static rtx +ix86_gen_memset_value_from_prev (by_pieces_prev *prevp, + scalar_int_mode mode) +{ + rtx prev = prevp->data; + + /* Use the previous data in the same mode. */ + if (prevp->mode == mode) + return prev; + + machine_mode prev_mode = prevp->mode; + size_t size = GET_MODE_SIZE (prev_mode); + + /* NB: Skip if the previous value is 1 byte or less. CONST_WIDE_INT + is in VOIDmode whose size is 0. */ + if (size <= 1) + return nullptr; + + rtx reg, reg_ti; + switch (size) + { + default: + gcc_unreachable (); + + case 2: + case 4: + return simplify_gen_subreg (mode, prev, prev_mode, 0); + + case 8: + /* In 64-bit mode, use SUBREG since word size is 8 bytes. */ + if (TARGET_64BIT) + return simplify_gen_subreg (mode, prev, prev_mode, 0); + + switch (GET_MODE_SIZE (mode)) + { + default: + gcc_unreachable (); + case 2: + case 4: +do_hi_si_mode: + /* In 32-bit mode, Extract the value from an 8-byte + register into an integer register first. */ + reg = gen_reg_rtx (SImode); + emit_move_insn (reg, + simplify_gen_subreg (SImode, prev, + prev_mode, 0)); + return simplify_gen_subreg (mode, reg, SImode, 0); + } + break; + + case 16: + switch (GET_MODE_SIZE (mode)) + { + default: + gcc_unreachable (); + case 2: + case 4: + /* Extract the value from a 16-byte vector register into + an integer register first. */ + goto do_hi_si_mode; + case 8: + return simplify_gen_subreg (mode, prev, prev_mode, 0); + case 16: + return prev; + } + break; + + case 32: + switch (GET_MODE_SIZE (mode)) + { + default: + gcc_unreachable (); + case 2: +do_himode: + /* Extract the value from a 32-byte vector register into + a 16-byte vector register first. */ + reg_ti = gen_reg_rtx (TImode); + emit_move_insn (reg_ti, + simplify_gen_subreg (TImode, prev, + prev_mode, 0)); + /* Then extract the value from a 16-byte vector register + into an integer register. */ + reg = gen_reg_rtx (SImode); + emit_move_insn (reg, + simplify_gen_subreg (SImode, reg_ti, + TImode, 0)); + return simplify_gen_subreg (mode, reg, SImode, 0); + + case 4: + case 8: +do_si_di_mode: + /* Extract the value from a 32-byte vector register into + a 16-byte vector register first. */ + reg_ti = gen_reg_rtx (TImode); + emit_move_insn (reg_ti, + simplify_gen_subreg (TImode, prev, + prev_mode, 0)); + /* Generate 4/8-byte SSE -> INT move instruction. */ + reg = gen_reg_rtx (mode); + emit_move_insn (reg, + simplify_gen_subreg (mode, reg_ti, + TImode, 0)); + return reg; + case 16: + return simplify_gen_subreg (mode, prev, prev_mode, 0); + case 32: + return prev; + } + + case 64: + switch (GET_MODE_SIZE (mode)) + { + default: + gcc_unreachable (); + case 2: + /* Extract the value from a 64-byte vector register into + a 16-byte vector register first. */ + goto do_himode; + case 4: + case 8: + /* Extract the value from a 64-byte vector register into + a 16-byte vector register first. */ + goto do_si_di_mode; + case 16: + case 32: + return simplify_gen_subreg (mode, prev, prev_mode, 0); + case 64: + return prev; + } + } + + return nullptr; +} + +/* Implement the TARGET_GEN_MEMSET_VALUE hook. */ + +static rtx +ix86_gen_memset_value (rtx data, void *prevp, scalar_int_mode mode) +{ + /* Don't use the previous value if size is 1. */ + if (GET_MODE_SIZE (mode) == 1) + return data; + + by_pieces_prev *prev = (by_pieces_prev *) prevp; + if (prev != nullptr && prev->data != nullptr) + { + rtx value = ix86_gen_memset_value_from_prev (prev, mode); + if (value) + return value; + } + + /* Use default_gen_memset_value for vector store won't be used. */ + if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode)) + return default_gen_memset_value (data, prevp, mode); + + rtx one, target; + scalar_mode one_mode; + + unsigned int incoming_stack_boundary + = ix86_minimum_incoming_stack_boundary (false, true); + + switch (GET_MODE_SIZE (mode)) + { + default: + gcc_unreachable (); + + case 64: + if (!TARGET_AVX512BW) + { + rtx tmp; + /* NB: Don't increase stack alignment requirement by using a + scratch SSE register. */ + if (GET_MODE_ALIGNMENT (V32QImode) > incoming_stack_boundary) + tmp = gen_rtx_REG (V32QImode, SCRATCH_SSE_REG); + else + tmp = gen_reg_rtx (V32QImode); + if (!ix86_expand_vector_init_duplicate (false, V32QImode, + tmp, data)) + gcc_unreachable (); + target = gen_rtx_VEC_CONCAT (V64QImode, tmp, tmp); + if (REGNO (tmp) == SCRATCH_SSE_REG) + { + tmp = gen_rtx_REG (V64QImode, SCRATCH_SSE_REG); + emit_move_insn (tmp, target); + return gen_rtx_REG (mode, SCRATCH_SSE_REG); + } + else + return convert_to_mode (mode, target, 1); + } + /* FALLTHRU */ + case 16: + case 32: + one_mode = QImode; + one = data; + break; + } + + unsigned int nunits = GET_MODE_SIZE (mode) / GET_MODE_SIZE (one_mode); + machine_mode vector_mode; + if (!mode_for_vector (one_mode, nunits).exists (&vector_mode)) + gcc_unreachable (); + + /* NB: Don't increase stack alignment requirement by using a scratch + SSE register. */ + if (GET_MODE_ALIGNMENT (vector_mode) > incoming_stack_boundary) + target = gen_rtx_REG (vector_mode, SCRATCH_SSE_REG); + else + target = gen_reg_rtx (vector_mode); + if (!ix86_expand_vector_init_duplicate (false, vector_mode, target, + one)) + gcc_unreachable (); + + if (REGNO (target) == SCRATCH_SSE_REG) + return gen_rtx_REG (mode, SCRATCH_SSE_REG); + else + return convert_to_mode (mode, target, 1); +} + +/* Implement the TARGET_READ_MEMSET_VALUE hook. */ + +static rtx +ix86_read_memset_value (const char *str, void *prevp, + scalar_int_mode mode) +{ + rtx value; + + by_pieces_prev *prev = (by_pieces_prev *) prevp; + if (prev != nullptr && prev->data != nullptr) + { + /* Don't use the previous value if size is 1. */ + if (GET_MODE_SIZE (mode) == 1) + return default_read_memset_value (str, nullptr, mode); + + value = ix86_gen_memset_value_from_prev (prev, mode); + if (value) + return value; + + return default_read_memset_value (str, nullptr, mode); + } + + /* Use default_gen_memset_value if vector store can't be used. + NB: Need AVX2 for fast vector duplication and gen_reg_rtx. */ + if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode) + || !TARGET_AVX2 + || !reg_rtx_no) + return default_read_memset_value (str, nullptr, mode); + + value = default_read_memset_value (str, nullptr, QImode); + return ix86_gen_memset_value (value, nullptr, mode); +} + /* Address space support. This is not "far pointers" in the 16-bit sense, but an easy way @@ -23953,6 +24207,12 @@ static bool ix86_libc_has_fast_function (int fcode ATTRIBUTE_UNUSED) #undef TARGET_LIBC_HAS_FAST_FUNCTION #define TARGET_LIBC_HAS_FAST_FUNCTION ix86_libc_has_fast_function +#undef TARGET_GEN_MEMSET_VALUE +#define TARGET_GEN_MEMSET_VALUE ix86_gen_memset_value + +#undef TARGET_READ_MEMSET_VALUE +#define TARGET_READ_MEMSET_VALUE ix86_read_memset_value + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::ix86_run_selftests diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 97d6f3863cb..45d86802c51 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1131,6 +1131,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define FIRST_MASK_REG MASK0_REG #define LAST_MASK_REG MASK7_REG +/* A scratch vector reg. */ +#define SCRATCH_SSE_REG \ + (TARGET_64BIT ? LAST_REX_SSE_REG : LAST_SSE_REG) + /* Override this in other tm.h files to cope with various OS lossage requiring a frame pointer. */ #ifndef SUBTARGET_FRAME_POINTER_REQUIRED diff --git a/gcc/testsuite/gcc.target/i386/pr90773-15.c b/gcc/testsuite/gcc.target/i386/pr90773-15.c new file mode 100644 index 00000000000..c0a96fed892 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-15.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern char *dst; + +void +foo (int c) +{ + __builtin_memset (dst, c, 17); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[\\t \]+%edi, %xmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+%dil, 16\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-16.c b/gcc/testsuite/gcc.target/i386/pr90773-16.c new file mode 100644 index 00000000000..d2d1ec6141c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-16.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 17); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+\\\$-1, 16\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-17.c b/gcc/testsuite/gcc.target/i386/pr90773-17.c new file mode 100644 index 00000000000..6c8da7d24ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-17.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 12, 19); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovd\[\\t \]+%xmm\[0-9\]+, 15\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-18.c b/gcc/testsuite/gcc.target/i386/pr90773-18.c new file mode 100644 index 00000000000..b0687abbe01 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-18.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 12, 9); +} + +/* { dg-final { scan-assembler-times "movabsq\[\\t \]+\\\$868082074056920076, %r" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "movl\[\\t \]+\\\$202116108, \\(%\[\^,\]+\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movl\[\\t \]+\\\$202116108, 4\\(%\[\^,\]+\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+\\\$12, 8\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-19.c b/gcc/testsuite/gcc.target/i386/pr90773-19.c new file mode 100644 index 00000000000..8aa5540bacc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-19.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 12, 9); +} + +/* { dg-final { scan-assembler-times "movabsq\[\\t \]+\\\$868082074056920076, %r" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "movl\[\\t \]+\\\$202116108, \\(%\[\^,\]+\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movl\[\\t \]+\\\$202116108, 4\\(%\[\^,\]+\\)" 1 { target ia32 } } } */ From patchwork Mon May 17 13:15:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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(localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 489E1C047F; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 03/12] x86: Avoid stack realignment when copying data Date: Mon, 17 May 2021 06:15:18 -0700 Message-Id: <20210517131527.3053833-4-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" To avoid stack realignment, use SCRATCH_SSE_REG to copy data from one memory location to another. gcc/ * config/i386/i386-expand.c (ix86_expand_vector_move): Use SCRATCH_SSE_REG to copy data from one memory location to another. gcc/testsuite/ * gcc.target/i386/eh_return-1.c: New test. --- gcc/config/i386/i386-expand.c | 16 ++++++++++++- gcc/testsuite/gcc.target/i386/eh_return-1.c | 26 +++++++++++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/eh_return-1.c diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 485825b3c15..f799678b273 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -431,7 +431,21 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[]) && !register_operand (op0, mode) && !register_operand (op1, mode)) { - emit_move_insn (op0, force_reg (GET_MODE (op0), op1)); + rtx tmp; + mode = GET_MODE (op0); + if (TARGET_SSE + && (GET_MODE_ALIGNMENT (mode) + > ix86_minimum_incoming_stack_boundary (false, true))) + { + /* NB: Don't increase stack alignment requirement by using + a scratch SSE register to copy data from one memory + location to another since it doesn't require a spill. */ + tmp = gen_rtx_REG (mode, SCRATCH_SSE_REG); + emit_move_insn (tmp, op1); + } + else + tmp = force_reg (mode, op1); + emit_move_insn (op0, tmp); return; } diff --git a/gcc/testsuite/gcc.target/i386/eh_return-1.c b/gcc/testsuite/gcc.target/i386/eh_return-1.c new file mode 100644 index 00000000000..671ba635e88 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/eh_return-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=haswell -mno-avx512f" } */ + +struct _Unwind_Context +{ + void *ra; + char array[48]; +}; + +extern long uw_install_context_1 (struct _Unwind_Context *); + +void +_Unwind_RaiseException (void) +{ + struct _Unwind_Context this_context, cur_context; + long offset = uw_install_context_1 (&this_context); + __builtin_memcpy (&this_context, &cur_context, + sizeof (struct _Unwind_Context)); + void *handler = __builtin_frob_return_addr ((&cur_context)->ra); + uw_install_context_1 (&cur_context); + __builtin_eh_return (offset, handler); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ From patchwork Mon May 17 13:15:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=jIaT5WfS; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKPl50TCz9sRf for ; Mon, 17 May 2021 23:15:39 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AB5A93891C06; Mon, 17 May 2021 13:15:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AB5A93891C06 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257336; bh=a7/fUNtEkB2R8fGEAJVPZbi/V1ArZQuLkf2f3KYz3qU=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=jIaT5WfSVP+SCnIc77v3+F7G/yo1rHqqpnkcqyf+uKjd+xsVz20EnsssMxsyT5411 OOShcmN0qAB/mpALM35Ck6Tpyeb/Z1wL45/gS/JbdJs2ER9qpJJkWRSVNpiL3ZsKwm 3mvkes4n9qbhW6YIT0Qlu9jPr+yhbyaOCbb+WfFU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id 3214E3835403 for ; Mon, 17 May 2021 13:15:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3214E3835403 Received: by mail-pj1-x1029.google.com with SMTP id g24so3650373pji.4 for ; Mon, 17 May 2021 06:15:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a7/fUNtEkB2R8fGEAJVPZbi/V1ArZQuLkf2f3KYz3qU=; b=Q1Y6+GxoMe/56DtWU7gA3JDD1QnkOWA+7byZ72GVAyZq6X+VslEApBoPgL/o4QwCfB GRzQRcOORADk2ecJJGtIEX2rVNrHNErzeOZCQoUC0fKYL6KedTW494gmhC9JyC0hF6vD Tp4ilIpwAG5A4rbbFDX6Y6Gxcslm0m25tCkmOB2GSM3bP324jcNc9NNgzQm/CU5wmF+N 4IdICL9AVSXfFETMX+y529W9PKWHcs3jKCOjypdv+tfr39fOfXEoG702s+7x9iMYRUuW mpzEs4fvo0Q7HSvpht8bfb9QS57SqruN2U52iX50UbYTkGlUzawDDmnucr4tG+OZAhCK UQIw== X-Gm-Message-State: AOAM533YMHu3qynHaAXG5dUtXycc7/HEUR5nvSeZZkM77BdOMcrQKbjv bsa04N/CdAIrOSPnzzB0DZk= X-Google-Smtp-Source: ABdhPJyNlqJf56Go6m6xolK4pGS8/j8+9vcaYPoY1FD9i/WqLK2ktMRCI4cG1GkVv0XZBgFsfrSluQ== X-Received: by 2002:a17:90a:4a92:: with SMTP id f18mr19734037pjh.49.1621257329197; Mon, 17 May 2021 06:15:29 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id c16sm10273159pgl.79.2021.05.17.06.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:28 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 53C3DC04C2; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 04/12] Remove MAX_BITSIZE_MODE_ANY_INT Date: Mon, 17 May 2021 06:15:19 -0700 Message-Id: <20210517131527.3053833-5-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" It is only defined for i386 and everyone uses the default: #define MAX_BITSIZE_MODE_ANY_INT (64*BITS_PER_UNIT) Whatever problems we had before, they have been fixed now. * config/i386/i386-modes.def (MAX_BITSIZE_MODE_ANY_INT): Removed. --- gcc/config/i386/i386-modes.def | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index dbddfd8e48f..4e7014be034 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -107,19 +107,10 @@ INT_MODE (XI, 64); PARTIAL_INT_MODE (HI, 16, P2QI); PARTIAL_INT_MODE (SI, 32, P2HI); -/* Mode used for signed overflow checking of TImode. As - MAX_BITSIZE_MODE_ANY_INT is only 160, wide-int.h reserves only that - rounded up to multiple of HOST_BITS_PER_WIDE_INT bits in wide_int etc., - so OImode is too large. For the overflow checking we actually need - just 1 or 2 bits beyond TImode precision. Use 160 bits to have - a multiple of 32. */ +/* Mode used for signed overflow checking of TImode. For the overflow + checking we actually need just 1 or 2 bits beyond TImode precision. + Use 160 bits to have a multiple of 32. */ PARTIAL_INT_MODE (OI, 160, POI); -/* Keep the OI and XI modes from confusing the compiler into thinking - that these modes could actually be used for computation. They are - only holders for vectors during data movement. Include POImode precision - though. */ -#define MAX_BITSIZE_MODE_ANY_INT (160) - /* The symbol Pmode stands for one of the above machine modes (usually SImode). The tm.h file specifies which one. It is not a distinct mode. */ From patchwork Mon May 17 13:15:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=nr1nT7Ht; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQV3fj7z9sSs for ; Mon, 17 May 2021 23:16:18 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 216E43892010; Mon, 17 May 2021 13:15:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 216E43892010 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257348; bh=cDri4DGJvMlZga1jqGqiaejcMnQOxgWnh9vsa9gvdsA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=nr1nT7HtFhlwb+EGj4fRUf7zSNN0JfQenYGBouwwk948ZYzoy5i7c+rWj+fJ6vHr6 5y92R4rspVlnZKymSnltoEJtd+kLwFYcm9/qSxPcHRnHfm+iTNUi88OnBpic9Afza+ nFTDGJ0kgjNqSYIVQ9+F9sUTF7Vr/4HhBM2kyN+k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by sourceware.org (Postfix) with ESMTPS id 9E7223833021 for ; Mon, 17 May 2021 13:15:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 9E7223833021 Received: by mail-pj1-x102f.google.com with SMTP id n6-20020a17090ac686b029015d2f7aeea8so4552822pjt.1 for ; Mon, 17 May 2021 06:15:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cDri4DGJvMlZga1jqGqiaejcMnQOxgWnh9vsa9gvdsA=; b=F8pNHJBOvE9i2X9Wak7HjbZcVPHEIzvV89dzzVp6NaB04daFZjSPrjzrbZiMxwbBgP acOHH/eQ+cWbn6j71fNGEvlGm9v4zrFuAooqkttSYXYdwPqegoRmd/S6Kc67/BSuiWsM qRH0IGCyKgc4cfACi73x1nIV3qxyNjLFm6jQsXljJ3sMdnZNiSB17pB4z0Nc8/W16Njr Jbi6B5Ecpqxf1CcvMZ39ax9Q9J1Dz5IThSOnL7n3WSmoXmkgxxLbfuuuyJz4EW7YL+Su PeDiCfbAF7JaU5Or7niKwQGRgJKmHQImw5UlqoeEjhSEZyVdE27mXlG6pGGEPw1OWrZt 5bog== X-Gm-Message-State: AOAM5313wj5fr8myzfi/iSIZFY8UGIx/SqDq3Bqz12nbydwY9//Y4Rmb KrKm7pQT1tPE8FjudQ++2Jg= X-Google-Smtp-Source: ABdhPJz/GoX9nJAzPP555xKFgal53EMaOu2xBU+GVEwWAQ/87N4gPb9Uw8R1L+HrqnoSloiYVxwL+w== X-Received: by 2002:a17:90a:8b12:: with SMTP id y18mr65230658pjn.153.1621257332745; Mon, 17 May 2021 06:15:32 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id 5sm7101431pjo.17.2021.05.17.06.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:31 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 55682C04D6; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 05/12] x86: Update piecewise move and store Date: Mon, 17 May 2021 06:15:20 -0700 Message-Id: <20210517131527.3053833-6-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" We can use TImode/OImode/XImode integers for piecewise move and store. When vector register is used for piecewise move and store, we don't increase stack_alignment_needed since vector register spill isn't required for piecewise move and store. Since stack_realign_needed is set to true by checking stack_alignment_estimated set by pseudo vector register usage, we also need to check stack_realign_needed to eliminate frame pointer. gcc/ * config/i386/i386.c (ix86_finalize_stack_frame_flags): Also check stack_realign_needed for stack realignment. (ix86_legitimate_constant_p): Always allow CONST_WIDE_INT smaller than the largest integer supported by vector register. * config/i386/i386.h (MOVE_MAX): Set to 64. (MOVE_MAX_PIECES): Set to bytes of the largest integer supported by vector register. (STORE_MAX_PIECES): New. gcc/testsuite/ * gcc.target/i386/pr90773-1.c: Adjust to expect movq for 32-bit. * gcc.target/i386/pr90773-4.c: Also run for 32-bit. * gcc.target/i386/pr90773-14.c: Likewise. * gcc.target/i386/pr90773-15.c: Likewise. * gcc.target/i386/pr90773-16.c: Likewise. * gcc.target/i386/pr90773-17.c: Likewise. --- gcc/config/i386/i386.c | 21 ++++++++++++--- gcc/config/i386/i386.h | 31 +++++++++++++++++----- gcc/testsuite/gcc.target/i386/pr90773-1.c | 10 +++---- gcc/testsuite/gcc.target/i386/pr90773-14.c | 2 +- gcc/testsuite/gcc.target/i386/pr90773-15.c | 6 ++--- gcc/testsuite/gcc.target/i386/pr90773-16.c | 2 +- gcc/testsuite/gcc.target/i386/pr90773-17.c | 2 +- gcc/testsuite/gcc.target/i386/pr90773-4.c | 2 +- 8 files changed, 53 insertions(+), 23 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8b9b2346478..b5c1436464f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -7943,8 +7943,17 @@ ix86_finalize_stack_frame_flags (void) assumed stack realignment might be needed or -fno-omit-frame-pointer is used, but in the end nothing that needed the stack alignment had been spilled nor stack access, clear frame_pointer_needed and say we - don't need stack realignment. */ - if ((stack_realign || (!flag_omit_frame_pointer && optimize)) + don't need stack realignment. + + When vector register is used for piecewise move and store, we don't + increase stack_alignment_needed as there is no register spill for + piecewise move and store. Since stack_realign_needed is set to true + by checking stack_alignment_estimated which is updated by pseudo + vector register usage, we also need to check stack_realign_needed to + eliminate frame pointer. */ + if ((stack_realign + || (!flag_omit_frame_pointer && optimize) + || crtl->stack_realign_needed) && frame_pointer_needed && crtl->is_leaf && crtl->sp_is_unchanging @@ -10403,7 +10412,13 @@ ix86_legitimate_constant_p (machine_mode mode, rtx x) /* FALLTHRU */ case E_OImode: case E_XImode: - if (!standard_sse_constant_p (x, mode)) + if (!standard_sse_constant_p (x, mode) + && GET_MODE_SIZE (TARGET_AVX512F + ? XImode + : (TARGET_AVX + ? OImode + : (TARGET_SSE2 + ? TImode : DImode))) < GET_MODE_SIZE (mode)) return false; default: break; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 45d86802c51..677afbf7031 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1754,7 +1754,7 @@ typedef struct ix86_args { /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ -#define MOVE_MAX 16 +#define MOVE_MAX 64 /* MOVE_MAX_PIECES is the number of bytes at a time which we can move efficiently, as opposed to MOVE_MAX which is the maximum @@ -1765,11 +1765,30 @@ typedef struct ix86_args { widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in 64-bit mode. */ #define MOVE_MAX_PIECES \ - ((TARGET_64BIT \ - && TARGET_SSE2 \ - && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ - && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ - ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) + ((TARGET_AVX512F && !TARGET_PREFER_AVX256) \ + ? 64 \ + : ((TARGET_AVX \ + && !TARGET_PREFER_AVX128 \ + && !TARGET_AVX256_SPLIT_UNALIGNED_LOAD \ + && !TARGET_AVX256_SPLIT_UNALIGNED_STORE) \ + ? 32 \ + : ((TARGET_SSE2 \ + && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ + && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ + ? 16 : UNITS_PER_WORD))) + +/* STORE_MAX_PIECES is the number of bytes at a time that we can + store efficiently. */ +#define STORE_MAX_PIECES \ + ((TARGET_AVX512F && !TARGET_PREFER_AVX256) \ + ? 64 \ + : ((TARGET_AVX \ + && !TARGET_PREFER_AVX128 \ + && !TARGET_AVX256_SPLIT_UNALIGNED_STORE) \ + ? 32 \ + : ((TARGET_SSE2 \ + && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ + ? 16 : UNITS_PER_WORD))) /* If a memory-to-memory move would take MOVE_RATIO or more simple move-instruction pairs, we will do a cpymem or libcall instead. diff --git a/gcc/testsuite/gcc.target/i386/pr90773-1.c b/gcc/testsuite/gcc.target/i386/pr90773-1.c index 1d9f282dc0d..4fd5a40d99d 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-1.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune=generic" } */ +/* { dg-options "-O2 -msse2 -mtune=generic" } */ extern char *dst, *src; @@ -9,9 +9,5 @@ foo (void) __builtin_memcpy (dst, src, 15); } -/* { dg-final { scan-assembler-times "movq\[\\t \]+\\(%\[\^,\]+\\)," 1 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movq\[\\t \]+7\\(%\[\^,\]+\\)," 1 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movl\[\\t \]+\\(%\[\^,\]+\\)," 1 { target ia32 } } } */ -/* { dg-final { scan-assembler-times "movl\[\\t \]+4\\(%\[\^,\]+\\)," 1 { target ia32 } } } */ -/* { dg-final { scan-assembler-times "movl\[\\t \]+8\\(%\[\^,\]+\\)," 1 { target ia32 } } } */ -/* { dg-final { scan-assembler-times "movl\[\\t \]+11\\(%\[\^,\]+\\)," 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movq\[\\t \]+\\(%\[\^,\]+\\)," 1 } } */ +/* { dg-final { scan-assembler-times "movq\[\\t \]+7\\(%\[\^,\]+\\)," 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-14.c b/gcc/testsuite/gcc.target/i386/pr90773-14.c index 6364916ecac..74ba5055960 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-14.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-14.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ extern char *dst; diff --git a/gcc/testsuite/gcc.target/i386/pr90773-15.c b/gcc/testsuite/gcc.target/i386/pr90773-15.c index c0a96fed892..880f71d1567 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-15.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-15.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -march=skylake-avx512" } */ extern char *dst; @@ -9,6 +9,6 @@ foo (int c) __builtin_memset (dst, c, 17); } -/* { dg-final { scan-assembler-times "vpbroadcastb\[\\t \]+%edi, %xmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpbroadcastb\[\\t \]+%.*, %xmm\[0-9\]+" 1 } } */ /* { dg-final { scan-assembler-times "vmovdqu\[\\t \]+%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ -/* { dg-final { scan-assembler-times "movb\[\\t \]+%dil, 16\\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+%.*, 16\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-16.c b/gcc/testsuite/gcc.target/i386/pr90773-16.c index d2d1ec6141c..32a976b10df 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-16.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-16.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -march=skylake-avx512" } */ extern char *dst; diff --git a/gcc/testsuite/gcc.target/i386/pr90773-17.c b/gcc/testsuite/gcc.target/i386/pr90773-17.c index 6c8da7d24ef..2d6fbf22a8b 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-17.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-17.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -march=skylake-avx512" } */ extern char *dst; diff --git a/gcc/testsuite/gcc.target/i386/pr90773-4.c b/gcc/testsuite/gcc.target/i386/pr90773-4.c index ec0bc0100ae..ee4c04678d1 100644 --- a/gcc/testsuite/gcc.target/i386/pr90773-4.c +++ b/gcc/testsuite/gcc.target/i386/pr90773-4.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ extern char *dst; From patchwork Mon May 17 13:15:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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(localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 608DDC0515; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 06/12] x86: Add AVX2 tests for PR middle-end/90773 Date: Mon, 17 May 2021 06:15:21 -0700 Message-Id: <20210517131527.3053833-7-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PR middle-end/90773 * gcc.target/i386/pr90773-20.c: New test. * gcc.target/i386/pr90773-21.c: Likewise. * gcc.target/i386/pr90773-22.c: Likewise. * gcc.target/i386/pr90773-23.c: Likewise. --- gcc/testsuite/gcc.target/i386/pr90773-20.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/pr90773-21.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/pr90773-22.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/pr90773-23.c | 13 +++++++++++++ 4 files changed, 52 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-20.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-21.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-22.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-23.c diff --git a/gcc/testsuite/gcc.target/i386/pr90773-20.c b/gcc/testsuite/gcc.target/i386/pr90773-20.c new file mode 100644 index 00000000000..e61e405f2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-20.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +extern char *dst; + +void +foo (int c) +{ + __builtin_memset (dst, c, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-21.c b/gcc/testsuite/gcc.target/i386/pr90773-21.c new file mode 100644 index 00000000000..16ad17f3cbb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-21.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +extern char *dst; + +void +foo (int c) +{ + __builtin_memset (dst, c, 34); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movw\[\\t \]%.*, 32\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-22.c b/gcc/testsuite/gcc.target/i386/pr90773-22.c new file mode 100644 index 00000000000..45a8ff65a84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-22.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movb\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-23.c b/gcc/testsuite/gcc.target/i386/pr90773-23.c new file mode 100644 index 00000000000..9256ce10ff0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-23.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 34); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movw\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */ From patchwork Mon May 17 13:15:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=uxKhiytD; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQL4s93z9sWQ for ; Mon, 17 May 2021 23:16:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DEDE83891C26; Mon, 17 May 2021 13:15:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEDE83891C26 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257346; bh=TjyTrvAwg3cIKw1zkXZEWHcA9FLqRaVIxlLqEaCZPy8=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=uxKhiytDPiEW2TyNkNQ7g/LORob170klwW/6aRyksGwLKiutZdAUFfwL7S/MotJtR 5Ud+ta3QRZYtE5L++afVIWBDEWaP41wxMwxabRfM5MoHKPO36L0PN+/H91PWxVKbcU RTR/Oy/ONmbffuf8FWY7XqHM2EunLk787LW3HHeU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 06773388E80F for ; Mon, 17 May 2021 13:15:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 06773388E80F Received: by mail-pf1-x436.google.com with SMTP id x188so4909897pfd.7 for ; Mon, 17 May 2021 06:15:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TjyTrvAwg3cIKw1zkXZEWHcA9FLqRaVIxlLqEaCZPy8=; b=QYQQDYuIAKBPfQGsGXaTsPmqbSmi9U/+Qdcr1bQlw179pxrYmXLhZA3hh8e4Z8PzTa QaQN9jcLfSho1lPmx+V8tacLnYDy/nIqOi6b+0rgEWjSqriA/fcpULBTgkiz2ROJD8/t OjdNLiFfkfrGH5WhBz9xXwJVMmvXQ4l5S5uRsQeAo4CC9OPIpr2AQEmbroWx8ZNz3u1Q zwgpGd889OFOAJGKT1LXP6S3dHLPaf1AarVAugb9y45mU0SEwf8H91QSWXe1ivNzF++T lzIyOqRsLedA7TTGeBxibPPq+vf/khH0zFlvDiAVIGXql/00h08rJskX8jxcAIAdjnDz qIcA== X-Gm-Message-State: AOAM532u6pZmrz/V5G/0Ngt6ub6ZZ2cSp0J7+scdUcjpC8aze5kXAZ8l QZb00Ab0Yv7bmxxvlHrzbC2ZHlAe2dP7Yg== X-Google-Smtp-Source: ABdhPJwUlVtnFC7ghiI7uG9vcvk4v83yVbqHX+1WbYBX1CRI0/QLgFw8W/7WGTmMWcGW1GgUu5WNyA== X-Received: by 2002:a63:9d4e:: with SMTP id i75mr60206467pgd.443.1621257333497; Mon, 17 May 2021 06:15:33 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id g1sm10424214pgi.64.2021.05.17.06.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:31 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 632A5C052E; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 07/12] x86: Add tests for piecewise move and store Date: Mon, 17 May 2021 06:15:22 -0700 Message-Id: <20210517131527.3053833-8-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3034.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" * gcc.target/i386/pieces-memcpy-10.c: New test. * gcc.target/i386/pieces-memcpy-11.c: Likewise. * gcc.target/i386/pieces-memcpy-12.c: Likewise. * gcc.target/i386/pieces-memcpy-13.c: Likewise. * gcc.target/i386/pieces-memcpy-14.c: Likewise. * gcc.target/i386/pieces-memcpy-15.c: Likewise. * gcc.target/i386/pieces-memcpy-16.c: Likewise. * gcc.target/i386/pieces-memcpy-17.c: Likewise. * gcc.target/i386/pieces-memcpy-18.c: Likewise. * gcc.target/i386/pieces-memcpy-19.c: Likewise. * gcc.target/i386/pieces-memset-1.c: Likewise. * gcc.target/i386/pieces-memset-2.c: Likewise. * gcc.target/i386/pieces-memset-3.c: Likewise. * gcc.target/i386/pieces-memset-4.c: Likewise. * gcc.target/i386/pieces-memset-5.c: Likewise. * gcc.target/i386/pieces-memset-6.c: Likewise. * gcc.target/i386/pieces-memset-7.c: Likewise. * gcc.target/i386/pieces-memset-8.c: Likewise. * gcc.target/i386/pieces-memset-9.c: Likewise. * gcc.target/i386/pieces-memset-10.c: Likewise. * gcc.target/i386/pieces-memset-11.c: Likewise. * gcc.target/i386/pieces-memset-12.c: Likewise. * gcc.target/i386/pieces-memset-13.c: Likewise. * gcc.target/i386/pieces-memset-14.c: Likewise. * gcc.target/i386/pieces-memset-15.c: Likewise. * gcc.target/i386/pieces-memset-16.c: Likewise. * gcc.target/i386/pieces-memset-17.c: Likewise. * gcc.target/i386/pieces-memset-18.c: Likewise. * gcc.target/i386/pieces-memset-19.c: Likewise. * gcc.target/i386/pieces-memset-20.c: Likewise. * gcc.target/i386/pieces-memset-21.c: Likewise. * gcc.target/i386/pieces-memset-22.c: Likewise. * gcc.target/i386/pieces-memset-23.c: Likewise. * gcc.target/i386/pieces-memset-24.c: Likewise. * gcc.target/i386/pieces-memset-25.c: Likewise. * gcc.target/i386/pieces-memset-26.c: Likewise. * gcc.target/i386/pieces-memset-27.c: Likewise. * gcc.target/i386/pieces-memset-28.c: Likewise. * gcc.target/i386/pieces-memset-29.c: Likewise. * gcc.target/i386/pieces-memset-30.c: Likewise. * gcc.target/i386/pieces-memset-31.c: Likewise. * gcc.target/i386/pieces-memset-32.c: Likewise. * gcc.target/i386/pieces-memset-33.c: Likewise. * gcc.target/i386/pieces-memset-34.c: Likewise. * gcc.target/i386/pieces-memset-35.c: Likewise. * gcc.target/i386/pieces-memset-36.c: Likewise. * gcc.target/i386/pieces-memset-37.c: Likewise. * gcc.target/i386/pieces-memset-38.c: Likewise. * gcc.target/i386/pieces-memset-39.c: Likewise. * gcc.target/i386/pieces-memset-40.c: Likewise. * gcc.target/i386/pieces-memset-41.c: Likewise. * gcc.target/i386/pieces-memset-42.c: Likewise. * gcc.target/i386/pieces-memset-43.c: Likewise. * gcc.target/i386/pieces-memset-44.c: Likewise. --- .../gcc.target/i386/pieces-memcpy-10.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memcpy-11.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memcpy-12.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memcpy-13.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memcpy-14.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memcpy-15.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memcpy-16.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memcpy-7.c | 15 +++++++++++++++ .../gcc.target/i386/pieces-memcpy-8.c | 14 ++++++++++++++ .../gcc.target/i386/pieces-memcpy-9.c | 14 ++++++++++++++ .../gcc.target/i386/pieces-memset-1.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-10.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-11.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-12.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-13.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-14.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-15.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-16.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-17.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-18.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-19.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-2.c | 12 ++++++++++++ .../gcc.target/i386/pieces-memset-20.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-21.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-22.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-23.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-24.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-25.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-26.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-27.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-28.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-29.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-3.c | 18 ++++++++++++++++++ .../gcc.target/i386/pieces-memset-30.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-31.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-32.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-33.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-34.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-35.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-36.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-37.c | 15 +++++++++++++++ .../gcc.target/i386/pieces-memset-38.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-39.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-4.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-40.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-41.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-42.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-43.c | 17 +++++++++++++++++ .../gcc.target/i386/pieces-memset-5.c | 12 ++++++++++++ .../gcc.target/i386/pieces-memset-6.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-7.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-8.c | 16 ++++++++++++++++ .../gcc.target/i386/pieces-memset-9.c | 16 ++++++++++++++++ 53 files changed, 860 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-11.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-12.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-13.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-14.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-7.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-8.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memcpy-9.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-10.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-11.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-12.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-13.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-14.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-15.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-16.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-17.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-18.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-19.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-20.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-21.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-22.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-23.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-24.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-25.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-26.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-27.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-28.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-29.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-30.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-31.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-32.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-33.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-34.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-35.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-36.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-37.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-38.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-39.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-40.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-41.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-42.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-43.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-5.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-6.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-7.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-8.c create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-9.c diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c new file mode 100644 index 00000000000..5faee21f9b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-11.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-11.c new file mode 100644 index 00000000000..b8917a7f917 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-11.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 64); +} + +/* { dg-final { scan-assembler-times "movdqu\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-12.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-12.c new file mode 100644 index 00000000000..f1432ebe517 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-12.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 64); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-13.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-13.c new file mode 100644 index 00000000000..97e6067fec9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-13.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 66); +} + +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-14.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-14.c new file mode 100644 index 00000000000..7addc4c0a28 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-14.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 33); +} + +/* { dg-final { scan-assembler-times "movdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c new file mode 100644 index 00000000000..695e8c3fa67 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c new file mode 100644 index 00000000000..b0643d05ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst, *src; + +void +foo (void) +{ + __builtin_memcpy (dst, src, 34); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-7.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-7.c new file mode 100644 index 00000000000..3d248d447ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +void +foo (int a1, int a2, int a3, int a4, int a5, int a6, char *dst, char *src) +{ + __builtin_memcpy (dst, src, 17); +} + +/* { dg-final { scan-assembler-times "movdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-8.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-8.c new file mode 100644 index 00000000000..c13a2beb2f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */ + +void +foo (int a1, int a2, int a3, int a4, int a5, int a6, char *dst, char *src) +{ + __builtin_memcpy (dst, src, 18); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-9.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-9.c new file mode 100644 index 00000000000..238f88b275e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-9.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +void +foo (int a1, int a2, int a3, int a4, int a5, int a6, char *dst, char *src) +{ + __builtin_memcpy (dst, src, 19); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-1.c b/gcc/testsuite/gcc.target/i386/pieces-memset-1.c new file mode 100644 index 00000000000..2b8032684b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 64); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-10.c b/gcc/testsuite/gcc.target/i386/pieces-memset-10.c new file mode 100644 index 00000000000..a6390d1bd8f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 64); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-11.c b/gcc/testsuite/gcc.target/i386/pieces-memset-11.c new file mode 100644 index 00000000000..3fb9038b04f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-11.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 64); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-12.c b/gcc/testsuite/gcc.target/i386/pieces-memset-12.c new file mode 100644 index 00000000000..fa834566097 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-12.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 66); +} + +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-13.c b/gcc/testsuite/gcc.target/i386/pieces-memset-13.c new file mode 100644 index 00000000000..7f2cd3f58ec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-13.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 33); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-14.c b/gcc/testsuite/gcc.target/i386/pieces-memset-14.c new file mode 100644 index 00000000000..45ece482464 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-14.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-15.c b/gcc/testsuite/gcc.target/i386/pieces-memset-15.c new file mode 100644 index 00000000000..bddf47d728e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-15.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-16.c b/gcc/testsuite/gcc.target/i386/pieces-memset-16.c new file mode 100644 index 00000000000..1c5d124cecc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 17); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-17.c b/gcc/testsuite/gcc.target/i386/pieces-memset-17.c new file mode 100644 index 00000000000..6cdb33557c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-17.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 17); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-18.c b/gcc/testsuite/gcc.target/i386/pieces-memset-18.c new file mode 100644 index 00000000000..adbd201b4e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-18.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 3, 18); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-19.c b/gcc/testsuite/gcc.target/i386/pieces-memset-19.c new file mode 100644 index 00000000000..7e9cf2e26d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 64); +} + +/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-2.c b/gcc/testsuite/gcc.target/i386/pieces-memset-2.c new file mode 100644 index 00000000000..649f344e8f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 64); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-20.c b/gcc/testsuite/gcc.target/i386/pieces-memset-20.c new file mode 100644 index 00000000000..b8747e669e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 64); +} + +/* { dg-final { scan-assembler-times "vpxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-21.c b/gcc/testsuite/gcc.target/i386/pieces-memset-21.c new file mode 100644 index 00000000000..4f001c6d06c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-21.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 66); +} + +/* { dg-final { scan-assembler-times "vpxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-22.c b/gcc/testsuite/gcc.target/i386/pieces-memset-22.c new file mode 100644 index 00000000000..5f3c454ef8f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-22.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 33); +} + +/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-23.c b/gcc/testsuite/gcc.target/i386/pieces-memset-23.c new file mode 100644 index 00000000000..a3b4ffc18e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-23.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 33); +} + +/* { dg-final { scan-assembler-times "vpxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-24.c b/gcc/testsuite/gcc.target/i386/pieces-memset-24.c new file mode 100644 index 00000000000..e222787b541 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-24.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 33); +} + +/* { dg-final { scan-assembler-times "vpxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-25.c b/gcc/testsuite/gcc.target/i386/pieces-memset-25.c new file mode 100644 index 00000000000..195ddb635eb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-25.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 17); +} + +/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-26.c b/gcc/testsuite/gcc.target/i386/pieces-memset-26.c new file mode 100644 index 00000000000..13606b2da54 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-26.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 17); +} + +/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-27.c b/gcc/testsuite/gcc.target/i386/pieces-memset-27.c new file mode 100644 index 00000000000..54a672b6015 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-27.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 17); +} + +/* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-28.c b/gcc/testsuite/gcc.target/i386/pieces-memset-28.c new file mode 100644 index 00000000000..83c2d3f0fde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-28.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 64); +} + +/* { dg-final { scan-assembler-times "pcmpeqd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-29.c b/gcc/testsuite/gcc.target/i386/pieces-memset-29.c new file mode 100644 index 00000000000..650e6fe66a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-29.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 64); +} + +/* { dg-final { scan-assembler-not "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm" } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-3.c b/gcc/testsuite/gcc.target/i386/pieces-memset-3.c new file mode 100644 index 00000000000..2aed6dbc68e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512bw -mno-avx512vl -mavx512f -mtune=intel" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 66); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* { dg-final { scan-assembler-times "vinserti64x4\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-30.c b/gcc/testsuite/gcc.target/i386/pieces-memset-30.c new file mode 100644 index 00000000000..dcec2c700fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-30.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 64); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-31.c b/gcc/testsuite/gcc.target/i386/pieces-memset-31.c new file mode 100644 index 00000000000..5d20af0938d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-31.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 66); +} + +/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-32.c b/gcc/testsuite/gcc.target/i386/pieces-memset-32.c new file mode 100644 index 00000000000..c5ca0bd17ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 33); +} + +/* { dg-final { scan-assembler-times "pcmpeqd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-33.c b/gcc/testsuite/gcc.target/i386/pieces-memset-33.c new file mode 100644 index 00000000000..a87d1b80ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-33.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 33); +} + +/* { dg-final { scan-assembler-not "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm" } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-34.c b/gcc/testsuite/gcc.target/i386/pieces-memset-34.c new file mode 100644 index 00000000000..0c2f1ee6049 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-34.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=haswell" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 33); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-35.c b/gcc/testsuite/gcc.target/i386/pieces-memset-35.c new file mode 100644 index 00000000000..b0f4a8b898e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-35.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 34); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-36.c b/gcc/testsuite/gcc.target/i386/pieces-memset-36.c new file mode 100644 index 00000000000..d1f1263c7b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-36.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 17); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-37.c b/gcc/testsuite/gcc.target/i386/pieces-memset-37.c new file mode 100644 index 00000000000..ec59497b116 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-37.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=generic" } */ + +void +foo (int a1, int a2, int a3, int a4, int a5, int a6, int x, char *dst) +{ + __builtin_memset (dst, x, 66); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-38.c b/gcc/testsuite/gcc.target/i386/pieces-memset-38.c new file mode 100644 index 00000000000..ed4a24a54fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-38.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=sandybridge" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 33); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-39.c b/gcc/testsuite/gcc.target/i386/pieces-memset-39.c new file mode 100644 index 00000000000..a330bff5f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-39.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512bw -mtune=generic" } */ + +void +foo (int a1, int a2, int a3, int a4, int a5, int a6, int x, char *dst) +{ + __builtin_memset (dst, x, 66); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* { dg-final { scan-assembler-not "vinserti64x4" } } */ +/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-4.c b/gcc/testsuite/gcc.target/i386/pieces-memset-4.c new file mode 100644 index 00000000000..9256919bfdf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 33); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-40.c b/gcc/testsuite/gcc.target/i386/pieces-memset-40.c new file mode 100644 index 00000000000..4eda73ead59 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-40.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -mavx2 -mtune=sandybridge" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 66); +} + +/* { dg-final { scan-assembler-times "vpbroadcastb\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 4 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-41.c b/gcc/testsuite/gcc.target/i386/pieces-memset-41.c new file mode 100644 index 00000000000..f86b6986da9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-41.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-42.c b/gcc/testsuite/gcc.target/i386/pieces-memset-42.c new file mode 100644 index 00000000000..df0c122aae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-42.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, 0, 33); +} + +/* { dg-final { scan-assembler-times "vpxor\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-43.c b/gcc/testsuite/gcc.target/i386/pieces-memset-43.c new file mode 100644 index 00000000000..2f2179c2df9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-43.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */ + +extern char *dst; + +void +foo (void) +{ + __builtin_memset (dst, -1, 33); +} + +/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 2 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-5.c b/gcc/testsuite/gcc.target/i386/pieces-memset-5.c new file mode 100644 index 00000000000..3e95db5efef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=haswell" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-6.c b/gcc/testsuite/gcc.target/i386/pieces-memset-6.c new file mode 100644 index 00000000000..571113c3a33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=intel" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 33); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-7.c b/gcc/testsuite/gcc.target/i386/pieces-memset-7.c new file mode 100644 index 00000000000..fd159869817 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-7.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx -msse2 -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 17); +} + +/* { dg-final { scan-assembler-times "movups\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-8.c b/gcc/testsuite/gcc.target/i386/pieces-memset-8.c new file mode 100644 index 00000000000..7df0019ef63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 17); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-9.c b/gcc/testsuite/gcc.target/i386/pieces-memset-9.c new file mode 100644 index 00000000000..ed45d590875 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-9.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=generic" } */ + +extern char *dst; + +void +foo (int x) +{ + __builtin_memset (dst, x, 17); +} + +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%xmm" 1 } } */ +/* No need to dynamically realign the stack here. */ +/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */ +/* Nor use a frame pointer. */ +/* { dg-final { scan-assembler-not "%\[re\]bp" } } */ From patchwork Mon May 17 13:15:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=qmTFifBu; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQC4xXgz9sRf for ; Mon, 17 May 2021 23:16:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 42AC83891C3B; Mon, 17 May 2021 13:15:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 42AC83891C3B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257343; bh=ENotfVzOqfEByeldXwpp9YMmurkGloeiY9w3RKYfh0Y=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=qmTFifBuEO6vj6NP/mFCqG8id3kb9nmbRmsKCiNOJ/pW0mIayUtGnyn5nCzj5YQ52 Qi9Zcwb7nPwD9GdIkfpTK8Hus/KzyKn1upcCKGH0skRi9hBc/oBFph9hijR/+eTXW9 hh5uwR5tXIXtfqWKA1fCpZugtMygOLRn4ZAYh9G8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id D1669383302A for ; Mon, 17 May 2021 13:15:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D1669383302A Received: by mail-pj1-x102e.google.com with SMTP id gm21so3646651pjb.5 for ; Mon, 17 May 2021 06:15:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ENotfVzOqfEByeldXwpp9YMmurkGloeiY9w3RKYfh0Y=; b=MXpZkmX0lvo0HUtHL/Bf+ekWKYW66DGukhsPpqus7M2okLNwV5vkdKAirIZs1zqG1C xGsvubE+yRpEyjVGGiBg+KP9JyNK9YAdTiDm59WdSwMt0MiKlRXoSpBL4quVUIZENB0d FQlnAJhWsWX2JLaz/rz84k2jqAaVo0d/QA3b7ME7j0G4KFU1H9g1ubB4P7XDGHu6yS37 Z/FVU0L0eqoVxXtYx7S61c0KNptR5Og3GbiFF5kBruTqNbelyrVGZTB5nO+p2yIcdXZK K/BPk+Uw+BUpZ4KQKQueZlxRLNYPQlTjx8YE7IWIS0n56t4tXSJMa3MPQO0JWuwOcnSb MDfw== X-Gm-Message-State: AOAM530fQjPMzMd5MtekFvyNzLvtbF21AoYDdBIr86Dcdpy4GSrXPX6W +R7N09BDmVrfcCTmHwsydeKnOLvXZkq6QA== X-Google-Smtp-Source: ABdhPJwtiZeRaxSH0h4qhPazQ784yqcc0CV4c1xX8ekbTWBiBZOwyT/XLhZ9EugJzJfuGPZC6NwIGg== X-Received: by 2002:a17:90a:4582:: with SMTP id v2mr18970775pjg.215.1621257333009; Mon, 17 May 2021 06:15:33 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id h3sm7623098pfh.114.2021.05.17.06.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:31 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 70BEFC056D; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 08/12] x86: Also pass -mno-avx to pr72839.c Date: Mon, 17 May 2021 06:15:23 -0700 Message-Id: <20210517131527.3053833-9-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Also pass -mno-avx to pr72839.c to avoid copying data with YMM or ZMM registers. * gcc.target/i386/pr72839.c: Also pass -mno-avx. --- gcc/testsuite/gcc.target/i386/pr72839.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/pr72839.c b/gcc/testsuite/gcc.target/i386/pr72839.c index ea724f70377..6888d9d0a55 100644 --- a/gcc/testsuite/gcc.target/i386/pr72839.c +++ b/gcc/testsuite/gcc.target/i386/pr72839.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target ia32 } */ -/* { dg-options "-O2 -mtune=lakemont" } */ +/* { dg-options "-O2 -mtune=lakemont -mno-avx" } */ extern char *strcpy (char *, const char *); From patchwork Mon May 17 13:15:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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(localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 71798C0573; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 09/12] x86: Also pass -mno-avx to cold-attribute-1.c Date: Mon, 17 May 2021 06:15:24 -0700 Message-Id: <20210517131527.3053833-10-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Also pass -mno-avx to pr72839.c to avoid copying data with YMM or ZMM registers. * gcc.target/i386/cold-attribute-1.c: Also pass -mno-avx. --- gcc/testsuite/gcc.target/i386/cold-attribute-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/cold-attribute-1.c b/gcc/testsuite/gcc.target/i386/cold-attribute-1.c index 57666ac60b6..658eb3e25bb 100644 --- a/gcc/testsuite/gcc.target/i386/cold-attribute-1.c +++ b/gcc/testsuite/gcc.target/i386/cold-attribute-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -mno-avx" } */ #include static inline __attribute__ ((cold)) void From patchwork Mon May 17 13:15:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=LlMlMvaP; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQf6gr2z9sWW for ; Mon, 17 May 2021 23:16:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DB2FA3891C20; Mon, 17 May 2021 13:15:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB2FA3891C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257353; bh=klBNDFPhKR1GPi9QH4Nb5uvdqQ5UzAPfms5xv6Aac0U=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=LlMlMvaPYMziAeC56PAj1KQcKNIgDKQzM1Z0ZHUu0p/En3jVqFcYmvWWneo9pUNFU YUC2pX+/krW50Ff8pmLPs2+Bmz2+tbD8BvHjAJbtCy33FnJ4HJo3KEqy+8F6c1AnEm EjCAF5/roEaSKVvmodxh6ru77NBWgqTPXGuWJ2dQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by sourceware.org (Postfix) with ESMTPS id A8BBF3835403 for ; Mon, 17 May 2021 13:15:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A8BBF3835403 Received: by mail-pj1-x1030.google.com with SMTP id gm21so3646704pjb.5 for ; Mon, 17 May 2021 06:15:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=klBNDFPhKR1GPi9QH4Nb5uvdqQ5UzAPfms5xv6Aac0U=; b=LiQePErTnix7Zzb2pkdHKK2SK3ae4yS4VM4Js+kTJsL2kdX+JfAhwLJENAsbidnDSy U7Bpz786dZTtQL4GeXlM/iDEb82iMkYja/4LIi0jm8WUowyRVkYLW1a0Qq62URAZK1o/ bDQz9UJUBMRCnKCc2gfGhutr/DoSzCPcKtA2N3XKRGx2yOH+0yLCHC+KfXHVz93NeQy4 ZdT8XTgNY4VN0jJtjysXdU1tTOHyT0FQ4TzIdDchpAcOKpkkUkjHrAJw16CZvx64aGxV rxUl4ZDR9zR62sX4tpEMunPQ+TsVZNnkvNvkxqLHzDgrtmCjbg0Vu+7nmObeVpedQalz mvDA== X-Gm-Message-State: AOAM533rHEZss5H/sJqNkPMlpcnBsxfyaWoBM5IE1cvN3/sGi5pnNdY1 XSIpPqcFPKqXkwhjfxE15f8= X-Google-Smtp-Source: ABdhPJzYXQZ5JTTAHlBiy2nfDJvbL+VVqQuWFOKwEKeTrcsIuyJJxcbSzlbrNZDNI2v5WqYPTwSGOw== X-Received: by 2002:a17:902:7c94:b029:e6:e1d7:62b7 with SMTP id y20-20020a1709027c94b02900e6e1d762b7mr60578658pll.29.1621257334848; Mon, 17 May 2021 06:15:34 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id f9sm1714372pfc.42.2021.05.17.06.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:34 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 7D8D2C0574; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 10/12] x86: Also pass -mno-avx to sw-1.c for ia32 Date: Mon, 17 May 2021 06:15:25 -0700 Message-Id: <20210517131527.3053833-11-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Also pass -mno-avx to sw-1.c for ia32 since copying data with YMM or ZMM registers disables shrink-wrapping when the second argument is passed on stack. * gcc.target/i386/sw-1.c: Also pass -mno-avx for ia32. --- gcc/testsuite/gcc.target/i386/sw-1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc/testsuite/gcc.target/i386/sw-1.c index aec095eda62..a9c89fca4ec 100644 --- a/gcc/testsuite/gcc.target/i386/sw-1.c +++ b/gcc/testsuite/gcc.target/i386/sw-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */ +/* { dg-additional-options "-mno-avx" { target ia32 } } */ /* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } } */ #include From patchwork Mon May 17 13:15:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=g7QmYpSA; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQl5bpPz9sXH for ; Mon, 17 May 2021 23:16:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7FDAE389201E; Mon, 17 May 2021 13:15:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7FDAE389201E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257356; bh=FXy3Syhc+oNswnDnGtzKewSCF4T/rrDdFLmy1d+tpMc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=g7QmYpSAkFF0sHuUU9Ps9QaSyWfuzGfLkLkmrvqZqUphMfO/ukL2qhFG69k5Zeo9U MjoVkt5H/88+Es7kt0uWLjiUwv+EsVZLlDJEOIAYlF4FAF6HnS31s1EybfnH8skcb/ 9B9DkIRsbesSxZA2AMQboi4FPm2T6Y1TkS8feWxc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 277D13835420 for ; Mon, 17 May 2021 13:15:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 277D13835420 Received: by mail-pl1-x629.google.com with SMTP id a11so3118266plh.3 for ; Mon, 17 May 2021 06:15:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FXy3Syhc+oNswnDnGtzKewSCF4T/rrDdFLmy1d+tpMc=; b=cm5iVqufXEkWKHyxZr+Wr7cvMHagJz66vpqS74BrTiTd6YP/k/GC5Sf22ErmncKLsu XZucj9py1wcyKEaqpKv3jsBATExkc2HOJgKBi9gM8y1R1t3kqJNYamYRTekxQJizBWrE MnafORc9GAh43+VEnuE2wUeng/F6ujbyHsURa8gFe1mGC/cJjE/bfTZHqXytQ5VawF46 fY/17SbvnNiAPMeI+nmgM8iOYeSZqP+xIkMmpxbD1p4Av03DZOgc3BbadIv4bcqlU8f5 CZ6DrzRXHB5bmewEFNYlviY+/XUYrh9+Nps/0T2cjjqWvC7l0lSUcSmzGtddHtAWd2Hl AG0g== X-Gm-Message-State: AOAM532Hd2VtdTOJZtTbayiLJsveejYVLniLxOMgYjBH0XaHMEQQxKH8 o7UQ1OYqOglVxveSBR+3NsY= X-Google-Smtp-Source: ABdhPJzNW5YgcxepeisIzj7kRRcET1IitjaOIE8jY1rfBzMgktLFh7sFp1b9fQ0Gt0GW8dnmW42ctg== X-Received: by 2002:a17:902:b609:b029:ec:e80d:7ebd with SMTP id b9-20020a170902b609b02900ece80d7ebdmr61308383pls.75.1621257335309; Mon, 17 May 2021 06:15:35 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id x19sm7480143pfp.153.2021.05.17.06.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:34 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 81219C0575; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 11/12] x86: Update gcc.target/i386/incoming-11.c Date: Mon, 17 May 2021 06:15:26 -0700 Message-Id: <20210517131527.3053833-12-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Expect no stack realignment since we no longer realign stack when copying data. * gcc.target/i386/incoming-11.c: Expect no stack realignment. --- gcc/testsuite/gcc.target/i386/incoming-11.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/incoming-11.c b/gcc/testsuite/gcc.target/i386/incoming-11.c index a830c96f7d1..4b822684b88 100644 --- a/gcc/testsuite/gcc.target/i386/incoming-11.c +++ b/gcc/testsuite/gcc.target/i386/incoming-11.c @@ -15,4 +15,4 @@ void f() for (i = 0; i < 100; i++) q[i] = 1; } -/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ From patchwork Mon May 17 13:15:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1479500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=cYTnOUhv; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FkKQq1w0Pz9sXH for ; Mon, 17 May 2021 23:16:35 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20BC6389202B; Mon, 17 May 2021 13:15:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 20BC6389202B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1621257357; bh=kXArcoQdCg9IkXnBWtf3fk8d6a2ZjRy5uQECS0ldH6E=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=cYTnOUhvfcDkto3Upr4w1ZrcwAPGDaZrDb8X6iOQVhK8oyikAO9Es0ZkgKuYIdYHf S1fQXjgaQyHAloN9YpXLgLYzXlYGh+xXZzsTu22zUsBZcZo93RgpqfHNJWQ0m/+0e5 7mdyafxNuXMlSZlLp6PgNi6rqXOlu2h/4H+qxDFw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id 1B1903891C18 for ; Mon, 17 May 2021 13:15:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 1B1903891C18 Received: by mail-pj1-x102e.google.com with SMTP id pi6-20020a17090b1e46b029015cec51d7cdso3677444pjb.5 for ; Mon, 17 May 2021 06:15:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kXArcoQdCg9IkXnBWtf3fk8d6a2ZjRy5uQECS0ldH6E=; b=j1/oOdVTsSX+Zv/9uMP6wvm7f12GP8a/BTZp9bBncCuBHt8p5SqtPOTVO/OKt8qKa2 9Nl8jxKqCPiawC3S5ekmv5oApi8QyFL/FakqcgaBUbcw8XIHdancb/qem3o0eErAvxG2 oGVDunVkibuCZnXEa2g9/A2tuYqy40zXeYR24dJaAxcv8kD3qUvRZQ+5/lpo0xVUWMAA 7MFjvf2M+FfTqYLKk9h4SSc3WzBlNp6rFjeJ3jVdSjGC9itcDtE3U+fcQ+8Bb8ajQ0gK y1t57wyRjQnCBfTIQGNe4ncQ/dOWlmRpFzbf0t5P9P9XMY9H+wCx+R9+mpbdFUDEj5DD DNaQ== X-Gm-Message-State: AOAM532cqQ+CJKpjeGi9144LTT6lvgDgDbruInyUShAWdR107i4OxR1j BsE4kxRhNU/J/GgAZdGxhPU= X-Google-Smtp-Source: ABdhPJws6YsSbYdwTummQbs5Cswr45maegiHhDNGarYYiVxDlWPjV3j18hDxwopEXwaIEeS9GW4+SQ== X-Received: by 2002:a17:902:ecc4:b029:ef:8e98:3cb0 with SMTP id a4-20020a170902ecc4b02900ef8e983cb0mr26619349plh.50.1621257336236; Mon, 17 May 2021 06:15:36 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.39.231]) by smtp.gmail.com with ESMTPSA id g18sm10019966pfb.178.2021.05.17.06.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 06:15:34 -0700 (PDT) Received: from gnu-cfl-2.. (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 8DED0C0576; Mon, 17 May 2021 06:15:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 12/12] constructor: Check if it is faster to load constant from memory Date: Mon, 17 May 2021 06:15:27 -0700 Message-Id: <20210517131527.3053833-13-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517131527.3053833-1-hjl.tools@gmail.com> References: <20210517131527.3053833-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3035.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" When expanding a constant constructor, don't call expand_constructor if it is more efficient to load the data from the memory via move by pieces. gcc/ PR middle-end/90773 * expr.c (expand_expr_real_1): Don't call expand_constructor if it is more efficient to load the data from the memory. gcc/testsuite/ PR middle-end/90773 * gcc.target/i386/pr90773-24.c: New test. * gcc.target/i386/pr90773-25.c: Likewise. --- gcc/expr.c | 10 ++++++++++ gcc/testsuite/gcc.target/i386/pr90773-24.c | 22 ++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr90773-25.c | 20 ++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-24.c create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-25.c diff --git a/gcc/expr.c b/gcc/expr.c index d09ee42e262..80e01ea1cbe 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -10886,6 +10886,16 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode, unsigned HOST_WIDE_INT ix; tree field, value; + /* Check if it is more efficient to load the data from + the memory directly. FIXME: How many stores do we + need here if not moved by pieces? */ + unsigned HOST_WIDE_INT bytes + = tree_to_uhwi (TYPE_SIZE_UNIT (type)); + if ((bytes / UNITS_PER_WORD) > 2 + && MOVE_MAX_PIECES > UNITS_PER_WORD + && can_move_by_pieces (bytes, TYPE_ALIGN (type))) + goto normal_inner_ref; + FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), ix, field, value) if (tree_int_cst_equal (field, index)) diff --git a/gcc/testsuite/gcc.target/i386/pr90773-24.c b/gcc/testsuite/gcc.target/i386/pr90773-24.c new file mode 100644 index 00000000000..4a4b62533dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-24.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +struct S +{ + long long s1 __attribute__ ((aligned (8))); + unsigned s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14; +}; + +const struct S array[] = { + { 0, 60, 640, 2112543726, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 4 } +}; + +void +foo (struct S *x) +{ + x[0] = array[0]; +} +/* { dg-final { scan-assembler-times "movups\[\\t \]%xmm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[\\t \]%xmm\[0-9\]+, 16\\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[\\t \]%xmm\[0-9\]+, 32\\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "movups\[\\t \]%xmm\[0-9\]+, 48\\(%\[\^,\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90773-25.c b/gcc/testsuite/gcc.target/i386/pr90773-25.c new file mode 100644 index 00000000000..2520b670989 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90773-25.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +struct S +{ + long long s1 __attribute__ ((aligned (8))); + unsigned s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14; +}; + +const struct S array[] = { + { 0, 60, 640, 2112543726, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 4 } +}; + +void +foo (struct S *x) +{ + x[0] = array[0]; +} +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, 32\\(%\[\^,\]+\\)" 1 } } */