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bh=cldMSRAx/TanOMw0R718BnMVkR0TWKv1sB6otiBbo8s=; b=pGD0KKGDJIQQvvmUaGAJt8b39b11Li1dhubMrVzZeOxM9OUs/gxQPfBOZjcp92+XG/ cOaUzWWaT9yDqw5qDFG4pUP0ddEa4+rgw38lNLYqO21GfgypYKTTmZRNbNjgpxSRiaIZ 9y6Z1i+mvLbjoFTBhc4QcetspLMg6xRqhYLtdbXt46YU2x/UiVDN58+aZ6O8yF3poGYu CSYYO0fOdYXURuFMZ0eCZ/FZ0kZSSQ9ZbGALXR81/HHrx0wVYCLwKY6eXULgebQlUn7Y TQN763+MQKrRcsvELB97O7sj3netIwyI1sV4b3TMXb9/os7ztmwJsrxgi5xJAG8nPHww 2YFg== X-Gm-Message-State: AOAM5314Ky2s0n11dfJLfbAPtZ7aWUR2ghZedp1iG5iE7bs2QcXJGnq8 /zteriDHL3qpuP/dJyZCdRqC8eGi1BKlK7+cCdHrEOM7RqE= X-Google-Smtp-Source: ABdhPJzDxc2ZcgmUy9v9iEWB1eJIXb3hZDRxcR3ChRoKfHsMEKgrsCAolGUNRVVZ4hipgJGK20mEdUxE3HC1dgWF1KE= X-Received: by 2002:a2e:9a18:: with SMTP id o24mr41101011lji.110.1621080416489; Sat, 15 May 2021 05:06:56 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Charles Papon Date: Sat, 15 May 2021 14:06:45 +0200 Message-ID: Subject: Fwd: lib: fix GET_FXX_REG assembly To: opensbi@lists.infradead.org X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210515_050658_815774_DB508430 X-CRM114-Status: UNSURE ( 5.84 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.1 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The previous implementation was producing some broken assembly. See github #212 for more details PR : https://github.com/riscv/opensbi/pull/214 --- include/sbi/riscv_fp.h | 32 ++++++++++++++++ 1 file changed, 16 insertions(+), 16 deletions(-) Content analysis details: (0.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:235 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [charles.papon.90[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [charles.papon.90[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The previous implementation was producing some broken assembly. See github #212 for more details PR : https://github.com/riscv/opensbi/pull/214 Signed-off-by: Charles Papon --- include/sbi/riscv_fp.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) \ + register ulong rf_address asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + volatile u32 value; \ + asm volatile("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp) : "r"(&value), "r"(rf_address) :"t0"); \ + value; \ }) #define SET_F32_REG(insn, pos, regs, val) \ ({ \ @@ -42,14 +42,14 @@ : "t0"); \ }) #define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0) -#define GET_F64_REG(insn, pos, regs) \ - ({ \ - register ulong value asm("a0") = \ - SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \ - : "=&r"(tmp), "+&r"(value)::"t0"); \ - sizeof(ulong) == 4 ? *(int64_t *)value : (int64_t)value; \ +#define GET_F64_REG(insn, pos, regs) \ + ({ \ + register ulong rf_address asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ + ulong tmp; \ + volatile u64 value; \ + asm volatile("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \ + : "=&r"(tmp) : "r"(&value), "r"(rf_address) :"t0"); \ + value; \ }) #define SET_F64_REG(insn, pos, regs, val) \ ({ \ diff --git a/include/sbi/riscv_fp.h b/include/sbi/riscv_fp.h index a685884..b2c0636 100644 --- a/include/sbi/riscv_fp.h +++ b/include/sbi/riscv_fp.h @@ -21,14 +21,14 @@ #ifdef __riscv_flen -#define GET_F32_REG(insn, pos, regs) \ - ({ \ - register s32 value asm("a0") = \ - SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ - ulong tmp; \ - asm("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \ - : "=&r"(tmp), "+&r"(value)::"t0"); \ - value; \ +#define GET_F32_REG(insn, pos, regs) \ + ({