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Fri, 07 May 2021 02:30:43 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1472Ueso23396824 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 7 May 2021 02:30:41 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D6A024C044; Fri, 7 May 2021 02:30:40 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 84D9E4C040; Fri, 7 May 2021 02:30:39 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.34]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 7 May 2021 02:30:39 +0000 (GMT) To: GCC Patches Subject: [PATCH] rs6000: Support more short/char to float conversion Message-ID: Date: Fri, 7 May 2021 10:30:38 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1FnoZ_s4XBBbuUcN63MhazNI35lF4kbo X-Proofpoint-GUID: uHrdZiKOLDIKsvR21_UybvKQva9k_YKV X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-06_16:2021-05-06, 2021-05-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2105070012 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, For some cases that when we load unsigned char/short values from the appropriate unsigned char/short memories and convert them to double/single precision floating point value, there would be implicit conversions to int first. It makes GCC not leverage the P9 instructions lxsibzx/lxsihzx. This patch is to add the related define_insn_and_split to support this kind of scenario. Bootstrapped/regtested on powerpc64le-linux-gnu P9 and powerpc64-linux-gnu P8. Is it ok for trunk? BR, Kewen ------ gcc/ChangeLog: * config/rs6000/rs6000.md (floatsi2_lfiwax__mem_zext): New define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/powerpc/p9-fpcvt-3.c: New test. --- gcc/config/rs6000/rs6000.md | 22 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c | 27 +++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c8cdc42533c..3ac7ed20852 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5504,6 +5504,28 @@ (define_insn_and_split "floatsi2_lfiwax_mem" [(set_attr "length" "8") (set_attr "type" "fpload")]) +(define_insn_and_split "floatsi2_lfiwax__mem_zext" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (float:SFDF + (zero_extend:SI + (match_operand:QHI 1 "indexed_or_indirect_operand" "Z,Z")))) + (clobber (match_scratch:DI 2 "=d,wa"))] + "TARGET_HARD_FLOAT && && TARGET_P9_VECTOR + && TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& 1" + [(pc)] +{ + operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]); + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (DImode); + emit_insn (gen_zero_extendhidi2 (operands[2], operands[1])); + emit_insn (gen_floatdi2 (operands[0], operands[2])); + DONE; +} + [(set_attr "length" "8") + (set_attr "type" "fpload")]) + (define_insn "lfiwzx" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,wa") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")] diff --git a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c new file mode 100644 index 00000000000..d3bbe36b759 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* Note that for unsigned cases, the differences from those ones in + p9-fpcvt-2.c is that they will be converted to int implicitly first + and then to floating point. */ + +double sc_df (signed char *p, double df) { return *p + df; } +double uc_df (unsigned char *p, double df) { return *p + df; } +double ss_df (signed short *p, double df) { return *p + df; } +double us_df (unsigned short *p, double df) { return *p + df; } + +float sc_sf (signed char *p, float sf) { return *p + sf; } +float uc_sf (unsigned char *p, float sf) { return *p + sf; } +float ss_sf (signed short *p, float sf) { return *p + sf; } +float us_sf (unsigned short *p, float sf) { return *p + sf; } + +/* { dg-final { scan-assembler "lxsibzx" } } */ +/* { dg-final { scan-assembler "lxsihzx" } } */ +/* { dg-final { scan-assembler "vextsb2d" } } */ +/* { dg-final { scan-assembler "vextsh2d" } } */ +/* { dg-final { scan-assembler-not "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "mfvsrwz" } } */ +/* { dg-final { scan-assembler-not "mtvsrd" } } */ +/* { dg-final { scan-assembler-not "mtvsrwa" } } */ +/* { dg-final { scan-assembler-not "mtvsrwz" } } */