From patchwork Wed May 5 19:36:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=OrC2JIKf; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fb6RW2LSGz9sPf for ; Thu, 6 May 2021 05:37:11 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 074EB396C83D; Wed, 5 May 2021 19:37:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 074EB396C83D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1620243425; bh=ujo7aBAL5RbzXJ88+dC9nooQBca2cNV11OT1NwUMyK0=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=OrC2JIKf4FOA8fUQB4pA/7SqiW/6fMFiINAZaR8ZU84FZFWJzXFyqm/Aru0EUYZCj yIEJqWHGAlidkZ6E60mQrCPM8RDT4k57RQKQEoe19bWQP8T6vGoJ0IarbAHbvd4tvX UJIZo09dT5CEKtKkPo1NHuaUR6EDcgInpjZzdEoM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by sourceware.org (Postfix) with ESMTPS id 15BAC385043F; Wed, 5 May 2021 19:37:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 15BAC385043F Received: by mail-ej1-f47.google.com with SMTP id f24so4647705ejc.6; Wed, 05 May 2021 12:37:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ujo7aBAL5RbzXJ88+dC9nooQBca2cNV11OT1NwUMyK0=; b=Y2R/Q6pesaoIZem0yhGVo7j/k4t4XeYwdxfPBnZ2FIaFN4Xe3Ftmg/CH8GlPVIrrVO bxNkZw0+d2o9JUBi3dlA3LyeKvomKjUrLN1Wj48hlPWtf2cGF9BMkf0nvNY6iyniVFa1 LJ9af7LSwfW44t2LSHringrxa3DPq5AKFT9GqMfAOLMOeAd4nywgsas4vcbPgN6QE3j7 cHJ5o8B/WVGYN0XdibQ1cCMd/JB8yCWvBCeL7HGmNqUkfKUPByEh/+kmsQ3t7yTIK3Rx kylipEhtqFHSG5gH0HJVlDRBEht29p1gF3i39MX5rt0o5DRfb3fg8o4opptpV1kTZye0 +i8Q== X-Gm-Message-State: AOAM532P01sWofH1C7NP19ZlZNVtDObz2dQo5GaQ9afhkfLaQugRC/X4 PnO/UtKAJX/Uk05hTG3kD4pppuV3LRNUexJi X-Google-Smtp-Source: ABdhPJwrXylpTIf8H8C+ik/A7R1bFK2CJP8Vtqvur4QKRNK5IF9NYM2gz+MPHXblYAx8ymfI/30pwA== X-Received: by 2002:a17:906:170d:: with SMTP id c13mr329168eje.491.1620243420828; Wed, 05 May 2021 12:37:00 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:00 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 01/10] RISC-V: Simplify memory model code [PR 100265] Date: Wed, 5 May 2021 21:36:42 +0200 Message-Id: <20210505193651.2075405-2-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" We don't have any special treatment of MEMMODEL_SYNC_* values, so let's hide them behind the memmodel_base() function. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_amo_acquire): Ignore MEMMODEL_SYNC_* values. * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Likewise. * config/riscv/riscv.c (riscv_print_operand): Eliminate MEMMODEL_SYNC_* values by calling memmodel_base(). --- gcc/config/riscv/riscv.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 27665e5b58f9..545f3d0cb82c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3350,20 +3350,17 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) acquire portion of memory model MODEL. */ static bool -riscv_memmodel_needs_amo_acquire (enum memmodel model) +riscv_memmodel_needs_amo_acquire (const enum memmodel model) { switch (model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -3376,20 +3373,17 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) implement the release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_release_fence (const enum memmodel model) { switch (model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -3414,6 +3408,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) { machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -3433,12 +3428,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; ", file); break; From patchwork Wed May 5 19:36:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=sotXO1V5; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fb6Rb4gWNz9sPf for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:01 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] Date: Wed, 5 May 2021 21:36:43 +0200 Message-Id: <20210505193651.2075405-3-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The ratified A extension supports '.aq', '.rl' and '.aqrl' as memory ordering suffixes. Let's emit them in case we get a '%A' conversion specifier for riscv_print_operand(). As '%A' was already used for a similar, but restricted, purpose (only '.aq' was emitted so far), this does not require any other changes. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_amo_acquire): Remove function. * config/riscv/riscv.c (riscv_print_amo_memory_ordering_suffix): Add function to emit AMO memory ordering suffixes. * config/riscv/riscv.c (riscv_print_operand): Call riscv_print_amo_memory_ordering_suffix() instead of riscv_memmodel_needs_amo_acquire(). --- gcc/config/riscv/riscv.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 545f3d0cb82c..3edd5c239d7c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3346,24 +3346,26 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } -/* Return true if the .AQ suffix should be added to an AMO to implement the - acquire portion of memory model MODEL. */ +/* Print the memory ordering suffix for AMOs. */ -static bool -riscv_memmodel_needs_amo_acquire (const enum memmodel model) +static void +riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) { switch (model) { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_ACQUIRE: + case MEMMODEL_RELAXED: + break; case MEMMODEL_CONSUME: - return true; - + case MEMMODEL_ACQUIRE: + fputs (".aq", file); + break; case MEMMODEL_RELEASE: - case MEMMODEL_RELAXED: - return false; - + fputs (".rl", file); + break; + case MEMMODEL_ACQ_REL: + case MEMMODEL_SEQ_CST: + fputs (".aqrl", file); + break; default: gcc_unreachable (); } @@ -3428,8 +3430,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) - fputs (".aq", file); + riscv_print_amo_memory_ordering_suffix (file, model); break; case 'F': From patchwork Wed May 5 19:36:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474545 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:02 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] Date: Wed, 5 May 2021 21:36:44 +0200 Message-Id: <20210505193651.2075405-4-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" A previous patch took care, that the proper memory ordering suffixes for AMOs are emitted. Therefore there is no reason to keep the fence generation mechanism for release operations. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Remove function. * config/riscv/riscv.c (riscv_print_operand): Remove %F format specifier. * config/riscv/sync.md: Remove %F format specifier uses. --- gcc/config/riscv/riscv.c | 29 ----------------------------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 8 insertions(+), 37 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 3edd5c239d7c..5fe65776e608 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3371,29 +3371,6 @@ riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ - -static bool -riscv_memmodel_needs_release_fence (const enum memmodel model) -{ - switch (model) - { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_RELEASE: - return true; - - case MEMMODEL_ACQUIRE: - case MEMMODEL_CONSUME: - case MEMMODEL_RELAXED: - return false; - - default: - gcc_unreachable (); - } -} - /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping @@ -3401,7 +3378,6 @@ riscv_memmodel_needs_release_fence (const enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. */ @@ -3433,11 +3409,6 @@ riscv_print_operand (FILE *file, rtx op, int letter) riscv_print_amo_memory_ordering_suffix (file, model); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 747a799e2377..aeeb2e854b68 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -65,7 +65,7 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set (attr "length") (const_int 8))]) (define_insn "atomic_" @@ -76,8 +76,8 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + "amo.%A2 zero,%z1,%0" +) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -89,8 +89,8 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amo.%A3 %0,%z2,%1" +) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,8 +101,8 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amoswap.%A3 %0,%z2,%1" +) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -115,7 +115,7 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + "1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" [(set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" From patchwork Wed May 5 19:36:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:03 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 04/10] RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] Date: Wed, 5 May 2021 21:36:45 +0200 Message-Id: <20210505193651.2075405-5-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Using AMOSWAP as atomic store does not allow us to do sub-word accesses. Further, it is not consistent with our atomic_load () implementation. The benefit of AMOSWAP is that the resulting code sequence will be smaller (comapred to FENCE+STORE), however, this does not weight out for the lack of sub-word accesses. Additionally, HW implementors have claimed that an optimal implementation AMOSWAP is slightly more expensive than FENCE+STORE. So let's use STORE instead of AMOSWAP. gcc/ PR 100265 * config/riscv/sync.md (atomic_store): Remove. --- gcc/config/riscv/sync.md | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index aeeb2e854b68..efd49745a8e2 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -57,17 +57,6 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. -(define_insn "atomic_store" - [(set (match_operand:GPR 0 "memory_operand" "=A") - (unspec_volatile:GPR - [(match_operand:GPR 1 "reg_or_0_operand" "rJ") - (match_operand:SI 2 "const_int_operand")] ;; model - UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC" - "amoswap.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) - (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Wed May 5 19:36:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=qxcPG2nM; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fb6Rs3Ndxz9sPf for ; Thu, 6 May 2021 05:37:29 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 689953A5300F; Wed, 5 May 2021 19:37:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 689953A5300F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1620243429; bh=xu2/DEicl3YWmxUuJgigsYglLms5rC32AQ1NYnfTWZQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=qxcPG2nMw4i/ldz39q2OscsQhI+enQftN/9FU4vz8BpJggv1x71f7SNyvkXLKwnq5 L0upsHrkk2LqWEF2JSNZGWq1HQAqqZipuWdqrBWOhTkQpYR9w1NvBdcsGTVeMQyuxG rIb62TRklgE82mRQ3vwQus3RCLinU8X+nCGsdHuY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) by sourceware.org (Postfix) with ESMTPS id 6B3EC3A4E87B; Wed, 5 May 2021 19:37:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6B3EC3A4E87B Received: by mail-ej1-f41.google.com with SMTP id y7so4633471ejj.9; Wed, 05 May 2021 12:37:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xu2/DEicl3YWmxUuJgigsYglLms5rC32AQ1NYnfTWZQ=; b=ZcjyYXiFIHHdttoT8nCn5HLESFw9sZFCWn6bqga3S+z+7Fa19L+CWmDbastb8T1tZy HljQrjQEroc7SCT/tv5F4ip1sUXViR6oECEqZUSEtf2lJRJ+igLO2ywIIsQGZz+Q/HR2 zIpYD4aTjbUqTD8+Bv+3+Xhgo4Ov8PC9gx1+LYSk2hvq72uzbdcrZyzP+WMSDgVOi66r qWTIWOqz0BzGhXmUeRuGfizp7MEuS4ITozV8te+AW63O32iixq25Ov/3opBEmjMO1wKE tMsaW2Z48LnaZ557S+mYkq0Y57d46naoiyd3CTiJBU43DPHmOT45hGQl1mECn++XuthT KVPQ== X-Gm-Message-State: AOAM53006HRCnXwWHz5/4W4hPczptFdislSoo1nczxoGWAQrEqWviRwt W1/dC0MDglgAZFpJPaC7QaD/JPDnpfAzb3F1 X-Google-Smtp-Source: ABdhPJx7gzEsRKu2rDdpIczk7cvSgELc+I13RNchWKspEmv8PmFdhFaywczcLYEZjV93mcfPLyC/xA== X-Received: by 2002:a17:906:d14c:: with SMTP id br12mr340248ejb.429.1620243424295; Wed, 05 May 2021 12:37:04 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:03 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 05/10] RISC-V: Emit fences according to chosen memory model [PR 100265] Date: Wed, 5 May 2021 21:36:46 +0200 Message-Id: <20210505193651.2075405-6-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" mem_thread_fence gets the desired memory model as operand. Let's emit fences according to this value (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). gcc/ PR 100265 * config/riscv/sync.md (mem_thread_fence): Emit fences according to given operand. * config/riscv/sync.md (mem_fence): Add INSNs for different fence flavours. * config/riscv/sync.md (mem_thread_fence_1): Remove. --- gcc/config/riscv/sync.md | 41 +++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index efd49745a8e2..406db1730b81 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -34,26 +34,41 @@ ;; Memory barriers. (define_expand "mem_thread_fence" - [(match_operand:SI 0 "const_int_operand" "")] ;; model + [(match_operand:SI 0 "const_int_operand")] ;; model "" { - if (INTVAL (operands[0]) != MEMMODEL_RELAXED) - { - rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); - MEM_VOLATILE_P (mem) = 1; - emit_insn (gen_mem_thread_fence_1 (mem, operands[0])); - } + enum memmodel model = memmodel_from_int (INTVAL (operands[0])); + if (!(is_mm_relaxed (model))) + emit_insn (gen_mem_fence (operands[0])); DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. -(define_insn "mem_thread_fence_1" +(define_expand "mem_fence" + [(set (match_dup 1) + (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")] + UNSPEC_MEMORY_BARRIER))] + "" +{ + operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (operands[1]) = 1; +}) + +(define_insn "*mem_fence" [(set (match_operand:BLK 0 "" "") - (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) - (match_operand:SI 1 "const_int_operand" "")] ;; model + (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] + UNSPEC_MEMORY_BARRIER))] "" - "fence\tiorw,iorw") +{ + enum memmodel model = memmodel_from_int (INTVAL (operands[1])); + if (is_mm_consume (model) || is_mm_acquire (model)) + return "fence\tr, rw"; + else if (is_mm_release (model)) + return "fence\trw, w"; + else if (is_mm_acq_rel (model)) + return "fence.tso"; + else + return "fence\trw, rw"; +}) ;; Atomic memory operations. From patchwork Wed May 5 19:36:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=v3QXD5yD; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Fb6Rx00lbz9sPf for ; Thu, 6 May 2021 05:37:32 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 921FC3A5300D; Wed, 5 May 2021 19:37:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 921FC3A5300D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1620243430; bh=xYPWDGbqPd5v4IzvxFqtSfKwuD0I4AtxaZQD68up5ow=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=v3QXD5yDB7AbnGSI22xrHTdZ834Hd5rwpczwpWBaWUDBEdRS7PpHek1DMA47aCo78 cmvZHQGekWJrWxhar1iWjrBjmoNj3BC4B+H0njTp/nJqvRmZxmauD+MX+JaMXrbSsv oTd6Jj8FtX6ILBhb3XSm5DGXSf53YMya8vI8FhMI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by sourceware.org (Postfix) with ESMTPS id 3C8BB383F412; Wed, 5 May 2021 19:37:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3C8BB383F412 Received: by mail-ed1-f42.google.com with SMTP id di13so3403521edb.2; Wed, 05 May 2021 12:37:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xYPWDGbqPd5v4IzvxFqtSfKwuD0I4AtxaZQD68up5ow=; b=jz3ok5T3G7Veqv9bUZoz3WivhOql86YSWpL/4pRuPg4ttxMU1WoATe/J7LjVka203I NQVIXhACh0VYLyCnA6QRVIPUBWkmQ5zHEr0eHunuM7mVEqMoPS/kpgotprvAwB5py8RT hXWr35BkinZATxvqjydnh69OBKncIBc5faW4CFMKC7wDRX3Rt43+1IZRxFQEfYoCnhwL Y/aKo5jzJTk/xfs9jMIKIXM7WSwCW9I0+o2qlox4g5da5UUpAYNFur5Iqa/qjRNKkGrR VX8oZ1Zeq4vh9fXYllTU+3VH576vTC6l4xcLdyP932yz8sL0H4InUxe2wSItqYtc422X NZnQ== X-Gm-Message-State: AOAM531qeMn3hSd2i9o/9rZdHTmUO3J0PIccCR7TpxFwcU2NkT1XI0hV jO3nYOyFzo5dyTg8Q9HWDtstLbAJyPVIJnbZ X-Google-Smtp-Source: ABdhPJzQbtxkMcWJv+SLYbvPM+asMPaMF1ZF9F8vyvU/XrWTrldtUPk84bxEKfL6JXVtYSo7PGDlYQ== X-Received: by 2002:a05:6402:c7:: with SMTP id i7mr724136edu.194.1620243425119; Wed, 05 May 2021 12:37:05 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:04 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 06/10] RISC-V: Implement atomic_{load,store} [PR 100265] Date: Wed, 5 May 2021 21:36:47 +0200 Message-Id: <20210505193651.2075405-7-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" A recent commit introduced a mechanism to emit proper fences for RISC-V. Additionally, we already have emit_move_insn (). Let's reuse this code and provide atomic_load and atomic_store for RISC-V (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). Note, that this works also for sub-word atomics. gcc/ PR 100265 * config/riscv/sync.md (atomic_load): New. * config/riscv/sync.md (atomic_store): New. --- gcc/config/riscv/sync.md | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 406db1730b81..ceec324dfa30 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -72,6 +73,46 @@ ;; Atomic memory operations. +(define_expand "atomic_load" + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "" + { + rtx target = operands[0]; + rtx mem = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_SEQ_CST))); + emit_move_insn (target, mem); + if (is_mm_acquire (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_ACQUIRE))); + + DONE; +}) + +(define_expand "atomic_store" + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "" + { + rtx mem = operands[0]; + rtx val = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_release (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_RELEASE))); + emit_move_insn (mem, val); + + DONE; +}) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Wed May 5 19:36:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:05 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Wed, 5 May 2021 21:36:48 +0200 Message-Id: <20210505193651.2075405-8-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" In order to emit LR/SC sequences, let's provide INSNs, which take care of memory ordering constraints. gcc/ PR 100266 * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New. * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New. * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ceec324dfa30..edff6520b87e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,8 @@ UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER + UNSPEC_LOAD_RESERVED + UNSPEC_STORE_CONDITIONAL ]) (define_code_iterator any_atomic [plus ior xor and]) @@ -113,6 +115,28 @@ DONE; }) +(define_insn "@riscv_load_reserved" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED))] + "TARGET_ATOMIC" + "lr.%A2 %0, %1" +) + +(define_insn "@riscv_store_conditional" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) + (set (match_operand:GPR 1 "memory_operand" "=A") + (unspec_volatile:GPR + [(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC" + "sc.%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Wed May 5 19:36:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:06 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 08/10] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] Date: Wed, 5 May 2021 21:36:49 +0200 Message-Id: <20210505193651.2075405-9-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The current model of the LR and SC INSNs requires a sign-extension to use the generated SImode value for conditional branches, which only operate on XLEN registers. However, the sign-extension is actually not required in both cases, therefore this patch introduces additional INSNs that consume the sign-extension. Rationale: The sign-extension of the loaded value of a LR.W is specified as sign-extended. Therefore, a sign-extension is not required. The sign-extension of the success value a SC.W is specified as non-zero. As sign-extended non-zero value remains non-zero, therefore the sign-extension is not required. gcc/ PR 100266 * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index edff6520b87e..49b860da8ef0 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -125,6 +125,21 @@ "lr.%A2 %0, %1" ) +;; This pattern allows to consume a sign-extension of the loaded value. +;; This is legal, because the specification of LR.W defines the loaded +;; value to be sign-extended. + +(define_insn "riscv_load_reserved" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (unspec_volatile:SI + [(match_operand:SI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED)))] + "TARGET_ATOMIC && TARGET_64BIT" + "lr.w%A2 %0, %1" +) + (define_insn "@riscv_store_conditional" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) @@ -137,6 +152,25 @@ "sc.%A3 %0, %z2, %1" ) +;; This pattern allows to consume a sign-extension of the success +;; value of SC.W, which can then be used for instructions which +;; require values of XLEN-size (e.g. conditional branches). +;; This is legal, because any non-zero value remains non-zero +;; after sign-extension. + +(define_insn "riscv_store_conditional" + [(set (match_operand:DI 0 "register_operand" "=&r") + (sign_extend:DI + (unspec_volatile:SI [(const_int 0)] UNSPEC_STORE_CONDITIONAL))) + (set (match_operand:SI 1 "memory_operand" "=A") + (unspec_volatile:SI + [(match_operand:SI 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC && TARGET_64BIT" + "sc.w%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Wed May 5 19:36:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:07 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 09/10] RISC-V: Provide programmatic implementation of CAS [PR 100266] Date: Wed, 5 May 2021 21:36:50 +0200 Message-Id: <20210505193651.2075405-10-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The existing CAS implementation uses an INSN definition, which provides the core LR/SC sequence. Additionally to that, there is a follow-up code, that evaluates the results and calculates the return values. This has two drawbacks: a) an extension to sub-word CAS implementations is not possible (even if, then it would be unmaintainable), and b) the implementation is hard to maintain/improve. This patch provides a programmatic implementation of CAS, similar like many other architectures are having one. The implementation supports both, RV32 and RV64. Additionally, the implementation does not introduce data dependencies for computation of the return value. Instead, we set the return value (success state of the CAS operation) based on structural information. This approach is also shown in the the RISC-V unpriv spec (as part of the sample code for a compare-and-swap function using LR/SC). The cost of this implementation is a single LI instruction on top, which is actually not required in case of success (it will be overwritten in the success case later). The resulting sequence requires 9 instructions in the success case. The previous implementation required 11 instructions in the succcess case (including a taken branch) and had a "subw;seqz;beqz" sequence, with direct dependencies. Below is the generated code of a 32-bit CAS sequence with the old implementation and the new implementation (ignore the ANDIs below). Old: f00: 419c lw a5,0(a1) f02: 1005272f lr.w a4,(a0) f06: 00f71563 bne a4,a5,f10 f0a: 18c526af sc.w a3,a2,(a0) f0e: faf5 bnez a3,f02 f10: 40f707bb subw a5,a4,a5 f14: 0017b513 seqz a0,a5 f18: c391 beqz a5,f1c f1a: c198 sw a4,0(a1) f1c: 8905 andi a0,a0,1 f1e: 8082 ret New: e28: 4194 lw a3,0(a1) e2a: 4701 li a4,0 e2c: 1005282f lr.w a6,(a0) e30: 00d81963 bne a6,a3,e42 e34: 18c527af sc.w a5,a2,(a0) e38: fbf5 bnez a5,e2c e3a: 4705 li a4,1 e3c: 00177513 andi a0,a4,1 e40: 8082 ret e42: 0105a023 sw a6,0(a1) e46: 00177513 andi a0,a4,1 e4a: 8082 ret gcc/ PR 100266 * config/riscv/riscv-protos.h (riscv_expand_compare_and_swap): New. * config/riscv/riscv.c (riscv_emit_unlikely_jump): New. * config/rsicv/riscv.c (riscv_expand_compare_and_swap): New. * config/rsicv/sync.md (atomic_cas_value_strong): Removed. * config/rsicv/sync.md (atomic_compare_and_swap): Call riscv_expand_compare_and_swap. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.c | 75 +++++++++++++++++++++++++++++++++ gcc/config/riscv/sync.md | 35 +-------------- 3 files changed, 77 insertions(+), 34 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 43d7224d6941..eb7e67d3b95a 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -59,6 +59,7 @@ extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx); +extern void riscv_expand_compare_and_swap (rtx[]); #endif extern rtx riscv_legitimize_call_address (rtx); extern void riscv_set_return_address (rtx, rtx); diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 5fe65776e608..a7b18d650daa 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2496,6 +2496,81 @@ riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code, cons, alt))); } +/* Mark the previous jump instruction as unlikely. */ + +static void +riscv_emit_unlikely_jump (rtx insn) +{ + rtx_insn *jump = emit_jump_insn (insn); + add_reg_br_prob_note (jump, profile_probability::very_unlikely ()); +} + +/* Expand code to perform a compare-and-swap. */ + +extern void +riscv_expand_compare_and_swap (rtx operands[]) +{ + rtx bval, oldval, mem, expval, newval, mod_s, mod_f, scratch, cond1, cond2; + machine_mode mode; + rtx_code_label *begin_label, *end_label; + + bval = operands[0]; + oldval = operands[1]; + mem = operands[2]; + expval = operands[3]; + newval = operands[4]; + mod_s = operands[6]; + mod_f = operands[7]; + mode = GET_MODE (mem); + scratch = gen_reg_rtx (mode); + begin_label = gen_label_rtx (); + end_label = gen_label_rtx (); + + /* No support for sub-word CAS. */ + if (mode == QImode || mode == HImode) + gcc_unreachable (); + + /* We use mod_f for LR and mod_s for SC below, but + RV does not have any guarantees for LR.rl and SC.aq. */ + if (is_mm_acquire (memmodel_base (INTVAL (mod_s))) + && is_mm_relaxed (memmodel_base (INTVAL (mod_f)))) + { + mod_f = GEN_INT (MEMMODEL_ACQUIRE); + mod_s = GEN_INT (MEMMODEL_RELAXED); + } + + /* Since we want to maintain a branch-free good-case, but also want + to not have two branches in the bad-case, we set bval to FALSE + on top of the sequence. In the bad case, we simply jump over + the assignment of bval to TRUE at the end of the sequence. */ + + emit_insn (gen_rtx_SET (bval, gen_rtx_CONST_INT (SImode, FALSE))); + + /* Make sure the scheduler does not move INSNs beyond here. */ + emit_insn (gen_blockage ()); + + emit_label (begin_label); + + emit_insn (gen_riscv_load_reserved (mode, oldval, mem, mod_f)); + + cond1 = gen_rtx_NE (mode, oldval, expval); + riscv_emit_unlikely_jump (gen_cbranch4 (Pmode, cond1, oldval, expval, + end_label)); + + emit_insn (gen_riscv_store_conditional (mode, scratch, mem, newval, mod_s)); + + /* Make sure the scheduler does not move INSNs beyond here. */ + emit_insn (gen_blockage ()); + + cond2 = gen_rtx_NE (mode, scratch, const0_rtx); + riscv_emit_unlikely_jump (gen_cbranch4 (Pmode, cond2, scratch, const0_rtx, + begin_label)); + + emit_insn (gen_rtx_SET (bval, gen_rtx_CONST_INT (SImode, TRUE))); + + emit_label (end_label); +} + /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at least PARM_BOUNDARY bits of alignment, but will be given anything up to PREFERRED_STACK_BOUNDARY bits if the type requires it. */ diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 49b860da8ef0..da8dbf698163 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -207,20 +207,6 @@ "amoswap.%A3 %0,%z2,%1" ) -(define_insn "atomic_cas_value_strong" - [(set (match_operand:GPR 0 "register_operand" "=&r") - (match_operand:GPR 1 "memory_operand" "+A")) - (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") - (match_operand:GPR 3 "reg_or_0_operand" "rJ") - (match_operand:SI 4 "const_int_operand") ;; mod_s - (match_operand:SI 5 "const_int_operand")] ;; mod_f - UNSPEC_COMPARE_AND_SWAP)) - (clobber (match_scratch:GPR 6 "=&r"))] - "TARGET_ATOMIC" - "1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" - [(set (attr "length") (const_int 20))]) - (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output (match_operand:GPR 1 "register_operand" "") ;; val output @@ -232,26 +218,7 @@ (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "TARGET_ATOMIC" { - emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], - operands[3], operands[4], - operands[6], operands[7])); - - rtx compare = operands[1]; - if (operands[3] != const0_rtx) - { - rtx difference = gen_rtx_MINUS (mode, operands[1], operands[3]); - compare = gen_reg_rtx (mode); - emit_insn (gen_rtx_SET (compare, difference)); - } - - if (word_mode != mode) - { - rtx reg = gen_reg_rtx (word_mode); - emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare))); - compare = reg; - } - - emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx))); + riscv_expand_compare_and_swap (operands); DONE; }) From patchwork Wed May 5 19:36:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1474552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:08 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 10/10] RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266] Date: Wed, 5 May 2021 21:36:51 +0200 Message-Id: <20210505193651.2075405-11-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Atomic instructions require zero-offset memory addresses. If we allow all addresses, the nonzero-offset addresses will be prepared in an extra register in an extra instruction before the actual atomic instruction. This patch introduces the predicate "riscv_sync_memory_operand", which restricts the memory operand to be suitable for atomic instructions. gcc/ PR 100266 * config/riscv/sync.md (riscv_sync_memory_operand): New. * config/riscv/sync.md (riscv_load_reserved): Use new predicate. * config/riscv/sync.md (riscv_store_conditional): Likewise. * config/riscv/sync.md (atomic_): Likewise. * config/riscv/sync.md (atomic_fetch_): Likewise. * config/riscv/sync.md (atomic_exchange): Likewise. * config/riscv/sync.md (atomic_compare_and_swap): Likewise. --- gcc/config/riscv/sync.md | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index da8dbf698163..cd9078a40248 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -30,6 +30,10 @@ UNSPEC_STORE_CONDITIONAL ]) +(define_predicate "riscv_sync_memory_operand" + (and (match_operand 0 "memory_operand") + (match_code "reg" "0"))) + (define_code_iterator any_atomic [plus ior xor and]) (define_code_attr atomic_optab [(plus "add") (ior "or") (xor "xor") (and "and")]) @@ -118,7 +122,7 @@ (define_insn "@riscv_load_reserved" [(set (match_operand:GPR 0 "register_operand" "=r") (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "A") + [(match_operand:GPR 1 "riscv_sync_memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_LOAD_RESERVED))] "TARGET_ATOMIC" @@ -133,7 +137,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "A") + [(match_operand:SI 1 "riscv_sync_memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_LOAD_RESERVED)))] "TARGET_ATOMIC && TARGET_64BIT" @@ -143,7 +147,7 @@ (define_insn "@riscv_store_conditional" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) - (set (match_operand:GPR 1 "memory_operand" "=A") + (set (match_operand:GPR 1 "riscv_sync_memory_operand" "=A") (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") (match_operand:SI 3 "const_int_operand")] ;; model @@ -162,7 +166,7 @@ [(set (match_operand:DI 0 "register_operand" "=&r") (sign_extend:DI (unspec_volatile:SI [(const_int 0)] UNSPEC_STORE_CONDITIONAL))) - (set (match_operand:SI 1 "memory_operand" "=A") + (set (match_operand:SI 1 "riscv_sync_memory_operand" "=A") (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") (match_operand:SI 3 "const_int_operand")] ;; model @@ -172,7 +176,7 @@ ) (define_insn "atomic_" - [(set (match_operand:GPR 0 "memory_operand" "+A") + [(set (match_operand:GPR 0 "riscv_sync_memory_operand" "+A") (unspec_volatile:GPR [(any_atomic:GPR (match_dup 0) (match_operand:GPR 1 "reg_or_0_operand" "rJ")) @@ -184,7 +188,7 @@ (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") - (match_operand:GPR 1 "memory_operand" "+A")) + (match_operand:GPR 1 "riscv_sync_memory_operand" "+A")) (set (match_dup 1) (unspec_volatile:GPR [(any_atomic:GPR (match_dup 1) @@ -198,7 +202,7 @@ (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "+A") + [(match_operand:GPR 1 "riscv_sync_memory_operand" "+A") (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) @@ -208,14 +212,14 @@ ) (define_expand "atomic_compare_and_swap" - [(match_operand:SI 0 "register_operand" "") ;; bool output - (match_operand:GPR 1 "register_operand" "") ;; val output - (match_operand:GPR 2 "memory_operand" "") ;; memory - (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value - (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value - (match_operand:SI 5 "const_int_operand" "") ;; is_weak - (match_operand:SI 6 "const_int_operand" "") ;; mod_s - (match_operand:SI 7 "const_int_operand" "")] ;; mod_f + [(match_operand:SI 0 "register_operand" "") ;; bool output + (match_operand:GPR 1 "register_operand" "") ;; val output + (match_operand:GPR 2 "riscv_sync_memory_operand" "") ;; memory + (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value + (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; mod_s + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "TARGET_ATOMIC" { riscv_expand_compare_and_swap (operands);