From patchwork Wed May 5 07:35:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpS63KPBz9sCD for ; Wed, 5 May 2021 17:36:37 +1000 (AEST) Received: from localhost ([::1]:59898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC5C-0007XM-Ct for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:36:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4U-0007X8-Bb for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:50 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57678 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4Q-00022d-83 for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:50 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4N-0000OI-Se; Wed, 05 May 2021 08:35:44 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:29 +0100 Message-Id: <20210505073538.11438-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 01/10] hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Introduce the TYPE_SUN4M_MACHINE and have all sun4m machines inherit it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-2-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 1a00816d9a..9d07fa43d6 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -107,6 +107,8 @@ struct sun4m_hwdef { uint8_t nvram_machine_id; }; +#define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") + const char *fw_cfg_arch_key_name(uint16_t key) { static const struct { @@ -1433,7 +1435,7 @@ static void ss5_class_init(ObjectClass *oc, void *data) static const TypeInfo ss5_type = { .name = MACHINE_TYPE_NAME("SS-5"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss5_class_init, }; @@ -1453,7 +1455,7 @@ static void ss10_class_init(ObjectClass *oc, void *data) static const TypeInfo ss10_type = { .name = MACHINE_TYPE_NAME("SS-10"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss10_class_init, }; @@ -1473,7 +1475,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) static const TypeInfo ss600mp_type = { .name = MACHINE_TYPE_NAME("SS-600MP"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss600mp_class_init, }; @@ -1493,7 +1495,7 @@ static void ss20_class_init(ObjectClass *oc, void *data) static const TypeInfo ss20_type = { .name = MACHINE_TYPE_NAME("SS-20"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss20_class_init, }; @@ -1512,7 +1514,7 @@ static void voyager_class_init(ObjectClass *oc, void *data) static const TypeInfo voyager_type = { .name = MACHINE_TYPE_NAME("Voyager"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = voyager_class_init, }; @@ -1531,7 +1533,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) static const TypeInfo ss_lx_type = { .name = MACHINE_TYPE_NAME("LX"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss_lx_class_init, }; @@ -1550,7 +1552,7 @@ static void ss4_class_init(ObjectClass *oc, void *data) static const TypeInfo ss4_type = { .name = MACHINE_TYPE_NAME("SS-4"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = ss4_class_init, }; @@ -1569,7 +1571,7 @@ static void scls_class_init(ObjectClass *oc, void *data) static const TypeInfo scls_type = { .name = MACHINE_TYPE_NAME("SPARCClassic"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = scls_class_init, }; @@ -1588,10 +1590,20 @@ static void sbook_class_init(ObjectClass *oc, void *data) static const TypeInfo sbook_type = { .name = MACHINE_TYPE_NAME("SPARCbook"), - .parent = TYPE_MACHINE, + .parent = TYPE_SUN4M_MACHINE, .class_init = sbook_class_init, }; +static const TypeInfo sun4m_machine_types[] = { + { + .name = TYPE_SUN4M_MACHINE, + .parent = TYPE_MACHINE, + .abstract = true, + } +}; + +DEFINE_TYPES(sun4m_machine_types) + static void sun4m_register_types(void) { type_register_static(&idreg_info); From patchwork Wed May 5 07:35:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpVP3dpSz9sCD for ; Wed, 5 May 2021 17:38:36 +1000 (AEST) Received: from localhost ([::1]:39806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC78-0002Uy-P8 for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:38:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4a-0007ZC-TQ for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:56 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57682 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4S-00023i-4U for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:56 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4O-0000OI-HI; Wed, 05 May 2021 08:35:46 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:30 +0100 Message-Id: <20210505073538.11438-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 02/10] hw/sparc/sun4m: Introduce Sun4mMachineClass X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Instead of passing the sun4m_hwdef structure via machine_init(), store it into the MachineClass. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-3-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 50 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 9d07fa43d6..c2bc8a9fa5 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -107,7 +107,16 @@ struct sun4m_hwdef { uint8_t nvram_machine_id; }; +struct Sun4mMachineClass { + /*< private >*/ + MachineClass parent_obj; + /*< public >*/ + const struct sun4m_hwdef *hwdef; +}; +typedef struct Sun4mMachineClass Sun4mMachineClass; + #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") +DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) const char *fw_cfg_arch_key_name(uint16_t key) { @@ -839,9 +848,9 @@ static void dummy_fdc_tc(void *opaque, int irq, int level) { } -static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, - MachineState *machine) +static void sun4m_hw_init(MachineState *machine) { + const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; DeviceState *slavio_intctl; unsigned int i; Nvram *nvram; @@ -1368,60 +1377,61 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { /* SPARCstation 5 hardware initialisation */ static void ss5_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[0], machine); + sun4m_hw_init(machine); } /* SPARCstation 10 hardware initialisation */ static void ss10_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[1], machine); + sun4m_hw_init(machine); } /* SPARCserver 600MP hardware initialisation */ static void ss600mp_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[2], machine); + sun4m_hw_init(machine); } /* SPARCstation 20 hardware initialisation */ static void ss20_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[3], machine); + sun4m_hw_init(machine); } /* SPARCstation Voyager hardware initialisation */ static void vger_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[4], machine); + sun4m_hw_init(machine); } /* SPARCstation LX hardware initialisation */ static void ss_lx_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[5], machine); + sun4m_hw_init(machine); } /* SPARCstation 4 hardware initialisation */ static void ss4_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[6], machine); + sun4m_hw_init(machine); } /* SPARCClassic hardware initialisation */ static void scls_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[7], machine); + sun4m_hw_init(machine); } /* SPARCbook hardware initialisation */ static void sbook_init(MachineState *machine) { - sun4m_hw_init(&sun4m_hwdefs[8], machine); + sun4m_hw_init(machine); } static void ss5_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 5"; mc->init = ss5_init; @@ -1431,6 +1441,7 @@ static void ss5_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[0]; } static const TypeInfo ss5_type = { @@ -1442,6 +1453,7 @@ static const TypeInfo ss5_type = { static void ss10_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 10"; mc->init = ss10_init; @@ -1451,6 +1463,7 @@ static void ss10_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[1]; } static const TypeInfo ss10_type = { @@ -1462,6 +1475,7 @@ static const TypeInfo ss10_type = { static void ss600mp_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCserver 600MP"; mc->init = ss600mp_init; @@ -1471,6 +1485,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[2]; } static const TypeInfo ss600mp_type = { @@ -1482,6 +1497,7 @@ static const TypeInfo ss600mp_type = { static void ss20_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 20"; mc->init = ss20_init; @@ -1491,6 +1507,7 @@ static void ss20_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[3]; } static const TypeInfo ss20_type = { @@ -1502,6 +1519,7 @@ static const TypeInfo ss20_type = { static void voyager_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation Voyager"; mc->init = vger_init; @@ -1510,6 +1528,7 @@ static void voyager_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[4]; } static const TypeInfo voyager_type = { @@ -1521,6 +1540,7 @@ static const TypeInfo voyager_type = { static void ss_lx_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation LX"; mc->init = ss_lx_init; @@ -1529,6 +1549,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[5]; } static const TypeInfo ss_lx_type = { @@ -1540,6 +1561,7 @@ static const TypeInfo ss_lx_type = { static void ss4_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 4"; mc->init = ss4_init; @@ -1548,6 +1570,7 @@ static void ss4_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[6]; } static const TypeInfo ss4_type = { @@ -1559,6 +1582,7 @@ static const TypeInfo ss4_type = { static void scls_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCClassic"; mc->init = scls_init; @@ -1567,6 +1591,7 @@ static void scls_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[7]; } static const TypeInfo scls_type = { @@ -1578,6 +1603,7 @@ static const TypeInfo scls_type = { static void sbook_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCbook"; mc->init = sbook_init; @@ -1586,6 +1612,7 @@ static void sbook_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sun4m_hwdefs[8]; } static const TypeInfo sbook_type = { @@ -1598,6 +1625,7 @@ static const TypeInfo sun4m_machine_types[] = { { .name = TYPE_SUN4M_MACHINE, .parent = TYPE_MACHINE, + .class_size = sizeof(Sun4mMachineClass), .abstract = true, } }; From patchwork Wed May 5 07:35:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474124 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpVQ4Flzz9sCD for ; Wed, 5 May 2021 17:38:38 +1000 (AEST) Received: from localhost ([::1]:39974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC79-0002Yz-My for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:38:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4Z-0007YG-RZ for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:55 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57690 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4U-00025f-1k for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:55 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4Q-0000OI-O4; Wed, 05 May 2021 08:35:48 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:31 +0100 Message-Id: <20210505073538.11438-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 03/10] hw/sparc/sun4m: Factor out sun4m_machine_class_init() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Factor out the class_init code common to all machines to sun4m_machine_class_init(). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-4-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 103 ++++------------------------------------------- 1 file changed, 8 insertions(+), 95 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index c2bc8a9fa5..56f927e66c 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -1374,58 +1374,15 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, }; -/* SPARCstation 5 hardware initialisation */ -static void ss5_init(MachineState *machine) +static void sun4m_machine_class_init(ObjectClass *oc, void *data) { - sun4m_hw_init(machine); -} - -/* SPARCstation 10 hardware initialisation */ -static void ss10_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCserver 600MP hardware initialisation */ -static void ss600mp_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCstation 20 hardware initialisation */ -static void ss20_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCstation Voyager hardware initialisation */ -static void vger_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCstation LX hardware initialisation */ -static void ss_lx_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCstation 4 hardware initialisation */ -static void ss4_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} - -/* SPARCClassic hardware initialisation */ -static void scls_init(MachineState *machine) -{ - sun4m_hw_init(machine); -} + MachineClass *mc = MACHINE_CLASS(oc); -/* SPARCbook hardware initialisation */ -static void sbook_init(MachineState *machine) -{ - sun4m_hw_init(machine); + mc->init = sun4m_hw_init; + mc->block_default_type = IF_SCSI; + mc->default_boot_order = "c"; + mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static void ss5_class_init(ObjectClass *oc, void *data) @@ -1434,13 +1391,8 @@ static void ss5_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 5"; - mc->init = ss5_init; - mc->block_default_type = IF_SCSI; mc->is_default = true; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[0]; } @@ -1456,13 +1408,8 @@ static void ss10_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 10"; - mc->init = ss10_init; - mc->block_default_type = IF_SCSI; mc->max_cpus = 4; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[1]; } @@ -1478,13 +1425,8 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCserver 600MP"; - mc->init = ss600mp_init; - mc->block_default_type = IF_SCSI; mc->max_cpus = 4; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[2]; } @@ -1500,13 +1442,8 @@ static void ss20_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 20"; - mc->init = ss20_init; - mc->block_default_type = IF_SCSI; mc->max_cpus = 4; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[3]; } @@ -1522,12 +1459,7 @@ static void voyager_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation Voyager"; - mc->init = vger_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[4]; } @@ -1543,12 +1475,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation LX"; - mc->init = ss_lx_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[5]; } @@ -1564,12 +1491,7 @@ static void ss4_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCstation 4"; - mc->init = ss4_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[6]; } @@ -1585,12 +1507,7 @@ static void scls_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCClassic"; - mc->init = scls_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[7]; } @@ -1606,12 +1523,7 @@ static void sbook_class_init(ObjectClass *oc, void *data) Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); mc->desc = "Sun4m platform, SPARCbook"; - mc->init = sbook_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; smc->hwdef = &sun4m_hwdefs[8]; } @@ -1626,6 +1538,7 @@ static const TypeInfo sun4m_machine_types[] = { .name = TYPE_SUN4M_MACHINE, .parent = TYPE_MACHINE, .class_size = sizeof(Sun4mMachineClass), + .class_init = sun4m_machine_class_init, .abstract = true, } }; From patchwork Wed May 5 07:35:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474125 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpVV3PR5z9sCD for ; Wed, 5 May 2021 17:38:42 +1000 (AEST) Received: from localhost ([::1]:40472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC7E-0002l4-5X for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:38:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4d-0007ds-G6 for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:59 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57696 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4W-00027U-2h for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:59 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4S-0000OI-MH; Wed, 05 May 2021 08:35:50 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:32 +0100 Message-Id: <20210505073538.11438-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 04/10] hw/sparc/sun4m: Register machine types in sun4m_machine_types[] X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-5-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 100 +++++++++++++++++------------------------------ 1 file changed, 36 insertions(+), 64 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 56f927e66c..a625c41cd3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -1396,12 +1396,6 @@ static void ss5_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[0]; } -static const TypeInfo ss5_type = { - .name = MACHINE_TYPE_NAME("SS-5"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss5_class_init, -}; - static void ss10_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1413,12 +1407,6 @@ static void ss10_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[1]; } -static const TypeInfo ss10_type = { - .name = MACHINE_TYPE_NAME("SS-10"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss10_class_init, -}; - static void ss600mp_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1430,12 +1418,6 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[2]; } -static const TypeInfo ss600mp_type = { - .name = MACHINE_TYPE_NAME("SS-600MP"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss600mp_class_init, -}; - static void ss20_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1447,12 +1429,6 @@ static void ss20_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[3]; } -static const TypeInfo ss20_type = { - .name = MACHINE_TYPE_NAME("SS-20"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss20_class_init, -}; - static void voyager_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1463,12 +1439,6 @@ static void voyager_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[4]; } -static const TypeInfo voyager_type = { - .name = MACHINE_TYPE_NAME("Voyager"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = voyager_class_init, -}; - static void ss_lx_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1479,12 +1449,6 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[5]; } -static const TypeInfo ss_lx_type = { - .name = MACHINE_TYPE_NAME("LX"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss_lx_class_init, -}; - static void ss4_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1495,12 +1459,6 @@ static void ss4_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[6]; } -static const TypeInfo ss4_type = { - .name = MACHINE_TYPE_NAME("SS-4"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = ss4_class_init, -}; - static void scls_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1511,12 +1469,6 @@ static void scls_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[7]; } -static const TypeInfo scls_type = { - .name = MACHINE_TYPE_NAME("SPARCClassic"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = scls_class_init, -}; - static void sbook_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1527,14 +1479,44 @@ static void sbook_class_init(ObjectClass *oc, void *data) smc->hwdef = &sun4m_hwdefs[8]; } -static const TypeInfo sbook_type = { - .name = MACHINE_TYPE_NAME("SPARCbook"), - .parent = TYPE_SUN4M_MACHINE, - .class_init = sbook_class_init, -}; - static const TypeInfo sun4m_machine_types[] = { { + .name = MACHINE_TYPE_NAME("SS-5"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss5_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-10"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss10_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-600MP"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss600mp_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-20"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss20_class_init, + }, { + .name = MACHINE_TYPE_NAME("Voyager"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = voyager_class_init, + }, { + .name = MACHINE_TYPE_NAME("LX"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss_lx_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-4"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss4_class_init, + }, { + .name = MACHINE_TYPE_NAME("SPARCClassic"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = scls_class_init, + }, { + .name = MACHINE_TYPE_NAME("SPARCbook"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = sbook_class_init, + }, { .name = TYPE_SUN4M_MACHINE, .parent = TYPE_MACHINE, .class_size = sizeof(Sun4mMachineClass), @@ -1551,16 +1533,6 @@ static void sun4m_register_types(void) type_register_static(&afx_info); type_register_static(&prom_info); type_register_static(&ram_info); - - type_register_static(&ss5_type); - type_register_static(&ss10_type); - type_register_static(&ss600mp_type); - type_register_static(&ss20_type); - type_register_static(&voyager_type); - type_register_static(&ss_lx_type); - type_register_static(&ss4_type); - type_register_static(&scls_type); - type_register_static(&sbook_type); } type_init(sun4m_register_types) From patchwork Wed May 5 07:35:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpSC1Mnxz9sSs for ; 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Wed, 05 May 2021 08:35:50 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:33 +0100 Message-Id: <20210505073538.11438-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 05/10] hw/sparc/sun4m: Fix code style for checkpatch.pl X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé We are going to move this code, fix its style first. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-6-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index a625c41cd3..956216591b 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -1181,11 +1181,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0xef0400000ULL, .esp_base = 0xef0800000ULL, .le_base = 0xef0c00000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, .aux2_base = 0xff1a01000ULL, .ecc_base = 0xf00000000ULL, - .ecc_version = 0x10000000, // version 0, implementation 1 + .ecc_version = 0x10000000, /* version 0, implementation 1 */ .nvram_machine_id = 0x72, .machine_id = ss10_id, .iommu_version = 0x03000000, @@ -1204,11 +1204,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0xef0081000ULL, .esp_base = 0xef0080000ULL, .le_base = 0xef0060000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, - .aux2_base = 0xff1a01000ULL, // XXX should not exist + .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ .ecc_base = 0xf00000000ULL, - .ecc_version = 0x00000000, // version 0, implementation 0 + .ecc_version = 0x00000000, /* version 0, implementation 0 */ .nvram_machine_id = 0x71, .machine_id = ss600mp_id, .iommu_version = 0x01000000, @@ -1230,7 +1230,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .esp_base = 0xef0800000ULL, .le_base = 0xef0c00000ULL, .bpp_base = 0xef4800000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, .aux2_base = 0xff1a01000ULL, .dbri_base = 0xee0000000ULL, @@ -1249,7 +1249,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { } }, .ecc_base = 0xf00000000ULL, - .ecc_version = 0x20000000, // version 0, implementation 2 + .ecc_version = 0x20000000, /* version 0, implementation 2 */ .nvram_machine_id = 0x72, .machine_id = ss20_id, .iommu_version = 0x13000000, @@ -1270,7 +1270,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0x78400000, .esp_base = 0x78800000, .le_base = 0x78c00000, - .apc_base = 0x71300000, // pmc + .apc_base = 0x71300000, /* pmc */ .aux1_base = 0x71900000, .aux2_base = 0x71910000, .nvram_machine_id = 0x80, @@ -1352,7 +1352,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { /* SPARCbook */ { .iommu_base = 0x10000000, - .tcx_base = 0x50000000, // XXX + .tcx_base = 0x50000000, /* XXX */ .slavio_base = 0x70000000, .ms_kb_base = 0x71000000, .serial_base = 0x71100000, From patchwork Wed May 5 07:35:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474122 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpSC0WyHz9sCD for ; Wed, 5 May 2021 17:36:43 +1000 (AEST) Received: from localhost ([::1]:60182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC5J-0007g5-1v for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:36:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4b-0007b0-UP for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:57 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57706 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4X-000281-RT for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:57 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4U-0000OI-MI; Wed, 05 May 2021 08:35:51 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:34 +0100 Message-Id: <20210505073538.11438-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 06/10] hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Remove the sun4m_hwdefs[] array by moving assigning the structure fields directly in each machine class_init() function. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210503171303.822501-7-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 248 ++++++++++++++++++++++------------------------- 1 file changed, 118 insertions(+), 130 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 956216591b..263732b904 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -1138,9 +1138,22 @@ enum { ss600mp_id, }; -static const struct sun4m_hwdef sun4m_hwdefs[] = { - /* SS-5 */ - { +static void sun4m_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->init = sun4m_hw_init; + mc->block_default_type = IF_SCSI; + mc->default_boot_order = "c"; + mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; +} + +static void ss5_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss5_hwdef = { .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1165,9 +1178,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss5_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SS-10 */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 5"; + mc->is_default = true; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &ss5_hwdef; +} + +static void ss10_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss10_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1190,9 +1213,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss10_id, .iommu_version = 0x03000000, .max_mem = 0xf00000000ULL, - }, - /* SS-600MP */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 10"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss10_hwdef; +} + +static void ss600mp_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss600mp_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1213,9 +1246,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss600mp_id, .iommu_version = 0x01000000, .max_mem = 0xf00000000ULL, - }, - /* SS-20 */ - { + }; + + mc->desc = "Sun4m platform, SPARCserver 600MP"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss600mp_hwdef; +} + +static void ss20_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss20_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1254,9 +1297,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss20_id, .iommu_version = 0x13000000, .max_mem = 0xf00000000ULL, - }, - /* Voyager */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 20"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss20_hwdef; +} + +static void voyager_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef voyager_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1277,9 +1330,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = vger_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* LX */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation Voyager"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &voyager_hwdef; +} + +static void ss_lx_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss_lx_hwdef = { .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1301,9 +1363,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = lx_id, .iommu_version = 0x04000000, .max_mem = 0x10000000, - }, - /* SS-4 */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation LX"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); + smc->hwdef = &ss_lx_hwdef; +} + +static void ss4_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss4_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .cs_base = 0x6c000000, @@ -1325,9 +1396,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss4_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SPARCClassic */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 4"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &ss4_hwdef; +} + +static void scls_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef scls_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1348,9 +1428,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = scls_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SPARCbook */ - { + }; + + mc->desc = "Sun4m platform, SPARCClassic"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); + smc->hwdef = &scls_hwdef; +} + +static void sbook_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef sbook_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, /* XXX */ .slavio_base = 0x70000000, @@ -1371,112 +1460,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = sbook_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, -}; - -static void sun4m_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->init = sun4m_hw_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static void ss5_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation 5"; - mc->is_default = true; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - smc->hwdef = &sun4m_hwdefs[0]; -} - -static void ss10_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation 10"; - mc->max_cpus = 4; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - smc->hwdef = &sun4m_hwdefs[1]; -} - -static void ss600mp_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCserver 600MP"; - mc->max_cpus = 4; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - smc->hwdef = &sun4m_hwdefs[2]; -} - -static void ss20_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation 20"; - mc->max_cpus = 4; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - smc->hwdef = &sun4m_hwdefs[3]; -} - -static void voyager_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation Voyager"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - smc->hwdef = &sun4m_hwdefs[4]; -} - -static void ss_lx_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation LX"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - smc->hwdef = &sun4m_hwdefs[5]; -} - -static void ss4_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCstation 4"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - smc->hwdef = &sun4m_hwdefs[6]; -} - -static void scls_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); - - mc->desc = "Sun4m platform, SPARCClassic"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - smc->hwdef = &sun4m_hwdefs[7]; -} - -static void sbook_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + }; mc->desc = "Sun4m platform, SPARCbook"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - smc->hwdef = &sun4m_hwdefs[8]; + smc->hwdef = &sbook_hwdef; } static const TypeInfo sun4m_machine_types[] = { From patchwork Wed May 5 07:35:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpXt63xQz9sCD for ; Wed, 5 May 2021 17:40:46 +1000 (AEST) Received: from localhost ([::1]:48528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC9E-0005yk-UX for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:40:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4c-0007cF-HS for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:58 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57712 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4a-0002Bb-8l for qemu-devel@nongnu.org; Wed, 05 May 2021 03:35:58 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4V-0000OI-Cs; Wed, 05 May 2021 08:35:54 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:35 +0100 Message-Id: <20210505073538.11438-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 07/10] hw/sparc: Allow building without the leon3 machine X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé When building without the leon3 machine, we get this link failure: /usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manager': target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack' This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c, which is only build when CONFIG_LEON3 is selected. Fix by moving the leon3_cache_control_int() / leon3_irq_manager() (which are specific to the leon3 machine) to hw/sparc/leon3.c. Move the trace events along (but don't rename them). leon3_irq_ack() is now locally used, declare it static to reduce its scope. Reviewed-by: Richard Henderson Reviewed-by: KONRAD Frederic Tested-by: KONRAD Frederic Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20210428141655.387430-2-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/leon3.c | 37 ++++++++++++++++++++++++++++++++++++- hw/sparc/trace-events | 2 ++ target/sparc/cpu.h | 6 ------ target/sparc/int32_helper.c | 37 ------------------------------------- target/sparc/trace-events | 4 ---- 5 files changed, 38 insertions(+), 48 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7e16eea9e6..98e3789cf8 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque) env->regbase[6] = s->sp; } -void leon3_irq_ack(void *irq_manager, int intno) +static void leon3_cache_control_int(CPUSPARCState *env) +{ + uint32_t state = 0; + + if (env->cache_control & CACHE_CTRL_IF) { + /* Instruction cache state */ + state = env->cache_control & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + trace_int_helper_icache_freeze(); + } + + env->cache_control &= ~CACHE_STATE_MASK; + env->cache_control |= state; + } + + if (env->cache_control & CACHE_CTRL_DF) { + /* Data cache state */ + state = (env->cache_control >> 2) & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + trace_int_helper_dcache_freeze(); + } + + env->cache_control &= ~(CACHE_STATE_MASK << 2); + env->cache_control |= (state << 2); + } +} + +static void leon3_irq_ack(void *irq_manager, int intno) { grlib_irqmp_ack((DeviceState *)irq_manager, intno); } @@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level) } } +static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) +{ + leon3_irq_ack(irq_manager, intno); + leon3_cache_control_int(env); +} + static void leon3_generic_hw_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index 355b07ae05..dfb53dc1a2 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 # leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650b..ff8ae73002 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp); int cpu_cwp_dec(CPUSPARCState *env1, int cwp); void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); -/* int_helper.c */ -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); - /* sun4m.c, sun4u.c */ void cpu_check_irqs(CPUSPARCState *env); -/* leon3.c */ -void leon3_irq_ack(void *irq_manager, int intno); - #if defined (TARGET_SPARC64) static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 817a463a17..d008dbdb65 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs) } #endif } - -#if !defined(CONFIG_USER_ONLY) -static void leon3_cache_control_int(CPUSPARCState *env) -{ - uint32_t state = 0; - - if (env->cache_control & CACHE_CTRL_IF) { - /* Instruction cache state */ - state = env->cache_control & CACHE_STATE_MASK; - if (state == CACHE_ENABLED) { - state = CACHE_FROZEN; - trace_int_helper_icache_freeze(); - } - - env->cache_control &= ~CACHE_STATE_MASK; - env->cache_control |= state; - } - - if (env->cache_control & CACHE_CTRL_DF) { - /* Data cache state */ - state = (env->cache_control >> 2) & CACHE_STATE_MASK; - if (state == CACHE_ENABLED) { - state = CACHE_FROZEN; - trace_int_helper_dcache_freeze(); - } - - env->cache_control &= ~(CACHE_STATE_MASK << 2); - env->cache_control |= (state << 2); - } -} - -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) -{ - leon3_irq_ack(irq_manager, intno); - leon3_cache_control_int(env); -} -#endif diff --git a/target/sparc/trace-events b/target/sparc/trace-events index 6a064e2327..e925ddd1cc 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x" int_helper_clear_softint(uint32_t softint) "new 0x%08x" int_helper_write_softint(uint32_t softint) "new 0x%08x" -# int32_helper.c -int_helper_icache_freeze(void) "Instruction cache: freeze" -int_helper_dcache_freeze(void) "Data cache: freeze" - # win_helper.c win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x" win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x" From patchwork Wed May 5 07:35:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpVW4w2Mz9sCD for ; Wed, 5 May 2021 17:38:43 +1000 (AEST) Received: from localhost ([::1]:40582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC7F-0002nl-N2 for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:38:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4f-0007g2-HJ for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:01 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57718 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4d-0002DS-T6 for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:01 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4Y-0000OI-WA; Wed, 05 May 2021 08:35:58 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:36 +0100 Message-Id: <20210505073538.11438-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 08/10] hw/sparc64: Remove unused "hw/char/serial.h" header X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20210428141655.387430-3-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sparc64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index e3f9219a10..cc0b9bd30d 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "hw/boards.h" -#include "hw/char/serial.h" #include "hw/sparc/sparc64.h" #include "qemu/timer.h" #include "sysemu/reset.h" From patchwork Wed May 5 07:35:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpZ26NSHz9sCD for ; Wed, 5 May 2021 17:41:46 +1000 (AEST) Received: from localhost ([::1]:50926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leCAC-00071i-TV for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:41:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4i-0007jB-25 for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57724 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4f-0002EX-QE for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:03 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4c-0000OI-Ha; Wed, 05 May 2021 08:36:00 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:37 +0100 Message-Id: <20210505073538.11438-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 09/10] hw/sparc64: Fix code style for checkpatch.pl X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20210428141655.387430-4-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sparc64.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index cc0b9bd30d..fd29a79edc 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env) return; } cs = env_cpu(env); - /* check if TM or SM in SOFTINT are set - setting these also causes interrupt 14 */ + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { pil |= 1 << 14; } - /* The bit corresponding to psrpil is (1<< psrpil), the next bit - is (2 << psrpil). */ + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); From patchwork Wed May 5 07:35:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1474128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZpY940q5z9sCD for ; Wed, 5 May 2021 17:41:01 +1000 (AEST) Received: from localhost ([::1]:49042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1leC9T-0006BE-HL for incoming@patchwork.ozlabs.org; Wed, 05 May 2021 03:40:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4m-0007l0-1J for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:08 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57730 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1leC4g-0002Ex-H8 for qemu-devel@nongnu.org; Wed, 05 May 2021 03:36:07 -0400 Received: from host81-154-26-71.range81-154.btcentralplus.com ([81.154.26.71] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1leC4e-0000OI-CU; Wed, 05 May 2021 08:36:01 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 5 May 2021 08:35:38 +0100 Message-Id: <20210505073538.11438-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> References: <20210505073538.11438-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 81.154.26.71 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 10/10] hw/sparc*: Move cpu_check_irqs() to target/sparc/ X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Since cpu_check_irqs() doesn't reference to anything outside of CPUSPARCState, it better belongs to the architectural code in target/, rather than the hardware specific code in hw/. Note: while we moved the trace events, we don't rename them. Remark: this allows us to build the leon3 machine stand alone, fixing this link failure (because cpu_check_irqs is defined in hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected): /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20210428141655.387430-5-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 32 ------------------ hw/sparc/trace-events | 2 -- hw/sparc64/sparc64.c | 66 ------------------------------------- hw/sparc64/trace-events | 4 --- target/sparc/int32_helper.c | 33 +++++++++++++++++++ target/sparc/int64_helper.c | 66 +++++++++++++++++++++++++++++++++++++ target/sparc/trace-events | 8 +++++ 7 files changed, 107 insertions(+), 104 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 263732b904..42e139849e 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -170,38 +170,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr, } } -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - if (env->pil_in && (env->interrupt_index == 0 || - (env->interrupt_index & ~15) == TT_EXTINT)) { - unsigned int i; - - for (i = 15; i > 0; i--) { - if (env->pil_in & (1 << i)) { - int old_interrupt = env->interrupt_index; - - env->interrupt_index = TT_EXTINT | i; - if (old_interrupt != env->interrupt_index) { - cs = env_cpu(env); - trace_sun4m_cpu_interrupt(i); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = env_cpu(env); - trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env = &cpu->env; diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index dfb53dc1a2..d3a30a816a 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -1,8 +1,6 @@ # See docs/devel/tracing.txt for syntax documentation. # sun4m.c -sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" -sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index fd29a79edc..8654e955eb 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -34,72 +34,6 @@ #define TICK_MAX 0x7fffffffffffffffULL -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - uint32_t pil = env->pil_in | - (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ - if (env->ivec_status & 0x20) { - return; - } - cs = env_cpu(env); - /* - * check if TM or SM in SOFTINT are set - * setting these also causes interrupt 14 - */ - if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { - pil |= 1 << 14; - } - - /* - * The bit corresponding to psrpil is (1<< psrpil), - * the next bit is (2 << psrpil). - */ - if (pil < (2 << env->psrpil)) { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - return; - } - - if (cpu_interrupts_enabled(env)) { - - unsigned int i; - - for (i = 15; i > env->psrpil; i--) { - if (pil & (1 << i)) { - int old_interrupt = env->interrupt_index; - int new_interrupt = TT_EXTINT | i; - - if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt - && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { - trace_sparc64_cpu_check_irqs_noset_irq(env->tl, - cpu_tsptr(env)->tt, - new_interrupt); - } else if (old_interrupt != new_interrupt) { - env->interrupt_index = new_interrupt; - trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, - new_interrupt); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, - env->interrupt_index); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUState *cs = CPU(cpu); diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index a0b29987d2..b85d14c30c 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64 # sparc64.c -sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" -sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" -sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" -sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index d008dbdb65..82e8418e46 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" #include "exec/log.h" @@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index) return excp_names[exception_index]; } +void cpu_check_irqs(CPUSPARCState *env) +{ + CPUState *cs; + + /* We should be holding the BQL before we mess with IRQs */ + g_assert(qemu_mutex_iothread_locked()); + + if (env->pil_in && (env->interrupt_index == 0 || + (env->interrupt_index & ~15) == TT_EXTINT)) { + unsigned int i; + + for (i = 15; i > 0; i--) { + if (env->pil_in & (1 << i)) { + int old_interrupt = env->interrupt_index; + + env->interrupt_index = TT_EXTINT | i; + if (old_interrupt != env->interrupt_index) { + cs = env_cpu(env); + trace_sun4m_cpu_interrupt(i); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { + cs = env_cpu(env); + trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); + env->interrupt_index = 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 7fb8ab211c..793e57c536 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -62,6 +62,72 @@ static const char * const excp_names[0x80] = { }; #endif +void cpu_check_irqs(CPUSPARCState *env) +{ + CPUState *cs; + uint32_t pil = env->pil_in | + (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); + + /* We should be holding the BQL before we mess with IRQs */ + g_assert(qemu_mutex_iothread_locked()); + + /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ + if (env->ivec_status & 0x20) { + return; + } + cs = env_cpu(env); + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ + if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { + pil |= 1 << 14; + } + + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ + if (pil < (2 << env->psrpil)) { + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); + env->interrupt_index = 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + return; + } + + if (cpu_interrupts_enabled(env)) { + + unsigned int i; + + for (i = 15; i > env->psrpil; i--) { + if (pil & (1 << i)) { + int old_interrupt = env->interrupt_index; + int new_interrupt = TT_EXTINT | i; + + if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt + && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { + trace_sparc64_cpu_check_irqs_noset_irq(env->tl, + cpu_tsptr(env)->tt, + new_interrupt); + } else if (old_interrupt != new_interrupt) { + env->interrupt_index = new_interrupt; + trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, + new_interrupt); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, + env->interrupt_index); + env->interrupt_index = 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); diff --git a/target/sparc/trace-events b/target/sparc/trace-events index e925ddd1cc..75e7093d5f 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -10,10 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, u mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64 mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64 +# int32_helper.c +sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" +sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" + # int64_helper.c int_helper_set_softint(uint32_t softint) "new 0x%08x" int_helper_clear_softint(uint32_t softint) "new 0x%08x" int_helper_write_softint(uint32_t softint) "new 0x%08x" +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" # win_helper.c win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"