From patchwork Fri Apr 30 07:12:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VdDntQq+; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FWk9z5hd8z9sXS for ; Fri, 30 Apr 2021 17:13:42 +1000 (AEST) Received: from localhost ([::1]:60714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcNLH-0008Si-EF for incoming@patchwork.ozlabs.org; Fri, 30 Apr 2021 03:13:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcNKl-0008RQ-T0; Fri, 30 Apr 2021 03:13:07 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:33313) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcNKk-0000Ia-72; Fri, 30 Apr 2021 03:13:07 -0400 Received: by mail-ej1-x62f.google.com with SMTP id t4so20419308ejo.0; Fri, 30 Apr 2021 00:13:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cN0ExC4hpilg3BSjgCzDHWu5wIAJzffjsHPo8GpLC24=; b=VdDntQq+L9iAWwe+03GCAtZ+nHJ1VQs5B9P3oe6GG6xzvNE+WWI/IMg1gtMt/NZJ4x iezF28cWIHNKO7AyA/WC5EIPoVJFdxRXzuW1ESXO0NCsiGuN4y1OLSyLzX1k7QmZ/3s0 graT/Vgjmp/W9XJnmWMZ7kZZu13V83bPZmOqZZdxORu+Lq/iMSXlE2d/FQlN3lJjvSEp wb7k9QrZBnWb44oZMKdy5kBm9Ko08zx0hutZTgWWDfxikA9X+RAAFLuPu+hYGk1HMaBI o5zjDjv8+T8rjW0PTUTrmsCcm1X/Kqs4ygSMjF9Rv06Vz2g5g4Rsv/eOh83h+M+S47V5 p33g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cN0ExC4hpilg3BSjgCzDHWu5wIAJzffjsHPo8GpLC24=; b=UD/TOgt+1gfLzQpkHkzA4waVtuDJLG1Kn+2FPQ38RR0h/MkqbsfADrpd53xG4M4caz J7BeYBDOa9J4VxgwNTTFq/LBTsr2FhlxfYJGRjp9m6+QvSZ9Z4a0WUT3AylrxR/NYef5 ZGS493VObER9UMkYQctB3XKlALL9DRXFzYKfPs1erIbE+xIsi67kF752xe++IOc3Phas tcK/VGSKG/DMOTWf1uQfP4JmkzNaCkf85UIC4zqQRCX3wOVRw+dB0Awve/28XppKA7KI uaqdXz+j2H6aQUZGxoFdJQ+kuWCwNT8fHtSiR1fBrYOlqAXhbHFx/xUaDTHzcduY4iTt SJxg== X-Gm-Message-State: AOAM531Ue8mGA1IosSkjWtletjJ/K52ifzbKlcHQmVE9y/S2np8R0IzA nlKjJixfPu1h8wdO+fUb5xI= X-Google-Smtp-Source: ABdhPJw21oCNnDMBFMnIfVlksyV0AuEhtXpc0OsHiGSWmAp52Rz2X3xCgWSq1sMQ7JwU2lil3RP3UA== X-Received: by 2002:a17:906:a017:: with SMTP id p23mr2730821ejy.460.1619766783988; Fri, 30 Apr 2021 00:13:03 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:03 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Date: Fri, 30 Apr 2021 15:12:55 +0800 Message-Id: <20210430071302.1489082-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use "static const char * const" for ethclk_names hw/riscv/sifive_u.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7b59942369..1b8af0c07a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -96,9 +96,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk"; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; + static const char * const ethclk_names[2] = { "pclk", "hclk" }; if (ms->dtb) { fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); @@ -413,8 +413,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); - qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, - sizeof(ethclk_names)); + qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", + (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); qemu_fdt_setprop(fdt, nodename, "local-mac-address", s->soc.gem.conf.macaddr.a, ETH_ALEN); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); From patchwork Fri Apr 30 07:12:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472008 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=lXfk7y00; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FWkBF6b8Sz9t0G for ; Fri, 30 Apr 2021 17:13:57 +1000 (AEST) Received: from localhost ([::1]:60836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcNLX-000053-Lk for incoming@patchwork.ozlabs.org; Fri, 30 Apr 2021 03:13:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcNKr-0008VQ-Kz; Fri, 30 Apr 2021 03:13:13 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:37580) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcNKn-0000Ky-9O; Fri, 30 Apr 2021 03:13:13 -0400 Received: by mail-ed1-x530.google.com with SMTP id y26so1789647eds.4; Fri, 30 Apr 2021 00:13:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dIT3vmQFKYv5ZTBRKHJJ6NBlN5EHRUN2L+JtZ54C9+0=; b=lXfk7y008KzSLqXSQIk1PbF/zOuH4Zb3lTUyoiaRo1/+NPEl3QymG4ehwQCr57Lu3I dwoXEP7ZWQaAAaLidBv89eLSeDFdSodqhq2Ewt0T0oEKS20SF7f52+/MyGmFezTTwR8O 9z89sPSSnCADCYQBItdIPzkQrf2WFMudAyNhyzNqHkgJHBEIL3PbioLeHMIDyTzAxfzT aDHcrmDqx74aetIR8bU1rrke5S/9LpMcT/7JjHgXTNWeF8iTnZgp+PsjU223JnCO424j ZTdcj9Bhd+hnLFU6Al1G2UVAPar3EqfSK4E8se8G6D9GM5HwxfzAmGIQS58gVLA3/EKk se1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dIT3vmQFKYv5ZTBRKHJJ6NBlN5EHRUN2L+JtZ54C9+0=; b=Hom2pkPUGjntZCHhUsaK5vWpTdSazZZupC4Lsr6KsqRL5STbHRkjCqeLunM2us4Z17 30SQBtCcWbDsR/mVHhpaqDo2fgsFFBmgD1LOyIsQOzK36hVd8nxsN5FDnaZ/D8vOR9Sf cEGoKEmwXVNPuEnoQOSZEkb6e7rw7WdX2QpJm1F6K2b7W9Ek841k4//FsUyzBOGLWHD+ HiD3eSvaoIdjFNb3UAJYRdrIXmYSHN6TxdyYf8vqifcPZmp0x9eyQ/oRT7ZM6mG60UfA dz8BEV4hjs57K821pYigWYvKvaEDCtI3HGDc3xBW0NBR3Fzl2rmw7KP04brFubdoCIKC Zxzw== X-Gm-Message-State: AOAM533AWAJc3yl2Vu0CFwu4XTlVPzUuBFPZWIWXGgiALlEawNWuB+KT CEq+A+Hc2CHW4gMl+FksJGQ= X-Google-Smtp-Source: ABdhPJymBxLMouSw4jg51PtwuxLyKsgbKvGi/lFcer3lx3tCNYK+D0C7iALUaV1DDRMokvFVMB2QKw== X-Received: by 2002:a50:f296:: with SMTP id f22mr4021101edm.254.1619766787285; Fri, 30 Apr 2021 00:13:07 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:06 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper Date: Fri, 30 Apr 2021 15:12:56 +0800 Message-Id: <20210430071302.1489082-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the compatible strings for the SiFive test device node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use "static const char * const" for compat hw/riscv/virt.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c0dc69ff33..992f1c58a9 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -395,8 +395,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, (long)memmap[VIRT_TEST].base); qemu_fdt_add_subnode(fdt, name); { - const char compat[] = "sifive,test1\0sifive,test0\0syscon"; - qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); + static const char * const compat[3] = { + "sifive,test1", "sifive,test0", "syscon" + }; + qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, + ARRAY_SIZE(compat)); } qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, From patchwork Fri Apr 30 07:12:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=V+NSzWr6; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FWkF14b9Mz9sWP for ; Fri, 30 Apr 2021 17:16:21 +1000 (AEST) Received: from localhost ([::1]:40522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcNNr-0003Tf-Ip for incoming@patchwork.ozlabs.org; Fri, 30 Apr 2021 03:16:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52576) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcNKs-000058-Pk; Fri, 30 Apr 2021 03:13:14 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:37599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcNKq-0000O1-Ip; Fri, 30 Apr 2021 03:13:14 -0400 Received: by mail-ej1-x631.google.com with SMTP id w3so103755315ejc.4; Fri, 30 Apr 2021 00:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xOvNP79h5k0ipvW8dOj5SnVBHNc0TchMfqvMAAD0ZMI=; b=V+NSzWr653hHLfoqf+zZxoeBL6/fOpenbfbpHORdmBm2mLtJ4I2aQdTzQFpQUsvTlU BKiHdAnmKGYKJPN4EZmPaP4Un+nyNb22fdaulWYW8N7BRm22fxNgUFGMGv15jMp5ITSF vmo5ZbQS0zIcBWewD2BqSW6LfnugAfEbt0/zD6yYtXRwVTR1yE1yEfgKIbtrBSVpCL9T 032OSFuTA/Vr8MOCUs3h7XBJz3oYfRQh1fph88LoXYcp9cOcRHRMo0YH9ZGEavsnMrjd zydP9/ccfrmo1bEaHpq6TJR8b1QVWsrCNnL6n2vakjlbitzGu+3hJRJD86NZc6Id1wtW mLrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xOvNP79h5k0ipvW8dOj5SnVBHNc0TchMfqvMAAD0ZMI=; b=ZqH2n1unszVIH0VIcoxc1o2t4PgFy17TnklZBwE6Dh1uTU+EeKQleoMXy88MTEBC2Q lXI2PlH14YSJbRdvys7AFWoHSM4oCW/mMhQnCl6OGs5+3HM9BIiu/i1tJqKl7gU9DjHj 0IQtExDMqK+hkHZCn/4Ba8zIHDkKI37IophbwIKTwOvqhTxCbrfvWmhmoyKGvpPkXff2 wl4kJ03zTbvkYiJIhE9ttoGdmIhv9ggNqsaweg3f5P295LaoTEgk/pZyumkjdzwuyvvu CkKY9i6GCRA9Nt7A3gR/u/iADvh+QSrU7x7P3jXR/6peirb0lcM/WMVPajX5g+V8yX7G +8kA== X-Gm-Message-State: AOAM533YEWb0EFzsI3oAPiyIcmWd1/AuDYai3wcHyB8eheb50MgtFja4 XBn3X3YWyPBHq0w+AWZbVoK/kJ3mwFA= X-Google-Smtp-Source: ABdhPJx7JHTL3Qrfdf31ToHERKW9Bf34cm8n9MIPtf+AJwq993c1n06dVEscJm0NJQhwfGtmEtIToQ== X-Received: by 2002:a17:906:7942:: with SMTP id l2mr2642679ejo.314.1619766790763; Fri, 30 Apr 2021 00:13:10 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:10 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings Date: Fri, 30 Apr 2021 15:12:57 +0800 Message-Id: <20210430071302.1489082-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use "static const char * const" for clint_compat hw/riscv/sifive_u.c | 6 +++++- hw/riscv/spike.c | 6 +++++- hw/riscv/virt.c | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1b8af0c07a..fd5cf7513b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -99,6 +99,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; static const char * const ethclk_names[2] = { "pclk", "hclk" }; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; if (ms->dtb) { fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); @@ -210,7 +213,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, nodename = g_strdup_printf("/soc/clint@%lx", (long)memmap[SIFIVE_U_DEV_CLINT].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, nodename, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 0x0, memmap[SIFIVE_U_DEV_CLINT].size); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ec7cb2f707..f094bb2158 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -60,6 +60,9 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; char *core_name, *cpu_name, *intc_name; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -153,7 +156,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, (memmap[SPIKE_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 992f1c58a9..4b32dc734f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -195,6 +195,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, char *name, *clint_name, *plic_name, *clust_name; hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; + static const char * const clint_compat[2] = { + "sifive,clint0", "riscv,clint0" + }; if (mc->dtb) { fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); @@ -300,7 +303,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", + (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", From patchwork Fri Apr 30 07:12:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Dd+HItGo; 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:13 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 4/8] hw/riscv: Support the official PLIC DT bindings Date: Fri, 30 Apr 2021 15:12:58 +0800 Message-Id: <20210430071302.1489082-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the compatible string in the upstream Linux kernel. "riscv,plic0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - use "static const char * const" for plic_compat hw/riscv/sifive_u.c | 6 +++++- hw/riscv/virt.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fd5cf7513b..b55e56890c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -102,6 +102,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; + static const char * const plic_compat[2] = { + "sifive,plic-1.0.0", "riscv,plic0" + }; if (ms->dtb) { fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); @@ -271,7 +274,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, (long)memmap[SIFIVE_U_DEV_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); + qemu_fdt_setprop_string_array(fdt, nodename, "compatible", + (char **)&plic_compat, ARRAY_SIZE(plic_compat)); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4b32dc734f..8a8ff04dab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -198,6 +198,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; + static const char * const plic_compat[2] = { + "sifive,plic-1.0.0", "riscv,plic0" + }; if (mc->dtb) { fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); @@ -320,7 +323,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, "#address-cells", FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); + qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", + (char **)&plic_compat, ARRAY_SIZE(plic_compat)); qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); From patchwork Fri Apr 30 07:12:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ewWGhqWC; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FWkJQ6KmRz9sWP for ; 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:17 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices Date: Fri, 30 Apr 2021 15:12:59 +0800 Message-Id: <20210430071302.1489082-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The supported device bullet list has an additional space before each entry, which makes a wrong indentation level. Correct it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/riscv/microchip-icicle-kit.rst | 20 +++++++-------- docs/system/riscv/sifive_u.rst | 30 +++++++++++----------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index 4fe97bce3f..e803131763 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -15,16 +15,16 @@ Supported devices The ``microchip-icicle-kit`` machine supports the following devices: - * 1 E51 core - * 4 U54 cores - * Core Level Interruptor (CLINT) - * Platform-Level Interrupt Controller (PLIC) - * L2 Loosely Integrated Memory (L2-LIM) - * DDR memory controller - * 5 MMUARTs - * 1 DMA controller - * 2 GEM Ethernet controllers - * 1 SDHC storage controller +* 1 E51 core +* 4 U54 cores +* Core Level Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* L2 Loosely Integrated Memory (L2-LIM) +* DDR memory controller +* 5 MMUARTs +* 1 DMA controller +* 2 GEM Ethernet controllers +* 1 SDHC storage controller Boot options ------------ diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 98e7562848..dcdfbda931 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -9,21 +9,21 @@ Supported devices The ``sifive_u`` machine supports the following devices: - * 1 E51 / E31 core - * Up to 4 U54 / U34 cores - * Core Level Interruptor (CLINT) - * Platform-Level Interrupt Controller (PLIC) - * Power, Reset, Clock, Interrupt (PRCI) - * L2 Loosely Integrated Memory (L2-LIM) - * DDR memory controller - * 2 UARTs - * 1 GEM Ethernet controller - * 1 GPIO controller - * 1 One-Time Programmable (OTP) memory with stored serial number - * 1 DMA controller - * 2 QSPI controllers - * 1 ISSI 25WP256 flash - * 1 SD card in SPI mode +* 1 E51 / E31 core +* Up to 4 U54 / U34 cores +* Core Level Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* Power, Reset, Clock, Interrupt (PRCI) +* L2 Loosely Integrated Memory (L2-LIM) +* DDR memory controller +* 2 UARTs +* 1 GEM Ethernet controller +* 1 GPIO controller +* 1 One-Time Programmable (OTP) memory with stored serial number +* 1 DMA controller +* 2 QSPI controllers +* 1 ISSI 25WP256 flash +* 1 SD card in SPI mode Please note the real world HiFive Unleashed board has a fixed configuration of 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode. From patchwork Fri Apr 30 07:13:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1472009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=DOMkwaAC; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FWkBW5VSxz9sXS for ; Fri, 30 Apr 2021 17:14:11 +1000 (AEST) Received: from localhost ([::1]:33316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcNLl-0000Qp-Nk for incoming@patchwork.ozlabs.org; Fri, 30 Apr 2021 03:14:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcNL3-0000OP-E6; Fri, 30 Apr 2021 03:13:26 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:34743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcNL1-0000US-3C; Fri, 30 Apr 2021 03:13:25 -0400 Received: by mail-ed1-x532.google.com with SMTP id i3so55716034edt.1; Fri, 30 Apr 2021 00:13:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fElpJp1+gGfKDOYhMNPiyFsjOP8fGNaHPojf2JKI0UE=; b=DOMkwaACvvdCEonFPiTR9zV9sOvi7lFjXk4VoXskT9NloL0D6OHjBNacWUyL0WzeOP ppnYapT6gxnSepPsTe5NjE/pPlsByhz2BJYKJTIrZnl56R23zxhICyFbU4tXpCEcLq/Q soWHagK+T6Iqp3oHL1Po+zcdOCP5DaJHWnk3pOebJVrOo826x/Xm8AteSI/erIoSf8pB Y2GhmGsYOkL4qPd2xvGV3lU5U2ZaN1LVhFqO4nx1xLZaNPVHotUvZEd+n5RMmHwvoE1C t/WSc7ysd7gxFO0GPZznHCBNZoWz91KPL+G9eGwNBCQ3JvQLvsYi01m+5i3Q++rvgPyE Ojqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fElpJp1+gGfKDOYhMNPiyFsjOP8fGNaHPojf2JKI0UE=; b=TZiZWONc0ZQTLLdHnYM8L528AGOmVH9LWNKqc8oN7kCpo0lkU0RuovgTkP+Ye2mlgM cg6ja1N63ZAqK/dJgzJNnESYO5K+a09+tks2LT8H5IQjxbIWOw+Od7ffYUIfGGmpjwFk JOSALxTmULR2axWysAcG4k8pNdVsGYMX1t+VdcYURNW5o5N/XkZJFejp/kEkEtn2nUiH uWUh3a6+3wY5dOiVTsGnAz1oA3diYsC+rHbsLr7YTdzvjQBMJ/LJITyJHCAMTgCNFpi7 Xpx1WoKyb/LBnayxHE6LuZkqZxk3TwwpTQxZM99skSGM0OYtnoK3JFQsdXJDwUVwmn2v AXqA== X-Gm-Message-State: AOAM530JGIjs19/FhwPnqwKMnMyaZEgVsttnLd6szOuTR1oy54VNAJtc tf21qPZlOz0VanoONcB/VNQ= X-Google-Smtp-Source: ABdhPJwbXian9OO0L8A3SXry/8SAFm7PXBD57dM3z/c66RCxy55l+isScQ+xSWwsYV9iOhbgch7Tvg== X-Received: by 2002:a05:6402:5211:: with SMTP id s17mr4006441edd.327.1619766801450; Fri, 30 Apr 2021 00:13:21 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:21 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage Date: Fri, 30 Apr 2021 15:13:00 +0800 Message-Id: <20210430071302.1489082-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Update the 'sifive_u' machine documentation to mention the '-dtb' option that can be used to pass a custom DTB to QEMU. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/riscv/sifive_u.rst | 47 +++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index dcdfbda931..32d0a1b85d 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -36,12 +36,21 @@ Hardware configuration information ---------------------------------- The ``sifive_u`` machine automatically generates a device tree blob ("dtb") -which it passes to the guest. This provides information about the addresses, -interrupt lines and other configuration of the various devices in the system. -Guest software should discover the devices that are present in the generated -DTB instead of using a DTB for the real hardware, as some of the devices are -not modeled by QEMU and trying to access these devices may cause unexpected -behavior. +which it passes to the guest, if there is no ``-dtb`` option. This provides +information about the addresses, interrupt lines and other configuration of +the various devices in the system. Guest software should discover the devices +that are present in the generated DTB instead of using a DTB for the real +hardware, as some of the devices are not modeled by QEMU and trying to access +these devices may cause unexpected behavior. + +If users want to provide their own DTB, they can use the ``-dtb`` option. +These DTBs should have the following requirements: + +* The /cpus node should contain at least one subnode for E51 and the number + of subnodes should match QEMU's ``-smp`` option +* The /memory reg size should match QEMU’s selected ram_size via ``-m`` +* Should contain a node for the CLINT device with a compatible string + "riscv,clint0" if using with OpenSBI BIOS images Boot options ------------ @@ -122,6 +131,32 @@ To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine: -initrd /path/to/rootfs.ext4 \ -append "root=/dev/ram" +Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT +node in fu540-c000.dtsi in the Linux kernel, + +.. code-block:: none + + clint: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg = <0x00 0x2000000 0x00 0x10000>; + }; + +with the following command line options: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 8G \ + -display none -serial stdio \ + -kernel arch/riscv/boot/Image \ + -dtb arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb \ + -initrd /path/to/rootfs.ext4 \ + -append "root=/dev/ram" + To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine in 32-bit mode, use the rv32_defconfig configuration. A patch is required to fix the 32-bit boot issue for Linux kernel v5.10. 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:24 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 7/8] hw/riscv: Use macros for BIOS image names Date: Fri, 30 Apr 2021 15:13:01 +0800 Message-Id: <20210430071302.1489082-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/boot.h | 5 +++++ hw/riscv/sifive_u.c | 6 ++---- hw/riscv/spike.c | 6 ++---- hw/riscv/virt.c | 6 ++---- 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 11a21dd584..0e89400b09 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -24,6 +24,11 @@ #include "hw/loader.h" #include "hw/riscv/riscv_hart.h" +#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" +#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf" +#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" +#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf" + bool riscv_is_32bit(RISCVHartArrayState *harts); target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b55e56890c..f30cc8004b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -561,12 +561,10 @@ static void sifive_u_machine_init(MachineState *machine) if (riscv_is_32bit(&s->soc.u_cpus)) { firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv32-generic-fw_dynamic.bin", - start_addr, NULL); + RISCV32_BIOS_BIN, start_addr, NULL); } else { firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv64-generic-fw_dynamic.bin", - start_addr, NULL); + RISCV64_BIOS_BIN, start_addr, NULL); } if (machine->kernel_filename) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index f094bb2158..98932fba62 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -259,13 +259,11 @@ static void spike_board_init(MachineState *machine) */ if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv32-generic-fw_dynamic.elf", - memmap[SPIKE_DRAM].base, + RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, htif_symbol_callback); } else { firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv64-generic-fw_dynamic.elf", - memmap[SPIKE_DRAM].base, + RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, htif_symbol_callback); } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8a8ff04dab..b03c5f8b5b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -682,12 +682,10 @@ static void virt_machine_init(MachineState *machine) if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv32-generic-fw_dynamic.bin", - start_addr, NULL); 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b19sm574462edd.66.2021.04.30.00.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 00:13:28 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot Date: Fri, 30 Apr 2021 15:13:02 +0800 Message-Id: <20210430071302.1489082-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com> References: <20210430071302.1489082-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the Microchip Icicle Kit machine only supports using '-bios' to load the HSS, and does not support '-kernel' for direct kernel booting just like other RISC-V machines do. One has to use U-Boot which is chain-loaded by HSS, to load a kernel for testing. This is not so convenient. Adding '-kernel' support together with the existing '-bios', we follow the following table to select which payload we execute: -bios | -kernel | payload ------+------------+-------- N | N | HSS Y | don't care | HSS N | Y | kernel This ensures backwards compatibility with how we used to expose '-bios' to users. When '-kernel' is used for direct boot, '-dtb' must be present to provide a valid device tree for the board, as we don't generate device tree. When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload like U-Boot or OS kernel directly. Documentation is updated to describe the direct kernel boot. Note as of today there is still no PolarFire SoC support in the upstream Linux kernel hence the document does not include instructions for that. It will be updated in the future. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/riscv/microchip-icicle-kit.rst | 30 ++++++-- hw/riscv/microchip_pfsoc.c | 81 +++++++++++++++++++++- 2 files changed, 103 insertions(+), 8 deletions(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index e803131763..54ced661e3 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -31,17 +31,37 @@ Boot options The ``microchip-icicle-kit`` machine can start using the standard -bios functionality for loading its BIOS image, aka Hart Software Services (HSS_). -HSS loads the second stage bootloader U-Boot from an SD card. It does not -support direct kernel loading via the -kernel option. One has to load kernel -from U-Boot. +HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel +can be loaded from U-Boot. It also supports direct kernel booting via the +-kernel option along with the device tree blob via -dtb. When direct kernel +boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload +like U-Boot or OS kernel directly. + +The user provided DTB should have the following requirements: + +* The /cpus node should contain at least one subnode for E51 and the number + of subnodes should match QEMU's ``-smp`` option +* The /memory reg size should match QEMU’s selected ram_size via ``-m`` +* Should contain a node for the CLINT device with a compatible string + "riscv,clint0" + +QEMU follows below truth table to select which payload to execute: + +===== ========== ======= +-bios -kernel payload +===== ========== ======= + N N HSS + Y don't care HSS + N Y kernel +===== ========== ======= The memory is set to 1537 MiB by default which is the minimum required high memory size by HSS. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1537 MiB when less than 1537 MiB ram is detected. -Boot the machine ----------------- +Running HSS +----------- HSS 2020.12 release is tested at the time of writing. To build an HSS image that can be booted by the ``microchip-icicle-kit`` machine, type the following diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c4146b7a6b..1919c09f2f 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -53,6 +53,7 @@ #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" +#include "sysemu/device_tree.h" #include "sysemu/sysemu.h" /* @@ -462,6 +463,12 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) MemoryRegion *mem_high = g_new(MemoryRegion, 1); MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); uint64_t mem_high_size; + hwaddr firmware_load_addr; + const char *firmware_name; + bool kernel_as_payload = false; + target_ulong firmware_end_addr, kernel_start_addr; + uint64_t kernel_entry; + uint32_t fdt_load_addr; DriveInfo *dinfo = drive_get_next(IF_SD); /* Sanity check on RAM size */ @@ -506,9 +513,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, mem_high_alias); - /* Load the firmware */ - riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); - /* Attach an SD card */ if (dinfo) { CadenceSDHCIState *sdhci = &(s->soc.sdhci); @@ -518,6 +522,77 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) &error_fatal); qdev_realize_and_unref(card, sdhci->bus, &error_fatal); } + + /* + * We follow the following table to select which payload we execute. + * + * -bios | -kernel | payload + * -------+------------+-------- + * N | N | HSS + * Y | don't care | HSS + * N | Y | kernel + * + * This ensures backwards compatibility with how we used to expose -bios + * to users but allows them to run through direct kernel booting as well. + * + * When -kernel is used for direct boot, -dtb must be present to provide + * a valid device tree for the board, as we don't generate device tree. + */ + + if (machine->kernel_filename && machine->dtb) { + int fdt_size; + machine->fdt = load_device_tree(machine->dtb, &fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + + firmware_name = RISCV64_BIOS_BIN; + firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base; + kernel_as_payload = true; + } + + if (!kernel_as_payload) { + firmware_name = BIOS_FILENAME; + firmware_load_addr = RESET_VECTOR; + } + + /* Load the firmware */ + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, + firmware_load_addr, NULL); + + if (kernel_as_payload) { + kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, + firmware_end_addr); + + kernel_entry = riscv_load_kernel(machine->kernel_filename, + kernel_start_addr, NULL); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-end", end); + } + + if (machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", + "bootargs", machine->kernel_cmdline); + } + + /* Compute the fdt load address in dram */ + fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, + machine->ram_size, machine->fdt); + /* Load the reset vector */ + riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, + memmap[MICROCHIP_PFSOC_ENVM_DATA].base, + memmap[MICROCHIP_PFSOC_ENVM_DATA].size, + kernel_entry, fdt_load_addr, machine->fdt); + } } static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)