From patchwork Thu Apr 15 12:10:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ioanna Alifieraki X-Patchwork-Id: 1466594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FLdV21pv8z9sWK; Thu, 15 Apr 2021 22:11:04 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1lX0pl-0001KT-UG; Thu, 15 Apr 2021 12:10:57 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lX0pj-0001Jv-TG for kernel-team@lists.ubuntu.com; Thu, 15 Apr 2021 12:10:55 +0000 Received: from mail-wm1-f72.google.com ([209.85.128.72]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lX0pj-0002rw-Kr for kernel-team@lists.ubuntu.com; Thu, 15 Apr 2021 12:10:55 +0000 Received: by mail-wm1-f72.google.com with SMTP id j3-20020a1c55030000b029012e7c06101aso1185715wmb.5 for ; Thu, 15 Apr 2021 05:10:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=xZ0dowDgdC6seKDLCU3zKk02QPcKThEfQpPT77PRFvo=; b=h92i7FBPix/RGEGhJ/4gR5wfsgun1cdOgtqlsSHy8aNnUphvdiNJg+pVCkS3FSZrl7 pFHO7ZAS+Fhm9eMfaElgqBiDoG5hbnCYU43cmOFwzGQGixsunhdV8dvkI6ypBdgzC6Y1 0bB+wsCd7POz8ToWisczwkcvAu9JH9Cq3BF361BJthiTWyddqTjr1wjMlzZQCe7ZQTUQ +bGYWwhRaUVx6XAXrdHpM8keheKrWCebdOk8GNScfONjpbtEFUuHbtOdDRO6Ed2X891C cDPU04906IxaZnFil1C6/hXRiLveaFOiQcoUbYvyf2Hydr5KRgtu7vRl4QvqqwHncQOj 1FZA== X-Gm-Message-State: AOAM5302SWLHQSvIMw+1GGCIl4loCKcJGsV3n6LLNkpDA8kvi/l4OZ/2 JK2nCvbH2J9c8eCSHHVSoHmSu7b0ygTJEx6lqVEfeGlHnuQC+51USCjd115Hbfwp24aqQ6iORcK ocK87uuQvizCCmvsQlEDFxV3ROwN6vUrnEVZFe2R9Mw== X-Received: by 2002:a1c:f20e:: with SMTP id s14mr2866842wmc.100.1618488655084; Thu, 15 Apr 2021 05:10:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMx99crJougLCpyYLP61J43Sw5HfWsKp/Cf6AV9OJMu5xmSVe56/eRw7opFcs2J8N2eBWQrg== X-Received: by 2002:a1c:f20e:: with SMTP id s14mr2866822wmc.100.1618488654857; Thu, 15 Apr 2021 05:10:54 -0700 (PDT) Received: from localhost ([2a02:587:c4ba:c200:dbb:6aa7:4f67:207f]) by smtp.gmail.com with ESMTPSA id f23sm2433099wmf.37.2021.04.15.05.10.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 Apr 2021 05:10:54 -0700 (PDT) From: Ioanna Alifieraki To: kernel-team@lists.ubuntu.com Subject: [SRU][Focal][PATCH] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Date: Thu, 15 Apr 2021 15:10:54 +0300 Message-Id: <20210415121054.9757-1-ioanna-maria.alifieraki@canonical.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Bhupesh Sharma BugLink: https://bugs.launchpad.net/bugs/1919275 TCR_EL1.TxSZ, which controls the VA space size, is configured by a single kernel image to support either 48-bit or 52-bit VA space. If the ARMv8.2-LVA optional feature is present and we are running with a 64KB page size, then it is possible to use 52-bits of address space for both userspace and kernel addresses. However, any kernel binary that supports 52-bit must also be able to fall back to 48-bit at early boot time if the hardware feature is not present. Since TCR_EL1.T1SZ indicates the size of the memory region addressed by TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like makedumpfile and crash-utility need to read this value from vmcoreinfo for determining if a virtual address lies in the linear map range. While at it also add documentation for TCR_EL1.T1SZ variable being added to vmcoreinfo. It indicates the size offset of the memory region addressed by TTBR1_EL1. Signed-off-by: Bhupesh Sharma Tested-by: John Donnelly Tested-by: Kamlakant Patel Tested-by: Amit Daniel Kachhap Reviewed-by: James Morse Reviewed-by: Amit Daniel Kachhap Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Ard Biesheuvel Cc: Dave Anderson Cc: Kazuhito Hagio Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: kexec@lists.infradead.org Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com [catalin.marinas@arm.com: removed vabits_actual from the commit log] Signed-off-by: Catalin Marinas (backported from commit bbdbc11804ff0b4130e7550113b452e96a74d16e) [hook 1: resolve conflict in documentation] Signed-off-by: Ioanna Alifieraki Acked-by: Tim Gardner Acked-by: Guilherme G. Piccoli --- Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 10 ++++++++++ 3 files changed, 22 insertions(+) diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst index 007a6b86e0ee..ba1aed57e55d 100644 --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst @@ -393,6 +393,17 @@ KERNELOFFSET The kernel randomization offset. Used to compute the page offset. If KASLR is disabled, this value is zero. +TCR_EL1.T1SZ +------------ + +Indicates the size offset of the memory region addressed by TTBR1_EL1. +The region size is 2^(64-T1SZ) bytes. + +TTBR1_EL1 is the table base address register specified by ARMv8-A +architecture which is used to lookup the page-tables for the Virtual +addresses in the higher VA range (refer to ARMv8 ARM document for +more details). + arm === diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 3df60f97da1f..a0f789fa25f3 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -215,6 +215,7 @@ #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) #define TCR_TxSZ_WIDTH 6 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) #define TCR_EPD0_SHIFT 7 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c index ca4c3e12d8c5..ec8095bfe23e 100644 --- a/arch/arm64/kernel/crash_core.c +++ b/arch/arm64/kernel/crash_core.c @@ -6,6 +6,14 @@ #include #include +#include + +static inline u64 get_tcr_el1_t1sz(void); + +static inline u64 get_tcr_el1_t1sz(void) +{ + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; +} void arch_crash_save_vmcoreinfo(void) { @@ -15,5 +23,7 @@ void arch_crash_save_vmcoreinfo(void) kimage_voffset); vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", PHYS_OFFSET); + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", + get_tcr_el1_t1sz()); vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); }