From patchwork Sun Apr 11 07:39:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464749 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=j/78xC8R; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3h427Y5z9sVq for ; Sun, 11 Apr 2021 17:40:52 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 79ED180484; Sun, 11 Apr 2021 09:40:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="j/78xC8R"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 671528066A; Sun, 11 Apr 2021 09:40:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D01FD80202 for ; Sun, 11 Apr 2021 09:40:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhYlpdnL; Sun, 11 Apr 2021 09:40:12 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126812; bh=zdUDFhnoPEU01b4unN3IUHVAFPWb5bpEn06dc+Buhq0=; h=From; b=j/78xC8RjWbf2Wkb6qvYfvnPxXDtmr4GvgshaaMmt1F+zesWKiAEsPKXjCNIwchOb DgxpxESVwW/Yxv6ztbKpnEq3BARZCaQFTJeBzcYrD8bL1rsJGPPr8o55Ye2ZdbEZun BuXbA0mJnLMOIpvnVoDvOl8lpxYKH8hw7DtiLiYgmUrcQa+6b0tWS08Fri3hzxvYXM 7v2ysYIVcA5mj1tcQ3Ehs1YTsPDBSSAkTTm2i9pPV+e7b4mHyYrI1INtbUWusFjRqA NQ9k2oqgqvJE7RWShWl7KVzV9CW484Zvq1JYtCzPCf0zO5/vkSlZNtCeUw+BkO6jnS AF85z0uLjiKkA== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7dc cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=CNNU2WlDxd8r9xRg_hQA:9 a=xmb-EsYY8bH0VWELuYED:22 a=pHzHmUro8NiASowvMSCR:22 a=n87TN5wuljxrRezIQYnT:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 01/12] pinctrl: single: fix format of structure documentation Date: Sun, 11 Apr 2021 09:39:39 +0200 Message-Id: <20210411073950.24772-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfNjbC0TV8S4FkEsrF3fEuaYeY9GgdmFq4FstyXWNj0bW//CZ5tQiUeOqHXvhKDiVzMZ4Qten+exY7pZA9vIeVd8tzba3rGYOHJRN7V4gW6/0zooolbHF MSHfTzD5QqRj2RK2LV8RCU/0VqYc8pT3xHGndEbUFU/xVkVVo60jmV994xayv/k4zEduRYlgCyw3easpjepiqwOveEmMje58L7MXcLNZh7oThfeeHcWUgtkn VA7ew/ZxIinZaRyPkveMuMDqDwhR03mE6SoeU8kHcEaemNY7kqZYF1wAoQ8QjqXvu/D34cMyXrp1kf/Cl1YltKp9ZLYLHA/TlfJSaEzZOEPLoL/RAZNVoVsH uiADaegqIkGIl2ngEvjCCTYUPub10Q== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean U-Boot adopted the kernel-doc annotation style. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 20c3c82aa9..c9a6c272bf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -10,23 +10,50 @@ #include #include +/** + * struct single_pdata - platform data + * @base: first configuration register + * @offset: index of last configuration register + * @mask: configuration-value mask bits + * @width: configuration register bit width + * @bits_per_mux: true if one register controls more than one pin + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + fdt_addr_t base; + int offset; + u32 mask; + int width; bool bits_per_mux; }; +/** + * struct single_fdt_pin_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls only one pin. + * + * @reg: configuration register offset + * @val: configuration register value + */ struct single_fdt_pin_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ + fdt32_t reg; + fdt32_t val; }; +/** + * struct single_fdt_bits_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls more than one pin. + * + * @reg: configuration register offset + * @val: configuration register value + * @mask: configuration register mask + */ struct single_fdt_bits_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ - fdt32_t mask; /* configuration register mask */ + fdt32_t reg; + fdt32_t val; + fdt32_t mask; }; /** From patchwork Sun Apr 11 07:39:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464750 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=pj4Pd1pl; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3hB2h2Tz9sVq for ; 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Sun, 11 Apr 2021 09:40:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhZlpdnU; Sun, 11 Apr 2021 09:40:13 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126813; bh=ASlkKTD37pqtbvwGTkPuC4gLO/4NXIHhrW2xKH8S/20=; h=From; b=pj4Pd1pl18VnTZf9LU3tqoogawmd8jzSAagPxyau+br6qNMWvFFedrqNOISbTbwLm IkU0aAOxw+oRtLfJXKzeIl+V+SNHvnHJovPsUnXCNUA7Zml3eql7XKFg2M/hfmjnHc xG5QMznUe0PUCUYQLNJX0JaqmQQfCgmDVeCjUCu1WADMo68oi+FhUmsEHTyvtrK8+x F2SxVsOOMV4KJd/CRppXLllWN5YDk/Jtg1yoJMnQQNVokACmIcBPRtnc+NTWGXRE8U gaMwwuGYfgcNCM6sXIpBRtkS28vQcgzu7Y2MpxH8t9AtTLTY/8OkwEYKziMiVGeFdr FkRxV4nlUPllw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7dd cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=sozttTNsAAAA:8 a=v0YLU9JjO2Y4mDxuVjMA:9 a=xmb-EsYY8bH0VWELuYED:22 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 02/12] pinctrl: single: fix the loop counter variable type Date: Sun, 11 Apr 2021 09:39:40 +0200 Message-Id: <20210411073950.24772-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfD33vhLSjuNxfUwRQ9tvS5sPQSgppOjLqVYk2b/dzNJf8TvmiERjoolqiDxs2WrPYwBxobpNrYu7Pb2CP/Dkdi6aKW0nqULM4KblmfLsgPJgEJsNI06P T9a6wN8kdSYXnvw4WpR9L+S26Ac89KGDGTf5OId0nWGBg6Oe8kuwu9iPyi7hmi2mBSR1rKWjLGXwjJKu5/AWOKpw043x4qbslYd8ilzhCPgVMTSw9PNz98TF GAFQncga1DI7bCNHcDensowpdz6NexDKqdajTNuYuD1xAYGKBDtHjLudcRi+7YgsP98oe8FEAst/btTBKXick7bRv1AbEUZNjOC634j7DlGrpnQ6a0nLiqxI g2PS3tDlwHfrYcQnP4FikfZgE19lIA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The 'n' variable is used as a loop counter, not as a physical address, and is used in a comparison with an int. So it makes sense to change its type from phys_addr_t to int. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass Reviewed-by: Pratyush Yadav --- (no changes since v2) Changes in v2: - Updated commit message. - Added Simon Glass review tag. - Added Pratyush Yadav review tag. drivers/pinctrl/pinctrl-single.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index c9a6c272bf..49ed15211d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -75,8 +75,8 @@ static int single_configure_pins(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_pin_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_pin_cfg); + phys_addr_t reg; u32 val; for (n = 0; n < count; n++, pins++) { @@ -109,8 +109,8 @@ static int single_configure_bits(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_bits_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_bits_cfg); + phys_addr_t reg; u32 val, mask; for (n = 0; n < count; n++, pins++) { From patchwork Sun Apr 11 07:39:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464752 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=ay8OWbEx; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3hh5hDBz9sVq for ; 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Sun, 11 Apr 2021 09:40:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhZlpdne; Sun, 11 Apr 2021 09:40:13 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126813; bh=yWhdoUJKRp2th0HecPQIEXplkalTulfUaCnVgtbEfPk=; h=From; b=ay8OWbExqNeBsFiJugdiBqlc6fGXZbwgQck3URpfmu/v050/cLSSdKsEAaZiL93Ik WOsvBeToN1kSMO13MWAzd86vpQvC29m5voVjiGzSW86Z5M4HwWPtH3kZ9iwebKiSzw 7gkedyQ4gfD/VY4b2l2Y0Q37UrgVVYUbArqM0PbW+Bmwu5Fxjk6/Le2yyRHTrxNG0+ XsEKQ/c046O3/+GSHtB8/JgMMSs8tFl02QCuKKzsBmKVXNlP1JLtRcOeW9oCOngSTk 8fsMCxG3DL1FRxDfvAjweQMDSd14YIp2KSP1YTeq1VYab6v6kxUph2IMI25OE+j/Nc RABk9428jfAVQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7dd cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=sozttTNsAAAA:8 a=wv_ar1DUYrJP48xX2MwA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 03/12] pinctrl: single: fix offset management Date: Sun, 11 Apr 2021 09:39:41 +0200 Message-Id: <20210411073950.24772-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfD33vhLSjuNxfUwRQ9tvS5sPQSgppOjLqVYk2b/dzNJf8TvmiERjoolqiDxs2WrPYwBxobpNrYu7Pb2CP/Dkdi6aKW0nqULM4KblmfLsgPJgEJsNI06P T9a6wN8kdSYXnvw4WpR9L+S26Ac89KGDGTf5OId0nWGBg6Oe8kuwu9iPnc2FNVs72rZBDoN5w8u2F6ke2PNUgMG85Q9fLrguXg7HfZJ6iaCeH0ozV9DJKOMp h/BM5++zmpEtTGQ0ri5fj/wdou68e21u8s9ZGBFYeOLj0MXUy5VnisPAG+0m2RYPYm/PrItw8JJ7bZ5IfwnEfCWOA0I1wGo34rOn35PBG9N1j7QnrAnb/EI2 kFJZosEY0mYKspSDIVMrL0cCKLIZzbqLLsyF6FlLc/ZA2DiWQxFWUgkOGSEEjIcxxvW5bghWLueLheftKy5TqnKnGJlcSA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The pinmux configuration DT node of a peripheral does not define a physical address but an offset. Only by adding it to the base address of the controller it is possible to calculate the physical address of the register to be configured. Printing an offset also requires a different formatting option than a physical address. Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- (no changes since v3) Changes in v3: - Added Pratyush Yadav review tag. drivers/pinctrl/pinctrl-single.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 49ed15211d..935b5e920d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -77,15 +77,17 @@ static int single_configure_pins(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_pin_cfg); phys_addr_t reg; - u32 val; + u32 offset, val; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; switch (pdata->width) { case 16: @@ -111,15 +113,17 @@ static int single_configure_bits(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_bits_cfg); phys_addr_t reg; - u32 val, mask; + u32 offset, val, mask; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; From patchwork Sun Apr 11 07:39:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464753 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhZlpdnv; Sun, 11 Apr 2021 09:40:14 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126814; bh=Q9cpyvx4da9tjvW7EuKYo5GNbrBLW8OzX0o6DBeDgI8=; h=From; b=Jv25hXbgGuWOLTbP9/8yxqRfPourqhONpkqhG4bGFDzNV6kxZL8xMo+1x9AZSyXOO CRMb6PbhqTMhwRUlTOOFHozx+5y4JXHbBoI1bo9fB3U77ATliiR5/TiSnMWrumXD+y bl5cLP9hjYCp1Ofk9O68ps7q6sB1atn8DIUrzUpmDsxBSkT2+egVhb+XbdkL8ZEWRy b01uzxbgIbefxCmivYEmkG+ZaNvRaOUKRPuGLZgiH+GWr3PfmXHrF0ytiClFbtTTLs HEPGZGwgM+4BvEOcG/59ZP1cxjZPr5l38Y5BoLagStFvDXgWSAQeP4vkhxyOL2boRw 5QEBvjJHrqsmw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7de cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=sozttTNsAAAA:8 a=u5BIsiXaYWSDGc_4nFgA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 04/12] pinctrl: single: fix debug messages formatting Date: Sun, 11 Apr 2021 09:39:42 +0200 Message-Id: <20210411073950.24772-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIP8Kdv0wOLPBWUnMHMFs1PsOUDB1nWuacsl+Qa27oH+cscEHIYBntJxY5Vt5ywJV4KjYY5VsNqr+LUg3uLeAS0c+fG3CYn1/HFsK4ZT5iBhh2fa+68a F+N3flzHRL/NlO82C5RizWKQialvrPCXXjLr48DNUrVuJ5bNK8WarwdOKMdU0gD6E9IlddDopo2khaEegFFZCiYQvLCVqcCxGPH9jly9avj+Sds4DPZPiv2z 3uG6CN1xuHC7aSbfCIeGW6CziLTB9vlYhx8Hwg63tfpP0RltaOWpOjgWkGOoEq9vuqoS53r2jWAfouhkMP1WWbBKsS/dXh9QkC4IezXaKUjBVJwdJz6HjX/c scM/OTledCqVBXgMYWoBj4gnpqHsXQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); prints the 'reg' address preceded by the prefix 0x0x instead of 0x. This because the printf '%pa' format specifier already prepends the prefix '0x' to the address displayed. Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- (no changes since v3) Changes in v3: - Updated commit message. - Added Pratyush Yadav review tag. Changes in v2: - Updated commit message - Split in 2 commits drivers/pinctrl/pinctrl-single.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 935b5e920d..cec00e289c 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -101,7 +101,7 @@ static int single_configure_pins(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } @@ -140,7 +140,7 @@ static int single_configure_bits(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } From patchwork Sun Apr 11 07:39:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464751 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- (no changes since v3) Changes in v3: - Added Pratyush Yadav review tag. Changes in v2: - Check dev_read_addr_size return value. drivers/pinctrl/pinctrl-single.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index cec00e289c..d5656de8e8 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -182,17 +182,19 @@ static int single_set_state(struct udevice *dev, static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; - u32 of_reg[2]; - int res; + fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); pdata->width = dev_read_u32_default(dev, "pinctrl-single,register-width", 0); - res = dev_read_u32_array(dev, "reg", of_reg, 2); - if (res) - return res; - pdata->offset = of_reg[1] - pdata->width / 8; + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get base register size\n"); + return -EINVAL; + } + + pdata->offset = size - pdata->width / BITS_PER_BYTE; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) { From patchwork Sun Apr 11 07:39:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464754 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=gkO8gS7Q; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3jF5Jnpz9sVq for ; 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Sun, 11 Apr 2021 09:40:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhalpdoI; Sun, 11 Apr 2021 09:40:15 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126815; bh=aYjTb4RaEaxpnwVlZ2u6DCLNXArLtyQH9ZkaBTUDByM=; h=From; b=gkO8gS7QWflpNvDhXlQGPS0BAI6CsY2CCvIIyNKOP8D41ORfMaKaegzMY5wRim9Oy GzD75QKRS6Uzc6uSDjRY74k9QxyudbX4+nHs9VvgMnWe9zV6tGCttzGpQ9cMlKM7qh hR9QFw+2jCJjI3X5kPRilVxCIcZlrW4mH8pMkmW4PP/tH1H73b200jUlzjSSQXstyS A4wJe9lul1jyMN69GcWTM0+cdlOxDeUYBEnTYGvOOB+KcovMILye76S/N6OUiuLXq6 c5sDyewQPUlRQRmZ9FiLEQT5PJhn5ekjS8iKuQ/KdvhlJWOOlYFYrxy7TR9q30Jufj RkfiwoolTK1yQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7df cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=AewqRzli-FD5yDso3x8A:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 06/12] pinctrl: single: check "register-width" DT property Date: Sun, 11 Apr 2021 09:39:44 +0200 Message-Id: <20210411073950.24772-7-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfK52negj8PqAC1km3fgbIZAybyI4OdPLJfFmUk0Tslg0mjuzQRPed/MLiwZjrIsMgts6fwZ9Sxvfk0qWOqCPjDxNT/kLQfRISZUMVLh92j7uU1EE0DU+ kGoSN0OO0qecB9bYx3TkyM1gBiCbnHVxoy1DZ3EhFXw4bHeCpdYmoJXHNroo6flpES2yBv/qbbI02vfby2B7DsvKF0PSZBiJ0WPuOR/cfxLCWf0xYxgEctdt NSFZqzGCtYGpdBY4HaFDlVLbptGDJBwq3ZixmV2++6plBiWqGKB2YeM8D+aFVCUb+YguT38iCt76rOdfmtv4tPPeOxhJQsj+Zoelgd3yQrbsJEj2HVLQ2rLp dbnwhsUNewL2+qHwp3toCQ6nhDrmJw== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean In more recent versions of the Linux kernel the driver's probe function returns an error if the "pinctrl-single,register-width" DT property is missing. The lack of this information, in fact, does not allow to know whether to access the registers of the controller at 8, 16, ... bits. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Updated commit message. - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d5656de8e8..5ade108875 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -22,7 +22,7 @@ struct single_pdata { fdt_addr_t base; int offset; u32 mask; - int width; + u32 width; bool bits_per_mux; }; @@ -184,9 +184,13 @@ static int single_of_to_plat(struct udevice *dev) fdt_addr_t addr; fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); + int ret; - pdata->width = - dev_read_u32_default(dev, "pinctrl-single,register-width", 0); + ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width); + if (ret) { + dev_err(dev, "missing register width\n"); + return ret; + } addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) { From patchwork Sun Apr 11 07:39:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464755 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=RVq8bb3v; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3jW3HN6z9sVq for ; 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Sun, 11 Apr 2021 09:40:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhblpdoS; Sun, 11 Apr 2021 09:40:15 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126815; bh=FvivucD2j3LuB6u+dcWj6glGDsRzqgUxapn0PUTIKv0=; h=From; b=RVq8bb3vyV2feDE2wJd+TXI19hrqLMERCGk7Oyzja+ngTs1+Z6FHP1Ghy9qn4HPSX q3CI4Z1xikSmWgf5MZQ4RMxS9hNFjxtJ5WR4N7bVfz/AWbL4hXOii/VnzSCWQSUFqp Hgn2ctIsyBefZm6H90QKqdaIt5Fc4dz1sgiSo2Ju6eKVDYHAL+OdYKCeO7f0lBblDt aN/j1H9IxQ9t7oMYW9+KiSG4WK7PEnwL85zOAq9mlX3qvQ9FHMmfWBm1RzAqGZS6TR T4eRl/faplWlBDpbCGa3IkmhcaDLpiQWziL11MA9pgfkCvAnpzUKEc3ETD759HsCOu sfY2uQ58K0G0Q== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7df cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=9az6cxj04SzJwZhvl5UA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 07/12] pinctrl: single: change function mask default value Date: Sun, 11 Apr 2021 09:39:45 +0200 Message-Id: <20210411073950.24772-8-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfK52negj8PqAC1km3fgbIZAybyI4OdPLJfFmUk0Tslg0mjuzQRPed/MLiwZjrIsMgts6fwZ9Sxvfk0qWOqCPjDxNT/kLQfRISZUMVLh92j7uU1EE0DU+ kGoSN0OO0qecB9bYx3TkyM1gBiCbnHVxoy1DZ3EhFXw4bHeCpdYmoJXHNroo6flpES2yBv/qbbI02vfby2B7DsvKF0PSZBiJ0WPuOR/cfxLCWf0xYxgEctdt NSFZqzGCtYGpdBY4HaFDlVLbptGDJBwq3ZixmV2++6plBiWqGKB2YeM8D+aFVCUb+YguT38iCt76rOdfmtv4tPPeOxhJQsj+Zoelgd3yQrbsJEj2HVLQ2rLp dbnwhsUNewL2+qHwp3toCQ6nhDrmJw== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The patch is inspired by more recent versions of the Linux driver. Replacing the default value 0xffffffff of the function mask with 0 is certainly more conservative in case the "pinctrl-single,function-mask" DT property is missing. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v3) Changes in v3: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5ade108875..630a6c08b8 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -79,6 +79,10 @@ static int single_configure_pins(struct udevice *dev, phys_addr_t reg; u32 offset, val; + /* If function mask is null, needn't enable it. */ + if (!pdata->mask) + return 0; + for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -207,8 +211,12 @@ static int single_of_to_plat(struct udevice *dev) } pdata->base = addr; - pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask", - 0xffffffff); + ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask); + if (ret) { + pdata->mask = 0; + dev_warn(dev, "missing function register mask\n"); + } + pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); return 0; From patchwork Sun Apr 11 07:39:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464756 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=ZpGmcvXa; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3jm0zPNz9sVq for ; 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Sun, 11 Apr 2021 09:40:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhblpdoe; Sun, 11 Apr 2021 09:40:16 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126816; bh=5+Aq8mZ3irk1lz5Y7dX9XTIpH2+e42wRuMEaJPq+ctk=; h=From; b=ZpGmcvXajgOFDGb3bNi6FrYzTj5AP6Nq2aVeejkKdktebH/LP/dE7YWxwQ9gx8kL7 9VrO9nRGcZ53anIuek6Y3xn5HuWIMDmnBvF82tuq2OezY1s8UKMuCrlH3GCuX4i+f9 CLSaTHsLfiE1sqWMy7OuUTK/JFI4R7nTSTjAAqacheOZp5JeoR0xrwgZlyP9Xna/8x O2raGgzbwh8ar2BwTpRHj7IcNhmXvS9WMNcfhI7rVvpNBizxIW/aOUVuulJRqZLO1V U8k/hfQaBB3BHHGNH7GLxWJ0pOCK5StAGtRMhB3uFfYDD+M6+207dPZKRoZnzbGCsv VX6vK/L1BY9Vw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7e0 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=SHmA3wKN3BWJ4-rrrCYA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 08/12] pinctrl: single: add register access functions Date: Sun, 11 Apr 2021 09:39:46 +0200 Message-Id: <20210411073950.24772-9-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfJeFOC3wnkZFiUr2qTHw5JMymSOI2yZ+FXrasjDnR0uizUpJmhSlNYuPHDtl6CKN+0dgO9SjCmAii/UJvgsitF8aKA7EokAxBI9X4XkhJkVSAE/ZAhTF /QMa2KHhWD1YN6av3csje/xsU68Rko6O/0nkgUACcyzT1OZVmmgbn+ogeF49vJsH6M1IH0XE4DN+kKeB5zCR+KeGOdULJ+4v9uLMliR3jrcN9ACDdb1If/3W O+atmTZwSruTWP+c8V89z211ROomOP+EDuYenBsm6t4bk1LruH/HHaH+87WzxypRX4bsFlOcIY9zXMeeCWqRQHJWVQPrghmPD7XMfPTUOaH+WkqsDkA3ejgK IInnXGNYpwfzdcPx7OlXve60Jb9PYQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The configuration of pinmux registers was implemented with duplicate code which can be removed by adding two functions for read/write access. Access to 8-bit registers has also been added. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v3) Changes in v3: - Added Simon Glass review tag. Changes in v2: - Updated commit message. - Remove pointer to access functions. drivers/pinctrl/pinctrl-single.c | 71 +++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 630a6c08b8..5b3ccc2281 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -56,6 +56,38 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + return readb(reg); + case 16: + return readw(reg); + default: /* 32 bits */ + return readl(reg); + } + + return readb(reg); +} + +static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + writeb(val, reg); + break; + case 16: + writew(val, reg); + break; + default: /* 32 bits */ + writel(val, reg); + } +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -93,19 +125,10 @@ static int single_configure_pins(struct udevice *dev, reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; - switch (pdata->width) { - case 16: - writew((readw(reg) & ~pdata->mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~pdata->mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, + reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + } return 0; } @@ -131,19 +154,7 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; - - switch (pdata->width) { - case 16: - writew((readw(reg) & ~mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; @@ -196,6 +207,16 @@ static int single_of_to_plat(struct udevice *dev) return ret; } + switch (pdata->width) { + case 8: + case 16: + case 32: + break; + default: + dev_err(dev, "wrong register width\n"); + return -EINVAL; + } + addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "failed to get base register size\n"); From patchwork Sun Apr 11 07:39:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464758 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5b3ccc2281..e99eb552f5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -26,6 +26,16 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_priv - private data + * @bits_per_pin: number of bits per pin + * @npins: number of selectable pins + */ +struct single_priv { + unsigned int bits_per_pin; + unsigned int npins; +}; + /** * struct single_fdt_pin_cfg - pin configuration * @@ -194,6 +204,30 @@ static int single_set_state(struct udevice *dev, return len; } +static int single_get_pins_count(struct udevice *dev) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->npins; +} + +static int single_probe(struct udevice *dev) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + u32 size; + + size = pdata->offset + pdata->width / BITS_PER_BYTE; + priv->npins = size / (pdata->width / BITS_PER_BYTE); + if (pdata->bits_per_mux) { + priv->bits_per_pin = fls(pdata->mask); + priv->npins *= (pdata->width / priv->bits_per_pin); + } + + dev_dbg(dev, "%d pins\n", priv->npins); + return 0; +} + static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; @@ -244,6 +278,7 @@ static int single_of_to_plat(struct udevice *dev) } const struct pinctrl_ops single_pinctrl_ops = { + .get_pins_count = single_get_pins_count, .set_state = single_set_state, }; @@ -258,5 +293,7 @@ U_BOOT_DRIVER(single_pinctrl) = { .of_match = single_pinctrl_match, .ops = &single_pinctrl_ops, .plat_auto = sizeof(struct single_pdata), + .priv_auto = sizeof(struct single_priv), .of_to_plat = single_of_to_plat, + .probe = single_probe, }; From patchwork Sun Apr 11 07:39:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464757 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index e99eb552f5..cdb5040852 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,10 +30,12 @@ struct single_pdata { * struct single_priv - private data * @bits_per_pin: number of bits per pin * @npins: number of selectable pins + * @pin_name: temporary buffer to store the pin name */ struct single_priv { unsigned int bits_per_pin; unsigned int npins; + char pin_name[PINNAME_SIZE]; }; /** @@ -204,6 +206,19 @@ static int single_set_state(struct udevice *dev, return len; } +static const char *single_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct single_priv *priv = dev_get_priv(dev); + + if (selector >= priv->npins) + snprintf(priv->pin_name, PINNAME_SIZE, "Error"); + else + snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector); + + return priv->pin_name; +} + static int single_get_pins_count(struct udevice *dev) { struct single_priv *priv = dev_get_priv(dev); @@ -279,6 +294,7 @@ static int single_of_to_plat(struct udevice *dev) const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, + .get_pin_name = single_get_pin_name, .set_state = single_set_state, }; From patchwork Sun Apr 11 07:39:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464759 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126817; bh=QwRSs1lcqNnQPSyIiyyyosn0Fz3Kezy5MHhhtUP25GE=; h=From; b=OshHsTjJbzratOuIjzpJ9ely4Bfqy2TrjuheHM130mEhEzMapceHZIqFZJJjiVvr6 knGpgjfwPvOrsBWu7dfhYrtzJLv5awimx0lQ54BKiydbVN3iAbb9/82WMxucht4nox EaTWnpgSbn8uhj6+LQYOV8JZZR3wGbsdGEKJsTVzSF5d2potEeWaWGMNS7UfWi9B+c C4aPijB4xikZ+r1sJsiMw05IdEoukqOEDmMfhCPmPAtausYi/RYfdorYMOUXlPsBQw JiVNp//qYOhAmGR5tjMmQvtpbdYGKb+yvHXXfCSHmXqfCF+Aqjn9cvusQGKqQPaQbw 83fxLWnDe/ZKw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7e1 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=d069haIMVjMWh2nAXtgA:9 a=651WY0wUjYG4HMiW:21 a=tRt1H8mtyS-9e9eN:21 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 11/12] pinctrl: single: add get_pin_muxing operation Date: Sun, 11 Apr 2021 09:39:49 +0200 Message-Id: <20210411073950.24772-12-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfCVVWStkorApYBG8/WBqsypbEBd8MfwaXDpdo2XDB2eOL/kDzLE0kKhgu1dQt3CKNsaI1B68ZP2nD+twpC81DYeym1byFTxiTNDwJuQIYLHFKhpKKMeM SZJKvc/UDx56qCiV4J9h0qVsLN/e/ePNDCjkckDfI+86qgUYeaRoZ+p+yN+wHn2I0h1NTvGUE7jtE5qU11/c51Ewy3JPFtBfqocxqujFzpbsXvJyyq7bIvUJ L2KC+68sX4wGy7nfM+fjPABDyTQO7g+xewcMz0J4YAY3g9R/Ogc4s2APvjjG9oRV3+P6L472H1ejrvrs2Q5iS6q5a2eXs9CqOTyBAdIcx1O0TxLTrNaVOSW/ 2pZWj6TOsPL/o3Gvlsalj65p9EC9i+ILE+1i8x5cj4FESC8Iah0sF7zNvOC9krg7cZwZ1MRO1d9050yTbB7hOje14F1Zag== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v3) Changes in v3: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 222 +++++++++++++++++++++++++++++-- 1 file changed, 213 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index cdb5040852..3ddb637ab7 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1,14 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) EETS GmbH, 2017, Felix Brack + * Copyright (C) 2021 Dario Binacchi */ #include #include #include +#include #include #include +#include #include +#include /** * struct single_pdata - platform data @@ -26,6 +30,20 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_func - pinctrl function + * @node: list node + * @name: pinctrl function name + * @npins: number of entries in pins array + * @pins: pins array + */ +struct single_func { + struct list_head node; + const char *name; + unsigned int npins; + unsigned int *pins; +}; + /** * struct single_priv - private data * @bits_per_pin: number of bits per pin @@ -36,6 +54,7 @@ struct single_priv { unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; + struct list_head functions; }; /** @@ -100,6 +119,121 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) } } +/** + * single_get_pin_by_offset() - get a pin based on the register offset + * @dev: single driver instance + * @offset: register offset from the base + */ +static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + + if (offset > pdata->offset) { + dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n", + offset, pdata->offset); + return -EINVAL; + } + + if (pdata->bits_per_mux) + return (offset * BITS_PER_BYTE) / priv->bits_per_pin; + + return offset / (pdata->width / BITS_PER_BYTE); +} + +static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + unsigned int mux_bytes; + + if (pin >= priv->npins) + return -EINVAL; + + mux_bytes = pdata->width / BITS_PER_BYTE; + if (pdata->bits_per_mux) { + int byte_num; + + byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE; + return (byte_num / mux_bytes) * mux_bytes; + } + + return pin * mux_bytes; +} + +static const char *single_get_pin_function(struct udevice *dev, + unsigned int pin) +{ + struct single_priv *priv = dev_get_priv(dev); + struct single_func *func; + int i; + + list_for_each_entry(func, &priv->functions, node) { + for (i = 0; i < func->npins; i++) { + if (pin == func->pins[i]) + return func->name; + + if (pin < func->pins[i]) + break; + } + } + + return NULL; +} + +static int single_get_pin_muxing(struct udevice *dev, unsigned int pin, + char *buf, int size) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + fdt_addr_t reg; + const char *fname; + unsigned int val; + int offset, pin_shift = 0; + + offset = single_get_offset_by_pin(dev, pin); + if (offset < 0) + return offset; + + reg = pdata->base + offset; + val = single_read(dev, reg); + + if (pdata->bits_per_mux) + pin_shift = pin % (pdata->width / priv->bits_per_pin) * + priv->bits_per_pin; + + val &= (pdata->mask << pin_shift); + fname = single_get_pin_function(dev, pin); + snprintf(buf, size, "%pa 0x%08x %s", ®, val, + fname ? fname : "UNCLAIMED"); + return 0; +} + +static struct single_func *single_allocate_function(struct udevice *dev, + unsigned int group_pins) +{ + struct single_func *func; + + func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL); + if (!func) + return ERR_PTR(-ENOMEM); + + func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins, + GFP_KERNEL); + if (!func->pins) + return ERR_PTR(-ENOMEM); + + return func; +} + +static int single_pin_compare(const void *s1, const void *s2) +{ + int pin1 = *(const unsigned int *)s1; + int pin2 = *(const unsigned int *)s2; + + return pin1 - pin2; +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -113,13 +247,16 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) * @size: Size of the 'pins' array in bytes. * The number of register/value pairs in the 'pins' array therefore * equals to 'size / sizeof(struct single_fdt_pin_cfg)'. + * @fname: Function name. */ static int single_configure_pins(struct udevice *dev, const struct single_fdt_pin_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); - int n, count = size / sizeof(struct single_fdt_pin_cfg); + struct single_priv *priv = dev_get_priv(dev); + int n, pin, count = size / sizeof(struct single_fdt_pin_cfg); + struct single_func *func; phys_addr_t reg; u32 offset, val; @@ -127,33 +264,61 @@ static int single_configure_pins(struct udevice *dev, if (!pdata->mask) return 0; + func = single_allocate_function(dev, count); + if (IS_ERR(func)) + return PTR_ERR(func); + + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { - dev_dbg(dev, " invalid register offset 0x%x\n", + dev_err(dev, " invalid register offset 0x%x\n", offset); continue; } reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset %x\n", + offset); + continue; + } + single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); - + func->pins[func->npins] = pin; + func->npins++; } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_configure_bits(struct udevice *dev, const struct single_fdt_bits_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); - int n, count = size / sizeof(struct single_fdt_bits_cfg); + struct single_priv *priv = dev_get_priv(dev); + int n, pin, count = size / sizeof(struct single_fdt_bits_cfg); + int npins_in_reg, pin_num_from_lsb; + struct single_func *func; phys_addr_t reg; - u32 offset, val, mask; + u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask; + + npins_in_reg = pdata->width / priv->bits_per_pin; + func = single_allocate_function(dev, count * npins_in_reg); + if (IS_ERR(func)) + return PTR_ERR(func); + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -164,11 +329,47 @@ static int single_configure_bits(struct udevice *dev, reg = pdata->base + offset; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset 0x%pa\n", + ®); + continue; + } + mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + + while (mask) { + bit_pos = __ffs(mask); + pin_num_from_lsb = bit_pos / priv->bits_per_pin; + mask_pos = pdata->mask << bit_pos; + val_pos = val & mask_pos; + submask = mask & mask_pos; + + if ((mask & mask_pos) == 0) { + dev_err(dev, "Invalid mask at 0x%x\n", offset); + break; + } + + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(dev, + "Invalid submask 0x%x at 0x%x\n", + submask, offset); + continue; + } + + func->pins[func->npins] = pin + pin_num_from_lsb; + func->npins++; + } } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_set_state(struct udevice *dev, @@ -186,7 +387,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid pin configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_pins(dev, prop, len); + single_configure_pins(dev, prop, len, config->name); return 0; } @@ -198,7 +399,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid bits configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_bits(dev, prop_bits, len); + single_configure_bits(dev, prop_bits, len, config->name); return 0; } @@ -232,6 +433,8 @@ static int single_probe(struct udevice *dev) struct single_priv *priv = dev_get_priv(dev); u32 size; + INIT_LIST_HEAD(&priv->functions); + size = pdata->offset + pdata->width / BITS_PER_BYTE; priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { @@ -296,6 +499,7 @@ const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, .get_pin_name = single_get_pin_name, .set_state = single_set_state, + .get_pin_muxing = single_get_pin_muxing, }; static const struct udevice_id single_pinctrl_match[] = { From patchwork Sun Apr 11 07:39:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464760 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 11 Apr 2021 09:40:18 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126818; bh=/sWnljJqDTKHahPSZvL3WH3XBZ/1lz/usyajK1eHIZg=; h=From; b=qp/ddc8iCt8cbo5csK/uqHR0Fuo3/2tDGQ7fXUtDuFLMkdsU4lx37LI/GXGN/+6/b dvSO11dwqooORdb8hrpxACKD73F6ZuydVgztNvpPzndL+83/q9vLVDr7ZxLR5BhhCn DsTzu/+0CwpIi7AA0eMkKKbzi+ggcBYfK2zsRnwJo90/YLUhXwNLRbjzwipUy8DnY1 0OOcGJ5PsELd+sYESDWPro/iLcKWmgTiCk/jzEesrR3JKt7xLOJBxiZh4j1bghnqUm izFnD2QTqL6OhzbUiYa8ggZ3cwWaWgEGJHdv1TzS/0gQEAaVHxemrHoHLBpnvIetQr qrfKV/kaGfOCQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7e2 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=tUrikdqTLrevZEpRUyoA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Bin Meng , Heinrich Schuchardt , Jean-Jacques Hiblot , Patrick Delaunay , Pratyush Yadav , Sean Anderson , Simon Glass , Wolfgang Wallner Subject: [PATCH v4 12/12] test: pinmux: add test for 'pinctrl-single' driver Date: Sun, 11 Apr 2021 09:39:50 +0200 Message-Id: <20210411073950.24772-13-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGFz/sufjvLkVLoAsok7lrZNjRMZTKgB1elnzOmMqNEA2jGGSjwFiAzR1Sqkf+OkLpAFWEP/teymNSVWLdMW6AV7912aXHpRdAmoRrtpNumKzAp784Ma 7ZP4dgGYgKWk8G189ALNrb8fzjZNKypqgfCCXhx9fD6HMeC1hsj9RnuoxMdorZgY3GimNu3QR+7pCVNztukyvtJimtrnpRJKCvDs9sfuljmAGIFkQZeoHNJ+ RI6KP4JcO3wr7cfLu2tCtIv1L1DE71bJChl3il/yglsC85vYi1PVpbLE2rQW9hvMo6az2glN0TU76Q2BOD+hybGSK8lvCpRqBIV9KvCyEfEhW6+lc6afjcoV yUBCwcxeoOw+z91R0gd4XPMCwwrQ8c0aLzKzg10JV3wLrGjxvY5KyP9hFS2gItH82FBU66WSe8l62ZsKATBCc3fieR+1WTvVlzI5fCIRahB0hqWe6ANTar6v Pyqkh4VMJ5BzCm8JN0ItFlIbLHBSn30fvOA0e9/1WMNKEPpqWdjbKFjfTodX3EEEQVDWhvcl8ZMbUPUz X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The test adds two pinmux nodes to the device tree, one to test when a register changes only one pin's mux (pinctrl-single,pins), and the other to test when more than one pin's mux is changed (pinctrl-single,bits). This required replacing the controller's register access functions when the driver is used on sandbox. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- Changes in v4: - Added CONFIG_PINCTRL_SINGLE to sandbox_flattree_defconfig to fix sandbox_flattree test errors. Changes in v2: - Added Simon Glass review tag. - Added error checking when the 'width' property is missing. - Fix coding style. arch/sandbox/dts/test.dts | 72 +++++++++++++++++++++++ configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + drivers/pinctrl/pinctrl-single.c | 31 ++++++++++ test/dm/pinmux.c | 91 ++++++++++++++++++++++++++++-- 5 files changed, 191 insertions(+), 5 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 899e75f260..60b2caf514 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -569,6 +569,9 @@ reg = <0 1>; compatible = "sandbox,i2c"; clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c0_pins>; + eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; @@ -649,6 +652,8 @@ lcd { u-boot,dm-pre-reloc; compatible = "sandbox,lcd-sdl"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_lcd_pins>; xres = <1366>; yres = <768>; }; @@ -899,6 +904,8 @@ pwm: pwm { compatible = "sandbox,pwm"; #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm_pins>; }; pwm2 { @@ -970,6 +977,9 @@ reg = <0 1>; compatible = "sandbox,spi"; cs-gpios = <0>, <0>, <&gpio_a 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_spi0_pins>; + spi.bin@0 { reg = <0>; compatible = "spansion,m25p16", "jedec,spi-nor"; @@ -1059,6 +1069,8 @@ uart0: serial { compatible = "sandbox,serial"; u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart0_pins>; }; usb_0: usb@0 { @@ -1325,6 +1337,66 @@ }; }; + pinctrl-single-no-width { + compatible = "pinctrl-single"; + reg = <0x0000 0x238>; + #pinctrl-cells = <1>; + pinctrl-single,function-mask = <0x7f>; + }; + + pinctrl-single-pins { + compatible = "pinctrl-single"; + reg = <0x0000 0x238>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + + pinmux_pwm_pins: pinmux_pwm_pins { + pinctrl-single,pins = < 0x48 0x06 >; + }; + + pinmux_spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + 0x190 0x0c + 0x194 0x0c + 0x198 0x23 + 0x19c 0x0c + >; + }; + + pinmux_uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x70 0x30 + 0x74 0x00 + >; + }; + }; + + pinctrl-single-bits { + compatible = "pinctrl-single"; + reg = <0x0000 0x50>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + + pinmux_i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,bits = < + 0x10 0x00002200 0x0000ff00 + >; + }; + + pinmux_lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + 0x40 0x22222200 0xffffff00 + 0x44 0x22222222 0xffffffff + 0x48 0x00000022 0x000000ff + 0x48 0x02000000 0x0f000000 + 0x4c 0x02000022 0x0f0000ff + >; + }; + }; + hwspinlock@0 { compatible = "sandbox,hwspinlock"; }; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5da8d1679e..233c326fad 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -198,6 +198,7 @@ CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y CONFIG_DM_PMIC=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index b68f938cb3..689b3a9e20 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -142,6 +142,7 @@ CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y CONFIG_DM_PMIC=y diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 3ddb637ab7..48bdd0f6f5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -51,6 +51,9 @@ struct single_func { * @pin_name: temporary buffer to store the pin name */ struct single_priv { +#if (IS_ENABLED(CONFIG_SANDBOX)) + u32 *sandbox_regs; +#endif unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; @@ -87,6 +90,8 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +#if (!IS_ENABLED(CONFIG_SANDBOX)) + static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) { struct single_pdata *pdata = dev_get_plat(dev); @@ -119,6 +124,24 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) } } +#else /* CONFIG_SANDBOX */ + +static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->sandbox_regs[reg]; +} + +static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + priv->sandbox_regs[reg] = val; +} + +#endif /* CONFIG_SANDBOX */ + /** * single_get_pin_by_offset() - get a pin based on the register offset * @dev: single driver instance @@ -436,6 +459,14 @@ static int single_probe(struct udevice *dev) INIT_LIST_HEAD(&priv->functions); size = pdata->offset + pdata->width / BITS_PER_BYTE; + #if (CONFIG_IS_ENABLED(SANDBOX)) + priv->sandbox_regs = + devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs), + GFP_KERNEL); + if (!priv->sandbox_regs) + return -ENOMEM; + #endif + priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { priv->bits_per_pin = fls(pdata->mask); diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c index 047184d4bc..265df4ccb9 100644 --- a/test/dm/pinmux.c +++ b/test/dm/pinmux.c @@ -9,16 +9,21 @@ #include #include -static int dm_test_pinmux(struct unit_test_state *uts) -{ - char buf[64]; - struct udevice *dev; - +static char buf[64]; #define test_muxing(selector, expected) do { \ ut_assertok(pinctrl_get_pin_muxing(dev, selector, buf, sizeof(buf))); \ ut_asserteq_str(expected, (char *)&buf); \ } while (0) +#define test_name(selector, expected) do { \ + ut_assertok(pinctrl_get_pin_name(dev, selector, buf, sizeof(buf))); \ + ut_asserteq_str(expected, (char *)&buf); \ +} while (0) + +static int dm_test_pinmux(struct unit_test_state *uts) +{ + struct udevice *dev; + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl", &dev)); test_muxing(0, "UART TX."); test_muxing(1, "UART RX."); @@ -54,4 +59,80 @@ static int dm_test_pinmux(struct unit_test_state *uts) return 0; } + DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT); + +static int dm_test_pinctrl_single(struct unit_test_state *uts) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-no-width", &dev); + ut_asserteq(-EINVAL, ret); + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SPI, "spi@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-pins", &dev)); + ut_asserteq(142, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(141, "PIN141"); + test_name(142, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(18, "0x00000048 0x00000006 pinmux_pwm_pins"); + test_muxing(28, "0x00000070 0x00000030 pinmux_uart0_pins"); + test_muxing(29, "0x00000074 0x00000000 pinmux_uart0_pins"); + test_muxing(100, "0x00000190 0x0000000c pinmux_spi0_pins"); + test_muxing(101, "0x00000194 0x0000000c pinmux_spi0_pins"); + test_muxing(102, "0x00000198 0x00000023 pinmux_spi0_pins"); + test_muxing(103, "0x0000019c 0x0000000c pinmux_spi0_pins"); + ret = pinctrl_get_pin_muxing(dev, 142, buf, sizeof(buf)); + ut_asserteq(-EINVAL, ret); + ut_assertok(uclass_get_device_by_name(UCLASS_I2C, "i2c@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_VIDEO, "lcd", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-bits", &dev)); + ut_asserteq(160, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(159, "PIN159"); + test_name(160, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(34, "0x00000010 0x00000200 pinmux_i2c0_pins"); + test_muxing(35, "0x00000010 0x00002000 pinmux_i2c0_pins"); + test_muxing(130, "0x00000040 0x00000200 pinmux_lcd_pins"); + test_muxing(131, "0x00000040 0x00002000 pinmux_lcd_pins"); + test_muxing(132, "0x00000040 0x00020000 pinmux_lcd_pins"); + test_muxing(133, "0x00000040 0x00200000 pinmux_lcd_pins"); + test_muxing(134, "0x00000040 0x02000000 pinmux_lcd_pins"); + test_muxing(135, "0x00000040 0x20000000 pinmux_lcd_pins"); + test_muxing(136, "0x00000044 0x00000002 pinmux_lcd_pins"); + test_muxing(137, "0x00000044 0x00000020 pinmux_lcd_pins"); + test_muxing(138, "0x00000044 0x00000200 pinmux_lcd_pins"); + test_muxing(139, "0x00000044 0x00002000 pinmux_lcd_pins"); + test_muxing(140, "0x00000044 0x00020000 pinmux_lcd_pins"); + test_muxing(141, "0x00000044 0x00200000 pinmux_lcd_pins"); + test_muxing(142, "0x00000044 0x02000000 pinmux_lcd_pins"); + test_muxing(143, "0x00000044 0x20000000 pinmux_lcd_pins"); + test_muxing(144, "0x00000048 0x00000002 pinmux_lcd_pins"); + test_muxing(145, "0x00000048 0x00000020 pinmux_lcd_pins"); + test_muxing(146, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(147, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(148, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(149, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(150, "0x00000048 0x02000000 pinmux_lcd_pins"); + test_muxing(151, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(152, "0x0000004c 0x00000002 pinmux_lcd_pins"); + test_muxing(153, "0x0000004c 0x00000020 pinmux_lcd_pins"); + test_muxing(154, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(155, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(156, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(157, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(158, "0x0000004c 0x02000000 pinmux_lcd_pins"); + test_muxing(159, "0x0000004c 0x00000000 UNCLAIMED"); + ret = pinctrl_get_pin_muxing(dev, 160, buf, sizeof(buf)); + ut_asserteq(-EINVAL, ret); + return 0; +} + +DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);